/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
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 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author$
 * $Date$
 * $RCSfile: spi_hw_reg.h,v $
 * $Revision$
 *
 *---------------------------------------------------------------------------*/

/** @file spi_hw_reg.h
 *  Define SPI hardware register information.
 */
#include "x_hal_5381.h"
#include "x_pinmux.h"
#ifndef SPI_HW_COMM_H
#define SPI_HW_COMM_H

//---------------------------------------------------------------------------
// Macro definitions
//-----------------------------------------------------------------------------
//PDWNC SPI
#if defined(CC_MT5895)
#define PDWNC_GSPI_BASE (PDWNC_BASE)
#else
#define PDWNC_GSPI_BASE (IO_VIRT + 0x20000 + 0x8000)
#endif

//Page PDWNC_GSPI
#define PDWNC_GSPI_DATA0 (PDWNC_GSPI_BASE + 0xB00)
    #define FLD_GSPI_DATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_DATA1 (PDWNC_GSPI_BASE + 0xB04)
    #define FLD_GSPI_DATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_DATA2 (PDWNC_GSPI_BASE + 0xB08)
    #define FLD_GSPI_DATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_DATA3 (PDWNC_GSPI_BASE + 0xB0C)
    #define FLD_GSPI_DATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_DATA4 (PDWNC_GSPI_BASE + 0xB10)
    #define FLD_GSPI_DATA4 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_DATA5 (PDWNC_GSPI_BASE + 0xB14)
    #define FLD_GSPI_DATA5 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_DATA6 (PDWNC_GSPI_BASE + 0xB18)
    #define FLD_GSPI_DATA6 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_DATA7 (PDWNC_GSPI_BASE + 0xB1C)
    #define FLD_GSPI_DATA7 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_CKCFG (PDWNC_GSPI_BASE + 0xB20)
    #define FLD_CLK_DIV Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_CPOL Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_CPHA Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_GSPI_CSACC (PDWNC_GSPI_BASE + 0xB24)
    #define FLD_CS_LEAD_LATENCY Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_CS_LAG_LATENCY Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_GSPI_CSACC2 (PDWNC_GSPI_BASE + 0xB28)
    #define FLD_CS_HOLD_LATENCY Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_GSPI_NOB (PDWNC_GSPI_BASE + 0xB30)
    #define FLD_NDATA_LEN Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_MDATA_LEN Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_GSPI_CON (PDWNC_GSPI_BASE + 0xB34)
    #define FLD_LSB_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GSPI_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GSPI_TRIG Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_GSPI_INTR_EN (PDWNC_GSPI_BASE + 0xB40)
    #define FLD_GSPI_DONE_INTR_EN Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_GSPI_INTR (PDWNC_GSPI_BASE + 0xB44)
    #define FLD_GSPI_DONE_INTR Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_GSPI_SHREG0 (PDWNC_GSPI_BASE + 0xB50)
    #define FLD_GSPI_SHREG0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_SHREG1 (PDWNC_GSPI_BASE + 0xB54)
    #define FLD_GSPI_SHREG1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_SHREG2 (PDWNC_GSPI_BASE + 0xB58)
    #define FLD_GSPI_SHREG2 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_SHREG3 (PDWNC_GSPI_BASE + 0xB5C)
    #define FLD_GSPI_SHREG3 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_SHREG4 (PDWNC_GSPI_BASE + 0xB60)
    #define FLD_GSPI_SHREG4 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_SHREG5 (PDWNC_GSPI_BASE + 0xB64)
    #define FLD_GSPI_SHREG5 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_SHREG6 (PDWNC_GSPI_BASE + 0xB68)
    #define FLD_GSPI_SHREG6 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GSPI_SHREG7 (PDWNC_GSPI_BASE + 0xB6C)
    #define FLD_GSPI_SHREG7 Fld(32,0,AC_FULLDW)//[31:0]




//-----------------------------------------------------------------------------
//PREPH spi
#define SPI_IO_BASE 					  (IO_VIRT + 0x20000 + 0x9000)

#define SPI_CFG0_REG (SPI_IO_BASE + 0x600)
    #define FLD_SPI_CS_SETUP_COUNT Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SPI_CS_HOLD_COUNT Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SPI_SCK_LOW_COUNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SPI_SCK_HIGH_COUNT Fld(8,0,AC_FULLB0)//[7:0]
#define SPI_CFG1_REG (SPI_IO_BASE + 0x604)
    #define FLD_SPI_GET_TICK_DLY Fld(2,30,AC_MSKB3)//[31:30]
    #define FLD_SPI_PACKET_LENGTH Fld(14,16,AC_MSKW32)//[29:16]
    #define FLD_SPI_PACKET_LOOP_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SPI_CS_IDLE_COUNT Fld(8,0,AC_FULLB0)//[7:0]
#define SPI_TX_SRC_REG (SPI_IO_BASE + 0x608)
    #define FLD_SPI_SPI_TX_SRC Fld(32,0,AC_FULLDW)//[31:0]
#define SPI_RX_DST_REG (SPI_IO_BASE + 0x60C)
    #define FLD_SPI_SPI_RX_DST Fld(32,0,AC_FULLDW)//[31:0]
#define SPI_TX_DATA_REG (SPI_IO_BASE + 0x610)
    #define FLD_SPI_SPI_TX_DATA Fld(32,0,AC_FULLDW)//[31:0]
#define SPI_RX_DATA_REG (SPI_IO_BASE + 0x614)
    #define FLD_SPI_SPI_RX_DATA Fld(32,0,AC_FULLDW)//[31:0]
#define SPI_CMD_REG (SPI_IO_BASE + 0x618)
    #define FLD_SPI_PAUSE_IE Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_SPI_FINISH_IE Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_SPI_TX_ENDIAN Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_SPI_RX_ENDIAN Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_SPI_RXMSBF Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_SPI_TXMSBF Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_SPI_TX_DMA_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_SPI_RX_DMA_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_SPI_CPOL Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_SPI_CPHA Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_SPI_CS_POL Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_SPI_SAMPLE_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SPI_CS_DEASSERT_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SPI_PAUSE_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SPI_RX_FIFO_ONLY_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SPI_RST Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SPI_RESUME Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SPI_CMD_ACT Fld(1,0,AC_MSKB0)//[0:0]
#define SPI_STATUS0_REG (SPI_IO_BASE + 0x61C)
    #define FLD_SPI_PAUSE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SPI_FINISH Fld(1,0,AC_MSKB0)//[0:0]
#define SPI_STATUS1_REG (SPI_IO_BASE + 0x620)
    #define FLD_SPI_BUSY Fld(1,0,AC_MSKB0)//[0:0]
#define SPI_DUMMY_REG (SPI_IO_BASE + 0x62C)
    #define FLD_SPI_SPI_DUMMY Fld(32,0,AC_FULLDW)//[31:0]
#define SPI_RESERVED_REG (SPI_IO_BASE + 0x630)
    #define FLD_SPI_REG_GSPI_DI_IN_PD_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SPI_REG_DMARBRST_CHB Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SPI_REG_DMARBRST Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SPI_REG_DMFMREQEN Fld(1,0,AC_MSKB0)//[0:0]
    
#define SPI_PAD_SEL_REG                   (SPI_IO_BASE+0x0024)

#define SPI_CFG0_SCK_HIGH_OFFSET          0
#define SPI_CFG0_SCK_LOW_OFFSET           8
#define SPI_CFG0_CS_HOLD_OFFSET           16
#define SPI_CFG0_CS_SETUP_OFFSET          24

#define SPI_CFG1_CS_IDLE_OFFSET           0
#define SPI_CFG1_PACKET_LOOP_OFFSET       8
#define SPI_CFG1_PACKET_LENGTH_OFFSET     16
#define SPI_CFG1_GET_TICK_DLY_OFFSET      30

#define SPI_CFG1_CS_IDLE_MASK             0xff
#define SPI_CFG1_PACKET_LOOP_MASK         0xff00
#define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000


//////////////////////////////////////////////////
//hese define is defined in capy but not husky,add these define to make husky build pass
#ifndef PIN_SPI_CS
#define PIN_SPI_CS  PIN_NO_PINMUX
#endif
#ifndef PIN_SPI_DI
#define PIN_SPI_DI  PIN_NO_PINMUX
#endif
#ifndef PIN_SPI_DO
#define PIN_SPI_DO  PIN_NO_PINMUX
#endif
#ifndef PIN_SPI_CLK
#define PIN_SPI_CLK  PIN_NO_PINMUX
#endif
#ifndef CKGEN_REG_PERI_GSPI_CKCFG
#define CKGEN_REG_PERI_GSPI_CKCFG 0
#endif
#ifndef FLD_PERI_GSPI_CK_SEL
#define FLD_PERI_GSPI_CK_SEL      0
#endif
/////////////////////////////////////////////////



#endif // SIF_HW_REG_H


