/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author$
 * $Date$
 * $RCSfile: dmx_tlv.h,v $
 * $Revision$
 *
 *---------------------------------------------------------------------------*/

/** @file dmx.h
 *  Demux driver - common definitions
 */


#ifndef TLV_H
#define TLV_H

//-----------------------------------------------------------------------------
// Include files
//-----------------------------------------------------------------------------
#include "dmx_mm_if.h"
#include "dmx_if.h"
#include "tlv_if.h"
#include "tlv_fvr_if.h"
#include "x_hal_5381.h"

#include "x_assert.h"

#ifndef CC_SECURE_WORLD
#include "dmx_debug.h"
#endif

#define TLV_DEBUG_BASE (DEMUX11_BASE + 0xA3C)  //0x578d8  //57A3C
#define TLV_DEBUG_BASE_W(base, word)          ((volatile UINT32*)(UPTR)(OFFSET_64BIT + (base)))[(word)]
#define TLV_UCODE_DEBUG_W(idx, word)  TLV_DEBUG_BASE_W((TLV_DEBUG_BASE + idx*104), word)

/*NTP STC config register*/
#define REG_PLLGP_CFG20             (IO_VIRT + 0x33050)
#define REG_PLLGP_CFG21             (IO_VIRT + 0x33054)
#define REG_PLLGP_CFG25             (IO_VIRT + 0x33064)
#define REG_CKGEN_DMX_NEW_NTP_CFG   (IO_VIRT + 0xd260)
#define REG_PLL_PWR_ON              (IO_VIRT + 0xde40)
#define REG_PLL_ISO_EN              (IO_VIRT + 0xde44)
#define REG_PLLGP_NORMAL_CFG0       (IO_VIRT + 0x33000)
#define REG_DMX_HADDS_27M_CFG0      (IO_VIRT + 0xde54)
#define REG_DMX_HADDS_27M_CFG1      (IO_VIRT + 0xde58)

#define REG_PLLGP_CFG               (IO_VIRT + 0x6103c)
#define REG_DMX_HADDS_CFG0          (IO_VIRT + 0xd4e4)
#define REG_DMX_HADDS_CFG1          (IO_VIRT + 0xd4e8)
#define REG_DMX_HADDS_CKCFG         (IO_VIRT + 0xd4ec)

//-----------------------------------------------------------------------------
// Configurations
//-----------------------------------------------------------------------------
#ifdef CC_MT5895
#define TLV_FRAMER_NUM      (4)   //Capy framer0/1/3 support TLV, 2 not support
#else
#define TLV_FRAMER_NUM      (2)   //Huksy ES2 only framer0/1 support TLV
#endif

#define TLV_PID_INDEX_TABLE(pidx)    ((volatile UINT32*)(UPTR)(DEMUX17_BASE + OFFSET_64BIT))[(pidx)]   //0x69000
//#define TLV_PID_INDEX_TABLE1(pidx)         TLV_PID_INDEX_TABLE(pidx)//((volatile UINT32*)(UPTR)(DEMUX10_BASE + 0x400 + OFFSET_64BIT))[(pidx)]
#define TLV_FVR_PID_INDEX_TABLE(pidx)    ((volatile UINT32*)(UPTR)(DEMUX17_BASE + OFFSET_64BIT + 0x200))[(pidx)]     //0x69000 + 128*4  

#define TLV_REG_FRAMER_CONTROL          33  //0x84  tlv framer0&1 setting
#define TLV_REG_FRAMER3_CONTROL         447 //0x6FC tlv framer2 setting

#define TLV_REG_FRAMER0_IP_UDP_MMTP_CFG 76 //0x130 IP/UDP/MMTP config
#define TLV_REG_FRAMER1_IP_UDP_MMTP_CFG 77 //0x134 IP/UDP/MMTP config
#define TLV_REG_FRAMER3_IP_UDP_MMTP_CFG 507 //0x7EC IP/UDP/MMTP config

#define TLV_REG_FRAMER0_SI_CTL          432 //0x6C0 framer0 Signal control word
#define TLV_REG_FRAMER1_SI_CTL          434 //0x6C8 framer1 Signal control word
#define TLV_REG_FRAMER3_SI_CTL          519 //0x81C framer2 Signal control word

#define TLV_DMEM_TLV_SI_CTL_WORD(idx)    ((volatile UINT32*)(UPTR)(DEMUX11_BASE + OFFSET_64BIT + 0xB10))[(idx)]



#define TLV_NTP_8K_SEL                  534 // 0x17858

/*NTP INT*/
#define TLV_REG_NTP0_INT_STATUS         364 // 0x175B0
#define TLV_REG_NTP0_INT_STATUS2        365 // 0x175b4
#define TLV_REG_NTP1_INT_STATUS         420 // 0x17690 
#define TLV_REG_NTP1_INT_STATUS2        421 // 0x17694
#define TLV_REG_NTP2_INT_STATUS         615 // 0x1799C
#define TLV_REG_NTP2_INT_STATUS2        616 // 0x179A0


#define TLV_REG_NTP0_VALUE_LOW          353 // 0x17584
#define TLV_REG_NTP0_VALUE_HIGH         354 // 0x17588
#define TLV_REG_NTP1_VALUE_LOW          381 // 0x175F4
#define TLV_REG_NTP1_VALUE_HIGH         382 // 0x175F8
#define TLV_REG_NTP2_VALUE_LOW          604 // 0x17970
#define TLV_REG_NTP2_VALUE_HIGH         605 // 0x17974

/*NTP STC0*/
#define TLV_NTP_STC0_CTRL               347 // 0x1756C
#define TLV_NTP_STC0_ERR_THRESHOLD      348 // 0x17570
#define TLV_NTP_STC0_FILTER_COFF0       349 // 0x17574          
#define TLV_NTP_STC0_FILTER_COFF1       350 // 0x17578          
#define TLV_NTP_STC0_FILTER_COFF2       351 // 0x1757c          
#define TLV_NTP_STC0_FILTER_COFF3       352 // 0x17580          

#define TLV_NTP_STC0_SNAP_LOW           355 // 0x1758c  STC SNAP [31: 0]
#define TLV_NTP_STC0_SNAP_HIGH          356 // 0x17590  STC SNAP [55:32]
#define TLV_NTP_STC0_DELTA_LOW          357 // 0x17594  NTP-STC low 32bit
#define TLV_NTP_STC0_DELTA_HIGH         358 // 0x17598  NTP-STC high 32bit
#define TLV_NTP_STC0_LOW                359 // 0x1759c  STC [31: 0]
#define TLV_NTP_STC0_HIGH               360 // 0x175a0  STC [55:32]

#define TLV_NTP_STC0_IIR_XN1            361 // 0x175a4
#define TLV_NTP_STC0_IIR_YN1            362 // 0x175a8
#define TLV_NTP_STC0_IIR_YN2            363 // 0x175ac

/*NTP STC1*/
#define TLV_NTP_STC1_CTRL               375 // 0x175DC
#define TLV_NTP_STC1_ERR_THRESHOLD      376 // 0x175E0
#define TLV_NTP_STC1_FILTER_COFF0       377 // 0x175E4          
#define TLV_NTP_STC1_FILTER_COFF1       378 // 0x175E8          
#define TLV_NTP_STC1_FILTER_COFF2       379 // 0x175EC          
#define TLV_NTP_STC1_FILTER_COFF3       380 // 0x175F0          

#define TLV_NTP_STC1_SNAP_LOW           383 // 0x175FC  STC SNAP [31: 0]
#define TLV_NTP_STC1_SNAP_HIGH          412 // 0x17670  STC SNAP [55:32]
#define TLV_NTP_STC1_DELTA_LOW          413 // 0x17674  NTP-STC low 32bit
#define TLV_NTP_STC1_DELTA_HIGH         414 // 0x17678  NTP-STC high 32bit
#define TLV_NTP_STC1_LOW                415 // 0x1767c  STC [31: 0]
#define TLV_NTP_STC1_HIGH               416 // 0x17680  STC [55:32]

#define TLV_NTP_STC1_IIR_XN1            417 // 0x17684
#define TLV_NTP_STC1_IIR_YN1            418 // 0x17688
#define TLV_NTP_STC1_IIR_YN2            419 // 0x1768c

/*NTP STC2*/
#define TLV_NTP_STC2_CTRL               598 // 0x17958
#define TLV_NTP_STC2_ERR_THRESHOLD      599 // 0x1795C
#define TLV_NTP_STC2_FILTER_COFF0       600 // 0x17960          
#define TLV_NTP_STC2_FILTER_COFF1       601 // 0x17964          
#define TLV_NTP_STC2_FILTER_COFF2       602 // 0x17968          
#define TLV_NTP_STC2_FILTER_COFF3       603 // 0x1796C          

#define TLV_NTP_STC2_SNAP_LOW           606 // 0x17978  STC SNAP [31: 0]
#define TLV_NTP_STC2_SNAP_HIGH          607 // 0x1797C  STC SNAP [56:32]
#define TLV_NTP_STC2_DELTA_LOW          608 // 0x17980  NTP-STC low 32bit
#define TLV_NTP_STC2_DELTA_HIGH         609 // 0x17984  NTP-STC high 32bit
#define TLV_NTP_STC2_LOW                610 // 0x17988  STC [31: 0]
#define TLV_NTP_STC2_HIGH               611 // 0x1798C  STC [55:32]

#define TLV_NTP_STC2_IIR_XN1            612 // 0x17990
#define TLV_NTP_STC2_IIR_YN1            613 // 0x17994
#define TLV_NTP_STC2_IIR_YN2            614 // 0x17998


/*
 *playback ip filter setting
**/
/***********Framer0 NTP CFG********/
#define TLV_REG_NTP0_IP_SRC_ADDR0       78 //(78,79,82,83)4 word 0x138 13C 148 14C  IP addr low to high
#define TLV_REG_NTP0_IP_SRC_ADDR1       79
#define TLV_REG_NTP0_IP_SRC_ADDR2       82
#define TLV_REG_NTP0_IP_SRC_ADDR3       83

#define TLV_REG_NTP0_IP_DST_ADDR0       47 //(47,54,55,56)4 word 0xBC D8 DC E0  IP addr low to high
#define TLV_REG_NTP0_IP_DST_ADDR1       54
#define TLV_REG_NTP0_IP_DST_ADDR2       55
#define TLV_REG_NTP0_IP_DST_ADDR3       56

#define TLV_REG_NTP0_UDP_PORT           57 //0xE4 bit[31:16] src port, bit[15:0] dst port

#define TLV_REG_FRAMER0_NTP_CTL         431 //0x6BC framer0 NTP control word

/***********Framer1 NTP CFG************/
#define TLV_REG_NTP1_IP_SRC_ADDR0       84 //(84,85,86,87)4 word 0x150 154 158 15C  IP addr low to high
#define TLV_REG_NTP1_IP_SRC_ADDR1       85
#define TLV_REG_NTP1_IP_SRC_ADDR2       86
#define TLV_REG_NTP1_IP_SRC_ADDR3       87

#define TLV_REG_NTP1_IP_DST_ADDR0       70 //(70,71,74,75)4 word 0x118 11C 128 12C  IP addr low to high
#define TLV_REG_NTP1_IP_DST_ADDR1       71
#define TLV_REG_NTP1_IP_DST_ADDR2       74
#define TLV_REG_NTP1_IP_DST_ADDR3       75

#define TLV_REG_NTP1_UDP_PORT           63 //0xFC bit[31:16] src port, bit[15:0] dst port

#define TLV_REG_FRAMER1_NTP_CTL         433 //0x6C4 framer0 NTP control word


/*******Framer0 MMTP IP UDP CFG   *******/
#define TLV_FRM0_IP0_SRC_ADDR0          34 //(34,35,36,37)4 word 0x88 8C 90 94  IP addr low to high
#define TLV_FRM0_IP0_SRC_ADDR1          35
#define TLV_FRM0_IP0_SRC_ADDR2          36
#define TLV_FRM0_IP0_SRC_ADDR3          37
#define TLV_FRM0_IP0_DST_ADDR0          41 //(41,42,43,44)4 word 0xA4 A8 AC B0  IP addr low to high
#define TLV_FRM0_IP0_DST_ADDR1          42
#define TLV_FRM0_IP0_DST_ADDR2          43
#define TLV_FRM0_IP0_DST_ADDR3          44
#define TLV_FRM0_IP0_UDP_PORT           45 //0xB4 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM0_IP1_SRC_ADDR0          100 //(100,101,102,103)4 word 0x190 194 198 19C  IP addr low to high
#define TLV_FRM0_IP1_SRC_ADDR1          101
#define TLV_FRM0_IP1_SRC_ADDR2          102
#define TLV_FRM0_IP1_SRC_ADDR3          103
#define TLV_FRM0_IP1_DST_ADDR0          104 //(104,105,106,107)4 word 0x1A0 1A4 1A8 1AC  IP addr low to high
#define TLV_FRM0_IP1_DST_ADDR1          105
#define TLV_FRM0_IP1_DST_ADDR2          106
#define TLV_FRM0_IP1_DST_ADDR3          107
#define TLV_FRM0_IP1_UDP_PORT           108 //0x1B0 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM0_IP2_SRC_ADDR0          109 //(109,110,111,116)4 word 0x1B4 1B8 1BC 1D0  IP addr low to high
#define TLV_FRM0_IP2_SRC_ADDR1          110
#define TLV_FRM0_IP2_SRC_ADDR2          111
#define TLV_FRM0_IP2_SRC_ADDR3          116
#define TLV_FRM0_IP2_DST_ADDR0          117 //(117,118,119,120)4 word 0x1D4 1D8 1DC 1E0  IP addr low to high
#define TLV_FRM0_IP2_DST_ADDR1          118
#define TLV_FRM0_IP2_DST_ADDR2          119
#define TLV_FRM0_IP2_DST_ADDR3          120
#define TLV_FRM0_IP2_UDP_PORT           121 //0x1E4 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM0_IP3_SRC_ADDR0          200 //(200,201,202,203)4 word 0x17320 324 328 32C  IP addr low to high
#define TLV_FRM0_IP3_SRC_ADDR1          201
#define TLV_FRM0_IP3_SRC_ADDR2          202
#define TLV_FRM0_IP3_SRC_ADDR3          203
#define TLV_FRM0_IP3_DST_ADDR0          204 //(204,205,206,207)4 word 0x17330 334 338 33C  IP addr low to high
#define TLV_FRM0_IP3_DST_ADDR1          205
#define TLV_FRM0_IP3_DST_ADDR2          206
#define TLV_FRM0_IP3_DST_ADDR3          207
#define TLV_FRM0_IP3_UDP_PORT           208 //0x17340 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM0_IP4_SRC_ADDR0          302 //(302,303,304,305)4 word 0x174B8 4BC 4C0 4C4  IP addr low to high
#define TLV_FRM0_IP4_SRC_ADDR1          303
#define TLV_FRM0_IP4_SRC_ADDR2          304
#define TLV_FRM0_IP4_SRC_ADDR3          305
#define TLV_FRM0_IP4_DST_ADDR0          306 //(306,307,308,309)4 word 0x174C8 4CC 4D0 4D4  IP addr low to high
#define TLV_FRM0_IP4_DST_ADDR1          307
#define TLV_FRM0_IP4_DST_ADDR2          308
#define TLV_FRM0_IP4_DST_ADDR3          309
#define TLV_FRM0_IP4_UDP_PORT           310 //0x174d8 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM0_IP5_SRC_ADDR0          311 //(311,312,313,314)4 word 0x174DC 4E0 4E4 4E8  IP addr low to high
#define TLV_FRM0_IP5_SRC_ADDR1          312
#define TLV_FRM0_IP5_SRC_ADDR2          313
#define TLV_FRM0_IP5_SRC_ADDR3          314
#define TLV_FRM0_IP5_DST_ADDR0          315 //(315,316,317,318)4 word 0x174EC 4F0 4F4 4F8  IP addr low to high
#define TLV_FRM0_IP5_DST_ADDR1          316
#define TLV_FRM0_IP5_DST_ADDR2          317
#define TLV_FRM0_IP5_DST_ADDR3          318
#define TLV_FRM0_IP5_UDP_PORT           319 //0x174FC bit[31:16] src port, bit[15:0] dst port


/*******Framer1 MMTP IP UDP CFG **********/
#define TLV_FRM1_IP0_SRC_ADDR0          58 //(58,59,60,61)4 word 0xE8 EC F0 F4  IP addr low to high
#define TLV_FRM1_IP0_SRC_ADDR1          59
#define TLV_FRM1_IP0_SRC_ADDR2          60
#define TLV_FRM1_IP0_SRC_ADDR3          61
#define TLV_FRM1_IP0_DST_ADDR0          66 //(66,67,68,69)4 word 0x108 10C 110 114  IP addr low to high
#define TLV_FRM1_IP0_DST_ADDR1          67
#define TLV_FRM1_IP0_DST_ADDR2          68
#define TLV_FRM1_IP0_DST_ADDR3          69
#define TLV_FRM1_IP0_UDP_PORT           62 //0xF8 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM1_IP1_SRC_ADDR0          122 //(122,123,124,125)4 word 0x1E8 1EC 1F0 1F4  IP addr low to high
#define TLV_FRM1_IP1_SRC_ADDR1          123
#define TLV_FRM1_IP1_SRC_ADDR2          124
#define TLV_FRM1_IP1_SRC_ADDR3          125
#define TLV_FRM1_IP1_DST_ADDR0          126 //(126,127,176,177)4 word 0x1F8 1FC 2C0 2C4  IP addr low to high
#define TLV_FRM1_IP1_DST_ADDR1          127
#define TLV_FRM1_IP1_DST_ADDR2          176
#define TLV_FRM1_IP1_DST_ADDR3          177
#define TLV_FRM1_IP1_UDP_PORT           178 //0x2C8 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM1_IP2_SRC_ADDR0          179 //(179,184,185,186)4 word 0x2CC 2E0 2E4 2E8  IP addr low to high
#define TLV_FRM1_IP2_SRC_ADDR1          184
#define TLV_FRM1_IP2_SRC_ADDR2          185
#define TLV_FRM1_IP2_SRC_ADDR3          186
#define TLV_FRM1_IP2_DST_ADDR0          187 //(187,196,197,198)4 word 0x2EC 310 314 318  IP addr low to high
#define TLV_FRM1_IP2_DST_ADDR1          196
#define TLV_FRM1_IP2_DST_ADDR2          197
#define TLV_FRM1_IP2_DST_ADDR3          198
#define TLV_FRM1_IP2_UDP_PORT           199 //0x31C bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM1_IP3_SRC_ADDR0          320 //(320,321,322,323)4 word 0x17500 504 508 50C  IP addr low to high
#define TLV_FRM1_IP3_SRC_ADDR1          321
#define TLV_FRM1_IP3_SRC_ADDR2          322
#define TLV_FRM1_IP3_SRC_ADDR3          323
#define TLV_FRM1_IP3_DST_ADDR0          324 //(324,325,326,327)4 word 0x17510 514 518 51C  IP addr low to high
#define TLV_FRM1_IP3_DST_ADDR1          325
#define TLV_FRM1_IP3_DST_ADDR2          326
#define TLV_FRM1_IP3_DST_ADDR3          327
#define TLV_FRM1_IP3_UDP_PORT           328 //0x17520 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM1_IP4_SRC_ADDR0          329 //(329,330,331,332)4 word 0x17524 528 52C 530  IP addr low to high
#define TLV_FRM1_IP4_SRC_ADDR1          330
#define TLV_FRM1_IP4_SRC_ADDR2          331
#define TLV_FRM1_IP4_SRC_ADDR3          332
#define TLV_FRM1_IP4_DST_ADDR0          333 //(333,334,335,336)4 word 0x17534 538 53C 540  IP addr low to high
#define TLV_FRM1_IP4_DST_ADDR1          334
#define TLV_FRM1_IP4_DST_ADDR2          335
#define TLV_FRM1_IP4_DST_ADDR3          336
#define TLV_FRM1_IP4_UDP_PORT           337 //0x17544 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM1_IP5_SRC_ADDR0          338 //(338,339,340,341)4 word 0x17548 54C 550 554  IP addr low to high
#define TLV_FRM1_IP5_SRC_ADDR1          339
#define TLV_FRM1_IP5_SRC_ADDR2          340
#define TLV_FRM1_IP5_SRC_ADDR3          341
#define TLV_FRM1_IP5_DST_ADDR0          342 //(342,343,344,345)4 word 0x17558 55C 560 564  IP addr low to high
#define TLV_FRM1_IP5_DST_ADDR1          343
#define TLV_FRM1_IP5_DST_ADDR2          344
#define TLV_FRM1_IP5_DST_ADDR3          345
#define TLV_FRM1_IP5_UDP_PORT           346 //0x17568 bit[31:16] src port, bit[15:0] dst port

/*******Framer2 MMTP IP UDP CFG **********/
#define TLV_FRM3_IP0_SRC_ADDR0          448 //(448,449,450,451)4 word 0x700 704 708 70C  IP addr low to high
#define TLV_FRM3_IP0_SRC_ADDR1          449
#define TLV_FRM3_IP0_SRC_ADDR2          450
#define TLV_FRM3_IP0_SRC_ADDR3          451
#define TLV_FRM3_IP0_DST_ADDR0          452 //(452,453,454,455)4 word 0x710 714 718 71C  IP addr low to high
#define TLV_FRM3_IP0_DST_ADDR1          453
#define TLV_FRM3_IP0_DST_ADDR2          454
#define TLV_FRM3_IP0_DST_ADDR3          455
#define TLV_FRM3_IP0_UDP_PORT           456 //0x720 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM3_IP1_SRC_ADDR0          457 //(457,458,459,460)4 word 0x724 728 72C 730  IP addr low to high
#define TLV_FRM3_IP1_SRC_ADDR1          458
#define TLV_FRM3_IP1_SRC_ADDR2          459
#define TLV_FRM3_IP1_SRC_ADDR3          460
#define TLV_FRM3_IP1_DST_ADDR0          461 //(461,462,463,464)4 word 0x734 738 73C 740  IP addr low to high
#define TLV_FRM3_IP1_DST_ADDR1          462
#define TLV_FRM3_IP1_DST_ADDR2          463
#define TLV_FRM3_IP1_DST_ADDR3          464
#define TLV_FRM3_IP1_UDP_PORT           465 //0x744 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM3_IP2_SRC_ADDR0          466 //(466,467,468,469)4 word 0x748 74C 750 754  IP addr low to high
#define TLV_FRM3_IP2_SRC_ADDR1          467
#define TLV_FRM3_IP2_SRC_ADDR2          468
#define TLV_FRM3_IP2_SRC_ADDR3          469
#define TLV_FRM3_IP2_DST_ADDR0          470 //(470,471,472,473)4 word 0x758 75C 760 764  IP addr low to high
#define TLV_FRM3_IP2_DST_ADDR1          471
#define TLV_FRM3_IP2_DST_ADDR2          472
#define TLV_FRM3_IP2_DST_ADDR3          473
#define TLV_FRM3_IP2_UDP_PORT           474 //0x768 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM3_IP3_SRC_ADDR0          475 //(475,476,477,478)4 word 0x76C 770 774 778  IP addr low to high
#define TLV_FRM3_IP3_SRC_ADDR1          476
#define TLV_FRM3_IP3_SRC_ADDR2          477
#define TLV_FRM3_IP3_SRC_ADDR3          478
#define TLV_FRM3_IP3_DST_ADDR0          479 //(479,480,481,482)4 word 0x77C 780 784 788  IP addr low to high
#define TLV_FRM3_IP3_DST_ADDR1          480
#define TLV_FRM3_IP3_DST_ADDR2          481
#define TLV_FRM3_IP3_DST_ADDR3          482
#define TLV_FRM3_IP3_UDP_PORT           483 //0x78C bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM3_IP4_SRC_ADDR0          484 //(484,485,586,487)4 word 0x790 794 798 79C  IP addr low to high
#define TLV_FRM3_IP4_SRC_ADDR1          485
#define TLV_FRM3_IP4_SRC_ADDR2          486
#define TLV_FRM3_IP4_SRC_ADDR3          487
#define TLV_FRM3_IP4_DST_ADDR0          488 //(488,489,490,491)4 word 0x7A0 7A4 7A8 7AC  IP addr low to high
#define TLV_FRM3_IP4_DST_ADDR1          489
#define TLV_FRM3_IP4_DST_ADDR2          490
#define TLV_FRM3_IP4_DST_ADDR3          491
#define TLV_FRM3_IP4_UDP_PORT           492 //0x7B0 bit[31:16] src port, bit[15:0] dst port

#define TLV_FRM3_IP5_SRC_ADDR0          493 //(493,494,495,496)4 word 0x7B4 7B8 7BC 7C0  IP addr low to high
#define TLV_FRM3_IP5_SRC_ADDR1          494
#define TLV_FRM3_IP5_SRC_ADDR2          495
#define TLV_FRM3_IP5_SRC_ADDR3          496
#define TLV_FRM3_IP5_DST_ADDR0          497 //(497,498,499,500)4 word 0x7C4 7C8 7CC 7D0  IP addr low to high
#define TLV_FRM3_IP5_DST_ADDR1          498
#define TLV_FRM3_IP5_DST_ADDR2          499
#define TLV_FRM3_IP5_DST_ADDR3          500
#define TLV_FRM3_IP5_UDP_PORT           501 //0x7D4 bit[31:16] src port, bit[15:0] dst port


/*CID FIlter config*/
#define TLV_REG_FRM0_CID0_CID1          437 //176D4
#define TLV_REG_FRM0_CID2_CID3          438 
#define TLV_REG_FRM0_CID4_CID5          439

#define TLV_REG_FRM1_CID0_CID1          440 //176E0
#define TLV_REG_FRM1_CID2_CID3          441 
#define TLV_REG_FRM1_CID4_CID5          442

#define TLV_REG_FRM3_CID0_CID1          520 //17820
#define TLV_REG_FRM3_CID2_CID3          521 
#define TLV_REG_FRM3_CID4_CID5          522

#define TLV_REG_FRM0_CID_INT            443 //176EC
#define TLV_REG_FRM1_CID_INT            444
#define TLV_REG_FRM3_CID_INT            523 //1782C clear int
#define TLV_REG_FRM3_CID_INT_R          524 //17830 read

/*DMEM*/
#define TLV_PLAYBACK_GBL_SIZE       (26)   // 104 bytes

#ifdef CC_MT5895
#define TLV_PLAYBACK_GBL_BASE       (DEMUX11_BASE + 0xA3C)  //0x57A3C
#else
#define TLV_PLAYBACK_GBL_BASE       (DEMUX11_BASE + 0x8d8)  //0x578d8
#endif

/*
 *Recording ip filter setting
**/
/*******Framer0 MMTP IP UDP CFG   *******/


/*******Framer1 MMTP IP UDP CFG **********/


#define MPU_TIME_INFO_UNIT_COUNT  (3000)
#define MPU_PTSDTS_TABLE_MAX_COUNT (3000)

#define TIMESTAMP_TABLE_NUM       4 //(video 1 + audio 3) 

#define TLV_REG_FRAMER0_TLV_DEBUG2      92 //0x170 framer0 debug word
#define TLV_REG_FRAMER1_TLV_DEBUG2      98 //0x188 framer1 debug word
#define TLV_REG_FRAMER3_TLV_DEBUG2      527 //0x83C framer3 debug word


typedef struct
{
    UINT32 u4MpuSeqNum;
    UINT64 u8PresentationTime;
    UPTR u4TlvAddr;  // for recording
    UINT64 u8MptAddrRingCounter;
}MPU_TIMESTAMP_DESCRTPTOR_T;

typedef struct
{
    UINT16 u2PID;
    UINT16 u2ReadIdx;
    UINT16 u2WriteIdx;
    UINT32 u4LastSeqNum;
    MPU_TIMESTAMP_DESCRTPTOR_T arTimeInfo[MPU_TIME_INFO_UNIT_COUNT];
}MPU_TIMESTAMP_DESCRTPTOR_TABLE_T;

typedef struct
{
    UINT32 u4MpuSeqNum;
    UINT8 u1LeapIndicator;
    UINT32 u4Timescale;
    UINT16 u2MpuDecTimeOffset;
    UINT16 u2DefaultPtsOffset;
    UINT8 u1NumOfAu;
    UINT16 au2DtsPtsOffset[256];
}MPU_EXT_TIMESTAMP_DESCRTPTOR_T;

typedef struct
{
    UINT16 u2PID;
    UINT16 u2ReadIdx;
    UINT16 u2WriteIdx;
    UINT32 u4LastSeqNum;
    MPU_EXT_TIMESTAMP_DESCRTPTOR_T arExtTimeInfo[MPU_TIME_INFO_UNIT_COUNT];
}MPU_EXT_TIMESTAMP_DESCRTPTOR_TABLE_T;


typedef struct
{
    UINT32 u4MpuSeqNum;
    UINT64 u8Pts;
    UINT64 u8Dts;
    UINT64 u8MpuPresentationTime;
    UPTR u4TlvAddr; // for recording
    UINT64 u8MptAddrRingCounter;
}MPU_PTSDTS_INFO_T;

typedef struct
{
    UINT16 u2PID;
    UINT16 u2ReadIdx;
    UINT16 u2WriteIdx;
    MPU_PTSDTS_INFO_T arPtsDtsInfo[MPU_PTSDTS_TABLE_MAX_COUNT];
}MPU_PTSDTS_INFO_TABLE_T;

typedef struct
{
    UINT8 u1TlvIdx;
    UINT16 u2PID;
    BOOL fgVaild;
    BOOL fgFvr;
}TIMESTAMP_TABLE_T;


EXTERN VOID _TLV_EnablePtsLog(BOOL fgEnable);
EXTERN void _TLV_SetIndicator(UINT8 u1Indicator);
EXTERN void _TLV_EnableLeapSecondWorkAround(BOOL fgEnable, UINT8 u1Indicator);
EXTERN void _TLV_Int(UINT32 u4Status);
EXTERN BOOL _TLV_DispatchFTuPInterrupt(UINT8 u1Type);

EXTERN void _TLV_SetFramerModeEx(UINT8 u1Framer, DMX_FRAMER_MODE_T eMode,
                        BOOL fgBypassMixSync, BOOL fgPosEdge, BOOL fgEnable, BOOL fgBypassIpFilter, BOOL fgBypassPidFilter);

EXTERN BOOL _TLV_SetFrontEndEx(UINT8 u1Idx, DMX_FRONTEND_T eFrontEnd);
EXTERN BOOL _TLV_SetTransmissionMode(UINT8 u1TsIdx, DMX_FRAMER_MODE_T eMode);

EXTERN BOOL _TLVSetIpUdpFilter(UINT8 u1FilterIdx, const DMX_TLV_IP_FILTER_T *prIpUdpFilter, BOOL fgFvr);

EXTERN BOOL _TLV_SetDbmBypassMode(UINT8 u1TsIndex, UINT8 u1PacketSize,	BOOL fgSteerToFTuP, BOOL fgReset);

/*PSI*/
EXTERN BOOL _TLV_InitPSIHandler(void);


/*ISR*/
EXTERN BOOL _TLV_AddPSI(DMX_PSI_MSG_T *prPSI);


/*tlv_init.c*/
EXTERN BOOL _TLV_NTP_STC_CLK_Init(void);
EXTERN BOOL _TLV_Init(void);
EXTERN BOOL _TLV_SetStcId(UINT8 u1TlvIdx, UINT8 u1StcId);
EXTERN BOOL _TLV_SelNtpMode(TLV_NTP_MODE_T eNtpMode);

EXTERN BOOL _TLV_ResetLeapIndicator(UINT8 u1TlvIdx, UINT8 u1StcId);


//EXTERN PID_STRUCT_T* _TLV_GetPidStruct(UINT32 u4PidIndex);

EXTERN BOOL _TLV_PSI_GetBuffer(UINT8 u1Pidx, UINT8 u1SerialNumber, UPTR u4FrameAddr,
                                USIZE u4SkipSize, USIZE u4CopySize, UCHAR* pu1Dest);
EXTERN BOOL _TLV_PSI_UnlockBuffer(UINT8 u1Pidx, UINT8 u1SerialNumber, USIZE u4Size, UPTR u4FrameAddr);
EXTERN BOOL _TLV_PSI_FlushBuffer(UINT8 u1Pidx);

EXTERN BOOL _TLV_MFU_GetBuffer(UINT8 u1Pidx, UINT8 u1SerialNumber, UPTR u4FrameAddr,
                                USIZE u4SkipSize, USIZE u4CopySize, UCHAR* pu1Dest);
EXTERN BOOL _TLV_MFU_UnlockBuffer(UINT8 u1Pidx, UINT8 u1SerialNumber, USIZE u4Size, UPTR u4FrameAddr);
EXTERN BOOL _TLV_MFU_FlushBuffer(UINT8 u1Pidx);

/*tlv_mulmm_api.c*/
EXTERN UINT8 _TLV_MUL_GetAvailableInst(DMX_TLV_CONN_TYPE_T eConnType);
EXTERN UINT8 _TLV_MUL_GetAvailablePidx(UINT8 u1Inst);
EXTERN UINT8 _TLV_MUL_GetAvailableFilter(UINT8 u1Inst);
EXTERN UINT8 _TLV_MUL_GetTsIdx(UINT8 u1Inst);

EXTERN BOOL _TLV_MUL_MoveData(UINT8 u1Inst, DMX_MM_DATA_T *prData);
EXTERN BOOL _TLV_MUL_MoveDataEx(UINT8 u1Inst, DMX_MM_DATA_T *prData, BOOL fgBypassMixSync, BOOL fgBypassIpFilter, BOOL fgBypassPidFilter);

EXTERN BOOL _TLV_MUL_FreeInst(UINT8 u1Inst);
EXTERN BOOL _TLV_MUL_FreePidx(UINT8 u1Pidx);
EXTERN BOOL _TLV_MUL_FreeFilter(UINT8 u1FilterIndex);


/*tlv_api.c*/
EXTERN BOOL _TLV_SetPid(UINT8 u1Pidx, UINT32 u4Flags, const TLV_PID_T* prPid);
EXTERN BOOL _TLV_FreePid(UINT8 u1Pidx);
//EXTERN BOOL _TLV_SetSI(UINT8 u1Pidx,  const DMX_TLV_IP_FILTER_T *prIpUdpFilter);

EXTERN BOOL _TLV_GetPidFifoInfo(UINT8 u1Pidx, UPTR *pu4BufStart, UPTR *pu4BufEnd, UPTR *pu4Rp, UPTR *pu4Wp, UINT32 *pu4DataSize);
EXTERN BOOL _TLV_UpdateReadPointer(UINT8 u1Pidx, UPTR u4Rp, UPTR u4FrameAddr);

EXTERN BOOL _TLV_FlushPidBuffer(UINT8 u1Pidx);
EXTERN BOOL _TLV_PidIndexTable_Set(UINT8 u1Pidx, UINT32 u4PidIndexTable);

/*tlv pts index table build functions*/
EXTERN UINT8 _Tlv_AllocTimestampTableIdx(UINT8 u1TlvIdx, UINT16 u2PID, BOOL fgPvr);
EXTERN BOOL _Tlv_FreeTimestampTableIdx(UINT8 u1TableIdx);
EXTERN UINT8 _Tlv_GetTimestampTableIdx(UINT8 u1TlvIdx, UINT16 u2PID, BOOL fgPvr);

EXTERN MPU_TIMESTAMP_DESCRTPTOR_TABLE_T * _TLV_GetTimeInfoTable(UINT8 u1TableIdx);
EXTERN MPU_EXT_TIMESTAMP_DESCRTPTOR_TABLE_T * _TLV_GetExtTimeInfoTable(UINT8 u1TableIdx);
EXTERN MPU_PTSDTS_INFO_TABLE_T * _TLV_GetPtsDtsInfoTable(UINT8 u1TableIdx);

EXTERN BOOL _Tlv_GetAudioPts(UINT8 u1TableIdx, UINT32 u4SeqNum,  DMX_AUDIO_PES_T *prPes);
EXTERN BOOL _Tlv_GetVideoPts(UINT8 u1TableIdx, UINT32 u4FrameType, UINT32 u4SeqNum, DMX_PES_MSG_T *prPes);
EXTERN BOOL _Tlv_Fvr_GetVideoPts(UINT8 u1TableIdx, UINT32 u4FrameType, UINT32 u4SeqNum,  
                          UINT64 *pu8Dts, UINT64 *pu8Pts, UINT64 *pu8PresentationTime, UPTR *pu4Addr, UINT64 *pu8RingCounter);

EXTERN BOOL _TLV_BuildPtsDtsTable(UINT8 u1TableIdx);
EXTERN BOOL _TlvMpuTimestampDescriptorParse(UINT8 u1TableIdx, UINT8 *pData, UINT8 u1Len, UPTR u4TlvAddr, UINT64 u8MptAddrRingCounter); //u4TlvAddr use for recording
EXTERN BOOL _TlvMpuExtTimestampDescriptorParse(UINT8 u1TableIdx, UINT8 *pData, UINT8 u1Len);
EXTERN UINT8 _TLV_MPT_GetBytes(UINT8** ppu1StartAddr, UINT8 *pu1buf, USIZE u4Size, UPTR u4EndAddr, USIZE u4BufLen);
EXTERN BOOL _TlvMptParser(UINT8 u1TlvIdx, UPTR u4SecRp, UINT32 u4SecLen, UPTR u4BufEnd, UINT32 u4BufLen, BOOL fgFvr);
EXTERN BOOL _TLV_ResetPtsInfoTable(UINT8 u1TableIdx);
EXTERN BOOL _TLV_Pts_Init(VOID);
EXTERN BOOL _TLV_ResetPtsLeapIndicator(UINT8 u1TlvIdx);

EXTERN BOOL _TLV_FVR_Init(void);
EXTERN BOOL _TLV_FVR_Start(UINT8 u1Idx);
EXTERN BOOL _TLV_FVR_Stop(UINT8 u1Idx);

EXTERN BOOL _TLV_FVR_DispatchuPInterrupt(UINT32 u4Status, UINT32 u4Status2);
EXTERN BOOL _TLV_FVR_SendPacketCountEvent(TLV_FVR_NOTIFY_INFO_T *prInfo);
EXTERN BOOL _TLV_FVR_SendPictureEvent(TLV_FVR_NOTIFY_INFO_T *prPicInfo);
EXTERN BOOL _TLV_FVR_SendMptEvent(UINT8 u1Pidx);

/*tlv_fvr_api.c*/
EXTERN BOOL _TLV_FVR_SetGBL(UINT8 u1Idx, UINT32 u4Flags, const FVR_GBL_T* prGBL);
EXTERN BOOL _TLV_FVR_GetGBL(UINT8 u1Idx, UINT32 u4Flags, FVR_GBL_T *prGBL);

EXTERN BOOL _TLV_FVR_SetPid(UINT8 u1Pidx, UINT32 u4Flags, const FVR_PID_T* prPid);
EXTERN BOOL _TLV_FVR_GetPid(UINT8 u1Pidx, UINT32 u4Flags, FVR_PID_T *prPid);
EXTERN BOOL _TLV_FVR_FreePid(UINT8 u1Pidx);
EXTERN BOOL _TLV_FVR_SetVideoTypeByPidx(UINT8 u1Pidx, FVR_VIDEO_TYPE_T eVideoType);


EXTERN BOOL _TLV_FVR_SetNtpIpFilter(UINT8 u1TsIdx,  UINT8 u1Pidx, const DMX_TLV_IP_FILTER_T *prIpFilter);

EXTERN BOOL _TLV_FVR_GetBufferInfo(UINT8 u1Idx, UPTR *pu4BufStart, UPTR *pu4BufEnd, UPTR *pu4Rp, UPTR *pu4Wp, UINT32 *pu4DataSize);
EXTERN BOOL _TLV_FVR_UpdateReadPointer(UINT8 u1Idx, UPTR u4Rp);
EXTERN BOOL _TLV_FVR_UpdateWritePointer(UINT8 u1Idx, UPTR u4Rp);
EXTERN BOOL _TLV_FVR_UnlockBuffer(UINT8 u1Idx, UPTR u4Addr, USIZE u4Size);
EXTERN BOOL _TLV_FVR_FlushBuffer(UINT8 u1Idx);
EXTERN BOOL _TLV_FVR_PidIndexTable_Set(UINT8 u1Pidx, UINT32 u4PidIndexTable);

/*tlv_ntp.c*/
EXTERN VOID _TLV_NTP_Int(UINT32 u4Status);

/*tlv_app_handler.c*/
EXTERN BOOL _TLV_APP_Init(void);
EXTERN BOOL _TLV_Add_AppData(UINT8 u1Pidx, UPTR u4Wp);
EXTERN BOOL _TLV_APP_StartFilter(UINT8 u1Pidx, UINT32 u4TimeDelt, UINT32 u4Count, 
                                UINT32 u4SeqNum, TLV_APPDATA_FILTER_MODE_T eMode);
EXTERN BOOL _TLV_APP_StopFilter(UINT8 u1Pidx);

/*tlv_ip_filter.c*/
EXTERN BOOL _TLV_InitIpFilter(void);
EXTERN VOID _TLV_CID_Int(UINT32 u4Status);
EXTERN VOID _TLV_CID_Int_uCode(UINT8 u1Pidx, BOOL fgPvr, UINT16 u2Cid);
EXTERN BOOL _TLV_FreeVirIpFilterIdx(UINT8 u1VirFilterIdx);
EXTERN BOOL _TLV_SetIpFilter(UINT8 u1VirFilterIdx, const DMX_TLV_IP_FILTER_T *prIpFilter, BOOL fgFvr);
EXTERN BOOL _TLV_SetNtpIpFilter(UINT8 u1TlvIdx, UINT8 u1Pidx, const DMX_TLV_IP_FILTER_T *prIpFilter, BOOL fgPvr);

EXTERN UINT8 _TLV_GetAvailableVirIpFilterIdx(UINT8 u1TlvIdx);
EXTERN UINT8 _TLV_GetPhyIpFilterIdxByVirIdx(UINT8 u1VirFilterIdx);

EXTERN BOOL _TLV_GetPhyIpInfo(UINT8 u1TlvIdx, UINT8 u1PhyFilterIdx,  DMX_TLV_IP_FILTER_T *prIpFilter);
EXTERN BOOL _TLV_GetVirIpInfo(UINT8 u1VirFilterIdx,  DMX_TLV_IP_FILTER_T *prIpFilter);
EXTERN BOOL _TLV_Update_InputType(UINT8 u1TlvIdx, DMX_FRONTEND_T eFrontEnd);

#endif  // DMX_H
