/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _HW_HDMI2P1_MAC_H_
#define _HW_HDMI2P1_MAC_H_

#define IO_HDMI2P1_MAC_BASE 0x600000
#define HDMI2P1_MAC_BASE (IO_VIRT + IO_HDMI2P1_MAC_BASE)

#define HD21MAC_CFG_0404_VDO_PROC (HDMI2P1_MAC_BASE + 0x404)
    #define HD21MAC_CFG_0404_VDO_PROC_REG_VSYNC_INIT_TIMING_SEL_P0 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0404_VDO_PROC_REG_VSYNC_INIT_NUM_P0 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_0404_VDO_PROC_REG_CLK_EN_P0 Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_0404_VDO_PROC_REG_CLK_SW_MD_EN_P0 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_0404_VDO_PROC_REG_CLK_DB_EN_P0 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_0404_VDO_PROC_REG_ALL_CLK_EN_P0 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0404_VDO_PROC_REG_SW_RST_P0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0408_VDO_PROC (HDMI2P1_MAC_BASE + 0x408)
    #define HD21MAC_CFG_0408_VDO_PROC_REG_420TO422_FSM_STATE_P0 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_420TO422_BYPASS_P0 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_420TO422_BLK_FULL_RANGE_P0 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_420TO422_PIX_SEL_P0 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_420TO422_FSM_RST_P0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_VSYNC_CLEAR_MODE_P0 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_CBCR_SWAP_P0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_SRC_YC422_P0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_DE_POL_P0 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_VSYNC_POL_P0 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0408_VDO_PROC_REG_HSYNC_POL_P0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_040C_VDO_PROC (HDMI2P1_MAC_BASE + 0x40C)
    #define HD21MAC_CFG_040C_VDO_PROC_REG_DE_TOTAL_STABLE_P0 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_040C_VDO_PROC_REG_DE_TOTAL_P0 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_0410_VDO_PROC (HDMI2P1_MAC_BASE + 0x410)
    #define HD21MAC_CFG_0410_VDO_PROC_REG_HTOTAL_STABLE_P0 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0410_VDO_PROC_REG_HTOTAL_P0 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_0414_VDO_PROC (HDMI2P1_MAC_BASE + 0x414)
    #define HD21MAC_CFG_0414_VDO_PROC_REG_FIFO_RD_PTR_P0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0414_VDO_PROC_REG_FIFO_WR_PTR_P0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0418_VDO_PROC (HDMI2P1_MAC_BASE + 0x418)
    #define HD21MAC_CFG_0418_VDO_PROC_REG_VFDE_POL_P0 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_HDE_POL_P0 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_MUTE_SEL_P0 Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_PSEUDO_STOP_P0 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_OUT_TIMING_SEL_P0 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_OUT_PORT_SWAP_P0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_1P_OUT_EN_P0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_12BTO10B_TRUNC_EN_P0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_12BTO10B_DITH_EN_P0 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_FAKE444_FORMAT_P0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_422TO444_MD_P0 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_0418_VDO_PROC_REG_FINAL_LINE_MODE_P0 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_041C_VDO_PROC (HDMI2P1_MAC_BASE + 0x41C)
    #define HD21MAC_CFG_041C_VDO_PROC_REG_GB_SIZE_P0 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_0420_VDO_PROC (HDMI2P1_MAC_BASE + 0x420)
    #define HD21MAC_CFG_0420_VDO_PROC_REG_DE_FORWARD_P0 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_0424_VDO_PROC (HDMI2P1_MAC_BASE + 0x424)
    #define HD21MAC_CFG_0424_VDO_PROC_REG_DE_LEN_SW_MD_P0 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0424_VDO_PROC_REG_DE_LEN_P0 Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0428_VDO_PROC (HDMI2P1_MAC_BASE + 0x428)
    #define HD21MAC_CFG_0428_VDO_PROC_REG_OUT_CLK_P0_DIV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_0428_VDO_PROC_REG_INTER_CLK_P0_DIV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_042C_VDO_PROC (HDMI2P1_MAC_BASE + 0x42C)
    #define HD21MAC_CFG_042C_VDO_PROC_REG_TMDS_CRC_ALG_SEL_R_P0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_042C_VDO_PROC_REG_CRC_CLR_R_P0 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_042C_VDO_PROC_REG_CRC_START_R_P0 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_042C_VDO_PROC_REG_CRC_MODE_R_P0 Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_042C_VDO_PROC_REG_TMDS_CRC_ALG_SEL_L_P0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_042C_VDO_PROC_REG_CRC_CLR_L_P0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_042C_VDO_PROC_REG_CRC_START_L_P0 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_042C_VDO_PROC_REG_CRC_MODE_L_P0 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_0430_VDO_PROC (HDMI2P1_MAC_BASE + 0x430)
    #define HD21MAC_CFG_0430_VDO_PROC_REG_STA_CRC_OUT_L_P0_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0434_VDO_PROC (HDMI2P1_MAC_BASE + 0x434)
    #define HD21MAC_CFG_0434_VDO_PROC_REG_STA_CRC_FAIL_L_P0 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0434_VDO_PROC_REG_STA_CRC_RDY_L_P0 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0434_VDO_PROC_REG_STA_CRC_OUT_L_P0_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0438_VDO_PROC (HDMI2P1_MAC_BASE + 0x438)
    #define HD21MAC_CFG_0438_VDO_PROC_REG_STA_CRC_OUT_R_P0_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_043C_VDO_PROC (HDMI2P1_MAC_BASE + 0x43C)
    #define HD21MAC_CFG_043C_VDO_PROC_REG_STA_CRC_FAIL_R_P0 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_043C_VDO_PROC_REG_STA_CRC_RDY_R_P0 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_043C_VDO_PROC_REG_STA_CRC_OUT_R_P0_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0440_VDO_PROC (HDMI2P1_MAC_BASE + 0x440)
    #define HD21MAC_CFG_0440_VDO_PROC_CLK_DIV_EN_P0 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0440_VDO_PROC_PATH_EN_P0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_04C4_VDO_PROC (HDMI2P1_MAC_BASE + 0x4C4)
    #define HD21MAC_CFG_04C4_VDO_PROC_REG_VSYNC_INIT_TIMING_SEL_P1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_04C4_VDO_PROC_REG_VSYNC_INIT_NUM_P1 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_04C4_VDO_PROC_REG_CLK_EN_P1 Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_04C4_VDO_PROC_REG_CLK_SW_MD_EN_P1 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_04C4_VDO_PROC_REG_CLK_DB_EN_P1 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_04C4_VDO_PROC_REG_ALL_CLK_EN_P1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_04C4_VDO_PROC_REG_SW_RST_P1 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_04C8_VDO_PROC (HDMI2P1_MAC_BASE + 0x4C8)
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_420TO422_FSM_STATE_P1 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_420TO422_BYPASS_P1 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_420TO422_BLK_FULL_RANGE_P1 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_420TO422_PIX_SEL_P1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_420TO422_FSM_RST_P1 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_VSYNC_CLEAR_MODE_P1 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_CBCR_SWAP_P1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_SRC_YC422_P1 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_DE_POL_P1 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_VSYNC_POL_P1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_04C8_VDO_PROC_REG_HSYNC_POL_P1 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_04CC_VDO_PROC (HDMI2P1_MAC_BASE + 0x4CC)
    #define HD21MAC_CFG_04CC_VDO_PROC_REG_DE_TOTAL_STABLE_P1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_04CC_VDO_PROC_REG_DE_TOTAL_P1 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_04D0_VDO_PROC (HDMI2P1_MAC_BASE + 0x4D0)
    #define HD21MAC_CFG_04D0_VDO_PROC_REG_HTOTAL_STABLE_P1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_04D0_VDO_PROC_REG_HTOTAL_P1 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_04D4_VDO_PROC (HDMI2P1_MAC_BASE + 0x4D4)
    #define HD21MAC_CFG_04D4_VDO_PROC_REG_FIFO_RD_PTR_P1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_04D4_VDO_PROC_REG_FIFO_WR_PTR_P1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_04D8_VDO_PROC (HDMI2P1_MAC_BASE + 0x4D8)
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_VFDE_POL_P1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_HDE_POL_P1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_MUTE_SEL_P1 Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_PSEUDO_STOP_P1 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_OUT_TIMING_SEL_P1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_OUT_PORT_SWAP_P1 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_1P_OUT_EN_P1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_12BTO10B_TRUNC_EN_P1 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_12BTO10B_DITH_EN_P1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_FAKE444_FORMAT_P1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_422TO444_MD_P1 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_04D8_VDO_PROC_REG_FINAL_LINE_MODE_P1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_04DC_VDO_PROC (HDMI2P1_MAC_BASE + 0x4DC)
    #define HD21MAC_CFG_04DC_VDO_PROC_REG_GB_SIZE_P1 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_04E0_VDO_PROC (HDMI2P1_MAC_BASE + 0x4E0)
    #define HD21MAC_CFG_04E0_VDO_PROC_REG_DE_FORWARD_P1 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_04E4_VDO_PROC (HDMI2P1_MAC_BASE + 0x4E4)
    #define HD21MAC_CFG_04E4_VDO_PROC_REG_DE_LEN_SW_MD_P1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_04E4_VDO_PROC_REG_DE_LEN_P1 Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_04E8_VDO_PROC (HDMI2P1_MAC_BASE + 0x4E8)
    #define HD21MAC_CFG_04E8_VDO_PROC_REG_OUT_CLK_P1_DIV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_04E8_VDO_PROC_REG_INTER_CLK_P1_DIV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_04EC_VDO_PROC (HDMI2P1_MAC_BASE + 0x4EC)
    #define HD21MAC_CFG_04EC_VDO_PROC_REG_TMDS_CRC_ALG_SEL_R_P1 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_04EC_VDO_PROC_REG_CRC_CLR_R_P1 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_04EC_VDO_PROC_REG_CRC_START_R_P1 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_04EC_VDO_PROC_REG_CRC_MODE_R_P1 Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_04EC_VDO_PROC_REG_TMDS_CRC_ALG_SEL_L_P1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_04EC_VDO_PROC_REG_CRC_CLR_L_P1 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_04EC_VDO_PROC_REG_CRC_START_L_P1 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_04EC_VDO_PROC_REG_CRC_MODE_L_P1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_04F0_VDO_PROC (HDMI2P1_MAC_BASE + 0x4F0)
    #define HD21MAC_CFG_04F0_VDO_PROC_REG_STA_CRC_OUT_L_P1_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_04F4_VDO_PROC (HDMI2P1_MAC_BASE + 0x4F4)
    #define HD21MAC_CFG_04F4_VDO_PROC_REG_STA_CRC_FAIL_L_P1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_04F4_VDO_PROC_REG_STA_CRC_RDY_L_P1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_04F4_VDO_PROC_REG_STA_CRC_OUT_L_P1_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_04F8_VDO_PROC (HDMI2P1_MAC_BASE + 0x4F8)
    #define HD21MAC_CFG_04F8_VDO_PROC_REG_STA_CRC_OUT_R_P1_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_04FC_VDO_PROC (HDMI2P1_MAC_BASE + 0x4FC)
    #define HD21MAC_CFG_04FC_VDO_PROC_REG_STA_CRC_FAIL_R_P1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_04FC_VDO_PROC_REG_STA_CRC_RDY_R_P1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_04FC_VDO_PROC_REG_STA_CRC_OUT_R_P1_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0500_VDO_PROC (HDMI2P1_MAC_BASE + 0x500)
    #define HD21MAC_CFG_0500_VDO_PROC_CLK_DIV_EN_P1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0500_VDO_PROC_PATH_EN_P1 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0580_VDO_PROC (HDMI2P1_MAC_BASE + 0x580)
    #define HD21MAC_CFG_0580_VDO_PROC_REG_DMA_ST_ADDR0_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0584_VDO_PROC (HDMI2P1_MAC_BASE + 0x584)
    #define HD21MAC_CFG_0584_VDO_PROC_REG_DMA_ST_ADDR0_1 Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0588_VDO_PROC (HDMI2P1_MAC_BASE + 0x588)
    #define HD21MAC_CFG_0588_VDO_PROC_REG_DMA_SIZE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_058C_VDO_PROC (HDMI2P1_MAC_BASE + 0x58C)
    #define HD21MAC_CFG_058C_VDO_PROC_REG_DMA_RESET Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_058C_VDO_PROC_REG_DMA_DEBUG_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_058C_VDO_PROC_REG_DMA_WBE_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_058C_VDO_PROC_REG_DMA_TEST_MODE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_058C_VDO_PROC_REG_DMA_SEL_DVI Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_058C_VDO_PROC_REG_DMA_START Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_058C_VDO_PROC_REG_DMA_WPRIORITY Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_058C_VDO_PROC_REG_DMA_THRESHOLD Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_0590_VDO_PROC (HDMI2P1_MAC_BASE + 0x590)
    #define HD21MAC_CFG_0590_VDO_PROC_REG_DMA_DEBUG_PORT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0594_VDO_PROC (HDMI2P1_MAC_BASE + 0x594)
    #define HD21MAC_CFG_0594_VDO_PROC_REG_DMA_DEBUG_PORT_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0598_VDO_PROC (HDMI2P1_MAC_BASE + 0x598)
    #define HD21MAC_CFG_0598_VDO_PROC_REG_EMP_LAST_VLD_BUF_IDX Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_0598_VDO_PROC_REG_EMP_LAST_FRAME_IS_EMPTY Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0598_VDO_PROC_REG_DMA_BIST_FAIL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0598_VDO_PROC_REG_FIFO_OVER_WRITE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0598_VDO_PROC_REG_DMA_DONE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_059C_VDO_PROC (HDMI2P1_MAC_BASE + 0x59C)
    #define HD21MAC_CFG_059C_VDO_PROC_REG_WBANK_OFFSET Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_059C_VDO_PROC_REG_DMA2MI_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_059C_VDO_PROC_REG_DMA_EMP_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_05A0_VDO_PROC (HDMI2P1_MAC_BASE + 0x5A0)
    #define HD21MAC_CFG_05A0_VDO_PROC_REG_DMA_ST_ADDR1_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_05A4_VDO_PROC (HDMI2P1_MAC_BASE + 0x5A4)
    #define HD21MAC_CFG_05A4_VDO_PROC_REG_DMA_ST_ADDR1_1 Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_05A8_VDO_PROC (HDMI2P1_MAC_BASE + 0x5A8)
    #define HD21MAC_CFG_05A8_VDO_PROC_REG_DMA_ST_ADDR2_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_05AC_VDO_PROC (HDMI2P1_MAC_BASE + 0x5AC)
    #define HD21MAC_CFG_05AC_VDO_PROC_REG_DMA_ST_ADDR2_1 Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_05B0_VDO_PROC (HDMI2P1_MAC_BASE + 0x5B0)
    #define HD21MAC_CFG_05B0_VDO_PROC_REG_CLR_MIU_HI_PRI Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_05B0_VDO_PROC_REG_CLR_MIU_BW_FAIL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_05B0_VDO_PROC_REG_EMP_REQ_DISABLE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_05B4_VDO_PROC (HDMI2P1_MAC_BASE + 0x5B4)
    #define HD21MAC_CFG_05B4_VDO_PROC_REG_EMP_MIU_READ_TYPE_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_05B4_VDO_PROC_REG_EMP_MIU_READ_BUF_LV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_05B4_VDO_PROC_REG_EMP_MIU_READ_HI_PRI_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_05B4_VDO_PROC_REG_EMP_MIU_READ_BW_FAIL_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_05B4_VDO_PROC_REG_EMP_MIU_HI_PRI_CTRL_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_05B4_VDO_PROC_REG_EMP_MIU_TYPE_CTRL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_05B8_VDO_PROC (HDMI2P1_MAC_BASE + 0x5B8)
    #define HD21MAC_CFG_05B8_VDO_PROC_REG_MIU_HI_PRI_THD Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_05B8_VDO_PROC_REG_MIU_HI_PRI_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_05B8_VDO_PROC_REG_MIU_USR_TYPE_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_05B8_VDO_PROC_REG_MIU_USR_TYPE Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_05BC_VDO_PROC (HDMI2P1_MAC_BASE + 0x5BC)
    #define HD21MAC_CFG_05BC_VDO_PROC_REG_MIU_TYPE_T1T2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_05BC_VDO_PROC_REG_MIU_TYPE_T0T1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_05C0_VDO_PROC (HDMI2P1_MAC_BASE + 0x5C0)
    #define HD21MAC_CFG_05C0_VDO_PROC_REG_R_MIU_BUF_SIZE Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_05C0_VDO_PROC_REG_R_MIU_HI_PRI Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_05C0_VDO_PROC_REG_R_MIU_BW_FAIL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_05C4_VDO_PROC (HDMI2P1_MAC_BASE + 0x5C4)
    #define HD21MAC_CFG_05C4_VDO_PROC_REG_CLR_MIU_BUF_LV Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_05C4_VDO_PROC_REG_CLR_MIU_TYPE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_05C4_VDO_PROC_REG_R_MIU_MAX_TYPE Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_05C4_VDO_PROC_REG_R_MIU_MIN_TYPE Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_05C4_VDO_PROC_REG_R_MIU_CUR_TYPE Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_05C8_VDO_PROC (HDMI2P1_MAC_BASE + 0x5C8)
    #define HD21MAC_CFG_05C8_VDO_PROC_REG_R_MIU_MAX_BUF_LV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_05C8_VDO_PROC_REG_R_MIU_MIN_BUF_LV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0608_MD_0 (HDMI2P1_MAC_BASE + 0x608)
    #define HD21MAC_CFG_0608_MD_0_REG_FVDO_DIVSEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0608_MD_0_REG_VDEXT_SYNMD Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0608_MD_0_REG_YCBCR_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0608_MD_0_REG_VIDEO_SELECT Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_0608_MD_0_REG_NO_SIGNAL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0608_MD_0_REG_AUTO_DETSRC Fld(2,5,AC_MSKB0)//[6:5]
    #define HD21MAC_CFG_0608_MD_0_REG_COMP_SRC Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0608_MD_0_REG_CSC_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0608_MD_0_REG_SOURCE_SELECT Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_060C_MD_0 (HDMI2P1_MAC_BASE + 0x60C)
    #define HD21MAC_CFG_060C_MD_0_REG_FRCV Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_060C_MD_0_REG_AUTO_UNLOCK Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_060C_MD_0_REG_DATA10BIT Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_060C_MD_0_REG_DATA8_ROUND Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_060C_MD_0_REG_VD16_C_AHEAD Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_060C_MD_0_REG_RESERVED Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_060C_MD_0_REG_DIRECT_DE Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_060C_MD_0_REG_DE_ONLY_ORI Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_060C_MD_0_REG_VS_DLYMD Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_060C_MD_0_REG_HS_REFEG Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_060C_MD_0_REG_VS_REFEG Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_060C_MD_0_REG_EXTEND_EARLY_LN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_060C_MD_0_REG_VWRAP Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_060C_MD_0_REG_HWRAP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0610_MD_0 (HDMI2P1_MAC_BASE + 0x610)
    #define HD21MAC_CFG_0610_MD_0_REG_SPRANGE_VST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0614_MD_0 (HDMI2P1_MAC_BASE + 0x614)
    #define HD21MAC_CFG_0614_MD_0_REG_SPRANGE_HST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0618_MD_0 (HDMI2P1_MAC_BASE + 0x618)
    #define HD21MAC_CFG_0618_MD_0_REG_SPRANGE_VDC Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_061C_MD_0 (HDMI2P1_MAC_BASE + 0x61C)
    #define HD21MAC_CFG_061C_MD_0_REG_SPRANGE_HDC_2P Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_061C_MD_0_REG_SPRANGE_HDC Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_0620_MD_0 (HDMI2P1_MAC_BASE + 0x620)
    #define HD21MAC_CFG_0620_MD_0_REG_VDCLK_INV Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0620_MD_0_REG_YPBPR_HS_SEPMD Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0620_MD_0_REG_VDCLK_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_0620_MD_0_REG_FOSVDCNT_MD Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0620_MD_0_REG_VDCNT Fld(2,5,AC_MSKB0)//[6:5]
    #define HD21MAC_CFG_0620_MD_0_REG_VD_NOMASK Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0620_MD_0_REG_IHSU Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0620_MD_0_REG_INTLAC_LOCKAVG Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0620_MD_0_REG_VDO_YC_SWAP Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0620_MD_0_REG_VDO_ML_SWAP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0624_MD_0 (HDMI2P1_MAC_BASE + 0x624)
    #define HD21MAC_CFG_0624_MD_0_REG_DUMMY09_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0624_MD_0_REG_CSC_DITHEN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0624_MD_0_REG_INTLAC_DET_EDGE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0624_MD_0_REG_FILED_ABSMD Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0624_MD_0_REG_INTLAC_AUTO Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0624_MD_0_REG_Y_LOCK Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_0628_MD_0 (HDMI2P1_MAC_BASE + 0x628)
    #define HD21MAC_CFG_0628_MD_0_REG_DUMMY0A_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0628_MD_0_REG_IP_INT_SEL Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_062C_MD_0 (HDMI2P1_MAC_BASE + 0x62C)
    #define HD21MAC_CFG_062C_MD_0_REG_DUMMY0B_0_14 Fld(15,0,AC_MSKW10)//[14:0]
#define HD21MAC_CFG_0630_MD_0 (HDMI2P1_MAC_BASE + 0x630)
    #define HD21MAC_CFG_0630_MD_0_REG_CS_DET_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0630_MD_0_REG_HDMI_444_REP Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0630_MD_0_REG_DUMMY0C_2_5 Fld(4,2,AC_MSKB0)//[5:2]
    #define HD21MAC_CFG_0630_MD_0_REG_AUTO_INTLAC_INV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0630_MD_0_REG_AUTO_INTLAC_MD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0634_MD_0 (HDMI2P1_MAC_BASE + 0x634)
    #define HD21MAC_CFG_0634_MD_0_REG_DUMMY0D_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0634_MD_0_REG_OVERSAP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0634_MD_0_REG_OVERSAP_PHS Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_0634_MD_0_REG_OVERSAP_CNT Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_0638_MD_0 (HDMI2P1_MAC_BASE + 0x638)
    #define HD21MAC_CFG_0638_MD_0_REG_AV_DET Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_UPR Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_UPG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_UPB Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_HIR Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_HIG Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_HIB Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_CALMD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_DATA_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_HISMD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_READY Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0638_MD_0_REG_ATG_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_063C_MD_0 (HDMI2P1_MAC_BASE + 0x63C)
    #define HD21MAC_CFG_063C_MD_0_REG_DUMMY0F_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_063C_MD_0_REG_AUTO_COAST Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_063C_MD_0_REG_OP2_COAST Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_063C_MD_0_REG_ATPSEL Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_063C_MD_0_REG_PIP_SW_DOUBLE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_063C_MD_0_REG_ATGSEL Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_0640_MD_0 (HDMI2P1_MAC_BASE + 0x640)
    #define HD21MAC_CFG_0640_MD_0_REG_THOLD Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_0640_MD_0_REG_ATS_PIXMD Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0640_MD_0_REG_JIT_R Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0640_MD_0_REG_JIT_SWCLR_SB Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0640_MD_0_REG_ATS_CBCR_MD_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0640_MD_0_REG_JITTER_HISMD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0640_MD_0_REG_JITTER Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0640_MD_0_REG_ATS_HISMD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0640_MD_0_REG_ATS_READY Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0640_MD_0_REG_ATS_EN Fld(1,0,AC_MSKB0)//[0:0]

//Page HDMI21_MAC_2
#define HD21MAC_CFG_0644_MD_0 (HDMI2P1_MAC_BASE + 0x644)
    #define HD21MAC_CFG_0644_MD_0_REG_ATGSEL_VALUE Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_0648_MD_0 (HDMI2P1_MAC_BASE + 0x648)
    #define HD21MAC_CFG_0648_MD_0_REG_ATS_VSTDBUF Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_064C_MD_0 (HDMI2P1_MAC_BASE + 0x64C)
    #define HD21MAC_CFG_064C_MD_0_REG_ATS_HSTDBUF Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0650_MD_0 (HDMI2P1_MAC_BASE + 0x650)
    #define HD21MAC_CFG_0650_MD_0_REG_ATS_VEDDBUF Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0654_MD_0 (HDMI2P1_MAC_BASE + 0x654)
    #define HD21MAC_CFG_0654_MD_0_REG_ATS_HEDDBUF Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0658_MD_0 (HDMI2P1_MAC_BASE + 0x658)
    #define HD21MAC_CFG_0658_MD_0_REG_JLST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_065C_MD_0 (HDMI2P1_MAC_BASE + 0x65C)
    #define HD21MAC_CFG_065C_MD_0_REG_DUMMY17_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_065C_MD_0_REG_PIX_TH Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_0660_MD_0 (HDMI2P1_MAC_BASE + 0x660)
    #define HD21MAC_CFG_0660_MD_0_REG_ATP_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0660_MD_0_REG_ATP_GTH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0664_MD_0 (HDMI2P1_MAC_BASE + 0x664)
    #define HD21MAC_CFG_0664_MD_0_REG_DUMMY19_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0664_MD_0_REG_ATP_GRY Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0664_MD_0_REG_ATP_TXT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0664_MD_0_REG_ATPMASK Fld(3,2,AC_MSKB0)//[4:2]
    #define HD21MAC_CFG_0664_MD_0_REG_ATP_READY Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0664_MD_0_REG_ATP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0668_MD_0 (HDMI2P1_MAC_BASE + 0x668)
    #define HD21MAC_CFG_0668_MD_0_REG_ATPV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_066C_MD_0 (HDMI2P1_MAC_BASE + 0x66C)
    #define HD21MAC_CFG_066C_MD_0_REG_ATPV_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0670_MD_0 (HDMI2P1_MAC_BASE + 0x670)
    #define HD21MAC_CFG_0670_MD_0_REG_DELAYLN_NUM Fld(6,4,AC_MSKW10)//[9:4]
    #define HD21MAC_CFG_0670_MD_0_REG_LB_TUNE_READY Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0670_MD_0_REG_UNDERRUN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0670_MD_0_REG_OVERRUN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0674_MD_0 (HDMI2P1_MAC_BASE + 0x674)
    #define HD21MAC_CFG_0674_MD_0_REG_VDO_VEDGE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0674_MD_0_REG_RAW_VSMD Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0674_MD_0_REG_HTT_FILTERMD Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0674_MD_0_REG_AUTO_NO_SIGNAL Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_0674_MD_0_REG_VS_TOL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_0674_MD_0_REG_VS2HS_2SMALL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0674_MD_0_REG_DE_LOCKH_MD Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0674_MD_0_REG_HSTOL Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_0678_MD_0 (HDMI2P1_MAC_BASE + 0x678)
    #define HD21MAC_CFG_0678_MD_0_REG_IPVS_ACT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0678_MD_0_REG_IPHS_ACT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0678_MD_0_REG_CS_DET Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0678_MD_0_REG_SOG_DET Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_0678_MD_0_REG_INTLAC_DET Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0678_MD_0_REG_FIELD_DET Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0678_MD_0_REG_HSPOL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0678_MD_0_REG_VSPOL Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0678_MD_0_REG_IPHCS_ACT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0678_MD_0_REG_IPHS_SB_S Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0678_MD_0_REG_IPVS_SB_S Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0678_MD_0_REG_OPHS Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0678_MD_0_REG_OPVS Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_067C_MD_0 (HDMI2P1_MAC_BASE + 0x67C)
    #define HD21MAC_CFG_067C_MD_0_REG_VS_PW_VDOMD Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_067C_MD_0_REG_HSPW_SEL Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_067C_MD_0_REG_VTT_FOR_READ Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0680_MD_0 (HDMI2P1_MAC_BASE + 0x680)
    #define HD21MAC_CFG_0680_MD_0_REG_LN4_DETMD Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0680_MD_0_REG_HTT_REPORT_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0680_MD_0_REG_HTT_FOR_READ Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_0684_MD_0 (HDMI2P1_MAC_BASE + 0x684)
    #define HD21MAC_CFG_0684_MD_0_REG_MEMSYN_TO_VS Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_0684_MD_0_REG_DE_ONLY_HTT_CHGMD Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0684_MD_0_REG_DE_ONLY_HTT_SRC Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_0684_MD_0_REG_ADC_VIDEO_FINV Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0684_MD_0_REG_EXT_FIELDMD Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0684_MD_0_REG_FIELD_DETMD Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0684_MD_0_REG_FIELD_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0684_MD_0_REG_FIELD_SWMD Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0684_MD_0_REG_COAST_HS_SEPMD Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0684_MD_0_REG_USR_VSPOL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0684_MD_0_REG_USR_VSPOLMD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0684_MD_0_REG_USR_HSPOL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0684_MD_0_REG_USR_HSPOLMD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0684_MD_0_REG_USR_INTLAC Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0684_MD_0_REG_USR_INTLACMD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0688_MD_0 (HDMI2P1_MAC_BASE + 0x688)
    #define HD21MAC_CFG_0688_MD_0_REG_VSPW Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0688_MD_0_REG_HSPW Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_068C_MD_0 (HDMI2P1_MAC_BASE + 0x68C)
    #define HD21MAC_CFG_068C_MD_0_REG_VD_FREE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_068C_MD_0_REG_MIN_VTT Fld(7,8,AC_MSKB1)//[14:8]
#define HD21MAC_CFG_0690_MD_0 (HDMI2P1_MAC_BASE + 0x690)
    #define HD21MAC_CFG_0690_MD_0_REG_COAST_FBD Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0690_MD_0_REG_VS_SEP_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0690_MD_0_REG_VIDEO_D1L_H Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0690_MD_0_REG_VIDEO_D1L_L Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0690_MD_0_REG_ADC_VIDEO Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0690_MD_0_REG_CS_CUT_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0690_MD_0_REG_EXTVS_SEPINV Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0690_MD_0_REG_COAST_SRC Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0690_MD_0_REG_COAST_POL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0694_MD_0 (HDMI2P1_MAC_BASE + 0x694)
    #define HD21MAC_CFG_0694_MD_0_REG_COAST_BBD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0698_MD_0 (HDMI2P1_MAC_BASE + 0x698)
    #define HD21MAC_CFG_0698_MD_0_REG_DUMMY26_12_15 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_0698_MD_0_REG_HTT_FILT_PATCH Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0698_MD_0_REG_MVOP_DIN_EN_INV Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0698_MD_0_REG_IP1_CATCH_UP_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0698_MD_0_REG_IP1_RDY_MASK_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0698_MD_0_REG_GR_DE_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0698_MD_0_REG_FILTER_NUM Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_0698_MD_0_REG_GR_HS_VIDEO Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0698_MD_0_REG_GR_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0698_MD_0_REG_HVTT_LOSE_MD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0698_MD_0_REG_IDCLK_INV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_069C_MD_0 (HDMI2P1_MAC_BASE + 0x69C)
    #define HD21MAC_CFG_069C_MD_0_REG_DUMMY27_9_15 Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_069C_MD_0_REG_LOCK_FIELD_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_069C_MD_0_REG_ATP_FILTERMD Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_069C_MD_0_REG_DE_ONLY_IDHTT Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_069C_MD_0_REG_GR_VS_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_069C_MD_0_REG_VS_PROTECT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_069C_MD_0_REG_DEGP Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_069C_MD_0_REG_TEST_BUS_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_06A0_MD_0 (HDMI2P1_MAC_BASE + 0x6A0)
    #define HD21MAC_CFG_06A0_MD_0_REG_HTT_ID_FOR_READ Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_06A4_MD_0 (HDMI2P1_MAC_BASE + 0x6A4)
    #define HD21MAC_CFG_06A4_MD_0_REG_LOCK2LOCK_REPORT Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_06A4_MD_0_REG_ATRANGE_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_06A4_MD_0_REG_VS_SEP_SEL_1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_06A4_MD_0_REG_VS_SEP_SEL_0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_06A4_MD_0_REG_INTLAC_DET_MODE Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_06A4_MD_0_REG_EUP_AU_HDTV_DET Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_06A4_MD_0_REG_EUP_HDTV_DET Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_06A4_MD_0_REG_EUP_AUTOFIELD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_06A4_MD_0_REG_EUP_HDTV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_06A8_MD_0 (HDMI2P1_MAC_BASE + 0x6A8)
    #define HD21MAC_CFG_06A8_MD_0_REG_ATRANGE_VST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_06AC_MD_0 (HDMI2P1_MAC_BASE + 0x6AC)
    #define HD21MAC_CFG_06AC_MD_0_REG_ATRANGE_HST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_06B0_MD_0 (HDMI2P1_MAC_BASE + 0x6B0)
    #define HD21MAC_CFG_06B0_MD_0_REG_ATRANGE_VDC Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_06B4_MD_0 (HDMI2P1_MAC_BASE + 0x6B4)
    #define HD21MAC_CFG_06B4_MD_0_REG_ATRANGE_HDC Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_06B8_MD_0 (HDMI2P1_MAC_BASE + 0x6B8)
    #define HD21MAC_CFG_06B8_MD_0_REG_GOP_CLK_FREE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_06B8_MD_0_REG_IP2_CLK_GATE_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_06BC_MD_0 (HDMI2P1_MAC_BASE + 0x6BC)
    #define HD21MAC_CFG_06BC_MD_0_REG_DE_BYPASS_MODE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_06BC_MD_0_REG_ATS_2P_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_06BC_MD_0_REG_ATS_DE_HST_FLT_OFF Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_06BC_MD_0_REG_ATS_HST_FLT_OFF Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_06BC_MD_0_REG_ATS_B_SKIP Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_06BC_MD_0_REG_ATS_G_SKIP Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_06BC_MD_0_REG_ATS_R_SKIP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_06C0_MD_0 (HDMI2P1_MAC_BASE + 0x6C0)
    #define HD21MAC_CFG_06C0_MD_0_REG_INSERT_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_06C0_MD_0_REG_INSERT_NUM Fld(11,0,AC_MSKW10)//[10:0]
#define HD21MAC_CFG_06C4_MD_0 (HDMI2P1_MAC_BASE + 0x6C4)
    #define HD21MAC_CFG_06C4_MD_0_REG_LOCK_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_06C4_MD_0_REG_LOCK_NUM Fld(11,0,AC_MSKW10)//[10:0]
#define HD21MAC_CFG_06C8_MD_0 (HDMI2P1_MAC_BASE + 0x6C8)
    #define HD21MAC_CFG_06C8_MD_0_REG_MEMSYN_TO_VS_NEW Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_06C8_MD_0_REG_VLOCK_MD Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_06C8_MD_0_REG_VLOCK_VAL Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_06CC_MD_0 (HDMI2P1_MAC_BASE + 0x6CC)
    #define HD21MAC_CFG_06CC_MD_0_REG_OP2_COAST_STATUS Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_06CC_MD_0_REG_AUTO_COAST_HV_LOSE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_06CC_MD_0_REG_AUTO_COAST_V_LOSE Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_06CC_MD_0_REG_AUTO_COAST_H_LOSE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_06CC_MD_0_REG_NO_SIGNAL_STATUS Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_06CC_MD_0_REG_AUTO_NOS_HV_LOSE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_06CC_MD_0_REG_AUTO_NOS_V_LOSE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_06CC_MD_0_REG_AUTO_NOS_H_LOSE Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_06CC_MD_0_REG_RGB_CLAMP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_06CC_MD_0_REG_AUTO_NOS_JITTER Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_06CC_MD_0_REG_ATG_NEW_RANGE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_06CC_MD_0_REG_ATG_NEW_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_06CC_MD_0_REG_ATG_NEW_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_06D0_MD_0 (HDMI2P1_MAC_BASE + 0x6D0)
    #define HD21MAC_CFG_06D0_MD_0_REG_HDMI_VMUTE_DET_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_06D0_MD_0_REG_WDT_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_06D0_MD_0_REG_WDT_VSEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_06D0_MD_0_REG_WDT_HSEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_06D4_MD_0 (HDMI2P1_MAC_BASE + 0x6D4)
    #define HD21MAC_CFG_06D4_MD_0_REG_SOG_VALID Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_06D4_MD_0_REG_CNT_NUMBER_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_06D4_MD_0_REG_MACROVISION_FILTER_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_06D4_MD_0_REG_MACROVISION_FILTER_RANGE Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_06D8_MD_0 (HDMI2P1_MAC_BASE + 0x6D8)
    #define HD21MAC_CFG_06D8_MD_0_REG_SEL_NEW_CSOURCE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_06D8_MD_0_REG_GENCSOG_RESET Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_06D8_MD_0_REG_EN_OVERCNT Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_06D8_MD_0_REG_OVERCNT Fld(7,0,AC_MSKB0)//[6:0]
#define HD21MAC_CFG_06DC_MD_0 (HDMI2P1_MAC_BASE + 0x6DC)
    #define HD21MAC_CFG_06DC_MD_0_REG_INTLAC_DET_EN Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_06E0_MD_0 (HDMI2P1_MAC_BASE + 0x6E0)
    #define HD21MAC_CFG_06E0_MD_0_REG_INTLAC_DET_ALL Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_06E4_MD_0 (HDMI2P1_MAC_BASE + 0x6E4)
    #define HD21MAC_CFG_06E4_MD_0_REG_FIELD_DET_EN Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_06E8_MD_0 (HDMI2P1_MAC_BASE + 0x6E8)
    #define HD21MAC_CFG_06E8_MD_0_REG_FIELD_DET_ALL Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_06EC_MD_0 (HDMI2P1_MAC_BASE + 0x6EC)
    #define HD21MAC_CFG_06EC_MD_0_REG_SPR_V_LOCK_P_IP_CNT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_06F0_MD_0 (HDMI2P1_MAC_BASE + 0x6F0)
    #define HD21MAC_CFG_06F0_MD_0_REG_SPR_V_LOCK_P_IP_CNT_1 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_06F4_MD_0 (HDMI2P1_MAC_BASE + 0x6F4)
    #define HD21MAC_CFG_06F4_MD_0_REG_HTT_RPT_MD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_06F8_MD_0 (HDMI2P1_MAC_BASE + 0x6F8)
    #define HD21MAC_CFG_06F8_MD_0_REG_IPM_TRIG_VCNT_2ND_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_06F8_MD_0_REG_IPM_TRIG_VCNT_2ND Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_06FC_MD_0 (HDMI2P1_MAC_BASE + 0x6FC)
    #define HD21MAC_CFG_06FC_MD_0_REG_ATGSEL_VALUE_Q Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_0700_MD_0 (HDMI2P1_MAC_BASE + 0x700)
    #define HD21MAC_CFG_0700_MD_0_REG_TEST_YINI Fld(3,11,AC_MSKB1)//[13:11]
    #define HD21MAC_CFG_0700_MD_0_REG_TEST_XINI Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_0700_MD_0_REG_TEST_BLK_WHT_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0700_MD_0_REG_TEST_REGION_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0700_MD_0_REG_TEST_REGION_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0700_MD_0_REG_TEST_GRAY_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0700_MD_0_REG_F_TEST_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0700_MD_0_REG_V_TEST_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0700_MD_0_REG_H_TEST_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0704_MD_0 (HDMI2P1_MAC_BASE + 0x704)
    #define HD21MAC_CFG_0704_MD_0_REG_TEST_VSIZE Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_0704_MD_0_REG_TEST_VST Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_0704_MD_0_REG_TEST_HSIZE Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_0704_MD_0_REG_TEST_HST Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_0708_MD_0 (HDMI2P1_MAC_BASE + 0x708)
    #define HD21MAC_CFG_0708_MD_0_REG_TEST_CB_V_WIDTH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0708_MD_0_REG_TEST_CB_H_WIDTH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_070C_MD_0 (HDMI2P1_MAC_BASE + 0x70C)
    #define HD21MAC_CFG_070C_MD_0_REG_TEST_SHIFT_TIME Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0710_MD_0 (HDMI2P1_MAC_BASE + 0x710)
    #define HD21MAC_CFG_0710_MD_0_REG_MEMSYN_TO_VS_FULLRG Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0710_MD_0_REG_MEMSYN_TO_VS_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0714_MD_0 (HDMI2P1_MAC_BASE + 0x714)
    #define HD21MAC_CFG_0714_MD_0_REG_EDCLK_PD_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0714_MD_0_REG_EDCLK_PD_ST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0718_MD_0 (HDMI2P1_MAC_BASE + 0x718)
    #define HD21MAC_CFG_0718_MD_0_REG_MEMSYN_TO_CMDQ_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_071C_MD_0 (HDMI2P1_MAC_BASE + 0x71C)
    #define HD21MAC_CFG_071C_MD_0_REG_IPM_TRIG_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0720_MD_0 (HDMI2P1_MAC_BASE + 0x720)
    #define HD21MAC_CFG_0720_MD_0_REG_FDET_CHECK_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0720_MD_0_REG_FDET_H_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0720_MD_0_REG_FDET_V_INV Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0720_MD_0_REG_FDET_VTOTAL_PIX_CNT_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0720_MD_0_REG_FDET_SYNC_SRC_SEL Fld(2,1,AC_MSKB0)//[2:1]
    #define HD21MAC_CFG_0720_MD_0_REG_FDET_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0724_MD_0 (HDMI2P1_MAC_BASE + 0x724)
    #define HD21MAC_CFG_0724_MD_0_REG_FDET_VTOTAL_TOR Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0724_MD_0_REG_FDET_VWIDTH_TOR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0728_MD_0 (HDMI2P1_MAC_BASE + 0x728)
    #define HD21MAC_CFG_0728_MD_0_REG_FDET_STATUS_INTLAC_DET2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0728_MD_0_REG_FDET_STATUS_INTLAC_DET1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0728_MD_0_REG_FDET_STATUS_INTLAC_DET0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_072C_MD_0 (HDMI2P1_MAC_BASE + 0x72C)
    #define HD21MAC_CFG_072C_MD_0_REG_FDET_STATUS_VWIDTH0 Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_0730_MD_0 (HDMI2P1_MAC_BASE + 0x730)
    #define HD21MAC_CFG_0730_MD_0_REG_FDET_STATUS_VWIDTH1 Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_0734_MD_0 (HDMI2P1_MAC_BASE + 0x734)
    #define HD21MAC_CFG_0734_MD_0_REG_FDET_STATUS_VTOTAL0_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0738_MD_0 (HDMI2P1_MAC_BASE + 0x738)
    #define HD21MAC_CFG_0738_MD_0_REG_FDET_STATUS_VTOTAL0_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_073C_MD_0 (HDMI2P1_MAC_BASE + 0x73C)
    #define HD21MAC_CFG_073C_MD_0_REG_FDET_STATUS_VTOTAL1_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0740_MD_0 (HDMI2P1_MAC_BASE + 0x740)
    #define HD21MAC_CFG_0740_MD_0_REG_FDET_STATUS_VTOTAL1_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_0744_MD_0 (HDMI2P1_MAC_BASE + 0x744)
    #define HD21MAC_CFG_0744_MD_0_REG_FDET_STATUS_VTOTAL2_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0748_MD_0 (HDMI2P1_MAC_BASE + 0x748)
    #define HD21MAC_CFG_0748_MD_0_REG_FDET_STATUS_VTOTAL2_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_074C_MD_0 (HDMI2P1_MAC_BASE + 0x74C)
    #define HD21MAC_CFG_074C_MD_0_REG_FDET_STATUS_VTOTAL3_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0750_MD_0 (HDMI2P1_MAC_BASE + 0x750)
    #define HD21MAC_CFG_0750_MD_0_REG_FDET_STATUS_VTOTAL3_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_077C_MD_0 (HDMI2P1_MAC_BASE + 0x77C)
    #define HD21MAC_CFG_077C_MD_0_REG_IPVS_SW_TRIG Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0780_MD_0 (HDMI2P1_MAC_BASE + 0x780)
    #define HD21MAC_CFG_0780_MD_0_REG_ATRANGE_DBG_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0780_MD_0_REG_ATRANGE_DBG_R Fld(5,10,AC_MSKB1)//[14:10]
    #define HD21MAC_CFG_0780_MD_0_REG_ATRANGE_DBG_G Fld(5,5,AC_MSKW10)//[9:5]
    #define HD21MAC_CFG_0780_MD_0_REG_ATRANGE_DBG_B Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_0784_MD_0 (HDMI2P1_MAC_BASE + 0x784)
    #define HD21MAC_CFG_0784_MD_0_REG_IP1_HDMI422_2P_CBCR_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0784_MD_0_REG_IP1_HDMI422_2P_RB_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0784_MD_0_REG_IP1_HDMI422_2P_MANUAL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0784_MD_0_REG_IP1_HDMI422_2P_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0784_MD_0_REG_IP1_HDMI422_2P_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0788_MD_0 (HDMI2P1_MAC_BASE + 0x788)
    #define HD21MAC_CFG_0788_MD_0_REG_DE_ONLY_HSTOL_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0788_MD_0_REG_DE_ONLY_HSTOL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_078C_MD_0 (HDMI2P1_MAC_BASE + 0x78C)
    #define HD21MAC_CFG_078C_MD_0_REG_OHT_AUTO_DET Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_078C_MD_0_REG_OHT_AUTO_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0790_MD_0 (HDMI2P1_MAC_BASE + 0x790)
    #define HD21MAC_CFG_0790_MD_0_REG_DEONLY_NEW_HS Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0790_MD_0_REG_IPHS_DB_EDGE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0790_MD_0_REG_IPHS_SB_P_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0794_MD_0 (HDMI2P1_MAC_BASE + 0x794)
    #define HD21MAC_CFG_0794_MD_0_REG_USR_VPOL_VS_WIDTH_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0794_MD_0_REG_USR_VPOL_VS_WIDTH Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_0798_MD_0 (HDMI2P1_MAC_BASE + 0x798)
    #define HD21MAC_CFG_0798_MD_0_REG_FULL_DELAYLN_NUM_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0798_MD_0_REG_FULL_DELAYLN_NUM Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_07C0_MD_0 (HDMI2P1_MAC_BASE + 0x7C0)
    #define HD21MAC_CFG_07C0_MD_0_REG_DUMMY70_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_07C0_MD_0_REG_IP1_VH_MNTR_VMD Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_07C0_MD_0_REG_IP1_VH_MNTR_HMD Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_07C0_MD_0_REG_IP1_VH_MNTR_V_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_07C0_MD_0_REG_IP1_VH_MNTR_H_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_07C4_MD_0 (HDMI2P1_MAC_BASE + 0x7C4)
    #define HD21MAC_CFG_07C4_MD_0_REG_IP1_VH_MNTR_VTOR Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_07C4_MD_0_REG_IP1_VH_MNTR_HTOR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_07DC_MD_0 (HDMI2P1_MAC_BASE + 0x7DC)
    #define HD21MAC_CFG_07DC_MD_0_REG_SC_FE_TOP_BYPASS_INPUT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_07DC_MD_0_REG_SC_FE_TOP_FLOCK_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_07DC_MD_0_REG_SC_FE_TOP_TESTCS_MODE Fld(1,0,AC_MSKB0)//[0:0]

//Page HDMI21_MAC_3
#define HD21MAC_CFG_0804_MD_WP_0 (HDMI2P1_MAC_BASE + 0x804)
    #define HD21MAC_CFG_0804_MD_WP_0_REG_DBL_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0804_MD_WP_0_REG_DBL_EN Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_0808_MD_WP_0 (HDMI2P1_MAC_BASE + 0x808)
    #define HD21MAC_CFG_0808_MD_WP_0_REG_IP_SW_RST_OSC Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0808_MD_WP_0_REG_IP_SW_RST_IP Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0808_MD_WP_0_REG_IP_SW_RST_ALL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_080C_MD_WP_0 (HDMI2P1_MAC_BASE + 0x80C)
    #define HD21MAC_CFG_080C_MD_WP_0_REG_NO_SIGNAL_GEN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_080C_MD_WP_0_REG_PDMD_ID Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0810_MD_WP_0 (HDMI2P1_MAC_BASE + 0x810)
    #define HD21MAC_CFG_0810_MD_WP_0_REG_CHG_HMD Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0810_MD_WP_0_REG_IPVS_INT_EDGE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0868_MD_WP_0 (HDMI2P1_MAC_BASE + 0x868)
    #define HD21MAC_CFG_0868_MD_WP_0_REG_HTT_CHG_READ Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0880_MD_WP_0 (HDMI2P1_MAC_BASE + 0x880)
    #define HD21MAC_CFG_0880_MD_WP_0_REG_IP1_WP_FIELD_INV Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0880_MD_WP_0_REG_IP1_WP_VS_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0880_MD_WP_0_REG_IP1_WP_FIELD_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0880_MD_WP_0_REG_IP1_WP_VS_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0884_MD_WP_0 (HDMI2P1_MAC_BASE + 0x884)
    #define HD21MAC_CFG_0884_MD_WP_0_REG_MVOP_DIN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0900_MD_WP_0 (HDMI2P1_MAC_BASE + 0x900)
    #define HD21MAC_CFG_0900_MD_WP_0_REG_C_IRQ_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0904_MD_WP_0 (HDMI2P1_MAC_BASE + 0x904)
    #define HD21MAC_CFG_0904_MD_WP_0_REG_C_IRQ_CLR Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0908_MD_WP_0 (HDMI2P1_MAC_BASE + 0x908)
    #define HD21MAC_CFG_0908_MD_WP_0_REG_C_IRQ_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_090C_MD_WP_0 (HDMI2P1_MAC_BASE + 0x90C)
    #define HD21MAC_CFG_090C_MD_WP_0_REG_IRQ_FINAL_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0910_MD_WP_0 (HDMI2P1_MAC_BASE + 0x910)
    #define HD21MAC_CFG_0910_MD_WP_0_REG_IRQ_RAW_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_09F8_MD_WP_0 (HDMI2P1_MAC_BASE + 0x9F8)
    #define HD21MAC_CFG_09F8_MD_WP_0_REG_DUMMY_7F_SETH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_09FC_MD_WP_0 (HDMI2P1_MAC_BASE + 0x9FC)
    #define HD21MAC_CFG_09FC_MD_WP_0_REG_DUMMY_7F_SETL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0A08_MD_1 (HDMI2P1_MAC_BASE + 0xA08)
    #define HD21MAC_CFG_0A08_MD_1_REG_FVDO_DIVSEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0A08_MD_1_REG_VDEXT_SYNMD Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0A08_MD_1_REG_YCBCR_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0A08_MD_1_REG_VIDEO_SELECT Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_0A08_MD_1_REG_NO_SIGNAL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A08_MD_1_REG_AUTO_DETSRC Fld(2,5,AC_MSKB0)//[6:5]
    #define HD21MAC_CFG_0A08_MD_1_REG_COMP_SRC Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A08_MD_1_REG_CSC_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A08_MD_1_REG_SOURCE_SELECT Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_0A0C_MD_1 (HDMI2P1_MAC_BASE + 0xA0C)
    #define HD21MAC_CFG_0A0C_MD_1_REG_FRCV Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0A0C_MD_1_REG_AUTO_UNLOCK Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0A0C_MD_1_REG_DATA10BIT Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0A0C_MD_1_REG_DATA8_ROUND Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0A0C_MD_1_REG_VD16_C_AHEAD Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0A0C_MD_1_REG_RESERVED Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0A0C_MD_1_REG_DIRECT_DE Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A0C_MD_1_REG_DE_ONLY_ORI Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A0C_MD_1_REG_VS_DLYMD Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0A0C_MD_1_REG_HS_REFEG Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A0C_MD_1_REG_VS_REFEG Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A0C_MD_1_REG_EXTEND_EARLY_LN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0A0C_MD_1_REG_VWRAP Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A0C_MD_1_REG_HWRAP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A10_MD_1 (HDMI2P1_MAC_BASE + 0xA10)
    #define HD21MAC_CFG_0A10_MD_1_REG_SPRANGE_VST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0A14_MD_1 (HDMI2P1_MAC_BASE + 0xA14)
    #define HD21MAC_CFG_0A14_MD_1_REG_SPRANGE_HST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0A18_MD_1 (HDMI2P1_MAC_BASE + 0xA18)
    #define HD21MAC_CFG_0A18_MD_1_REG_SPRANGE_VDC Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0A1C_MD_1 (HDMI2P1_MAC_BASE + 0xA1C)
    #define HD21MAC_CFG_0A1C_MD_1_REG_SPRANGE_HDC_2P Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0A1C_MD_1_REG_SPRANGE_HDC Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_0A20_MD_1 (HDMI2P1_MAC_BASE + 0xA20)
    #define HD21MAC_CFG_0A20_MD_1_REG_VDCLK_INV Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0A20_MD_1_REG_YPBPR_HS_SEPMD Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0A20_MD_1_REG_VDCLK_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_0A20_MD_1_REG_FOSVDCNT_MD Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A20_MD_1_REG_VDCNT Fld(2,5,AC_MSKB0)//[6:5]
    #define HD21MAC_CFG_0A20_MD_1_REG_VD_NOMASK Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A20_MD_1_REG_IHSU Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A20_MD_1_REG_INTLAC_LOCKAVG Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0A20_MD_1_REG_VDO_YC_SWAP Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A20_MD_1_REG_VDO_ML_SWAP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A24_MD_1 (HDMI2P1_MAC_BASE + 0xA24)
    #define HD21MAC_CFG_0A24_MD_1_REG_DUMMY09_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A24_MD_1_REG_CSC_DITHEN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A24_MD_1_REG_INTLAC_DET_EDGE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A24_MD_1_REG_FILED_ABSMD Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0A24_MD_1_REG_INTLAC_AUTO Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A24_MD_1_REG_Y_LOCK Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_0A28_MD_1 (HDMI2P1_MAC_BASE + 0xA28)
    #define HD21MAC_CFG_0A28_MD_1_REG_DUMMY0A_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A28_MD_1_REG_IP_INT_SEL Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0A2C_MD_1 (HDMI2P1_MAC_BASE + 0xA2C)
    #define HD21MAC_CFG_0A2C_MD_1_REG_DUMMY0B_0_14 Fld(15,0,AC_MSKW10)//[14:0]
#define HD21MAC_CFG_0A30_MD_1 (HDMI2P1_MAC_BASE + 0xA30)
    #define HD21MAC_CFG_0A30_MD_1_REG_CS_DET_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A30_MD_1_REG_HDMI_444_REP Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A30_MD_1_REG_DUMMY0C_2_5 Fld(4,2,AC_MSKB0)//[5:2]
    #define HD21MAC_CFG_0A30_MD_1_REG_AUTO_INTLAC_INV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A30_MD_1_REG_AUTO_INTLAC_MD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A34_MD_1 (HDMI2P1_MAC_BASE + 0xA34)
    #define HD21MAC_CFG_0A34_MD_1_REG_DUMMY0D_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A34_MD_1_REG_OVERSAP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A34_MD_1_REG_OVERSAP_PHS Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_0A34_MD_1_REG_OVERSAP_CNT Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_0A38_MD_1 (HDMI2P1_MAC_BASE + 0xA38)
    #define HD21MAC_CFG_0A38_MD_1_REG_AV_DET Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_UPR Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_UPG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_UPB Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_HIR Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_HIG Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_HIB Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_CALMD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_DATA_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_HISMD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_READY Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A38_MD_1_REG_ATG_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A3C_MD_1 (HDMI2P1_MAC_BASE + 0xA3C)
    #define HD21MAC_CFG_0A3C_MD_1_REG_DUMMY0F_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A3C_MD_1_REG_AUTO_COAST Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A3C_MD_1_REG_OP2_COAST Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A3C_MD_1_REG_ATPSEL Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_0A3C_MD_1_REG_PIP_SW_DOUBLE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A3C_MD_1_REG_ATGSEL Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_0A40_MD_1 (HDMI2P1_MAC_BASE + 0xA40)
    #define HD21MAC_CFG_0A40_MD_1_REG_THOLD Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_0A40_MD_1_REG_ATS_PIXMD Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0A40_MD_1_REG_JIT_R Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A40_MD_1_REG_JIT_SWCLR_SB Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A40_MD_1_REG_ATS_CBCR_MD_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0A40_MD_1_REG_JITTER_HISMD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A40_MD_1_REG_JITTER Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A40_MD_1_REG_ATS_HISMD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0A40_MD_1_REG_ATS_READY Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A40_MD_1_REG_ATS_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A44_MD_1 (HDMI2P1_MAC_BASE + 0xA44)
    #define HD21MAC_CFG_0A44_MD_1_REG_ATGSEL_VALUE Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_0A48_MD_1 (HDMI2P1_MAC_BASE + 0xA48)
    #define HD21MAC_CFG_0A48_MD_1_REG_ATS_VSTDBUF Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0A4C_MD_1 (HDMI2P1_MAC_BASE + 0xA4C)
    #define HD21MAC_CFG_0A4C_MD_1_REG_ATS_HSTDBUF Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0A50_MD_1 (HDMI2P1_MAC_BASE + 0xA50)
    #define HD21MAC_CFG_0A50_MD_1_REG_ATS_VEDDBUF Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0A54_MD_1 (HDMI2P1_MAC_BASE + 0xA54)
    #define HD21MAC_CFG_0A54_MD_1_REG_ATS_HEDDBUF Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0A58_MD_1 (HDMI2P1_MAC_BASE + 0xA58)
    #define HD21MAC_CFG_0A58_MD_1_REG_JLST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0A5C_MD_1 (HDMI2P1_MAC_BASE + 0xA5C)
    #define HD21MAC_CFG_0A5C_MD_1_REG_DUMMY17_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A5C_MD_1_REG_PIX_TH Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_0A60_MD_1 (HDMI2P1_MAC_BASE + 0xA60)
    #define HD21MAC_CFG_0A60_MD_1_REG_ATP_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A60_MD_1_REG_ATP_GTH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0A64_MD_1 (HDMI2P1_MAC_BASE + 0xA64)
    #define HD21MAC_CFG_0A64_MD_1_REG_DUMMY19_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A64_MD_1_REG_ATP_GRY Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A64_MD_1_REG_ATP_TXT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0A64_MD_1_REG_ATPMASK Fld(3,2,AC_MSKB0)//[4:2]
    #define HD21MAC_CFG_0A64_MD_1_REG_ATP_READY Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A64_MD_1_REG_ATP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A68_MD_1 (HDMI2P1_MAC_BASE + 0xA68)
    #define HD21MAC_CFG_0A68_MD_1_REG_ATPV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0A6C_MD_1 (HDMI2P1_MAC_BASE + 0xA6C)
    #define HD21MAC_CFG_0A6C_MD_1_REG_ATPV_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0A70_MD_1 (HDMI2P1_MAC_BASE + 0xA70)
    #define HD21MAC_CFG_0A70_MD_1_REG_DELAYLN_NUM Fld(6,4,AC_MSKW10)//[9:4]
    #define HD21MAC_CFG_0A70_MD_1_REG_LB_TUNE_READY Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A70_MD_1_REG_UNDERRUN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A70_MD_1_REG_OVERRUN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A74_MD_1 (HDMI2P1_MAC_BASE + 0xA74)
    #define HD21MAC_CFG_0A74_MD_1_REG_VDO_VEDGE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0A74_MD_1_REG_RAW_VSMD Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0A74_MD_1_REG_HTT_FILTERMD Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0A74_MD_1_REG_AUTO_NO_SIGNAL Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_0A74_MD_1_REG_VS_TOL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_0A74_MD_1_REG_VS2HS_2SMALL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A74_MD_1_REG_DE_LOCKH_MD Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A74_MD_1_REG_HSTOL Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_0A78_MD_1 (HDMI2P1_MAC_BASE + 0xA78)
    #define HD21MAC_CFG_0A78_MD_1_REG_IPVS_ACT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0A78_MD_1_REG_IPHS_ACT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0A78_MD_1_REG_CS_DET Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0A78_MD_1_REG_SOG_DET Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_0A78_MD_1_REG_INTLAC_DET Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0A78_MD_1_REG_FIELD_DET Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0A78_MD_1_REG_HSPOL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0A78_MD_1_REG_VSPOL Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0A78_MD_1_REG_IPHCS_ACT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A78_MD_1_REG_IPHS_SB_S Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A78_MD_1_REG_IPVS_SB_S Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0A78_MD_1_REG_OPHS Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A78_MD_1_REG_OPVS Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A7C_MD_1 (HDMI2P1_MAC_BASE + 0xA7C)
    #define HD21MAC_CFG_0A7C_MD_1_REG_VS_PW_VDOMD Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0A7C_MD_1_REG_HSPW_SEL Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0A7C_MD_1_REG_VTT_FOR_READ Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0A80_MD_1 (HDMI2P1_MAC_BASE + 0xA80)
    #define HD21MAC_CFG_0A80_MD_1_REG_LN4_DETMD Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0A80_MD_1_REG_HTT_REPORT_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0A80_MD_1_REG_HTT_FOR_READ Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_0A84_MD_1 (HDMI2P1_MAC_BASE + 0xA84)
    #define HD21MAC_CFG_0A84_MD_1_REG_MEMSYN_TO_VS Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_0A84_MD_1_REG_DE_ONLY_HTT_CHGMD Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0A84_MD_1_REG_DE_ONLY_HTT_SRC Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_0A84_MD_1_REG_ADC_VIDEO_FINV Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0A84_MD_1_REG_EXT_FIELDMD Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0A84_MD_1_REG_FIELD_DETMD Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0A84_MD_1_REG_FIELD_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0A84_MD_1_REG_FIELD_SWMD Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A84_MD_1_REG_COAST_HS_SEPMD Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A84_MD_1_REG_USR_VSPOL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0A84_MD_1_REG_USR_VSPOLMD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A84_MD_1_REG_USR_HSPOL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A84_MD_1_REG_USR_HSPOLMD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0A84_MD_1_REG_USR_INTLAC Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A84_MD_1_REG_USR_INTLACMD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A88_MD_1 (HDMI2P1_MAC_BASE + 0xA88)
    #define HD21MAC_CFG_0A88_MD_1_REG_VSPW Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A88_MD_1_REG_HSPW Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0A8C_MD_1 (HDMI2P1_MAC_BASE + 0xA8C)
    #define HD21MAC_CFG_0A8C_MD_1_REG_VD_FREE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0A8C_MD_1_REG_MIN_VTT Fld(7,8,AC_MSKB1)//[14:8]
#define HD21MAC_CFG_0A90_MD_1 (HDMI2P1_MAC_BASE + 0xA90)
    #define HD21MAC_CFG_0A90_MD_1_REG_COAST_FBD Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0A90_MD_1_REG_VS_SEP_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A90_MD_1_REG_VIDEO_D1L_H Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A90_MD_1_REG_VIDEO_D1L_L Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A90_MD_1_REG_ADC_VIDEO Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0A90_MD_1_REG_CS_CUT_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A90_MD_1_REG_EXTVS_SEPINV Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0A90_MD_1_REG_COAST_SRC Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A90_MD_1_REG_COAST_POL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A94_MD_1 (HDMI2P1_MAC_BASE + 0xA94)
    #define HD21MAC_CFG_0A94_MD_1_REG_COAST_BBD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0A98_MD_1 (HDMI2P1_MAC_BASE + 0xA98)
    #define HD21MAC_CFG_0A98_MD_1_REG_DUMMY26_12_15 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_0A98_MD_1_REG_HTT_FILT_PATCH Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0A98_MD_1_REG_MVOP_DIN_EN_INV Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0A98_MD_1_REG_IP1_CATCH_UP_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0A98_MD_1_REG_IP1_RDY_MASK_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0A98_MD_1_REG_GR_DE_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A98_MD_1_REG_FILTER_NUM Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_0A98_MD_1_REG_GR_HS_VIDEO Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0A98_MD_1_REG_GR_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0A98_MD_1_REG_HVTT_LOSE_MD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0A98_MD_1_REG_IDCLK_INV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0A9C_MD_1 (HDMI2P1_MAC_BASE + 0xA9C)
    #define HD21MAC_CFG_0A9C_MD_1_REG_DUMMY27_9_15 Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_0A9C_MD_1_REG_LOCK_FIELD_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0A9C_MD_1_REG_ATP_FILTERMD Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0A9C_MD_1_REG_DE_ONLY_IDHTT Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0A9C_MD_1_REG_GR_VS_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0A9C_MD_1_REG_VS_PROTECT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0A9C_MD_1_REG_DEGP Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0A9C_MD_1_REG_TEST_BUS_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_0AA0_MD_1 (HDMI2P1_MAC_BASE + 0xAA0)
    #define HD21MAC_CFG_0AA0_MD_1_REG_HTT_ID_FOR_READ Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0AA4_MD_1 (HDMI2P1_MAC_BASE + 0xAA4)
    #define HD21MAC_CFG_0AA4_MD_1_REG_LOCK2LOCK_REPORT Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_0AA4_MD_1_REG_ATRANGE_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0AA4_MD_1_REG_VS_SEP_SEL_1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0AA4_MD_1_REG_VS_SEP_SEL_0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0AA4_MD_1_REG_INTLAC_DET_MODE Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_0AA4_MD_1_REG_EUP_AU_HDTV_DET Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0AA4_MD_1_REG_EUP_HDTV_DET Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0AA4_MD_1_REG_EUP_AUTOFIELD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0AA4_MD_1_REG_EUP_HDTV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0AA8_MD_1 (HDMI2P1_MAC_BASE + 0xAA8)
    #define HD21MAC_CFG_0AA8_MD_1_REG_ATRANGE_VST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0AAC_MD_1 (HDMI2P1_MAC_BASE + 0xAAC)
    #define HD21MAC_CFG_0AAC_MD_1_REG_ATRANGE_HST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0AB0_MD_1 (HDMI2P1_MAC_BASE + 0xAB0)
    #define HD21MAC_CFG_0AB0_MD_1_REG_ATRANGE_VDC Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0AB4_MD_1 (HDMI2P1_MAC_BASE + 0xAB4)
    #define HD21MAC_CFG_0AB4_MD_1_REG_ATRANGE_HDC Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0AB8_MD_1 (HDMI2P1_MAC_BASE + 0xAB8)
    #define HD21MAC_CFG_0AB8_MD_1_REG_GOP_CLK_FREE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0AB8_MD_1_REG_IP2_CLK_GATE_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0ABC_MD_1 (HDMI2P1_MAC_BASE + 0xABC)
    #define HD21MAC_CFG_0ABC_MD_1_REG_DE_BYPASS_MODE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0ABC_MD_1_REG_ATS_2P_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0ABC_MD_1_REG_ATS_DE_HST_FLT_OFF Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0ABC_MD_1_REG_ATS_HST_FLT_OFF Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0ABC_MD_1_REG_ATS_B_SKIP Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0ABC_MD_1_REG_ATS_G_SKIP Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0ABC_MD_1_REG_ATS_R_SKIP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0AC0_MD_1 (HDMI2P1_MAC_BASE + 0xAC0)
    #define HD21MAC_CFG_0AC0_MD_1_REG_INSERT_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0AC0_MD_1_REG_INSERT_NUM Fld(11,0,AC_MSKW10)//[10:0]
#define HD21MAC_CFG_0AC4_MD_1 (HDMI2P1_MAC_BASE + 0xAC4)
    #define HD21MAC_CFG_0AC4_MD_1_REG_LOCK_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0AC4_MD_1_REG_LOCK_NUM Fld(11,0,AC_MSKW10)//[10:0]
#define HD21MAC_CFG_0AC8_MD_1 (HDMI2P1_MAC_BASE + 0xAC8)
    #define HD21MAC_CFG_0AC8_MD_1_REG_MEMSYN_TO_VS_NEW Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_0AC8_MD_1_REG_VLOCK_MD Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0AC8_MD_1_REG_VLOCK_VAL Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_0ACC_MD_1 (HDMI2P1_MAC_BASE + 0xACC)
    #define HD21MAC_CFG_0ACC_MD_1_REG_OP2_COAST_STATUS Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0ACC_MD_1_REG_AUTO_COAST_HV_LOSE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0ACC_MD_1_REG_AUTO_COAST_V_LOSE Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_0ACC_MD_1_REG_AUTO_COAST_H_LOSE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_0ACC_MD_1_REG_NO_SIGNAL_STATUS Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0ACC_MD_1_REG_AUTO_NOS_HV_LOSE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_0ACC_MD_1_REG_AUTO_NOS_V_LOSE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0ACC_MD_1_REG_AUTO_NOS_H_LOSE Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0ACC_MD_1_REG_RGB_CLAMP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0ACC_MD_1_REG_AUTO_NOS_JITTER Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0ACC_MD_1_REG_ATG_NEW_RANGE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0ACC_MD_1_REG_ATG_NEW_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0ACC_MD_1_REG_ATG_NEW_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0AD0_MD_1 (HDMI2P1_MAC_BASE + 0xAD0)
    #define HD21MAC_CFG_0AD0_MD_1_REG_HDMI_VMUTE_DET_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0AD0_MD_1_REG_WDT_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0AD0_MD_1_REG_WDT_VSEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_0AD0_MD_1_REG_WDT_HSEL Fld(4,0,AC_MSKB0)//[3:0]

//Page HDMI21_MAC_4
#define HD21MAC_CFG_0AD4_MD_1 (HDMI2P1_MAC_BASE + 0xAD4)
    #define HD21MAC_CFG_0AD4_MD_1_REG_SOG_VALID Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0AD4_MD_1_REG_CNT_NUMBER_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_0AD4_MD_1_REG_MACROVISION_FILTER_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_0AD4_MD_1_REG_MACROVISION_FILTER_RANGE Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_0AD8_MD_1 (HDMI2P1_MAC_BASE + 0xAD8)
    #define HD21MAC_CFG_0AD8_MD_1_REG_SEL_NEW_CSOURCE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0AD8_MD_1_REG_GENCSOG_RESET Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0AD8_MD_1_REG_EN_OVERCNT Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0AD8_MD_1_REG_OVERCNT Fld(7,0,AC_MSKB0)//[6:0]
#define HD21MAC_CFG_0ADC_MD_1 (HDMI2P1_MAC_BASE + 0xADC)
    #define HD21MAC_CFG_0ADC_MD_1_REG_INTLAC_DET_EN Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_0AE0_MD_1 (HDMI2P1_MAC_BASE + 0xAE0)
    #define HD21MAC_CFG_0AE0_MD_1_REG_INTLAC_DET_ALL Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_0AE4_MD_1 (HDMI2P1_MAC_BASE + 0xAE4)
    #define HD21MAC_CFG_0AE4_MD_1_REG_FIELD_DET_EN Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_0AE8_MD_1 (HDMI2P1_MAC_BASE + 0xAE8)
    #define HD21MAC_CFG_0AE8_MD_1_REG_FIELD_DET_ALL Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_0AEC_MD_1 (HDMI2P1_MAC_BASE + 0xAEC)
    #define HD21MAC_CFG_0AEC_MD_1_REG_SPR_V_LOCK_P_IP_CNT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0AF0_MD_1 (HDMI2P1_MAC_BASE + 0xAF0)
    #define HD21MAC_CFG_0AF0_MD_1_REG_SPR_V_LOCK_P_IP_CNT_1 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_0AF4_MD_1 (HDMI2P1_MAC_BASE + 0xAF4)
    #define HD21MAC_CFG_0AF4_MD_1_REG_HTT_RPT_MD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0AF8_MD_1 (HDMI2P1_MAC_BASE + 0xAF8)
    #define HD21MAC_CFG_0AF8_MD_1_REG_IPM_TRIG_VCNT_2ND_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0AF8_MD_1_REG_IPM_TRIG_VCNT_2ND Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0AFC_MD_1 (HDMI2P1_MAC_BASE + 0xAFC)
    #define HD21MAC_CFG_0AFC_MD_1_REG_ATGSEL_VALUE_Q Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_0B00_MD_1 (HDMI2P1_MAC_BASE + 0xB00)
    #define HD21MAC_CFG_0B00_MD_1_REG_TEST_YINI Fld(3,11,AC_MSKB1)//[13:11]
    #define HD21MAC_CFG_0B00_MD_1_REG_TEST_XINI Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_0B00_MD_1_REG_TEST_BLK_WHT_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0B00_MD_1_REG_TEST_REGION_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0B00_MD_1_REG_TEST_REGION_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0B00_MD_1_REG_TEST_GRAY_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0B00_MD_1_REG_F_TEST_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0B00_MD_1_REG_V_TEST_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0B00_MD_1_REG_H_TEST_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0B04_MD_1 (HDMI2P1_MAC_BASE + 0xB04)
    #define HD21MAC_CFG_0B04_MD_1_REG_TEST_VSIZE Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_0B04_MD_1_REG_TEST_VST Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_0B04_MD_1_REG_TEST_HSIZE Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_0B04_MD_1_REG_TEST_HST Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_0B08_MD_1 (HDMI2P1_MAC_BASE + 0xB08)
    #define HD21MAC_CFG_0B08_MD_1_REG_TEST_CB_V_WIDTH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0B08_MD_1_REG_TEST_CB_H_WIDTH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0B0C_MD_1 (HDMI2P1_MAC_BASE + 0xB0C)
    #define HD21MAC_CFG_0B0C_MD_1_REG_TEST_SHIFT_TIME Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0B10_MD_1 (HDMI2P1_MAC_BASE + 0xB10)
    #define HD21MAC_CFG_0B10_MD_1_REG_MEMSYN_TO_VS_FULLRG Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0B10_MD_1_REG_MEMSYN_TO_VS_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0B14_MD_1 (HDMI2P1_MAC_BASE + 0xB14)
    #define HD21MAC_CFG_0B14_MD_1_REG_EDCLK_PD_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0B14_MD_1_REG_EDCLK_PD_ST Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0B18_MD_1 (HDMI2P1_MAC_BASE + 0xB18)
    #define HD21MAC_CFG_0B18_MD_1_REG_MEMSYN_TO_CMDQ_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0B1C_MD_1 (HDMI2P1_MAC_BASE + 0xB1C)
    #define HD21MAC_CFG_0B1C_MD_1_REG_IPM_TRIG_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0B20_MD_1 (HDMI2P1_MAC_BASE + 0xB20)
    #define HD21MAC_CFG_0B20_MD_1_REG_FDET_CHECK_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_0B20_MD_1_REG_FDET_H_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0B20_MD_1_REG_FDET_V_INV Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0B20_MD_1_REG_FDET_VTOTAL_PIX_CNT_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0B20_MD_1_REG_FDET_SYNC_SRC_SEL Fld(2,1,AC_MSKB0)//[2:1]
    #define HD21MAC_CFG_0B20_MD_1_REG_FDET_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0B24_MD_1 (HDMI2P1_MAC_BASE + 0xB24)
    #define HD21MAC_CFG_0B24_MD_1_REG_FDET_VTOTAL_TOR Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0B24_MD_1_REG_FDET_VWIDTH_TOR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0B28_MD_1 (HDMI2P1_MAC_BASE + 0xB28)
    #define HD21MAC_CFG_0B28_MD_1_REG_FDET_STATUS_INTLAC_DET2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0B28_MD_1_REG_FDET_STATUS_INTLAC_DET1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0B28_MD_1_REG_FDET_STATUS_INTLAC_DET0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0B2C_MD_1 (HDMI2P1_MAC_BASE + 0xB2C)
    #define HD21MAC_CFG_0B2C_MD_1_REG_FDET_STATUS_VWIDTH0 Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_0B30_MD_1 (HDMI2P1_MAC_BASE + 0xB30)
    #define HD21MAC_CFG_0B30_MD_1_REG_FDET_STATUS_VWIDTH1 Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_0B34_MD_1 (HDMI2P1_MAC_BASE + 0xB34)
    #define HD21MAC_CFG_0B34_MD_1_REG_FDET_STATUS_VTOTAL0_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0B38_MD_1 (HDMI2P1_MAC_BASE + 0xB38)
    #define HD21MAC_CFG_0B38_MD_1_REG_FDET_STATUS_VTOTAL0_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_0B3C_MD_1 (HDMI2P1_MAC_BASE + 0xB3C)
    #define HD21MAC_CFG_0B3C_MD_1_REG_FDET_STATUS_VTOTAL1_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0B40_MD_1 (HDMI2P1_MAC_BASE + 0xB40)
    #define HD21MAC_CFG_0B40_MD_1_REG_FDET_STATUS_VTOTAL1_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_0B44_MD_1 (HDMI2P1_MAC_BASE + 0xB44)
    #define HD21MAC_CFG_0B44_MD_1_REG_FDET_STATUS_VTOTAL2_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0B48_MD_1 (HDMI2P1_MAC_BASE + 0xB48)
    #define HD21MAC_CFG_0B48_MD_1_REG_FDET_STATUS_VTOTAL2_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_0B4C_MD_1 (HDMI2P1_MAC_BASE + 0xB4C)
    #define HD21MAC_CFG_0B4C_MD_1_REG_FDET_STATUS_VTOTAL3_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0B50_MD_1 (HDMI2P1_MAC_BASE + 0xB50)
    #define HD21MAC_CFG_0B50_MD_1_REG_FDET_STATUS_VTOTAL3_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_0B7C_MD_1 (HDMI2P1_MAC_BASE + 0xB7C)
    #define HD21MAC_CFG_0B7C_MD_1_REG_IPVS_SW_TRIG Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0B80_MD_1 (HDMI2P1_MAC_BASE + 0xB80)
    #define HD21MAC_CFG_0B80_MD_1_REG_ATRANGE_DBG_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0B80_MD_1_REG_ATRANGE_DBG_R Fld(5,10,AC_MSKB1)//[14:10]
    #define HD21MAC_CFG_0B80_MD_1_REG_ATRANGE_DBG_G Fld(5,5,AC_MSKW10)//[9:5]
    #define HD21MAC_CFG_0B80_MD_1_REG_ATRANGE_DBG_B Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_0B84_MD_1 (HDMI2P1_MAC_BASE + 0xB84)
    #define HD21MAC_CFG_0B84_MD_1_REG_IP1_HDMI422_2P_CBCR_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0B84_MD_1_REG_IP1_HDMI422_2P_RB_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_0B84_MD_1_REG_IP1_HDMI422_2P_MANUAL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0B84_MD_1_REG_IP1_HDMI422_2P_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0B84_MD_1_REG_IP1_HDMI422_2P_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0B88_MD_1 (HDMI2P1_MAC_BASE + 0xB88)
    #define HD21MAC_CFG_0B88_MD_1_REG_DE_ONLY_HSTOL_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0B88_MD_1_REG_DE_ONLY_HSTOL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_0B8C_MD_1 (HDMI2P1_MAC_BASE + 0xB8C)
    #define HD21MAC_CFG_0B8C_MD_1_REG_OHT_AUTO_DET Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0B8C_MD_1_REG_OHT_AUTO_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0B90_MD_1 (HDMI2P1_MAC_BASE + 0xB90)
    #define HD21MAC_CFG_0B90_MD_1_REG_DEONLY_NEW_HS Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_0B90_MD_1_REG_IPHS_DB_EDGE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0B90_MD_1_REG_IPHS_SB_P_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0B94_MD_1 (HDMI2P1_MAC_BASE + 0xB94)
    #define HD21MAC_CFG_0B94_MD_1_REG_USR_VPOL_VS_WIDTH_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0B94_MD_1_REG_USR_VPOL_VS_WIDTH Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_0B98_MD_1 (HDMI2P1_MAC_BASE + 0xB98)
    #define HD21MAC_CFG_0B98_MD_1_REG_FULL_DELAYLN_NUM_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_0B98_MD_1_REG_FULL_DELAYLN_NUM Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_0BC0_MD_1 (HDMI2P1_MAC_BASE + 0xBC0)
    #define HD21MAC_CFG_0BC0_MD_1_REG_DUMMY70_8_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0BC0_MD_1_REG_IP1_VH_MNTR_VMD Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_0BC0_MD_1_REG_IP1_VH_MNTR_HMD Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_0BC0_MD_1_REG_IP1_VH_MNTR_V_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0BC0_MD_1_REG_IP1_VH_MNTR_H_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0BC4_MD_1 (HDMI2P1_MAC_BASE + 0xBC4)
    #define HD21MAC_CFG_0BC4_MD_1_REG_IP1_VH_MNTR_VTOR Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_0BC4_MD_1_REG_IP1_VH_MNTR_HTOR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_0BDC_MD_1 (HDMI2P1_MAC_BASE + 0xBDC)
    #define HD21MAC_CFG_0BDC_MD_1_REG_SC_FE_TOP_BYPASS_INPUT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0BDC_MD_1_REG_SC_FE_TOP_FLOCK_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0BDC_MD_1_REG_SC_FE_TOP_TESTCS_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0C04_MD_WP_1 (HDMI2P1_MAC_BASE + 0xC04)
    #define HD21MAC_CFG_0C04_MD_WP_1_REG_DBL_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_0C04_MD_WP_1_REG_DBL_EN Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_0C08_MD_WP_1 (HDMI2P1_MAC_BASE + 0xC08)
    #define HD21MAC_CFG_0C08_MD_WP_1_REG_IP_SW_RST_OSC Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_0C08_MD_WP_1_REG_IP_SW_RST_IP Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_0C08_MD_WP_1_REG_IP_SW_RST_ALL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0C0C_MD_WP_1 (HDMI2P1_MAC_BASE + 0xC0C)
    #define HD21MAC_CFG_0C0C_MD_WP_1_REG_NO_SIGNAL_GEN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_0C0C_MD_WP_1_REG_PDMD_ID Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0C10_MD_WP_1 (HDMI2P1_MAC_BASE + 0xC10)
    #define HD21MAC_CFG_0C10_MD_WP_1_REG_CHG_HMD Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0C10_MD_WP_1_REG_IPVS_INT_EDGE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0C68_MD_WP_1 (HDMI2P1_MAC_BASE + 0xC68)
    #define HD21MAC_CFG_0C68_MD_WP_1_REG_HTT_CHG_READ Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0C80_MD_WP_1 (HDMI2P1_MAC_BASE + 0xC80)
    #define HD21MAC_CFG_0C80_MD_WP_1_REG_IP1_WP_FIELD_INV Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_0C80_MD_WP_1_REG_IP1_WP_VS_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_0C80_MD_WP_1_REG_IP1_WP_FIELD_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_0C80_MD_WP_1_REG_IP1_WP_VS_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0C84_MD_WP_1 (HDMI2P1_MAC_BASE + 0xC84)
    #define HD21MAC_CFG_0C84_MD_WP_1_REG_MVOP_DIN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_0D00_MD_WP_1 (HDMI2P1_MAC_BASE + 0xD00)
    #define HD21MAC_CFG_0D00_MD_WP_1_REG_C_IRQ_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0D04_MD_WP_1 (HDMI2P1_MAC_BASE + 0xD04)
    #define HD21MAC_CFG_0D04_MD_WP_1_REG_C_IRQ_CLR Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0D08_MD_WP_1 (HDMI2P1_MAC_BASE + 0xD08)
    #define HD21MAC_CFG_0D08_MD_WP_1_REG_C_IRQ_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0D0C_MD_WP_1 (HDMI2P1_MAC_BASE + 0xD0C)
    #define HD21MAC_CFG_0D0C_MD_WP_1_REG_IRQ_FINAL_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0D10_MD_WP_1 (HDMI2P1_MAC_BASE + 0xD10)
    #define HD21MAC_CFG_0D10_MD_WP_1_REG_IRQ_RAW_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0DF8_MD_WP_1 (HDMI2P1_MAC_BASE + 0xDF8)
    #define HD21MAC_CFG_0DF8_MD_WP_1_REG_DUMMY_7F_SETH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_0DFC_MD_WP_1 (HDMI2P1_MAC_BASE + 0xDFC)
    #define HD21MAC_CFG_0DFC_MD_WP_1_REG_DUMMY_7F_SETL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1238_DSCD (HDMI2P1_MAC_BASE + 0x1238)
    #define HD21MAC_CFG_1238_DSCD_REG_BISTFAIL_DSCD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_123C_DSCD (HDMI2P1_MAC_BASE + 0x123C)
    #define HD21MAC_CFG_123C_DSCD_REG_BISTFAIL_DSCD_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1240_DSCD (HDMI2P1_MAC_BASE + 0x1240)
    #define HD21MAC_CFG_1240_DSCD_REG_PPS1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1240_DSCD_REG_PPS0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1244_DSCD (HDMI2P1_MAC_BASE + 0x1244)
    #define HD21MAC_CFG_1244_DSCD_REG_PPS3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1244_DSCD_REG_PPS2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1248_DSCD (HDMI2P1_MAC_BASE + 0x1248)
    #define HD21MAC_CFG_1248_DSCD_REG_PPS5 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1248_DSCD_REG_PPS4 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_124C_DSCD (HDMI2P1_MAC_BASE + 0x124C)
    #define HD21MAC_CFG_124C_DSCD_REG_PPS7 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_124C_DSCD_REG_PPS6 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1250_DSCD (HDMI2P1_MAC_BASE + 0x1250)
    #define HD21MAC_CFG_1250_DSCD_REG_PPS9 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1250_DSCD_REG_PPS8 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1254_DSCD (HDMI2P1_MAC_BASE + 0x1254)
    #define HD21MAC_CFG_1254_DSCD_REG_PPS11 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1254_DSCD_REG_PPS10 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1258_DSCD (HDMI2P1_MAC_BASE + 0x1258)
    #define HD21MAC_CFG_1258_DSCD_REG_PPS13 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1258_DSCD_REG_PPS12 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_125C_DSCD (HDMI2P1_MAC_BASE + 0x125C)
    #define HD21MAC_CFG_125C_DSCD_REG_PPS15 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_125C_DSCD_REG_PPS14 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1260_DSCD (HDMI2P1_MAC_BASE + 0x1260)
    #define HD21MAC_CFG_1260_DSCD_REG_PPS17 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1260_DSCD_REG_PPS16 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1264_DSCD (HDMI2P1_MAC_BASE + 0x1264)
    #define HD21MAC_CFG_1264_DSCD_REG_PPS19 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1264_DSCD_REG_PPS18 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1268_DSCD (HDMI2P1_MAC_BASE + 0x1268)
    #define HD21MAC_CFG_1268_DSCD_REG_PPS21 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1268_DSCD_REG_PPS20 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_126C_DSCD (HDMI2P1_MAC_BASE + 0x126C)
    #define HD21MAC_CFG_126C_DSCD_REG_PPS23 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_126C_DSCD_REG_PPS22 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1270_DSCD (HDMI2P1_MAC_BASE + 0x1270)
    #define HD21MAC_CFG_1270_DSCD_REG_PPS25 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1270_DSCD_REG_PPS24 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1274_DSCD (HDMI2P1_MAC_BASE + 0x1274)
    #define HD21MAC_CFG_1274_DSCD_REG_PPS27 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1274_DSCD_REG_PPS26 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1278_DSCD (HDMI2P1_MAC_BASE + 0x1278)
    #define HD21MAC_CFG_1278_DSCD_REG_PPS29 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1278_DSCD_REG_PPS28 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_127C_DSCD (HDMI2P1_MAC_BASE + 0x127C)
    #define HD21MAC_CFG_127C_DSCD_REG_PPS31 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_127C_DSCD_REG_PPS30 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1280_DSCD (HDMI2P1_MAC_BASE + 0x1280)
    #define HD21MAC_CFG_1280_DSCD_REG_PPS33 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1280_DSCD_REG_PPS32 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1284_DSCD (HDMI2P1_MAC_BASE + 0x1284)
    #define HD21MAC_CFG_1284_DSCD_REG_PPS35 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1284_DSCD_REG_PPS34 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1288_DSCD (HDMI2P1_MAC_BASE + 0x1288)
    #define HD21MAC_CFG_1288_DSCD_REG_PPS37 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1288_DSCD_REG_PPS36 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_128C_DSCD (HDMI2P1_MAC_BASE + 0x128C)
    #define HD21MAC_CFG_128C_DSCD_REG_PPS39 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_128C_DSCD_REG_PPS38 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1290_DSCD (HDMI2P1_MAC_BASE + 0x1290)
    #define HD21MAC_CFG_1290_DSCD_REG_PPS41 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1290_DSCD_REG_PPS40 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1294_DSCD (HDMI2P1_MAC_BASE + 0x1294)
    #define HD21MAC_CFG_1294_DSCD_REG_PPS43 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1294_DSCD_REG_PPS42 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1298_DSCD (HDMI2P1_MAC_BASE + 0x1298)
    #define HD21MAC_CFG_1298_DSCD_REG_PPS45 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1298_DSCD_REG_PPS44 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_129C_DSCD (HDMI2P1_MAC_BASE + 0x129C)
    #define HD21MAC_CFG_129C_DSCD_REG_PPS47 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_129C_DSCD_REG_PPS46 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12A0_DSCD (HDMI2P1_MAC_BASE + 0x12A0)
    #define HD21MAC_CFG_12A0_DSCD_REG_PPS49 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12A0_DSCD_REG_PPS48 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12A4_DSCD (HDMI2P1_MAC_BASE + 0x12A4)
    #define HD21MAC_CFG_12A4_DSCD_REG_PPS51 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12A4_DSCD_REG_PPS50 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12A8_DSCD (HDMI2P1_MAC_BASE + 0x12A8)
    #define HD21MAC_CFG_12A8_DSCD_REG_PPS53 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12A8_DSCD_REG_PPS52 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12AC_DSCD (HDMI2P1_MAC_BASE + 0x12AC)
    #define HD21MAC_CFG_12AC_DSCD_REG_PPS55 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12AC_DSCD_REG_PPS54 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12B0_DSCD (HDMI2P1_MAC_BASE + 0x12B0)
    #define HD21MAC_CFG_12B0_DSCD_REG_PPS57 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12B0_DSCD_REG_PPS56 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12B4_DSCD (HDMI2P1_MAC_BASE + 0x12B4)
    #define HD21MAC_CFG_12B4_DSCD_REG_PPS59 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12B4_DSCD_REG_PPS58 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12B8_DSCD (HDMI2P1_MAC_BASE + 0x12B8)
    #define HD21MAC_CFG_12B8_DSCD_REG_PPS61 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12B8_DSCD_REG_PPS60 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12BC_DSCD (HDMI2P1_MAC_BASE + 0x12BC)
    #define HD21MAC_CFG_12BC_DSCD_REG_PPS63 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12BC_DSCD_REG_PPS62 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12C0_DSCD (HDMI2P1_MAC_BASE + 0x12C0)
    #define HD21MAC_CFG_12C0_DSCD_REG_PPS65 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12C0_DSCD_REG_PPS64 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12C4_DSCD (HDMI2P1_MAC_BASE + 0x12C4)
    #define HD21MAC_CFG_12C4_DSCD_REG_PPS67 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12C4_DSCD_REG_PPS66 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12C8_DSCD (HDMI2P1_MAC_BASE + 0x12C8)
    #define HD21MAC_CFG_12C8_DSCD_REG_PPS69 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12C8_DSCD_REG_PPS68 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12CC_DSCD (HDMI2P1_MAC_BASE + 0x12CC)
    #define HD21MAC_CFG_12CC_DSCD_REG_PPS71 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12CC_DSCD_REG_PPS70 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12D0_DSCD (HDMI2P1_MAC_BASE + 0x12D0)
    #define HD21MAC_CFG_12D0_DSCD_REG_PPS73 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12D0_DSCD_REG_PPS72 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12D4_DSCD (HDMI2P1_MAC_BASE + 0x12D4)
    #define HD21MAC_CFG_12D4_DSCD_REG_PPS75 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12D4_DSCD_REG_PPS74 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12D8_DSCD (HDMI2P1_MAC_BASE + 0x12D8)
    #define HD21MAC_CFG_12D8_DSCD_REG_PPS77 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12D8_DSCD_REG_PPS76 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12DC_DSCD (HDMI2P1_MAC_BASE + 0x12DC)
    #define HD21MAC_CFG_12DC_DSCD_REG_PPS79 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12DC_DSCD_REG_PPS78 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12E0_DSCD (HDMI2P1_MAC_BASE + 0x12E0)
    #define HD21MAC_CFG_12E0_DSCD_REG_PPS81 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12E0_DSCD_REG_PPS80 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12E4_DSCD (HDMI2P1_MAC_BASE + 0x12E4)
    #define HD21MAC_CFG_12E4_DSCD_REG_PPS83 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12E4_DSCD_REG_PPS82 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12E8_DSCD (HDMI2P1_MAC_BASE + 0x12E8)
    #define HD21MAC_CFG_12E8_DSCD_REG_PPS85 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12E8_DSCD_REG_PPS84 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12EC_DSCD (HDMI2P1_MAC_BASE + 0x12EC)
    #define HD21MAC_CFG_12EC_DSCD_REG_PPS87 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12EC_DSCD_REG_PPS86 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12F0_DSCD (HDMI2P1_MAC_BASE + 0x12F0)
    #define HD21MAC_CFG_12F0_DSCD_REG_PPS89 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12F0_DSCD_REG_PPS88 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12F4_DSCD (HDMI2P1_MAC_BASE + 0x12F4)
    #define HD21MAC_CFG_12F4_DSCD_REG_PPS91 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12F4_DSCD_REG_PPS90 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12F8_DSCD (HDMI2P1_MAC_BASE + 0x12F8)
    #define HD21MAC_CFG_12F8_DSCD_REG_PPS93 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12F8_DSCD_REG_PPS92 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_12FC_DSCD (HDMI2P1_MAC_BASE + 0x12FC)
    #define HD21MAC_CFG_12FC_DSCD_REG_PPS95 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_12FC_DSCD_REG_PPS94 Fld(8,8,AC_FULLB1)//[15:8]

    //Page HDMI21_MAC_5
#define HD21MAC_CFG_1300_DSCD (HDMI2P1_MAC_BASE + 0x1300)
    #define HD21MAC_CFG_1300_DSCD_REG_PPS97 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1300_DSCD_REG_PPS96 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1304_DSCD (HDMI2P1_MAC_BASE + 0x1304)
    #define HD21MAC_CFG_1304_DSCD_REG_PPS99 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1304_DSCD_REG_PPS98 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1308_DSCD (HDMI2P1_MAC_BASE + 0x1308)
    #define HD21MAC_CFG_1308_DSCD_REG_PPS101 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1308_DSCD_REG_PPS100 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_130C_DSCD (HDMI2P1_MAC_BASE + 0x130C)
    #define HD21MAC_CFG_130C_DSCD_REG_PPS103 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_130C_DSCD_REG_PPS102 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1310_DSCD (HDMI2P1_MAC_BASE + 0x1310)
    #define HD21MAC_CFG_1310_DSCD_REG_PPS105 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1310_DSCD_REG_PPS104 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1314_DSCD (HDMI2P1_MAC_BASE + 0x1314)
    #define HD21MAC_CFG_1314_DSCD_REG_PPS107 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1314_DSCD_REG_PPS106 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1318_DSCD (HDMI2P1_MAC_BASE + 0x1318)
    #define HD21MAC_CFG_1318_DSCD_REG_PPS109 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1318_DSCD_REG_PPS108 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_131C_DSCD (HDMI2P1_MAC_BASE + 0x131C)
    #define HD21MAC_CFG_131C_DSCD_REG_PPS111 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_131C_DSCD_REG_PPS110 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1320_DSCD (HDMI2P1_MAC_BASE + 0x1320)
    #define HD21MAC_CFG_1320_DSCD_REG_PPS113 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1320_DSCD_REG_PPS112 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1324_DSCD (HDMI2P1_MAC_BASE + 0x1324)
    #define HD21MAC_CFG_1324_DSCD_REG_PPS115 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1324_DSCD_REG_PPS114 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1328_DSCD (HDMI2P1_MAC_BASE + 0x1328)
    #define HD21MAC_CFG_1328_DSCD_REG_PPS117 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1328_DSCD_REG_PPS116 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_132C_DSCD (HDMI2P1_MAC_BASE + 0x132C)
    #define HD21MAC_CFG_132C_DSCD_REG_PPS119 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_132C_DSCD_REG_PPS118 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1330_DSCD (HDMI2P1_MAC_BASE + 0x1330)
    #define HD21MAC_CFG_1330_DSCD_REG_PPS121 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1330_DSCD_REG_PPS120 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1334_DSCD (HDMI2P1_MAC_BASE + 0x1334)
    #define HD21MAC_CFG_1334_DSCD_REG_PPS123 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1334_DSCD_REG_PPS122 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1338_DSCD (HDMI2P1_MAC_BASE + 0x1338)
    #define HD21MAC_CFG_1338_DSCD_REG_PPS125 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1338_DSCD_REG_PPS124 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_133C_DSCD (HDMI2P1_MAC_BASE + 0x133C)
    #define HD21MAC_CFG_133C_DSCD_REG_PPS127 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_133C_DSCD_REG_PPS126 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_1340_DSCD (HDMI2P1_MAC_BASE + 0x1340)
    #define HD21MAC_CFG_1340_DSCD_REG_ENTROPY_SHIFT_BLANKING Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1344_DSCD (HDMI2P1_MAC_BASE + 0x1344)
    #define HD21MAC_CFG_1344_DSCD_REG_ENTROPY_SHIFT_BLANKING_SLICE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1348_DSCD (HDMI2P1_MAC_BASE + 0x1348)
    #define HD21MAC_CFG_1348_DSCD_REG_CTXSW_R_TIME Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1348_DSCD_REG_CTXSW_W_TIME Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_134C_DSCD (HDMI2P1_MAC_BASE + 0x134C)
    #define HD21MAC_CFG_134C_DSCD_REG_READ_BACK_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_134C_DSCD_REG_READ_BACK_AUTO_VSYNC_RST Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_134C_DSCD_REG_INI_DEC_LINE_DELAY_Q1M Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_134C_DSCD_REG_SHIFT_EN_TRIG_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_134C_DSCD_REG_IN_BUF_ACC_BYPASS Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_134C_DSCD_REG_SLICE_NUM Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_1350_DSCD (HDMI2P1_MAC_BASE + 0x1350)
    #define HD21MAC_CFG_1350_DSCD_REG_INI_DEC_DELAY_USER Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1354_DSCD (HDMI2P1_MAC_BASE + 0x1354)
    #define HD21MAC_CFG_1354_DSCD_REG_INI_DEC_LINE_DELAY Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1358_DSCD (HDMI2P1_MAC_BASE + 0x1358)
    #define HD21MAC_CFG_1358_DSCD_REG_IN_BUF_FULL_READ_BACK Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1358_DSCD_REG_RB_EMPTY_READ_BACK Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_135C_DSCD (HDMI2P1_MAC_BASE + 0x135C)
    #define HD21MAC_CFG_135C_DSCD_REG_READ_BACK_MASK Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_135C_DSCD_REG_OUT_BUF_FULL_READ_BACK Fld(3,1,AC_MSKB0)//[3:1]
    #define HD21MAC_CFG_135C_DSCD_REG_IN_AFF_FULL_READ_BACK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1360_DSCD (HDMI2P1_MAC_BASE + 0x1360)
    #define HD21MAC_CFG_1360_DSCD_REG_PPS_RB_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1364_DSCD (HDMI2P1_MAC_BASE + 0x1364)
    #define HD21MAC_CFG_1364_DSCD_REG_PPS128OR4BYTE_IN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1380_DSCD (HDMI2P1_MAC_BASE + 0x1380)
    #define HD21MAC_CFG_1380_DSCD_REG_PPS_RB_32BYTE_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1380_DSCD_REG_PPS_RB_32BYTE_0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1384_DSCD (HDMI2P1_MAC_BASE + 0x1384)
    #define HD21MAC_CFG_1384_DSCD_REG_PPS_RB_32BYTE_3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1384_DSCD_REG_PPS_RB_32BYTE_2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1388_DSCD (HDMI2P1_MAC_BASE + 0x1388)
    #define HD21MAC_CFG_1388_DSCD_REG_PPS_RB_32BYTE_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1388_DSCD_REG_PPS_RB_32BYTE_4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_138C_DSCD (HDMI2P1_MAC_BASE + 0x138C)
    #define HD21MAC_CFG_138C_DSCD_REG_PPS_RB_32BYTE_7 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_138C_DSCD_REG_PPS_RB_32BYTE_6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1390_DSCD (HDMI2P1_MAC_BASE + 0x1390)
    #define HD21MAC_CFG_1390_DSCD_REG_PPS_RB_32BYTE_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1390_DSCD_REG_PPS_RB_32BYTE_8 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1394_DSCD (HDMI2P1_MAC_BASE + 0x1394)
    #define HD21MAC_CFG_1394_DSCD_REG_PPS_RB_32BYTE_11 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1394_DSCD_REG_PPS_RB_32BYTE_10 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1398_DSCD (HDMI2P1_MAC_BASE + 0x1398)
    #define HD21MAC_CFG_1398_DSCD_REG_PPS_RB_32BYTE_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1398_DSCD_REG_PPS_RB_32BYTE_12 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_139C_DSCD (HDMI2P1_MAC_BASE + 0x139C)
    #define HD21MAC_CFG_139C_DSCD_REG_PPS_RB_32BYTE_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_139C_DSCD_REG_PPS_RB_32BYTE_14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_13A0_DSCD (HDMI2P1_MAC_BASE + 0x13A0)
    #define HD21MAC_CFG_13A0_DSCD_REG_PPS_RB_32BYTE_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_13A0_DSCD_REG_PPS_RB_32BYTE_16 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_13A4_DSCD (HDMI2P1_MAC_BASE + 0x13A4)
    #define HD21MAC_CFG_13A4_DSCD_REG_PPS_RB_32BYTE_19 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_13A4_DSCD_REG_PPS_RB_32BYTE_18 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_13A8_DSCD (HDMI2P1_MAC_BASE + 0x13A8)
    #define HD21MAC_CFG_13A8_DSCD_REG_PPS_RB_32BYTE_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_13A8_DSCD_REG_PPS_RB_32BYTE_20 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_13AC_DSCD (HDMI2P1_MAC_BASE + 0x13AC)
    #define HD21MAC_CFG_13AC_DSCD_REG_PPS_RB_32BYTE_23 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_13AC_DSCD_REG_PPS_RB_32BYTE_22 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_13B0_DSCD (HDMI2P1_MAC_BASE + 0x13B0)
    #define HD21MAC_CFG_13B0_DSCD_REG_PPS_RB_32BYTE_25 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_13B0_DSCD_REG_PPS_RB_32BYTE_24 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_13B4_DSCD (HDMI2P1_MAC_BASE + 0x13B4)
    #define HD21MAC_CFG_13B4_DSCD_REG_PPS_RB_32BYTE_27 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_13B4_DSCD_REG_PPS_RB_32BYTE_26 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_13B8_DSCD (HDMI2P1_MAC_BASE + 0x13B8)
    #define HD21MAC_CFG_13B8_DSCD_REG_PPS_RB_32BYTE_29 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_13B8_DSCD_REG_PPS_RB_32BYTE_28 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_13BC_DSCD (HDMI2P1_MAC_BASE + 0x13BC)
    #define HD21MAC_CFG_13BC_DSCD_REG_PPS_RB_32BYTE_31 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_13BC_DSCD_REG_PPS_RB_32BYTE_30 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_13E0_DSCD (HDMI2P1_MAC_BASE + 0x13E0)
    #define HD21MAC_CFG_13E0_DSCD_REG_OUTPUT_CRC_WRAP_CNT Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_13E0_DSCD_REG_INPUT_CRC_WRAP_CNT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_13E0_DSCD_REG_CRC_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_13E0_DSCD_REG_422_OUT_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_13E0_DSCD_REG_USE_STR_PPS Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_13E0_DSCD_REG_SLICE_WIDTH_AUTO_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_13E0_DSCD_REG_INI_DEC_DELAY_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_13E0_DSCD_REG_AUTO_SLICE_ID_CHG Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_13E0_DSCD_REG_SW_RST_VSYNC Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_13E0_DSCD_REG_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_13E4_DSCD (HDMI2P1_MAC_BASE + 0x13E4)
    #define HD21MAC_CFG_13E4_DSCD_REG_INPUT_CRC_R_CR Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_13E8_DSCD (HDMI2P1_MAC_BASE + 0x13E8)
    #define HD21MAC_CFG_13E8_DSCD_REG_INPUT_CRC_G_Y Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_13EC_DSCD (HDMI2P1_MAC_BASE + 0x13EC)
    #define HD21MAC_CFG_13EC_DSCD_REG_INPUT_CRC_B_CB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_13F0_DSCD (HDMI2P1_MAC_BASE + 0x13F0)
    #define HD21MAC_CFG_13F0_DSCD_REG_OUTPUT_CRC_R_CR Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_13F4_DSCD (HDMI2P1_MAC_BASE + 0x13F4)
    #define HD21MAC_CFG_13F4_DSCD_REG_OUTPUT_CRC_G_Y Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_13F8_DSCD (HDMI2P1_MAC_BASE + 0x13F8)
    #define HD21MAC_CFG_13F8_DSCD_REG_OUTPUT_CRC_B_CB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_13FC_DSCD (HDMI2P1_MAC_BASE + 0x13FC)
    #define HD21MAC_CFG_13FC_DSCD_REG_OUTPUT_CRC_TEST_CONFIG Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_1800_GP_TOP (HDMI2P1_MAC_BASE + 0x1800)
    #define HD21MAC_CFG_1800_GP_TOP_REG_DET_CKDIV_CNT_MISC Fld(6,6,AC_MSKW10)//[11:6]
    #define HD21MAC_CFG_1800_GP_TOP_REG_DET_CKSEL_MISC Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_1804_GP_TOP (HDMI2P1_MAC_BASE + 0x1804)
    #define HD21MAC_CFG_1804_GP_TOP_REG_DVI2MIU_CKSEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_1804_GP_TOP_REG_RX2TX_HDCP8P_PORT_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_1804_GP_TOP_REG_DVI2MIU_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1804_GP_TOP_REG_CFG_OUT_PIN_DSD_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1804_GP_TOP_REG_I2S_MCLK_192FS_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1804_GP_TOP_REG_AUMCKO_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_1804_GP_TOP_REG_DP_AUD_HBR_CTRL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1808_GP_TOP (HDMI2P1_MAC_BASE + 0x1808)
    #define HD21MAC_CFG_1808_GP_TOP_REG_AU_CLK_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_1808_GP_TOP_REG_CKG_STANDBY_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_180C_GP_TOP (HDMI2P1_MAC_BASE + 0x180C)
    #define HD21MAC_CFG_180C_GP_TOP_REG_CLKGEN_EN_MISC_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1810_GP_TOP (HDMI2P1_MAC_BASE + 0x1810)
    #define HD21MAC_CFG_1810_GP_TOP_REG_CLKGEN_EN_MISC_1 Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_1814_GP_TOP (HDMI2P1_MAC_BASE + 0x1814)
    #define HD21MAC_CFG_1814_GP_TOP_REG_CLKGEN_INV_MISC Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1818_GP_TOP (HDMI2P1_MAC_BASE + 0x1818)
    #define HD21MAC_CFG_1818_GP_TOP_REG_CLK_XTALI_DIV2_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1818_GP_TOP_REG_DVI_TESTMUX_SEL Fld(3,6,AC_MSKW10)//[8:6]
    #define HD21MAC_CFG_1818_GP_TOP_REG_DVI2MIU_CLK_DIV2_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1818_GP_TOP_REG_CLK_EXTMD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1818_GP_TOP_REG_TST_CLKMUX_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_1818_GP_TOP_REG_TST_CLKMUX Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1818_GP_TOP_REG_PDALL_NEG Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_181C_GP_TOP (HDMI2P1_MAC_BASE + 0x181C)
    #define HD21MAC_CFG_181C_GP_TOP_REG_MISC_CLK_INV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_181C_GP_TOP_REG_PD_MISC_CLK Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1820_GP_TOP (HDMI2P1_MAC_BASE + 0x1820)
    #define HD21MAC_CFG_1820_GP_TOP_REG_CLK_CTSN_TMDS_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1820_GP_TOP_REG_DVI2MIU_NEW_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1820_GP_TOP_REG_DVI2MIU_SD_CKSEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1820_GP_TOP_REG_CLK_FOR_CTSN_DIV2_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1820_GP_TOP_REG_AUDIO_SRC_SEL_CAPY_DBG Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1840_GP_TOP (HDMI2P1_MAC_BASE + 0x1840)
    #define HD21MAC_CFG_1840_GP_TOP_REG_1P2P_EN_P0 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1840_GP_TOP_REG_DUAL_LINK_SEL_P0 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIXEL_REP_EN_P0 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_SELF_DIV4_EN_P0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_SELF_DIV2_EN_P0 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_SD_4P_CLK_DIV4_EN_P0 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_SD_4P_CLK_DIV2_EN_P0 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_SD_REP_CLK_DIV2_EN_P0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_420T_CLK_DIV4_EN_P0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_SD_CLK_DIV4_EN_P0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_CLK_DIV4_EN_P0 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_420T_CLK_DIV2_EN_P0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_SD_CLK_DIV2_EN_P0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1840_GP_TOP_REG_PIX_CLK_DIV2_EN_P0 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1840_GP_TOP_REG_CLK_XTALI_DIV2_EN_P0 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1840_GP_TOP_REG_TMDS_CLK_DIV2_EN_P0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1844_GP_TOP (HDMI2P1_MAC_BASE + 0x1844)
    #define HD21MAC_CFG_1844_GP_TOP_REG_DEC_HDCP_CLK_INV_P0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1844_GP_TOP_REG_PD_DEC_HDCP_CLK_P0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1848_GP_TOP (HDMI2P1_MAC_BASE + 0x1848)
    #define HD21MAC_CFG_1848_GP_TOP_REG_DC_DEPACK_CLK_INV_P0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1848_GP_TOP_REG_PD_DC_DEPACK_CLK_P0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_184C_GP_TOP (HDMI2P1_MAC_BASE + 0x184C)
    #define HD21MAC_CFG_184C_GP_TOP_REG_TMDS_CLK_2X_DIV2_EN_P0 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_184C_GP_TOP_REG_LINK_CLK_TOP_DIV2_EN_P0 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_184C_GP_TOP_REG_LINK_CLK_DIV2_EN_P0 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_184C_GP_TOP_REG_PIX_CLK_DIV16_8P_EN_P0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_184C_GP_TOP_REG_PIX_CLK_DIV8_8P_EN_P0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_184C_GP_TOP_REG_PIX_CLK_DIV4_8P_EN_P0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_184C_GP_TOP_REG_PIX_CLK_DIV2_8P_EN_P0 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_184C_GP_TOP_REG_PIX_CLK_DIV16_EN_P0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_184C_GP_TOP_REG_PIX_CLK_DIV8_EN_P0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_184C_GP_TOP_REG_TMDS_CLK_TOP_DIV2_EN_P0 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_184C_GP_TOP_REG_PIX_SD_CLK_DIV4_2ND_EN_P0 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_184C_GP_TOP_REG_PIX_SD_CLK_DIV2_2ND_EN_P0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1850_GP_TOP (HDMI2P1_MAC_BASE + 0x1850)
    #define HD21MAC_CFG_1850_GP_TOP_REG_SYNC_TRIG_TMDS_DIV2_P0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1850_GP_TOP_REG_SYNC_MD_TMDS_DIV2_P0 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1850_GP_TOP_REG_SYNC_TRIG_LINK_DIV2_P0 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1850_GP_TOP_REG_SYNC_MD_LINK_DIV2_P0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1860_GP_TOP (HDMI2P1_MAC_BASE + 0x1860)
    #define HD21MAC_CFG_1860_GP_TOP_REG_1P2P_EN_P1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1860_GP_TOP_REG_DUAL_LINK_SEL_P1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIXEL_REP_EN_P1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_SELF_DIV4_EN_P1 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_SELF_DIV2_EN_P1 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_SD_4P_CLK_DIV4_EN_P1 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_SD_4P_CLK_DIV2_EN_P1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_SD_REP_CLK_DIV2_EN_P1 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_420T_CLK_DIV4_EN_P1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_SD_CLK_DIV4_EN_P1 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_CLK_DIV4_EN_P1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_420T_CLK_DIV2_EN_P1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_SD_CLK_DIV2_EN_P1 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1860_GP_TOP_REG_PIX_CLK_DIV2_EN_P1 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1860_GP_TOP_REG_CLK_XTALI_DIV2_EN_P1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1860_GP_TOP_REG_TMDS_CLK_DIV2_EN_P1 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1864_GP_TOP (HDMI2P1_MAC_BASE + 0x1864)
    #define HD21MAC_CFG_1864_GP_TOP_REG_DEC_HDCP_CLK_INV_P1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1864_GP_TOP_REG_PD_DEC_HDCP_CLK_P1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1868_GP_TOP (HDMI2P1_MAC_BASE + 0x1868)
    #define HD21MAC_CFG_1868_GP_TOP_REG_DC_DEPACK_CLK_INV_P1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1868_GP_TOP_REG_PD_DC_DEPACK_CLK_P1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_186C_GP_TOP (HDMI2P1_MAC_BASE + 0x186C)
    #define HD21MAC_CFG_186C_GP_TOP_REG_DC_DEPACK_CLK_INV_P2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_186C_GP_TOP_REG_PD_DC_DEPACK_CLK_P2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1870_GP_TOP (HDMI2P1_MAC_BASE + 0x1870)
    #define HD21MAC_CFG_1870_GP_TOP_REG_DC_DEPACK_CLK_INV_P3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1870_GP_TOP_REG_PD_DC_DEPACK_CLK_P3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1874_GP_TOP (HDMI2P1_MAC_BASE + 0x1874)
    #define HD21MAC_CFG_1874_GP_TOP_REG_TMDS_CLK_2X_DIV2_EN_P1 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1874_GP_TOP_REG_LINK_CLK_TOP_DIV2_EN_P1 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1874_GP_TOP_REG_LINK_CLK_DIV2_EN_P1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1874_GP_TOP_REG_PIX_CLK_DIV16_8P_EN_P1 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1874_GP_TOP_REG_PIX_CLK_DIV8_8P_EN_P1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1874_GP_TOP_REG_PIX_CLK_DIV4_8P_EN_P1 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1874_GP_TOP_REG_PIX_CLK_DIV2_8P_EN_P1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1874_GP_TOP_REG_PIX_CLK_DIV16_EN_P1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1874_GP_TOP_REG_PIX_CLK_DIV8_EN_P1 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1874_GP_TOP_REG_TMDS_CLK_TOP_DIV2_EN_P1 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1874_GP_TOP_REG_PIX_SD_CLK_DIV4_2ND_EN_P1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1874_GP_TOP_REG_PIX_SD_CLK_DIV2_2ND_EN_P1 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1878_GP_TOP (HDMI2P1_MAC_BASE + 0x1878)
    #define HD21MAC_CFG_1878_GP_TOP_REG_SYNC_TRIG_TMDS_DIV2_P1 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1878_GP_TOP_REG_SYNC_MD_TMDS_DIV2_P1 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1878_GP_TOP_REG_SYNC_TRIG_LINK_DIV2_P1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1878_GP_TOP_REG_SYNC_MD_LINK_DIV2_P1 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1880_GP_TOP (HDMI2P1_MAC_BASE + 0x1880)
    #define HD21MAC_CFG_1880_GP_TOP_REG_1P2P_EN_P2 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1880_GP_TOP_REG_DUAL_LINK_SEL_P2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIXEL_REP_EN_P2 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_SELF_DIV4_EN_P2 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_SELF_DIV2_EN_P2 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_SD_4P_CLK_DIV4_EN_P2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_SD_4P_CLK_DIV2_EN_P2 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_SD_REP_CLK_DIV2_EN_P2 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_420T_CLK_DIV4_EN_P2 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_SD_CLK_DIV4_EN_P2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_CLK_DIV4_EN_P2 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_420T_CLK_DIV2_EN_P2 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_SD_CLK_DIV2_EN_P2 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1880_GP_TOP_REG_PIX_CLK_DIV2_EN_P2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1880_GP_TOP_REG_CLK_XTALI_DIV2_EN_P2 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1880_GP_TOP_REG_TMDS_CLK_DIV2_EN_P2 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1884_GP_TOP (HDMI2P1_MAC_BASE + 0x1884)
    #define HD21MAC_CFG_1884_GP_TOP_REG_DEC_HDCP_CLK_INV_P2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1884_GP_TOP_REG_PD_DEC_HDCP_CLK_P2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_188C_GP_TOP (HDMI2P1_MAC_BASE + 0x188C)
    #define HD21MAC_CFG_188C_GP_TOP_REG_TMDS_CLK_2X_DIV2_EN_P2 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_188C_GP_TOP_REG_LINK_CLK_TOP_DIV2_EN_P2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_188C_GP_TOP_REG_LINK_CLK_DIV2_EN_P2 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_188C_GP_TOP_REG_PIX_CLK_DIV16_8P_EN_P2 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_188C_GP_TOP_REG_PIX_CLK_DIV8_8P_EN_P2 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_188C_GP_TOP_REG_PIX_CLK_DIV4_8P_EN_P2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_188C_GP_TOP_REG_PIX_CLK_DIV2_8P_EN_P2 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_188C_GP_TOP_REG_PIX_CLK_DIV16_EN_P2 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_188C_GP_TOP_REG_PIX_CLK_DIV8_EN_P2 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_188C_GP_TOP_REG_TMDS_CLK_TOP_DIV2_EN_P2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_188C_GP_TOP_REG_PIX_SD_CLK_DIV4_2ND_EN_P2 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_188C_GP_TOP_REG_PIX_SD_CLK_DIV2_2ND_EN_P2 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1890_GP_TOP (HDMI2P1_MAC_BASE + 0x1890)
    #define HD21MAC_CFG_1890_GP_TOP_REG_SYNC_TRIG_TMDS_DIV2_P2 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1890_GP_TOP_REG_SYNC_MD_TMDS_DIV2_P2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1890_GP_TOP_REG_SYNC_TRIG_LINK_DIV2_P2 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1890_GP_TOP_REG_SYNC_MD_LINK_DIV2_P2 Fld(1,0,AC_MSKB0)//[0:0]

    //Page HDMI21_MAC_6
#define HD21MAC_CFG_18A0_GP_TOP (HDMI2P1_MAC_BASE + 0x18A0)
    #define HD21MAC_CFG_18A0_GP_TOP_REG_1P2P_EN_P3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_DUAL_LINK_SEL_P3 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIXEL_REP_EN_P3 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_SELF_DIV4_EN_P3 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_SELF_DIV2_EN_P3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_SD_4P_CLK_DIV4_EN_P3 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_SD_4P_CLK_DIV2_EN_P3 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_SD_REP_CLK_DIV2_EN_P3 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_420T_CLK_DIV4_EN_P3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_SD_CLK_DIV4_EN_P3 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_CLK_DIV4_EN_P3 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_420T_CLK_DIV2_EN_P3 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_SD_CLK_DIV2_EN_P3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_PIX_CLK_DIV2_EN_P3 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_CLK_XTALI_DIV2_EN_P3 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_18A0_GP_TOP_REG_TMDS_CLK_DIV2_EN_P3 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_18A4_GP_TOP (HDMI2P1_MAC_BASE + 0x18A4)
    #define HD21MAC_CFG_18A4_GP_TOP_REG_DEC_HDCP_CLK_INV_P3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_18A4_GP_TOP_REG_PD_DEC_HDCP_CLK_P3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_18AC_GP_TOP (HDMI2P1_MAC_BASE + 0x18AC)
    #define HD21MAC_CFG_18AC_GP_TOP_REG_TMDS_CLK_2X_DIV2_EN_P3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_LINK_CLK_TOP_DIV2_EN_P3 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_LINK_CLK_DIV2_EN_P3 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_PIX_CLK_DIV16_8P_EN_P3 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_PIX_CLK_DIV8_8P_EN_P3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_PIX_CLK_DIV4_8P_EN_P3 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_PIX_CLK_DIV2_8P_EN_P3 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_PIX_CLK_DIV16_EN_P3 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_PIX_CLK_DIV8_EN_P3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_TMDS_CLK_TOP_DIV2_EN_P3 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_PIX_SD_CLK_DIV4_2ND_EN_P3 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_18AC_GP_TOP_REG_PIX_SD_CLK_DIV2_2ND_EN_P3 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_18B0_GP_TOP (HDMI2P1_MAC_BASE + 0x18B0)
    #define HD21MAC_CFG_18B0_GP_TOP_REG_SYNC_TRIG_TMDS_DIV2_P3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_18B0_GP_TOP_REG_SYNC_MD_TMDS_DIV2_P3 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_18B0_GP_TOP_REG_SYNC_TRIG_LINK_DIV2_P3 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_18B0_GP_TOP_REG_SYNC_MD_LINK_DIV2_P3 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_18C8_GP_TOP (HDMI2P1_MAC_BASE + 0x18C8)
    #define HD21MAC_CFG_18C8_GP_TOP_REG_ARC_CONTROL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_18CC_GP_TOP (HDMI2P1_MAC_BASE + 0x18CC)
    #define HD21MAC_CFG_18CC_GP_TOP_REG_MHL_PORT_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_18D0_GP_TOP (HDMI2P1_MAC_BASE + 0x18D0)
    #define HD21MAC_CFG_18D0_GP_TOP_REG_SW_RESET Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_18D4_GP_TOP (HDMI2P1_MAC_BASE + 0x18D4)
    #define HD21MAC_CFG_18D4_GP_TOP_REG_XTAL_FREQ Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_18D4_GP_TOP_REG_SRAM_SD_EN_GROUP_PORT3 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_18D4_GP_TOP_REG_SRAM_SD_EN_GROUP_PORT2 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_18D4_GP_TOP_REG_SRAM_SD_EN_GROUP_PORT1 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_18D4_GP_TOP_REG_SRAM_SD_EN_GROUP_PORT0 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_18D4_GP_TOP_REG_SRAM_SD_EN_GROUP_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_18D8_GP_TOP (HDMI2P1_MAC_BASE + 0x18D8)
    #define HD21MAC_CFG_18D8_GP_TOP_REG_WDT_WIDTH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_18D8_GP_TOP_REG_WDT_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_18D8_GP_TOP_REG_WDT_TESTMD Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_18D8_GP_TOP_REG_TESTMUX_SEL Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_18DC_GP_TOP (HDMI2P1_MAC_BASE + 0x18DC)
    #define HD21MAC_CFG_18DC_GP_TOP_REG_COMBO_RX_GP_IRQ Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_18E0_GP_TOP (HDMI2P1_MAC_BASE + 0x18E0)
    #define HD21MAC_CFG_18E0_GP_TOP_REG_COMBO_RX_GP_IRQ_ENABLE_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_18E0_GP_TOP_REG_COMBO_RX_GP_IRQ_ENABLE_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_18E0_GP_TOP_REG_COMBO_RX_GP_IRQ_ENABLE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_18F0_GP_TOP (HDMI2P1_MAC_BASE + 0x18F0)
    #define HD21MAC_CFG_18F0_GP_TOP_REG_SRAM_BIST_FAIL_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_18F4_GP_TOP (HDMI2P1_MAC_BASE + 0x18F4)
    #define HD21MAC_CFG_18F4_GP_TOP_REG_SRAM_BIST_FAIL_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_18F8_GP_TOP (HDMI2P1_MAC_BASE + 0x18F8)
    #define HD21MAC_CFG_18F8_GP_TOP_REG_SRAM_BIST_FAIL_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_18FC_GP_TOP (HDMI2P1_MAC_BASE + 0x18FC)
    #define HD21MAC_CFG_18FC_GP_TOP_REG_SRAM_BIST_FAIL_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1900_GP_TOP (HDMI2P1_MAC_BASE + 0x1900)
    #define HD21MAC_CFG_1900_GP_TOP_REG_XIU_ACK_DIS Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1900_GP_TOP_REG_HDCP_DATA_TRIG Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1900_GP_TOP_REG_LOAD_ADDR_TRIG Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1900_GP_TOP_REG_HDCP_SRAM_ACCESS Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1900_GP_TOP_REG_ENWRITE_HDCP Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1900_GP_TOP_REG_EN_SRAM_RD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1900_GP_TOP_REG_XIU2HDCPKEY_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1904_GP_TOP (HDMI2P1_MAC_BASE + 0x1904)
    #define HD21MAC_CFG_1904_GP_TOP_REG_CPU_ADR Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1908_GP_TOP (HDMI2P1_MAC_BASE + 0x1908)
    #define HD21MAC_CFG_1908_GP_TOP_REG_SRAM_RDATA Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1908_GP_TOP_REG_CPU_WDATA Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1910_GP_TOP (HDMI2P1_MAC_BASE + 0x1910)
    #define HD21MAC_CFG_1910_GP_TOP_REG_HDMI2_RESERVED2 Fld(3,13,AC_MSKB1)//[15:13]
    #define HD21MAC_CFG_1910_GP_TOP_REG_RST_CTSN_SYNTH Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1910_GP_TOP_REG_HDMI2_RESERVED1 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1910_GP_TOP_REG_SYNTH_NO_INPUT_LOCK_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1910_GP_TOP_REG_SYNTH_NO_INPUT_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1910_GP_TOP_REG_CLR_SYNTH_LOCK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1910_GP_TOP_REG_EN_CTS_N_SYNTH Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1910_GP_TOP_REG_HDMI2_RESERVED0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1910_GP_TOP_REG_SYNTH_PLL_LOCK_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1910_GP_TOP_REG_SYNTH_256FS_EXPANDER Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1910_GP_TOP_REG_SYNTH_PLL_LOCK_FREQ Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1910_GP_TOP_REG_SYNTH_FREQ_GAIN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1910_GP_TOP_REG_SYNTH_PH_GAIN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1910_GP_TOP_REG_SYNTH_SEL_CTS_REF Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1914_GP_TOP (HDMI2P1_MAC_BASE + 0x1914)
    #define HD21MAC_CFG_1914_GP_TOP_REG_DVI_NO_INPUT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1914_GP_TOP_REG_CTS_N_SYNTH_FREQ Fld(15,0,AC_MSKW10)//[14:0]
#define HD21MAC_CFG_1918_GP_TOP (HDMI2P1_MAC_BASE + 0x1918)
    #define HD21MAC_CFG_1918_GP_TOP_REG_LOAD_HDMI_AUD_FREQ Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1918_GP_TOP_REG_EN_P3_CLKPIX2X Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1918_GP_TOP_REG_EN_P2_CLKPIX2X Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1918_GP_TOP_REG_EN_P1_CLKPIX2X Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1918_GP_TOP_REG_EN_P0_CLKPIX2X Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1918_GP_TOP_REG_SYNTH_PLL_LOCK_EN Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_191C_GP_TOP (HDMI2P1_MAC_BASE + 0x191C)
    #define HD21MAC_CFG_191C_GP_TOP_REG_LOAD_HDMI_AUD_FREQ_VAL_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1920_GP_TOP (HDMI2P1_MAC_BASE + 0x1920)
    #define HD21MAC_CFG_1920_GP_TOP_REG_AFF_RST_CONDI Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_1920_GP_TOP_REG_LOAD_HDMI_AUD_FREQ_VAL_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1924_GP_TOP (HDMI2P1_MAC_BASE + 0x1924)
    #define HD21MAC_CFG_1924_GP_TOP_REG_AFIFO_TH Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_1924_GP_TOP_REG_ASFLAT_CHK Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_1924_GP_TOP_REG_AFIFO_RST Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1924_GP_TOP_REG_DIS_DST_HEADER_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1924_GP_TOP_REG_EN_EMPTY_RD_HEADER_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1924_GP_TOP_REG_AFIFO12_OVER Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1924_GP_TOP_REG_AFIFO12_UNDER Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1924_GP_TOP_REG_AUD_8P_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1924_GP_TOP_REG_AUDIO_LAYOUT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1924_GP_TOP_REG_FLAT_ASMP_RCVD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1924_GP_TOP_REG_AFIFO34_FULL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1924_GP_TOP_REG_AFIFO34_EMPTY Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1924_GP_TOP_REG_AFIFO12_FULL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1924_GP_TOP_REG_AFIFO12_EMPTY Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1928_GP_TOP (HDMI2P1_MAC_BASE + 0x1928)
    #define HD21MAC_CFG_1928_GP_TOP_REG_HDMI_AU_FIFO_MUTE_EN Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1928_GP_TOP_REG_HDMI_AUDIO_MUTE_EN Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_192C_GP_TOP (HDMI2P1_MAC_BASE + 0x192C)
    #define HD21MAC_CFG_192C_GP_TOP_REG_AUDIO_RESERVED Fld(13,3,AC_MSKW10)//[15:3]
    #define HD21MAC_CFG_192C_GP_TOP_REG_GLOBAL_MUTE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_192C_GP_TOP_REG_AUDIO_SRC_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1930_GP_TOP (HDMI2P1_MAC_BASE + 0x1930)
    #define HD21MAC_CFG_1930_GP_TOP_REG_AFR3_BIST_FAIL Fld(1,0,AC_MSKB0)//[0:0]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AFL3_BIST_FAIL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AHF3_BIST_FAIL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AFR2_BIST_FAIL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AFL2_BIST_FAIL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AHF2_BIST_FAIL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AFR1_BIST_FAIL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AFL1_BIST_FAIL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AHF1_BIST_FAIL Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AFR0_BIST_FAIL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AFL0_BIST_FAIL Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1930_GP_TOP_REG_AHF0_BIST_FAIL Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1930_GP_TOP_REG_3D_PKT_VLD Fld(4,12,AC_MSKB1)//[15:12]
#define HD21MAC_CFG_1934_GP_TOP (HDMI2P1_MAC_BASE + 0x1934)
    #define HD21MAC_CFG_1934_GP_TOP_REG_HDMI_AUDIO_STATUS_EN Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_1934_GP_TOP_REG_SW_AUDIO_VLD_CNT Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21MAC_CFG_1934_GP_TOP_REG_EN_SW_AUDIO_VLD Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_194C_GP_TOP (HDMI2P1_MAC_BASE + 0x194C)
    #define HD21MAC_CFG_194C_GP_TOP_REG_AUD_FIFO_WRITE_SHIFT_PROT Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_194C_GP_TOP_REG_AUD_FIFO_READ_SHIFT_PROT Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_194C_GP_TOP_REG_AUD_FIFO_FULL_DIFF Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_194C_GP_TOP_REG_AUD_FIFO_EMPTY_DIFF Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1964_GP_TOP (HDMI2P1_MAC_BASE + 0x1964)
    #define HD21MAC_CFG_1964_GP_TOP_REG_TESTBUS2RIU_GATE Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1964_GP_TOP_REG_TO_SC3_CK_STB Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1964_GP_TOP_REG_TO_SC3_DE_STB Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1964_GP_TOP_REG_TO_SC2_CK_STB Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1964_GP_TOP_REG_TO_SC2_DE_STB Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1964_GP_TOP_REG_TO_SC1_CK_STB Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1964_GP_TOP_REG_TO_SC1_DE_STB Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1964_GP_TOP_REG_TO_SC0_CK_STB Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1964_GP_TOP_REG_TO_SC0_DE_STB Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1968_GP_TOP (HDMI2P1_MAC_BASE + 0x1968)
    #define HD21MAC_CFG_1968_GP_TOP_REG_COMBO_TOP_RESERVED_0 Fld(15,1,AC_MSKW10)//[15:1]
    #define HD21MAC_CFG_1968_GP_TOP_REG_EMP_P_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_196C_GP_TOP (HDMI2P1_MAC_BASE + 0x196C)
    #define HD21MAC_CFG_196C_GP_TOP_REG_COMBO_TOP_RESERVED_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1970_GP_TOP (HDMI2P1_MAC_BASE + 0x1970)
    #define HD21MAC_CFG_1970_GP_TOP_REG_COMBO_TOP_RESERVED_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1974_GP_TOP (HDMI2P1_MAC_BASE + 0x1974)
    #define HD21MAC_CFG_1974_GP_TOP_REG_COMBO_TOP_RESERVED_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1978_GP_TOP (HDMI2P1_MAC_BASE + 0x1978)
    #define HD21MAC_CFG_1978_GP_TOP_REG_COMBO_TOP_RESERVED_4 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_197C_GP_TOP (HDMI2P1_MAC_BASE + 0x197C)
    #define HD21MAC_CFG_197C_GP_TOP_REG_COMBO_TOP_RESERVED_5 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1980_GP_TOP (HDMI2P1_MAC_BASE + 0x1980)
    #define HD21MAC_CFG_1980_GP_TOP_REG_COMBO_TOP_RESERVED_6 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1984_GP_TOP (HDMI2P1_MAC_BASE + 0x1984)
    #define HD21MAC_CFG_1984_GP_TOP_REG_COMBO_TOP_RESERVED_7 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1988_GP_TOP (HDMI2P1_MAC_BASE + 0x1988)
    #define HD21MAC_CFG_1988_GP_TOP_REG_COMBO_TOP_RESERVED_8 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_198C_GP_TOP (HDMI2P1_MAC_BASE + 0x198C)
    #define HD21MAC_CFG_198C_GP_TOP_REG_COMBO_TOP_RESERVED_9 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1990_GP_TOP (HDMI2P1_MAC_BASE + 0x1990)
    #define HD21MAC_CFG_1990_GP_TOP_REG_COMBO_TOP_RESERVED_10 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1994_GP_TOP (HDMI2P1_MAC_BASE + 0x1994)
    #define HD21MAC_CFG_1994_GP_TOP_REG_DVI2MIU_CK_LINK2TMDS_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1994_GP_TOP_REG_DVI2MIU_WRPTR_STS Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_1994_GP_TOP_REG_DVI2MIU_TST_1 Fld(6,6,AC_MSKW10)//[11:6]
    #define HD21MAC_CFG_1994_GP_TOP_REG_DVI2MIU_TST Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_1998_GP_TOP (HDMI2P1_MAC_BASE + 0x1998)
    #define HD21MAC_CFG_1998_GP_TOP_REG_DVI2MIU_DIS_CLK_STABLE_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1998_GP_TOP_REG_DVI2MIU_RDPTR_STS Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_1998_GP_TOP_REG_DVI2MIU_TST_3 Fld(6,6,AC_MSKW10)//[11:6]
    #define HD21MAC_CFG_1998_GP_TOP_REG_DVI2MIU_TST_2 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_199C_GP_TOP (HDMI2P1_MAC_BASE + 0x199C)
    #define HD21MAC_CFG_199C_GP_TOP_REG_TEST_BUS_RD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19A0_GP_TOP (HDMI2P1_MAC_BASE + 0x19A0)
    #define HD21MAC_CFG_19A0_GP_TOP_REG_DVI2MIU_FIFO_RD_OFFSET Fld(3,13,AC_MSKB1)//[15:13]
    #define HD21MAC_CFG_19A0_GP_TOP_REG_DVI2MIU_FIFO_PT_RST Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_19A0_GP_TOP_REG_DVI2MIU_CK_DIV2_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_19A0_GP_TOP_REG_DVI2MIU_EMP_SRC Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_19A0_GP_TOP_REG_TEST_BUS_RD_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_19A4_GP_TOP (HDMI2P1_MAC_BASE + 0x19A4)
    #define HD21MAC_CFG_19A4_GP_TOP_REG_COMBO_TOP_RESERVED_15 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19A8_GP_TOP (HDMI2P1_MAC_BASE + 0x19A8)
    #define HD21MAC_CFG_19A8_GP_TOP_REG_EMP_HFRONT_P_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19AC_GP_TOP (HDMI2P1_MAC_BASE + 0x19AC)
    #define HD21MAC_CFG_19AC_GP_TOP_REG_EMP_HSYNC_P_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19B0_GP_TOP (HDMI2P1_MAC_BASE + 0x19B0)
    #define HD21MAC_CFG_19B0_GP_TOP_REG_EMP_HBACK_P_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19B4_GP_TOP (HDMI2P1_MAC_BASE + 0x19B4)
    #define HD21MAC_CFG_19B4_GP_TOP_REG_EMP_HCACTIVE_BYTE_P_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19B8_GP_TOP (HDMI2P1_MAC_BASE + 0x19B8)
    #define HD21MAC_CFG_19B8_GP_TOP_REG_COMBO_TOP_RD_RESERVED_4 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19C0_GP_TOP (HDMI2P1_MAC_BASE + 0x19C0)
    #define HD21MAC_CFG_19C0_GP_TOP_REG_HD21_RESERVED Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_19C0_GP_TOP_REG_CK_PIX_SHARE_SRC_SEL_P0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_19C0_GP_TOP_REG_HDMI_FRL_MD_OVE_P0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_19C0_GP_TOP_REG_HDMI_FRL_MD_OV_P0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_19C0_GP_TOP_REG_CK_PIX_SELF_SRC_SEL_P0 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_19C0_GP_TOP_REG_TMDSPLL_MD_P0 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_19C0_GP_TOP_REG_CKG_LX_SEL_P0 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_19C4_GP_TOP (HDMI2P1_MAC_BASE + 0x19C4)
    #define HD21MAC_CFG_19C4_GP_TOP_REG_HD21RX2DSCD_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_19C8_GP_TOP (HDMI2P1_MAC_BASE + 0x19C8)
    #define HD21MAC_CFG_19C8_GP_TOP_REG_MISC_CLK_INV_EXT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_19C8_GP_TOP_REG_PD_MISC_CLK_EXT Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_19CC_GP_TOP (HDMI2P1_MAC_BASE + 0x19CC)
    #define HD21MAC_CFG_19CC_GP_TOP_REG_HD21_CLK_INV Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19D0_GP_TOP (HDMI2P1_MAC_BASE + 0x19D0)
    #define HD21MAC_CFG_19D0_GP_TOP_REG_HD21_CLK_GATE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19D4_GP_TOP (HDMI2P1_MAC_BASE + 0x19D4)
    #define HD21MAC_CFG_19D4_GP_TOP_REG_HD21_CLK_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19D8_GP_TOP (HDMI2P1_MAC_BASE + 0x19D8)
    #define HD21MAC_CFG_19D8_GP_TOP_REG_HD21_CLK_DEPACK_GATE_P1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_19D8_GP_TOP_REG_HD21_CLK_DEPACK_GATE_P0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_19DC_GP_TOP (HDMI2P1_MAC_BASE + 0x19DC)
    #define HD21MAC_CFG_19DC_GP_TOP_REG_HD21_CLK_DEPACK_GATE_P3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_19DC_GP_TOP_REG_HD21_CLK_DEPACK_GATE_P2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_19E0_GP_TOP (HDMI2P1_MAC_BASE + 0x19E0)
    #define HD21MAC_CFG_19E0_GP_TOP_REG_HD21_RESERVED_P1 Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_19E0_GP_TOP_REG_CK_PIX_SHARE_SRC_SEL_P1 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_19E0_GP_TOP_REG_HDMI_FRL_MD_OVE_P1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_19E0_GP_TOP_REG_HDMI_FRL_MD_OV_P1 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_19E0_GP_TOP_REG_CK_PIX_SELF_SRC_SEL_P1 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_19E0_GP_TOP_REG_TMDSPLL_MD_P1 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_19E0_GP_TOP_REG_CKG_LX_SEL_P1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_19E4_GP_TOP (HDMI2P1_MAC_BASE + 0x19E4)
    #define HD21MAC_CFG_19E4_GP_TOP_REG_HD21_RESERVED_P2 Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_19E4_GP_TOP_REG_CK_PIX_SHARE_SRC_SEL_P2 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_19E4_GP_TOP_REG_HDMI_FRL_MD_OVE_P2 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_19E4_GP_TOP_REG_HDMI_FRL_MD_OV_P2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_19E4_GP_TOP_REG_CK_PIX_SELF_SRC_SEL_P2 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_19E4_GP_TOP_REG_TMDSPLL_MD_P2 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_19E4_GP_TOP_REG_CKG_LX_SEL_P2 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_19E8_GP_TOP (HDMI2P1_MAC_BASE + 0x19E8)
    #define HD21MAC_CFG_19E8_GP_TOP_REG_HD21_RESERVED_P3 Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_19E8_GP_TOP_REG_CK_PIX_SHARE_SRC_SEL_P3 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_19E8_GP_TOP_REG_HDMI_FRL_MD_OVE_P3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_19E8_GP_TOP_REG_HDMI_FRL_MD_OV_P3 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_19E8_GP_TOP_REG_CK_PIX_SELF_SRC_SEL_P3 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_19E8_GP_TOP_REG_TMDSPLL_MD_P3 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_19E8_GP_TOP_REG_CKG_LX_SEL_P3 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_19BC_GP_TOP (HDMI2P1_MAC_BASE + 0x19BC)
    #define HD21MAC_CFG_19BC_GP_TOP_REG_AV_TS_LATCH_PULSE_GEN_P1 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_19BC_GP_TOP_REG_AV_TS_LATCH_PULSE_GEN_P0 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_19EC_GP_TOP (HDMI2P1_MAC_BASE + 0x19EC)
    #define HD21MAC_CFG_19EC_GP_TOP_REG_AV_TS_LATCH_PULSE_GEN_P3 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_19EC_GP_TOP_REG_AV_TS_LATCH_PULSE_GEN_P2 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_19F0_GP_TOP (HDMI2P1_MAC_BASE + 0x19F0)
    #define HD21MAC_CFG_19F0_GP_TOP_REG_FORCE_TIMESTAMP_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define HD21MAC_CFG_19F0_GP_TOP_REG_RESET_TIMESTAMP Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_19F0_GP_TOP_REG_VIDEO_TIMESTAMP_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_19F0_GP_TOP_REG_AV_TS_LATCH_PULSE_GEN_AUD Fld(5,8,AC_MSKB1)//[12:8]
#define HD21MAC_CFG_19F4_GP_TOP (HDMI2P1_MAC_BASE + 0x19F4)
    #define HD21MAC_CFG_19F4_GP_TOP_REG_FORCE_TIMESTAMP_VALUE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19F8_GP_TOP (HDMI2P1_MAC_BASE + 0x19F8)
    #define HD21MAC_CFG_19F8_GP_TOP_REG_FORCE_TIMESTAMP_VALUE_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_19FC_GP_TOP (HDMI2P1_MAC_BASE + 0x19FC)
    #define HD21MAC_CFG_19FC_GP_TOP_REG_AV_TIMESTAMP_INC Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1A08_GP_MISC (HDMI2P1_MAC_BASE + 0x1A08)
    #define HD21MAC_CFG_1A08_GP_MISC_REG_CLK_INV_P2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1A08_GP_MISC_REG_CLK_GATE_P2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1A0C_GP_MISC (HDMI2P1_MAC_BASE + 0x1A0C)
    #define HD21MAC_CFG_1A0C_GP_MISC_REG_CLK_INV_P3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1A0C_GP_MISC_REG_CLK_GATE_P3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1A10_GP_MISC (HDMI2P1_MAC_BASE + 0x1A10)
    #define HD21MAC_CFG_1A10_GP_MISC_REG_CLK_INV_COM Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1A10_GP_MISC_REG_CLK_GATE_COM Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1A14_GP_MISC (HDMI2P1_MAC_BASE + 0x1A14)
    #define HD21MAC_CFG_1A14_GP_MISC_REG_DSC_CK_INV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_1A14_GP_MISC_REG_DSC_CK_GATE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_1B00_GP_MISC (HDMI2P1_MAC_BASE + 0x1B00)
    #define HD21MAC_CFG_1B00_GP_MISC_REG_CAPY_IRQ_FNL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_1B00_GP_MISC_REG_CAPY_IRQ_MSK Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_1B00_GP_MISC_REG_CAPY_IRQ_FCE Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_1B00_GP_MISC_REG_CAPY_IRQ_CLR Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1B0C_GP_MISC (HDMI2P1_MAC_BASE + 0x1B0C)
    #define HD21MAC_CFG_1B0C_GP_MISC_REG_FREQ_FRAC_P2 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1B10_GP_MISC (HDMI2P1_MAC_BASE + 0x1B10)
    #define HD21MAC_CFG_1B10_GP_MISC_REG_FREQ_HD21PIXL_P2 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1B14_GP_MISC (HDMI2P1_MAC_BASE + 0x1B14)
    #define HD21MAC_CFG_1B14_GP_MISC_REG_FREQ_VP_INTER_P2 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1B18_GP_MISC (HDMI2P1_MAC_BASE + 0x1B18)
    #define HD21MAC_CFG_1B18_GP_MISC_REG_FREQ_8K_INTER_P2 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1B1C_GP_MISC (HDMI2P1_MAC_BASE + 0x1B1C)
    #define HD21MAC_CFG_1B1C_GP_MISC_REG_SRC420_FLG_P2 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1B1C_GP_MISC_REG_VP2XC_LR_FLG_P2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_1B1C_GP_MISC_REG_VP2XC_DIV_OVE_P2 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_1B1C_GP_MISC_REG_VP_INTER_DIV_OVE_P2 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1B1C_GP_MISC_REG_MD_CK_SEL_P2 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1B1C_GP_MISC_REG_FREQ_VP2XC_P2 Fld(10,0,AC_MSKW10)//[9:0]

    //Page HDMI21_MAC_7
#define HD21MAC_CFG_1B20_GP_MISC (HDMI2P1_MAC_BASE + 0x1B20)
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_FRAC_DIG_DIV_P2 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_FRAC_DIG_DIV_P2 Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_HD21PIXL_DIV_P2 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_VP_INTER_DIV_P2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_MST_8K_XC_INTER_DIV_P2 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_VP2XC_DIV_P2 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_FRAC_DIG_DIV_P3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_FRAC_DIG_DIV_P3 Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_HD21PIXL_DIV_P3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_VP_INTER_DIV_P3 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_MST_8K_XC_INTER_DIV_P3 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1B20_GP_MISC_REG_AT_VP2XC_DIV_P3 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1B24_GP_MISC (HDMI2P1_MAC_BASE + 0x1B24)
    #define HD21MAC_CFG_1B24_GP_MISC_REG_HD21PIXL_DIV_P2 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_1B24_GP_MISC_REG_VP_INTER_DIV_P2 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_1B24_GP_MISC_REG_MST_8K_XC_INTER_DIV_P2 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_1B24_GP_MISC_REG_VP2XC_DIV_P2 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_1B28_GP_MISC (HDMI2P1_MAC_BASE + 0x1B28)
    #define HD21MAC_CFG_1B28_GP_MISC_REG_HD21PIXL_DIV_P3 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_1B28_GP_MISC_REG_VP_INTER_DIV_P3 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_1B28_GP_MISC_REG_MST_8K_XC_INTER_DIV_P3 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_1B28_GP_MISC_REG_VP2XC_DIV_P3 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_1B2C_GP_MISC (HDMI2P1_MAC_BASE + 0x1B2C)
    #define HD21MAC_CFG_1B2C_GP_MISC_REG_FREQ_FRAC_P3 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1B30_GP_MISC (HDMI2P1_MAC_BASE + 0x1B30)
    #define HD21MAC_CFG_1B30_GP_MISC_REG_FREQ_HD21PIXL_P3 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1B34_GP_MISC (HDMI2P1_MAC_BASE + 0x1B34)
    #define HD21MAC_CFG_1B34_GP_MISC_REG_FREQ_VP_INTER_P3 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1B38_GP_MISC (HDMI2P1_MAC_BASE + 0x1B38)
    #define HD21MAC_CFG_1B38_GP_MISC_REG_FREQ_8K_INTER_P3 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1B3C_GP_MISC (HDMI2P1_MAC_BASE + 0x1B3C)
    #define HD21MAC_CFG_1B3C_GP_MISC_REG_MD_CK_SEL_P3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1B3C_GP_MISC_REG_VP_INTER_DIV_OVE_P3 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1B3C_GP_MISC_REG_VP2XC_DIV_OVE_P3 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_1B3C_GP_MISC_REG_VP2XC_LR_FLG_P3 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_1B3C_GP_MISC_REG_SRC420_FLG_P3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1B3C_GP_MISC_REG_FREQ_VP2XC_P3 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1B40_GP_MISC (HDMI2P1_MAC_BASE + 0x1B40)
    #define HD21MAC_CFG_1B40_GP_MISC_REG_SDM_PCW_P2_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1B44_GP_MISC (HDMI2P1_MAC_BASE + 0x1B44)
    #define HD21MAC_CFG_1B44_GP_MISC_REG_SDM_PCW_P2_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1B48_GP_MISC (HDMI2P1_MAC_BASE + 0x1B48)
    #define HD21MAC_CFG_1B48_GP_MISC_REG_SDM_PCW_OVE_P2 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1B48_GP_MISC_REG_SDM_EN_P2 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1B48_GP_MISC_REG_SDM_POSDIV_P2 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_1B48_GP_MISC_REG_SDM_BLP_P2 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1B48_GP_MISC_REG_SDM_GLITCH_FREE_EN_P2 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1B48_GP_MISC_REG_SDM_DIV3_EN_P2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1B48_GP_MISC_REG_SDM_FRA_EN_P2 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1B48_GP_MISC_REG_SDM_PCW_CHG_P2 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1B80_GP_MISC (HDMI2P1_MAC_BASE + 0x1B80)
    #define HD21MAC_CFG_1B80_GP_MISC_REG_SDM_PCW_P3_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1B84_GP_MISC (HDMI2P1_MAC_BASE + 0x1B84)
    #define HD21MAC_CFG_1B84_GP_MISC_REG_SDM_PCW_P3_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1B88_GP_MISC (HDMI2P1_MAC_BASE + 0x1B88)
    #define HD21MAC_CFG_1B88_GP_MISC_REG_SDM_PCW_OVE_P3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1B88_GP_MISC_REG_SDM_EN_P3 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1B88_GP_MISC_REG_SDM_POSDIV_P3 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_1B88_GP_MISC_REG_SDM_BLP_P3 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1B88_GP_MISC_REG_SDM_GLITCH_FREE_EN_P3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1B88_GP_MISC_REG_SDM_DIV3_EN_P3 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1B88_GP_MISC_REG_SDM_FRA_EN_P3 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1B88_GP_MISC_REG_SDM_PCW_CHG_P3 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1BC0_GP_MISC (HDMI2P1_MAC_BASE + 0x1BC0)
    #define HD21MAC_CFG_1BC0_GP_MISC_REG_TO_VP_DE_LEN0_OVE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1BC0_GP_MISC_REG_TO_VP_DE_LEN0 Fld(11,0,AC_MSKW10)//[10:0]
#define HD21MAC_CFG_1BC4_GP_MISC (HDMI2P1_MAC_BASE + 0x1BC4)
    #define HD21MAC_CFG_1BC4_GP_MISC_REG_TO_VP_DE_LEN1_OVE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1BC4_GP_MISC_REG_TO_VP_DE_LEN1 Fld(11,0,AC_MSKW10)//[10:0]
#define HD21MAC_CFG_1BC8_GP_MISC (HDMI2P1_MAC_BASE + 0x1BC8)
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_RST_ERR_CNT_SW_MD_P3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_RST_ERR_CNT_P3 Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_RST_ERR_CNT_SW_MD_P2 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_RST_ERR_CNT_P2 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_DSC_DECODE_FAIL_P1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_DSC_DECODE_FAIL_P0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_PHY_TRAINING_DONE_1_OVE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_PHY_TRAINING_DONE_1 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_PHY_TRAINING_DONE_0_OVE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1BC8_GP_MISC_REG_PHY_TRAINING_DONE_0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1C00_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C00)
    #define HD21MAC_CFG_1C00_FRL_TOP_P0_REG_TESTBUS_SEL Fld(7,0,AC_MSKB0)//[6:0]
#define HD21MAC_CFG_1C04_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C04)
    #define HD21MAC_CFG_1C04_FRL_TOP_P0_REG_WB_DET_USER_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C08_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C08)
    #define HD21MAC_CFG_1C08_FRL_TOP_P0_REG_WB_DET_USER_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1C0C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C0C)
    #define HD21MAC_CFG_1C0C_FRL_TOP_P0_REG_WB_DET_UNLOCK_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1C0C_FRL_TOP_P0_REG_WB_DET_LOCK_TH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1C10_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C10)
    #define HD21MAC_CFG_1C10_FRL_TOP_P0_REG_WB_DET_FSM_PAUSE_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1C10_FRL_TOP_P0_REG_WB_DET_FSM_PAUSE_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1C10_FRL_TOP_P0_REG_WB_DET_FSM_PAUSE_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1C10_FRL_TOP_P0_REG_WB_DET_FSM_PAUSE_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1C10_FRL_TOP_P0_REG_WB_DET_FSM_RST_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1C10_FRL_TOP_P0_REG_WB_DET_FSM_RST_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1C10_FRL_TOP_P0_REG_WB_DET_FSM_RST_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1C10_FRL_TOP_P0_REG_WB_DET_FSM_RST_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1C14_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C14)
    #define HD21MAC_CFG_1C14_FRL_TOP_P0_REG_WB_DET_SFT_OV_EN_L1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1C14_FRL_TOP_P0_REG_WB_DET_SFT_OV_VALUE_L1 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_1C14_FRL_TOP_P0_REG_WB_DET_SFT_OV_EN_L0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1C14_FRL_TOP_P0_REG_WB_DET_SFT_OV_VALUE_L0 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_1C18_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C18)
    #define HD21MAC_CFG_1C18_FRL_TOP_P0_REG_WB_DET_SFT_OV_EN_L3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1C18_FRL_TOP_P0_REG_WB_DET_SFT_OV_VALUE_L3 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_1C18_FRL_TOP_P0_REG_WB_DET_SFT_OV_EN_L2 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1C18_FRL_TOP_P0_REG_WB_DET_SFT_OV_VALUE_L2 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_1C1C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C1C)
    #define HD21MAC_CFG_1C1C_FRL_TOP_P0_REG_TEST_PATH_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1C1C_FRL_TOP_P0_REG_WB_DET_CODE_BIT_REVERSE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1C20_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C20)
    #define HD21MAC_CFG_1C20_FRL_TOP_P0_REG_WB_DET_SFT_STS_L1 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_1C20_FRL_TOP_P0_REG_WB_DET_SFT_STS_L0 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_1C24_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C24)
    #define HD21MAC_CFG_1C24_FRL_TOP_P0_REG_WB_DET_SFT_STS_L3 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_1C24_FRL_TOP_P0_REG_WB_DET_SFT_STS_L2 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_1C28_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C28)
    #define HD21MAC_CFG_1C28_FRL_TOP_P0_REG_WB_DET_CNT_STS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1C28_FRL_TOP_P0_REG_WB_DET_CNT_STS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1C2C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C2C)
    #define HD21MAC_CFG_1C2C_FRL_TOP_P0_REG_WB_DET_CNT_STS_L3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1C2C_FRL_TOP_P0_REG_WB_DET_CNT_STS_L2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1C30_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C30)
    #define HD21MAC_CFG_1C30_FRL_TOP_P0_REG_WB_DET_FSM_STS_L3 Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_1C30_FRL_TOP_P0_REG_WB_DET_FSM_STS_L2 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_1C30_FRL_TOP_P0_REG_WB_DET_FSM_STS_L1 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_1C30_FRL_TOP_P0_REG_WB_DET_FSM_STS_L0 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1C34_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C34)
    #define HD21MAC_CFG_1C34_FRL_TOP_P0_REG_WB_DET_SFT_BUF_STS_L1 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_1C34_FRL_TOP_P0_REG_WB_DET_SFT_BUF_STS_L0 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_1C38_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C38)
    #define HD21MAC_CFG_1C38_FRL_TOP_P0_REG_WB_DET_SFT_BUF_STS_L3 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_1C38_FRL_TOP_P0_REG_WB_DET_SFT_BUF_STS_L2 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_1C3C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C3C)
    #define HD21MAC_CFG_1C3C_FRL_TOP_P0_REG_WB_DET_LOSE_IRQ_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1C3C_FRL_TOP_P0_REG_WB_DET_LOSE_IRQ_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1C3C_FRL_TOP_P0_REG_WB_DET_LOSE_IRQ_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1C3C_FRL_TOP_P0_REG_WB_DET_LOSE_IRQ_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1C3C_FRL_TOP_P0_REG_WB_DET_LOSE_IRQ_CLR_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1C3C_FRL_TOP_P0_REG_WB_DET_LOSE_IRQ_CLR_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1C3C_FRL_TOP_P0_REG_WB_DET_LOSE_IRQ_CLR_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1C3C_FRL_TOP_P0_REG_WB_DET_LOSE_IRQ_CLR_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1C40_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C40)
    #define HD21MAC_CFG_1C40_FRL_TOP_P0_REG_IGNORE_1816B_ERROR_IN_TRAIN_PERIOD Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1C40_FRL_TOP_P0_REG_MASK_SCDC_TO_CLR_ERROR_CNT Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1C40_FRL_TOP_P0_REG_ERROR_CNT_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_1C40_FRL_TOP_P0_REG_RD_ERR_CNT_THR Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_1C40_FRL_TOP_P0_REG_RD_ERR_INIT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1C40_FRL_TOP_P0_REG_EN_16B_OUT_INV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1C40_FRL_TOP_P0_REG_EN_18B_IN_INV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1C44_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C44)
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_RED_CNT_CLR_L3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_RED_CNT_CLR_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_RED_CNT_CLR_L1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_RED_CNT_CLR_L0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_RMD_CNT_CLR_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_RMD_CNT_CLR_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_RMD_CNT_CLR_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_RMD_CNT_CLR_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_CLR_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_CLR_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_CLR_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1C44_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_CLR_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1C48_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C48)
    #define HD21MAC_CFG_1C48_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C4C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C4C)
    #define HD21MAC_CFG_1C4C_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C50_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C50)
    #define HD21MAC_CFG_1C50_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C54_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C54)
    #define HD21MAC_CFG_1C54_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C58_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C58)
    #define HD21MAC_CFG_1C58_FRL_TOP_P0_REG_18B16B_RMD_CNT_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C5C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C5C)
    #define HD21MAC_CFG_1C5C_FRL_TOP_P0_REG_18B16B_RMD_CNT_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C60_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C60)
    #define HD21MAC_CFG_1C60_FRL_TOP_P0_REG_18B16B_RMD_CNT_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C64_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C64)
    #define HD21MAC_CFG_1C64_FRL_TOP_P0_REG_18B16B_RMD_CNT_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C68_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C68)
    #define HD21MAC_CFG_1C68_FRL_TOP_P0_REG_18B16B_RED_CNT_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C6C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C6C)
    #define HD21MAC_CFG_1C6C_FRL_TOP_P0_REG_18B16B_RED_CNT_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C70_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C70)
    #define HD21MAC_CFG_1C70_FRL_TOP_P0_REG_18B16B_RED_CNT_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C74_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C74)
    #define HD21MAC_CFG_1C74_FRL_TOP_P0_REG_18B16B_RED_CNT_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C78_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C78)
    #define HD21MAC_CFG_1C78_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_VLD_TO_SCDC_CLR_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1C78_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_VLD_TO_SCDC_CLR_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1C78_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_VLD_TO_SCDC_CLR_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1C78_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_VLD_TO_SCDC_CLR_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1C78_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_TO_SCDC_CLR_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1C78_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_TO_SCDC_CLR_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1C78_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_TO_SCDC_CLR_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1C78_FRL_TOP_P0_REG_18B16B_SYMBOL_ERROR_CNT_TO_SCDC_CLR_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1C80_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C80)
    #define HD21MAC_CFG_1C80_FRL_TOP_P0_REG_LFSR_SEED_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C84_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C84)
    #define HD21MAC_CFG_1C84_FRL_TOP_P0_REG_LFSR_SEED_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C88_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C88)
    #define HD21MAC_CFG_1C88_FRL_TOP_P0_REG_LFSR_SEED_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C8C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C8C)
    #define HD21MAC_CFG_1C8C_FRL_TOP_P0_REG_LFSR_SEED_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1C94_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C94)
    #define HD21MAC_CFG_1C94_FRL_TOP_P0_REG_INTERLANESKEW_LANE0_CATCH Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_1C94_FRL_TOP_P0_REG_INTERLANESKEW_FORCE_SYMBOL_LOCK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1C94_FRL_TOP_P0_REG_INTERLANESKEW_LOSELOCK_THR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1C98_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C98)
    #define HD21MAC_CFG_1C98_FRL_TOP_P0_REG_INTERLANESKEW_RPTR_OV_EN_L3 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_1C98_FRL_TOP_P0_REG_INTERLANESKEW_RPTR_OV_EN_L2 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_1C98_FRL_TOP_P0_REG_INTERLANESKEW_RPTR_OV_EN_L1 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1C98_FRL_TOP_P0_REG_INTERLANESKEW_RPTR_OV_L3 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_1C98_FRL_TOP_P0_REG_INTERLANESKEW_RPTR_OV_L2 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_1C98_FRL_TOP_P0_REG_INTERLANESKEW_RPTR_OV_L1 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_1C9C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1C9C)
    #define HD21MAC_CFG_1C9C_FRL_TOP_P0_REG_INTERLANESKEW_RPTR_L2 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_1C9C_FRL_TOP_P0_REG_INTERLANESKEW_RPTR_L1 Fld(5,3,AC_MSKB0)//[7:3]
    #define HD21MAC_CFG_1C9C_FRL_TOP_P0_REG_INTERLANESKEW_LOCK Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1C9C_FRL_TOP_P0_REG_INTERLANESKEW_UNLOCK_IRQ Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1C9C_FRL_TOP_P0_REG_INTERLANESKEW_UNLOCK_IRQ_CLR Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1CA0_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CA0)
    #define HD21MAC_CFG_1CA0_FRL_TOP_P0_REG_SHIFT_CNT_TOL Fld(4,0,AC_MSKB0)//[3:0]
    #define HD21MAC_CFG_1CA0_FRL_TOP_P0_REG_INTERLANESKEW_RPTR_L3 Fld(5,8,AC_MSKB1)//[12:8]
#define HD21MAC_CFG_1CA8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CA8)
    #define HD21MAC_CFG_1CA8_FRL_TOP_P0_REG_SR_SSB_CHECK_TIME Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_1CA8_FRL_TOP_P0_REG_SR_SSB_32_PERIOD_OK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1CA8_FRL_TOP_P0_REG_FEC_ENGINE_BYPASS Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1CA8_FRL_TOP_P0_REG_SR_SSB_CHECK_OK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1CA8_FRL_TOP_P0_REG_FEC_DEC_BITERR_ADDED Fld(5,4,AC_MSKW10)//[8:4]
    #define HD21MAC_CFG_1CA8_FRL_TOP_P0_REG_FEC_DEC_ERROR_AUTO_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1CA8_FRL_TOP_P0_REG_FEC_DEC_OUT_MODE Fld(2,1,AC_MSKB0)//[2:1]
    #define HD21MAC_CFG_1CA8_FRL_TOP_P0_REG_FEC_DEC_ALWAYS_FIX Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1CAC_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CAC)
    #define HD21MAC_CFG_1CAC_FRL_TOP_P0_REG_FEC_DEC_BLOCK_WINDOW Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CB0_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CB0)
    #define HD21MAC_CFG_1CB0_FRL_TOP_P0_REG_FEC_ERROR_CNT_TO_SCDC_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_1CB0_FRL_TOP_P0_REG_SR_SSB_DELAY Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1CB4_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CB4)
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALID_SCDC_CLR_L3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALID_SCDC_CLR_L2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALID_SCDC_CLR_L1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALID_SCDC_CLR_L0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_SCDC_CLR_L3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_SCDC_CLR_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_SCDC_CLR_L1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_SCDC_CLR_L0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_CLR_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_CLR_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_CLR_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_CLR_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RESET_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RESET_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RESET_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1CB4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RESET_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1CB8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CB8)
    #define HD21MAC_CFG_1CB8_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_SEL_L3 Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_1CB8_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_SEL_L2 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_1CB8_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_SEL_L1 Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_1CB8_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_SEL_L0 Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_1CC0_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CC0)
    #define HD21MAC_CFG_1CC0_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_0_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CC4_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CC4)
    #define HD21MAC_CFG_1CC4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_1_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CC8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CC8)
    #define HD21MAC_CFG_1CC8_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_0_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CCC_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CCC)
    #define HD21MAC_CFG_1CCC_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_1_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CD0_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CD0)
    #define HD21MAC_CFG_1CD0_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_0_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CD4_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CD4)
    #define HD21MAC_CFG_1CD4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_1_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CD8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CD8)
    #define HD21MAC_CFG_1CD8_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_0_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CDC_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CDC)
    #define HD21MAC_CFG_1CDC_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_1_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CE0_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CE0)
    #define HD21MAC_CFG_1CE0_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CE4_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CE4)
    #define HD21MAC_CFG_1CE4_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CE8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CE8)
    #define HD21MAC_CFG_1CE8_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CEC_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CEC)
    #define HD21MAC_CFG_1CEC_FRL_TOP_P0_REG_FEC_DEC_ERROR_CNT_VALUE_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1CF0_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CF0)
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOSE_LOCK_IRQ_CLR_L3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOSE_LOCK_IRQ_CLR_L2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOSE_LOCK_IRQ_CLR_L1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOSE_LOCK_IRQ_CLR_L0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOSE_LOCK_IRQ_L3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOSE_LOCK_IRQ_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOSE_LOCK_IRQ_L1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOSE_LOCK_IRQ_L0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOCK_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOCK_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOCK_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_LOCK_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_MASK_SYMBOL_LOCK_IN_TRAIN_SEQ Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_TRAINING_EN_VALUE_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_TRAINING_EN_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1CF0_FRL_TOP_P0_REG_SYMBOL_ERROR_INCLUDE_RD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1CF4_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CF4)
    #define HD21MAC_CFG_1CF4_FRL_TOP_P0_REG_SYMBOL_UNLOCK_THR Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1CF4_FRL_TOP_P0_REG_SYMBOL_LOCK_THR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1CF8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1CF8)
    #define HD21MAC_CFG_1CF8_FRL_TOP_P0_REG_SYMBOL_UNLOCK_THR_NORMAL Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1CF8_FRL_TOP_P0_REG_SYMBOL_LOCK_THR_NORMAL Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1D00_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D00)
    #define HD21MAC_CFG_1D00_FRL_TOP_P0_REG_LANE_LINK_QUALITY_ERROR_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D04_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D04)
    #define HD21MAC_CFG_1D04_FRL_TOP_P0_REG_LANE_LINK_QUALITY_ERROR_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D08_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D08)
    #define HD21MAC_CFG_1D08_FRL_TOP_P0_REG_LANE_LINK_QUALITY_ERROR_L2 Fld(16,0,AC_FULLW10)//[15:0]

    //Page HDMI21_MAC_8
#define HD21MAC_CFG_1D0C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D0C)
    #define HD21MAC_CFG_1D0C_FRL_TOP_P0_REG_LANE_LINK_QUALITY_ERROR_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D10_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D10)
    #define HD21MAC_CFG_1D10_FRL_TOP_P0_REG_LANE_LINK_QUALITY_ERROR_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1D10_FRL_TOP_P0_REG_LANE_LINK_QUALITY_ERROR_CLR_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1D10_FRL_TOP_P0_REG_LANE_LINK_QUALITY_ERROR_CLR_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1D10_FRL_TOP_P0_REG_LANE_LINK_QUALITY_ERROR_CLR_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1D10_FRL_TOP_P0_REG_LANE_LINK_QUALITY_ERROR_CLR_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1D14_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D14)
    #define HD21MAC_CFG_1D14_FRL_TOP_P0_REG_FEC_HW_RESET Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D18_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D18)
    #define HD21MAC_CFG_1D18_FRL_TOP_P0_REG_SR_SSB_PERIOD_L0 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_1D1C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D1C)
    #define HD21MAC_CFG_1D1C_FRL_TOP_P0_REG_SR_SSB_PERIOD_L1 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_1D20_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D20)
    #define HD21MAC_CFG_1D20_FRL_TOP_P0_REG_SR_SSB_PERIOD_L2 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_1D24_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D24)
    #define HD21MAC_CFG_1D24_FRL_TOP_P0_REG_SR_SSB_PERIOD_L3 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_1D40_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D40)
    #define HD21MAC_CFG_1D40_FRL_TOP_P0_REG_BIST_FALI_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D44_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D44)
    #define HD21MAC_CFG_1D44_FRL_TOP_P0_REG_BIST_FALI_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1D48_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D48)
    #define HD21MAC_CFG_1D48_FRL_TOP_P0_REG_TESTBUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D4C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D4C)
    #define HD21MAC_CFG_1D4C_FRL_TOP_P0_REG_TESTBUS_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1D80_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D80)
    #define HD21MAC_CFG_1D80_FRL_TOP_P0_REG_18B16B_SR_P_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D84_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D84)
    #define HD21MAC_CFG_1D84_FRL_TOP_P0_REG_18B16B_SR_P_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1D88_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D88)
    #define HD21MAC_CFG_1D88_FRL_TOP_P0_REG_18B16B_SR_N_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D8C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D8C)
    #define HD21MAC_CFG_1D8C_FRL_TOP_P0_REG_18B16B_SR_N_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1D90_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D90)
    #define HD21MAC_CFG_1D90_FRL_TOP_P0_REG_18B16B_SSB_P_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D94_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D94)
    #define HD21MAC_CFG_1D94_FRL_TOP_P0_REG_18B16B_SSB_P_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1D98_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D98)
    #define HD21MAC_CFG_1D98_FRL_TOP_P0_REG_18B16B_SSB_N_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1D9C_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1D9C)
    #define HD21MAC_CFG_1D9C_FRL_TOP_P0_REG_18B16B_SSB_N_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_1DC0_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DC0)
    #define HD21MAC_CFG_1DC0_FRL_TOP_P0_REG_RESERVED_R_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DC4_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DC4)
    #define HD21MAC_CFG_1DC4_FRL_TOP_P0_REG_RESERVED_R_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DC8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DC8)
    #define HD21MAC_CFG_1DC8_FRL_TOP_P0_REG_RESERVED_R_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DCC_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DCC)
    #define HD21MAC_CFG_1DCC_FRL_TOP_P0_REG_RESERVED_R_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DD0_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DD0)
    #define HD21MAC_CFG_1DD0_FRL_TOP_P0_REG_RESERVED_RW_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DD4_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DD4)
    #define HD21MAC_CFG_1DD4_FRL_TOP_P0_REG_RESERVED_RW_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DD8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DD8)
    #define HD21MAC_CFG_1DD8_FRL_TOP_P0_REG_RESERVED_RW_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DDC_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DDC)
    #define HD21MAC_CFG_1DDC_FRL_TOP_P0_REG_RESERVED_RW_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DE8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DE8)
    #define HD21MAC_CFG_1DE8_FRL_TOP_P0_REG_SW_RESET_WHEN_TRAINING_BEGIN_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DEC_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DEC)
    #define HD21MAC_CFG_1DEC_FRL_TOP_P0_REG_SW_RESET_WHEN_TRAINING_BEGIN_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DF0_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DF0)
    #define HD21MAC_CFG_1DF0_FRL_TOP_P0_REG_SW_RESET_WHEN_TRAINING_BEGIN_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DF4_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DF4)
    #define HD21MAC_CFG_1DF4_FRL_TOP_P0_REG_SW_RESET_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DF8_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DF8)
    #define HD21MAC_CFG_1DF8_FRL_TOP_P0_REG_SW_RESET_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1DFC_FRL_TOP_P0 (HDMI2P1_MAC_BASE + 0x1DFC)
    #define HD21MAC_CFG_1DFC_FRL_TOP_P0_REG_SW_RESET_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E00_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E00)
    #define HD21MAC_CFG_1E00_FRL_DEC_P0_REG_FRL_DECODE_ERROR_MASK Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1E00_FRL_DEC_P0_REG_FRL_LANE_NUM_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1E00_FRL_DEC_P0_REG_FRL_LANE_NUM Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1E04_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E04)
    #define HD21MAC_CFG_1E04_FRL_DEC_P0_REG_TESTBUS_MUX Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1E04_FRL_DEC_P0_REG_BYPASS_SSB_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1E04_FRL_DEC_P0_REG_FRL_TMDS_CLK_CTRL_RST Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1E08_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E08)
    #define HD21MAC_CFG_1E08_FRL_DEC_P0_REG_TYPE_DETECT_L_OFFSET Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1E08_FRL_DEC_P0_REG_FRL_DECODE_RESET Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_1E08_FRL_DEC_P0_REG_FRL_DECODE_RESERVED_RESET Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_1E08_FRL_DEC_P0_REG_FRL_DECODE_TIMING_DETECT_RESET Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1E08_FRL_DEC_P0_REG_FRL_DECODE_SRAM_RESET Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1E08_FRL_DEC_P0_REG_FRL_DECODE_DEPACKER_RESET Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1E08_FRL_DEC_P0_REG_FRL_DECODE_TYPE_DETECT_RESET Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1E0C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E0C)
    #define HD21MAC_CFG_1E0C_FRL_DEC_P0_REG_FRL_SRAM_RST_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1E0C_FRL_DEC_P0_REG_FRL_SRAM_SW_RST Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1E0C_FRL_DEC_P0_REG_FRL_SRAM_EMPTY_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1E0C_FRL_DEC_P0_REG_FRL_SRAM_EMPTY Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1E0C_FRL_DEC_P0_REG_FRL_SRAM_FULL_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1E0C_FRL_DEC_P0_REG_FRL_SRAM_FULL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1E10_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E10)
    #define HD21MAC_CFG_1E10_FRL_DEC_P0_REG_FRL_SRAM_READ_START Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1E14_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E14)
    #define HD21MAC_CFG_1E14_FRL_DEC_P0_REG_VTYPE_401_CNT_THRD Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1E14_FRL_DEC_P0_REG_ISLAND_PREAMBLE Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_1E14_FRL_DEC_P0_REG_VIDEO_PREAMBLE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_1E18_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E18)
    #define HD21MAC_CFG_1E18_FRL_DEC_P0_REG_TMDS_DEPACKER_VIDEO_GB_VALUE_MASK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1E40_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E40)
    #define HD21MAC_CFG_1E40_FRL_DEC_P0_REG_FRL_TIMING_DETECT_VTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E44_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E44)
    #define HD21MAC_CFG_1E44_FRL_DEC_P0_REG_FRL_TIMING_DETECT_HTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E48_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E48)
    #define HD21MAC_CFG_1E48_FRL_DEC_P0_REG_FRL_TIMING_DETECT_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E4C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E4C)
    #define HD21MAC_CFG_1E4C_FRL_DEC_P0_REG_FRL_TIMING_DETECT_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E50_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E50)
    #define HD21MAC_CFG_1E50_FRL_DEC_P0_REG_FRL_TIMING_DETECT_V_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E54_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E54)
    #define HD21MAC_CFG_1E54_FRL_DEC_P0_REG_FRL_TIMING_DETECT_VSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E58_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E58)
    #define HD21MAC_CFG_1E58_FRL_DEC_P0_REG_FRL_TIMING_DETECT_V_BACK_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E5C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E5C)
    #define HD21MAC_CFG_1E5C_FRL_DEC_P0_REG_FRL_TIMING_DETECT_H_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E60_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E60)
    #define HD21MAC_CFG_1E60_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_VTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E64_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E64)
    #define HD21MAC_CFG_1E64_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_HTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E68_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E68)
    #define HD21MAC_CFG_1E68_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E6C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E6C)
    #define HD21MAC_CFG_1E6C_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E70_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E70)
    #define HD21MAC_CFG_1E70_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_V_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E74_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E74)
    #define HD21MAC_CFG_1E74_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_VSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E78_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E78)
    #define HD21MAC_CFG_1E78_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_V_BACK_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E7C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E7C)
    #define HD21MAC_CFG_1E7C_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_H_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E80_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E80)
    #define HD21MAC_CFG_1E80_FRL_DEC_P0_REG_FRL_TIMING_DETECT_HSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E84_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E84)
    #define HD21MAC_CFG_1E84_FRL_DEC_P0_REG_FRL_TIMING_DETECT_H_BACK_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E88_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E88)
    #define HD21MAC_CFG_1E88_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_VDE_STABLE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1E88_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_HDE_STABLE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1E88_FRL_DEC_P0_REG_FRL_TIMING_DETECT_VDE_STABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1E88_FRL_DEC_P0_REG_FRL_TIMING_DETECT_HDE_STABLE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1E8C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E8C)
    #define HD21MAC_CFG_1E8C_FRL_DEC_P0_REG_FRL_VIDEO_HDE_CNT_STABLE_CNT_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E90_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E90)
    #define HD21MAC_CFG_1E90_FRL_DEC_P0_REG_FRL_VIDEO_VDE_CNT_STABLE_CNT_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E94_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E94)
    #define HD21MAC_CFG_1E94_FRL_DEC_P0_REG_TMDS_VIDEO_HDE_CNT_STABLE_CNT_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1E98_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1E98)
    #define HD21MAC_CFG_1E98_FRL_DEC_P0_REG_TMDS_VIDEO_VDE_CNT_STABLE_CNT_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1EA0_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1EA0)
    #define HD21MAC_CFG_1EA0_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_HSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1EA4_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1EA4)
    #define HD21MAC_CFG_1EA4_FRL_DEC_P0_REG_TMDS_TIMING_DETECT_H_BACK_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1EA8_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1EA8)
    #define HD21MAC_CFG_1EA8_FRL_DEC_P0_REG_FRL_HDE_CNT_STABLE_EQ_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1EAC_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1EAC)
    #define HD21MAC_CFG_1EAC_FRL_DEC_P0_REG_TMDS_HDE_CNT_STABLE_EQ_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1EC0_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1EC0)
    #define HD21MAC_CFG_1EC0_FRL_DEC_P0_REG_HV_REGEN_V_VRR_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1EC0_FRL_DEC_P0_REG_HV_REGEN_V_FRONT_SYNC_MUX Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1EC0_FRL_DEC_P0_REG_HSYNC_REGEN_MUX Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1EC0_FRL_DEC_P0_REG_HV_REGEN_H_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1EC0_FRL_DEC_P0_REG_HV_REGEN_V_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1EC4_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1EC4)
    #define HD21MAC_CFG_1EC4_FRL_DEC_P0_REG_HV_REGEN_V_FRONT_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1EC8_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1EC8)
    #define HD21MAC_CFG_1EC8_FRL_DEC_P0_REG_HV_REGEN_V_SYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1ECC_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1ECC)
    #define HD21MAC_CFG_1ECC_FRL_DEC_P0_REG_HV_REGEN_H_FRONT_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1ED0_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1ED0)
    #define HD21MAC_CFG_1ED0_FRL_DEC_P0_REG_HV_REGEN_H_SYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F00_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F00)
    #define HD21MAC_CFG_1F00_FRL_DEC_P0_REG_FRL_DECODE_IRQ_STATUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F04_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F04)
    #define HD21MAC_CFG_1F04_FRL_DEC_P0_REG_FRL_DECODE_IRQ_STATUS_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F08_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F08)
    #define HD21MAC_CFG_1F08_FRL_DEC_P0_REG_FRL_DECODE_IRQ_FINAL_STATUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F0C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F0C)
    #define HD21MAC_CFG_1F0C_FRL_DEC_P0_REG_FRL_DECODE_IRQ_FINAL_STATUS_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F10_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F10)
    #define HD21MAC_CFG_1F10_FRL_DEC_P0_REG_FRL_DECODE_IRQ_CLR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F14_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F14)
    #define HD21MAC_CFG_1F14_FRL_DEC_P0_REG_FRL_DECODE_IRQ_CLR_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F18_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F18)
    #define HD21MAC_CFG_1F18_FRL_DEC_P0_REG_FRL_DECODE_IRQ_MASK_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F1C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F1C)
    #define HD21MAC_CFG_1F1C_FRL_DEC_P0_REG_FRL_DECODE_IRQ_MASK_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F20_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F20)
    #define HD21MAC_CFG_1F20_FRL_DEC_P0_REG_FRL_DECODE_IRQ_FORCE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F24_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F24)
    #define HD21MAC_CFG_1F24_FRL_DEC_P0_REG_FRL_DECODE_IRQ_FORCE_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F40_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F40)
    #define HD21MAC_CFG_1F40_FRL_DEC_P0_REG_CTSN_SYNTH_RING_CNT_PERIOD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F44_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F44)
    #define HD21MAC_CFG_1F44_FRL_DEC_P0_REG_CTSN_SYNTH_RING_CNT_PERIOD_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_1F48_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F48)
    #define HD21MAC_CFG_1F48_FRL_DEC_P0_REG_CTSN_SYNTH_RING_CNT_SIZE Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_1F48_FRL_DEC_P0_REG_CTSN_SYNTH_REFRESH_RATIO_MUX Fld(2,1,AC_MSKB0)//[2:1]
    #define HD21MAC_CFG_1F48_FRL_DEC_P0_REG_CTSN_SYNTH_CNT_EN_START_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1F4C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F4C)
    #define HD21MAC_CFG_1F4C_FRL_DEC_P0_REG_CTSN_SYNTH_CNT_FAST_DIV_VAL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_1F4C_FRL_DEC_P0_REG_CTSN_SYNTH_RATIO_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1F4C_FRL_DEC_P0_REG_CTSN_SYNTH_RATIO_OVE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1F50_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F50)
    #define HD21MAC_CFG_1F50_FRL_DEC_P0_REG_CTSN_SYNTH_PERIOD_OV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F54_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F54)
    #define HD21MAC_CFG_1F54_FRL_DEC_P0_REG_CTSN_SYNTH_PERIOD_OV_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1F58_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F58)
    #define HD21MAC_CFG_1F58_FRL_DEC_P0_REG_CTSN_SYNTH_ADD_OV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F5C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F5C)
    #define HD21MAC_CFG_1F5C_FRL_DEC_P0_REG_CTSN_SYNTH_ADD_OV_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1F60_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F60)
    #define HD21MAC_CFG_1F60_FRL_DEC_P0_REG_CTSN_SYNTH_STABLE_PERIOD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1F64_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F64)
    #define HD21MAC_CFG_1F64_FRL_DEC_P0_REG_CTSN_SYNTH_BIG_CHG_PERIOD_THR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F68_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F68)
    #define HD21MAC_CFG_1F68_FRL_DEC_P0_REG_CTSN_SYNTH_BIG_CHG_PERIOD_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1F68_FRL_DEC_P0_REG_CTSN_SYNTH_BIG_CHG_PERIOD_THR_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1F6C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F6C)
    #define HD21MAC_CFG_1F6C_FRL_DEC_P0_REG_CTSN_SYNTH_BIG_CHG_ADD_THR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F70_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F70)
    #define HD21MAC_CFG_1F70_FRL_DEC_P0_REG_CTSN_SYNTH_BIG_CHG_ADD_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1F70_FRL_DEC_P0_REG_CTSN_SYNTH_BIG_CHG_ADD_THR_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1F74_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F74)
    #define HD21MAC_CFG_1F74_FRL_DEC_P0_REG_CTSN_SYNTH_BIG_CHG_RECORD_PERIOD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1F78_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F78)
    #define HD21MAC_CFG_1F78_FRL_DEC_P0_REG_CTSN_SYNTH_TMDS_CNT_DIFF_PERIOD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F7C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F7C)
    #define HD21MAC_CFG_1F7C_FRL_DEC_P0_REG_CTSN_SYNTH_TMDS_CNT_DIFF_CLEAR Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_1F7C_FRL_DEC_P0_REG_CTSN_SYNTH_TMDS_CNT_DIFF_MODE Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_1F7C_FRL_DEC_P0_REG_CTSN_SYNTH_TMDS_CNT_DIFF_PERIOD_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_1F80_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F80)
    #define HD21MAC_CFG_1F80_FRL_DEC_P0_REG_CLK_TMDS_DE_JITTER_EN_OV Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1F80_FRL_DEC_P0_REG_CLK_TMDS_DE_JITTER_EN_OVE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1F80_FRL_DEC_P0_REG_CTSN_SYNTH_CNT_RST_OVE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1F80_FRL_DEC_P0_REG_CTSN_SYNTH_CNT_RST_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1F84_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F84)
    #define HD21MAC_CFG_1F84_FRL_DEC_P0_REG_CTSN_SYNTH_TMDS_DIFF_CUR_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_1F84_FRL_DEC_P0_REG_CTSN_SYNTH_CNT_EN_START_MODE Fld(2,4,AC_MSKB0)//[5:4]
#define HD21MAC_CFG_1F88_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F88)
    #define HD21MAC_CFG_1F88_FRL_DEC_P0_REG_CTSN_SYNTH_RING_CNT_SWITCH_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F8C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F8C)
    #define HD21MAC_CFG_1F8C_FRL_DEC_P0_REG_CTSN_SYNTH_RING_CNT_SWITCH_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_1F90_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F90)
    #define HD21MAC_CFG_1F90_FRL_DEC_P0_REG_CTSN_SYNTH_BIG_CHG_INCREASE_NUM Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_1F90_FRL_DEC_P0_REG_CTSN_SYNTH_BIG_CHG_NUM Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_1F94_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F94)
    #define HD21MAC_CFG_1F94_FRL_DEC_P0_REG_CTSN_SYNTH_MAX_TMDS_CURRENT_LEAD Fld(3,1,AC_MSKB0)//[3:1]
    #define HD21MAC_CFG_1F94_FRL_DEC_P0_REG_CLK_TMDS_DE_JITTER_EN_HW Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1F98_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F98)
    #define HD21MAC_CFG_1F98_FRL_DEC_P0_REG_CTSN_SYNTH_MAX_TMDS_DIFF_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1F9C_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1F9C)
    #define HD21MAC_CFG_1F9C_FRL_DEC_P0_REG_CTSN_SYNTH_MAX_TMDS_DIFF_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_1FA0_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FA0)
    #define HD21MAC_CFG_1FA0_FRL_DEC_P0_REG_CTSN_SYNTH_STAT_TMDS_DIFF_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1FA4_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FA4)
    #define HD21MAC_CFG_1FA4_FRL_DEC_P0_REG_CTSN_SYNTH_STAT_TMDS_DIFF_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_1FA8_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FA8)
    #define HD21MAC_CFG_1FA8_FRL_DEC_P0_REG_CTSN_SYNTH_MAX_STAT_TMDS_DIFF_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1FAC_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FAC)
    #define HD21MAC_CFG_1FAC_FRL_DEC_P0_REG_CTSN_SYNTH_MAX_STAT_TMDS_DIFF_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_1FB0_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FB0)
    #define HD21MAC_CFG_1FB0_FRL_DEC_P0_REG_CTSN_SYNTH_MAX_TMDS_CURRENT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1FB4_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FB4)
    #define HD21MAC_CFG_1FB4_FRL_DEC_P0_REG_CTSN_SYNTH_MAX_TMDS_CURRENT_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_1FB8_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FB8)
    #define HD21MAC_CFG_1FB8_FRL_DEC_P0_REG_CTSN_SYNTH_MIN_TMDS_CURRENT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_1FBC_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FBC)
    #define HD21MAC_CFG_1FBC_FRL_DEC_P0_REG_CTSN_SYNTH_MIN_TMDS_CURRENT_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_1FC0_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FC0)
    #define HD21MAC_CFG_1FC0_FRL_DEC_P0_REG_FRL_HSYNC_POLARITY_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_1FC0_FRL_DEC_P0_REG_FRL_VSYNC_POLARITY_INV Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_1FC0_FRL_DEC_P0_REG_FRL_HSYNC_POLARITY_DETECT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_1FC0_FRL_DEC_P0_REG_FRL_VSYNC_POLARITY_DETECT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_1FC0_FRL_DEC_P0_REG_TMDS_HSYNC_POLARITY_SW Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_1FC0_FRL_DEC_P0_REG_TMDS_VSYNC_POLARITY_SW Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_1FC4_FRL_DEC_P0 (HDMI2P1_MAC_BASE + 0x1FC4)
    #define HD21MAC_CFG_1FC4_FRL_DEC_P0_REG_FRL_DEPACK_BUG_EN Fld(1,4,AC_MSKB0)//[4:4]

#define HD21MAC_CFG_2000_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2000)
    #define HD21MAC_CFG_2000_DTOP_P0_REG_SW_RESERVED1 Fld(9,7,AC_MSKW10)//[15:7]
    #define HD21MAC_CFG_2000_DTOP_P0_REG_BOUNDARY_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2000_DTOP_P0_REG_ACCU_ERR_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2000_DTOP_P0_REG_EQ_NEW_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2000_DTOP_P0_REG_SW_RESERVED0 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2004_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2004)
    #define HD21MAC_CFG_2004_DTOP_P0_REG_PHR_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2008_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2008)
    #define HD21MAC_CFG_2008_DTOP_P0_REG_PHG_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_200C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x200C)
    #define HD21MAC_CFG_200C_DTOP_P0_REG_PHB_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2010_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2010)
    #define HD21MAC_CFG_2010_DTOP_P0_REG_TMUX_SEL2 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_2010_DTOP_P0_REG_SCMB_STATUS Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2010_DTOP_P0_REG_ACCLSB16BIT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2010_DTOP_P0_REG_ACC8LSB_EXT_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2010_DTOP_P0_REG_ACC8LSB_SELECT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2014_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2014)
    #define HD21MAC_CFG_2014_DTOP_P0_RESERVED_05_15 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_FIFO_EMPTY_STS_CH0 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_FIFO_FULL_STS_CH0 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_EMPTY_IRQ_STS_CH0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_FULL_IRQ_STS_CH0 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_FIFO_RPTR_STS_CH0 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_FIFO_WPTR_STS_CH0 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_FULL_IRQ_CLR_CH0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_EMPTY_IRQ_CLR_CH0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_FIFO_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_8BTO10B_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2014_DTOP_P0_REG_DELAY_1T_ALIGNMENT_STATUS Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2018_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2018)
    #define HD21MAC_CFG_2018_DTOP_P0_RESERVED_06_15 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2018_DTOP_P0_REG_FIFO_EMPTY_STS_CH1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2018_DTOP_P0_REG_FIFO_FULL_STS_CH1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2018_DTOP_P0_REG_EMPTY_IRQ_STS_CH1 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2018_DTOP_P0_REG_FULL_IRQ_STS_CH1 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2018_DTOP_P0_REG_FIFO_RPTR_STS_CH1 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_2018_DTOP_P0_REG_FIFO_WPTR_STS_CH1 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_2018_DTOP_P0_REG_FULL_IRQ_CLR_CH1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2018_DTOP_P0_REG_EMPTY_IRQ_CLR_CH1 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2018_DTOP_P0_RESERVED_06_00 Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_201C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x201C)
    #define HD21MAC_CFG_201C_DTOP_P0_REG_DVIR_RD_ONLY_RESERVED Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_201C_DTOP_P0_REG_DVI_ERSTR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2020_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2020)
    #define HD21MAC_CFG_2020_DTOP_P0_REG_DVIG_RD_ONLY_RESERVED Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2020_DTOP_P0_REG_DVI_ERSTG Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2024_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2024)
    #define HD21MAC_CFG_2024_DTOP_P0_REG_DVIB_RD_ONLY_RESERVED Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2024_DTOP_P0_REG_DVI_ERSTB Fld(8,0,AC_FULLB0)//[7:0]

    //Page HDMI21_MAC_9
#define HD21MAC_CFG_2028_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2028)
    #define HD21MAC_CFG_2028_DTOP_P0_REG_DVI_RESERVED_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2028_DTOP_P0_REG_DVI_PHASE_THD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_202C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x202C)
    #define HD21MAC_CFG_202C_DTOP_P0_REG_DVI_PH_CH_SEL Fld(2,0,AC_MSKB0)//[1:0]
    #define HD21MAC_CFG_202C_DTOP_P0_REG_DVI_RDST Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_202C_DTOP_P0_REG_DVI_ERRD Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_202C_DTOP_P0_REG_DVI_RESERVED_0 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_202C_DTOP_P0_REG_DVI_ERTH Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2030_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2030)
    #define HD21MAC_CFG_2030_DTOP_P0_REG_DVI_INIT_VALUE Fld(5,0,AC_MSKB0)//[4:0]
    #define HD21MAC_CFG_2030_DTOP_P0_REG_DVI_ENSTRCTRL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2030_DTOP_P0_REG_DVI_ENFALLEDGE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2030_DTOP_P0_REG_DVI_PM_SWAP Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2030_DTOP_P0_REG_SFTERFIL Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2030_DTOP_P0_REG_DVI_OVRIDE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2030_DTOP_P0_REG_DVI_RESERVED_1 Fld(6,10,AC_MSKB1)//[15:10]
#define HD21MAC_CFG_2034_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2034)
    #define HD21MAC_CFG_2034_DTOP_P0_REG_DVI_RESERVED_10 Fld(3,0,AC_MSKB0)//[2:0]
    #define HD21MAC_CFG_2034_DTOP_P0_REG_DET_CLK_CNT Fld(13,3,AC_MSKW10)//[15:3]
#define HD21MAC_CFG_2038_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2038)
    #define HD21MAC_CFG_2038_DTOP_P0_REG_DVI_RESERVED_3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2038_DTOP_P0_REG_DVI_RESERVED_2 Fld(4,0,AC_MSKB0)//[3:0]
    #define HD21MAC_CFG_2038_DTOP_P0_REG_AUTO_CLR_ENZ Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2038_DTOP_P0_REG_DVI_RBSWAP Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2038_DTOP_P0_REG_DVI_GATEODCLK Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2038_DTOP_P0_REG_DVI_DELOCKEN Fld(1,7,AC_MSKB0)//[7:7]
#define HD21MAC_CFG_203C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x203C)
    #define HD21MAC_CFG_203C_DTOP_P0_REG_SET_CMPVALUE43_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_203C_DTOP_P0_REG_SET_CMPVALUE43_RESERVED Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_203C_DTOP_P0_REG_SET_CMPVALUE43 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_2040_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2040)
    #define HD21MAC_CFG_2040_DTOP_P0_REG_SET_CMPVALUE85_RESERVED Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2040_DTOP_P0_REG_SET_CMPVALUE85 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_2044_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2044)
    #define HD21MAC_CFG_2044_DTOP_P0_REG_SET_CMPVALUE170_RESERVED Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2044_DTOP_P0_REG_SET_CMPVALUE170 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_2048_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2048)
    #define HD21MAC_CFG_2048_DTOP_P0_REG_COMP_TOL_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2048_DTOP_P0_REG_COMP_TOL Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_2048_DTOP_P0_REG_SET_CMPVALUE Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_204C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x204C)
    #define HD21MAC_CFG_204C_DTOP_P0_REG_SET_CMPVALUE2_RESERVED Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_204C_DTOP_P0_REG_ENLARGE_COM_TOL Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_204C_DTOP_P0_REG_SET_CMPVALUE2 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_2050_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2050)
    #define HD21MAC_CFG_2050_DTOP_P0_REG_DVT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2054_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2054)
    #define HD21MAC_CFG_2054_DTOP_P0_REG_WDT_WIDTH Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2054_DTOP_P0_REG_WDT_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2054_DTOP_P0_REG_WDT_TESTMD Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2054_DTOP_P0_REG_DVT_PH Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2054_DTOP_P0_REG_CH_PH64 Fld(3,11,AC_MSKB1)//[13:11]
    #define HD21MAC_CFG_2054_DTOP_P0_REG_OV_EQ_DONE_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2054_DTOP_P0_REG_OV_EQ_DONE_VALUE Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2058_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2058)
    #define HD21MAC_CFG_2058_DTOP_P0_REG_DVI_RPT_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_205C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x205C)
    #define HD21MAC_CFG_205C_DTOP_P0_REG_DVI_RPT_STATUS1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2060_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2060)
    #define HD21MAC_CFG_2060_DTOP_P0_REG_DBG_RPT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2064_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2064)
    #define HD21MAC_CFG_2064_DTOP_P0_REG_DBG_GP0_TST Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2064_DTOP_P0_REG_ALIGN_DEAD_PROT Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2064_DTOP_P0_REG_SELF_TEST_SMALL_DE_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2064_DTOP_P0_REG_SELF_TEST_CH_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_2064_DTOP_P0_REG_DBG_TST Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2068_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2068)
    #define HD21MAC_CFG_2068_DTOP_P0_RESERVED_1A_15 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2068_DTOP_P0_REG_FIFO_EMPTY_STS_CH2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2068_DTOP_P0_REG_FIFO_FULL_STS_CH2 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2068_DTOP_P0_REG_EMPTY_IRQ_STS_CH2 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2068_DTOP_P0_REG_FULL_IRQ_STS_CH2 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2068_DTOP_P0_REG_FIFO_RPTR_STS_CH2 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_2068_DTOP_P0_REG_FIFO_WPTR_STS_CH2 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_2068_DTOP_P0_REG_FULL_IRQ_CLR_CH2 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2068_DTOP_P0_REG_EMPTY_IRQ_CLR_CH2 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2068_DTOP_P0_RESERVED_1A_00 Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_206C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x206C)
    #define HD21MAC_CFG_206C_DTOP_P0_REG_DVI_RESERVED_5 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2070_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2070)
    #define HD21MAC_CFG_2070_DTOP_P0_REG_VCLK_UNSTABLE_TIMES Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21MAC_CFG_2070_DTOP_P0_REG_VCLK_STABLE_TIMES Fld(7,0,AC_MSKB0)//[6:0]
#define HD21MAC_CFG_2074_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2074)
    #define HD21MAC_CFG_2074_DTOP_P0_REG_DVI_RESERVED_12 Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_2074_DTOP_P0_REG_REF_CNT_NUM_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2074_DTOP_P0_REG_VCLK_CHK_RANGE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2078_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2078)
    #define HD21MAC_CFG_2078_DTOP_P0_REG_VS_RPT_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2078_DTOP_P0_REG_VS_RPT_INTERVAL Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21MAC_CFG_2078_DTOP_P0_REG_FORCE_DEC_MD Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_2078_DTOP_P0_REG_DVI_RESERVED_6 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2078_DTOP_P0_REG_VFILTER_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2078_DTOP_P0_REG_TIMER_V_DIV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_207C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x207C)
    #define HD21MAC_CFG_207C_DTOP_P0_REG_CK_STABLE_NUM Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_207C_DTOP_P0_REG_CK_UNSTABLE_NUM Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_207C_DTOP_P0_REG_CK_FSM_RST Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_207C_DTOP_P0_REG_CK_FSM_PAUSE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_207C_DTOP_P0_REG_CK_RISE_IRQ_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_207C_DTOP_P0_REG_CK_FALL_IRQ_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_207C_DTOP_P0_REG_CK_STABLE_SEL_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2080_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2080)
    #define HD21MAC_CFG_2080_DTOP_P0_REG_MANUAL_EQUALIZER_0 Fld(2,0,AC_MSKB0)//[1:0]
    #define HD21MAC_CFG_2080_DTOP_P0_REG_MANUAL_EQUALIZER_1 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_2080_DTOP_P0_REG_MANUAL_EQUALIZER_2 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_2080_DTOP_P0_REG_DVI_RESERVED_13 Fld(10,6,AC_MSKW10)//[15:6]
#define HD21MAC_CFG_2084_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2084)
    #define HD21MAC_CFG_2084_DTOP_P0_REG_EQ_RESERVED_0 Fld(11,5,AC_MSKW10)//[15:5]
    #define HD21MAC_CFG_2084_DTOP_P0_REG_CK_UNSTABLE_FLAG_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2084_DTOP_P0_REG_TMDS_CK_FALL_IRQ_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2084_DTOP_P0_REG_TMDS_CK_RISE_IRQ_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2084_DTOP_P0_REG_CK_STABLE_GATE_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2084_DTOP_P0_REG_VCLK_STABLE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_208C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x208C)
    #define HD21MAC_CFG_208C_DTOP_P0_REG_SW_RESET Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_208C_DTOP_P0_REG_ENABLE_AUTO_RUN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_208C_DTOP_P0_REG_DVI_RESERVED_14 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_208C_DTOP_P0_REG_DVI_RD_ONLY_RESERVED0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2098_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2098)
    #define HD21MAC_CFG_2098_DTOP_P0_REG_DVI_RD_ONLY_RESERVED1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_209C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x209C)
    #define HD21MAC_CFG_209C_DTOP_P0_REG_MHL_HW_MODE_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_209C_DTOP_P0_REG_DYNAMIC_SEQ_ALIGN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_209C_DTOP_P0_REG_RST_MHL_SEQ_CHK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_209C_DTOP_P0_REG_REF_WBDRY_RDY Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_209C_DTOP_P0_REG_MHL_PACK_PIX_MD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_209C_DTOP_P0_REG_MHL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_20A0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20A0)
    #define HD21MAC_CFG_20A0_DTOP_P0_REG_MHL_RSV Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_20A4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20A4)
    #define HD21MAC_CFG_20A4_DTOP_P0_REG_CSYNC_CFG0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_20A4_DTOP_P0_REG_DVI_RESERVED_7 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_20A8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20A8)
    #define HD21MAC_CFG_20A8_DTOP_P0_REG_CSYNC_CFG2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_20A8_DTOP_P0_REG_CSYNC_CFG1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_20AC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20AC)
    #define HD21MAC_CFG_20AC_DTOP_P0_REG_PH_ALIGN_EVER_OV Fld(1,7,AC_MSKB0)//[7:7]
#define HD21MAC_CFG_20B0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20B0)
    #define HD21MAC_CFG_20B0_DTOP_P0_REG_DEC_HDCP_TSTBUS_SEL Fld(4,12,AC_MSKB1)//[15:12]
#define HD21MAC_CFG_20B4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20B4)
    #define HD21MAC_CFG_20B4_DTOP_P0_REG_RCV_GCP_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_20B4_DTOP_P0_REG_BCHPRTY_ERR Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_20B4_DTOP_P0_REG_BCHERR_CORRECTED Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_20B4_DTOP_P0_REG_DIS_BCHCORR Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_20B4_DTOP_P0_REG_AVMUTE_DISBCHCHK Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_20B4_DTOP_P0_REG_AVMUTE_OVERRIDE_DATA Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_20B4_DTOP_P0_REG_AVMUTE_OVERRIDE_TRIGGER Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_20B4_DTOP_P0_REG_AVMUTE_DIS Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_20B4_DTOP_P0_REG_AVMUTE_RST Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_20B8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20B8)
    #define HD21MAC_CFG_20B8_DTOP_P0_REG_DVI_RESERVED_8 Fld(10,6,AC_MSKW10)//[15:6]
    #define HD21MAC_CFG_20B8_DTOP_P0_REG_REVERSE_DEC Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_20B8_DTOP_P0_REG_REVERSE_DATA Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_20B8_DTOP_P0_REG_FRAME_CLR_AUTO Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_20BC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20BC)
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_DE_STABLE_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_CK_STABLE_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_RESERVED Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_FSM_STATUS Fld(3,10,AC_MSKB1)//[12:10]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_EQ_CNT_STATUS Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_UNSTABLE_RST Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_LARGE_DE_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_ENV_VLD_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_ENV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_FOREVER Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_PAUSE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_20BC_DTOP_P0_REG_AUTO_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_20C0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20C0)
    #define HD21MAC_CFG_20C0_DTOP_P0_REG_AUTO_EQ_50MHZ_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_20C0_DTOP_P0_REG_AUTO_EQ_100MHZ_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_20C0_DTOP_P0_REG_AUTO_EQ_NUM Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_20C0_DTOP_P0_REG_RESERVED_DVI4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_20C4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20C4)
    #define HD21MAC_CFG_20C4_DTOP_P0_REG_DEP_FILTER_LEN Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_20C4_DTOP_P0_REG_DEP_RESERVED_1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_20C4_DTOP_P0_REG_DE_FSM_STATUS Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_20C4_DTOP_P0_REG_DEP_RESERVED_0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_20C4_DTOP_P0_REG_DEP_FSM_PAUSE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_20C4_DTOP_P0_REG_DEP_FSM_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_20C4_DTOP_P0_REG_DE_FILTER_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_20C8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20C8)
    #define HD21MAC_CFG_20C8_DTOP_P0_REG_DEP_CONTINUOUS_NUM Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_20C8_DTOP_P0_REG_DEP_CHANGE_TOL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_20C8_DTOP_P0_REG_DEP_TIMEOUT_TH Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_20C8_DTOP_P0_REG_DEP_SMALL_DE_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_20C8_DTOP_P0_REG_DEP_DE_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_20C8_DTOP_P0_REG_DEP_CH_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_20CC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20CC)
    #define HD21MAC_CFG_20CC_DTOP_P0_REG_DE_RD_ONLY_RESERVED Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_20CC_DTOP_P0_REG_DE_PERIOD Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_20D0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20D0)
    #define HD21MAC_CFG_20D0_DTOP_P0_REG_SELF_TEST_RD_ONLY_RESERVED1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_20D4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20D4)
    #define HD21MAC_CFG_20D4_DTOP_P0_REG_STEERCTRL_CUR2 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_20D4_DTOP_P0_REG_STEERCTRL_CUR1 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_20D4_DTOP_P0_REG_STEERCTRL_CUR0 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_20D4_DTOP_P0_REG_DECSTATE_CHK Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_20E8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20E8)
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_SCMB_FLG_ERR Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_WB_TIMER_TH Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_SCMB_EN_BOTH Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_WB_SCMB_AUTO Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_ALIGN_SRC_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_KW_DLY_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_WB_RST Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_DEC2HDCP_SRC_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_WB2ALN_SRC_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_DIS_SSCP_ONLY Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_DIS_CH_INFO Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_20E8_DTOP_P0_REG_SCMB_FLG_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_20EC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20EC)
    #define HD21MAC_CFG_20EC_DTOP_P0_REG_ADCDVI_IRQ_MASK Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_4 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_20F0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20F0)
    #define HD21MAC_CFG_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_7 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_6 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_5 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_4 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_20F0_DTOP_P0_REG_ADCDVI_IRQ_FORCE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_20F4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20F4)
    #define HD21MAC_CFG_20F4_DTOP_P0_REG_ADCDVI_IRQ_CLR_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_20F8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20F8)
    #define HD21MAC_CFG_20F8_DTOP_P0_REG_MAC_RST Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2100_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2100)
    #define HD21MAC_CFG_2100_DTOP_P0_REG_SW_CLR_ERR_CNT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2100_DTOP_P0_REG_SW_PROBE_ADR Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_2100_DTOP_P0_REG_CHANNEL_SWAP Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2100_DTOP_P0_REG_PIX_SWAP Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2100_DTOP_P0_REG_FORCE_HDMIDET_OFF Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2100_DTOP_P0_REG_SW_PROBE_ON Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2100_DTOP_P0_REG_LOG_TYP Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2100_DTOP_P0_REG_HDMI20_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2100_DTOP_P0_REG_SW_HDE_ON Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2100_DTOP_P0_REG_FSM_ERR_CLEAR Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2104_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2104)
    #define HD21MAC_CFG_2104_DTOP_P0_REG_SW_HDE_LENGTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2108_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2108)
    #define HD21MAC_CFG_2108_DTOP_P0_REG_LFSR_SEED_CH0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_210C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x210C)
    #define HD21MAC_CFG_210C_DTOP_P0_REG_LFSR_SEED_CH1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2110_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2110)
    #define HD21MAC_CFG_2110_DTOP_P0_REG_LFSR_SEED_CH2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2114_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2114)
    #define HD21MAC_CFG_2114_DTOP_P0_REG_LOG_ERRNO Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2118_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2118)
    #define HD21MAC_CFG_2118_DTOP_P0_REG_LOG_HLOC Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_211C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x211C)
    #define HD21MAC_CFG_211C_DTOP_P0_REG_LOG_VLOC Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2120_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2120)
    #define HD21MAC_CFG_2120_DTOP_P0_REG_FSM_ERRCNT_MSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2124_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2124)
    #define HD21MAC_CFG_2124_DTOP_P0_REG_FSM_ERRCNT_LSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2128_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2128)
    #define HD21MAC_CFG_2128_DTOP_P0_REG_ERR_WADR_MSB Fld(6,0,AC_MSKB0)//[5:0]
    #define HD21MAC_CFG_2128_DTOP_P0_REG_ERRLOG_BIST_FAIL_MSB Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2128_DTOP_P0_REG_FSM_ERR_FLAG_MSB Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_212C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x212C)
    #define HD21MAC_CFG_212C_DTOP_P0_REG_ERR_WADR_LSB Fld(6,0,AC_MSKB0)//[5:0]
    #define HD21MAC_CFG_212C_DTOP_P0_REG_ERRLOG_BIST_FAIL_LSB Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_212C_DTOP_P0_REG_FSM_ERR_FLAG_LSB Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2130_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2130)
    #define HD21MAC_CFG_2130_DTOP_P0_REG_ERR_HLOC_MSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2134_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2134)
    #define HD21MAC_CFG_2134_DTOP_P0_REG_ERR_HLOC_LSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2138_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2138)
    #define HD21MAC_CFG_2138_DTOP_P0_REG_ERR_VLOC_MSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_213C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x213C)
    #define HD21MAC_CFG_213C_DTOP_P0_REG_ERR_VLOC_LSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2140_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2140)
    #define HD21MAC_CFG_2140_DTOP_P0_REG_TMDS_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2140_DTOP_P0_REG_DATA_SWAP Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2140_DTOP_P0_REG_ERR_NOT_INC_WBNG Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2140_DTOP_P0_REG_ERR_STATUS_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2140_DTOP_P0_REG_ERR_STATUS_LD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2140_DTOP_P0_REG_ERR_CHANNEL_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_2144_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2144)
    #define HD21MAC_CFG_2144_DTOP_P0_REG_SCV_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2144_DTOP_P0_REG_TERC4_CNT Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2148_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2148)
    #define HD21MAC_CFG_2148_DTOP_P0_REG_UNSCMB_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2148_DTOP_P0_REG_DIS_DC_BALANCE_COUNT Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2148_DTOP_P0_REG_DIS_SCDC_ERRCNT_CLR Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2148_DTOP_P0_REG_DEC_ERROR_CH2 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2148_DTOP_P0_REG_DEC_ERROR_CH1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2148_DTOP_P0_REG_DEC_ERROR_CH0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2148_DTOP_P0_REG_DEC_ERR_CLR_CH2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2148_DTOP_P0_REG_DEC_ERR_CLR_CH1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2148_DTOP_P0_REG_DEC_ERR_CLR_CH0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_214C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x214C)
    #define HD21MAC_CFG_214C_DTOP_P0_REG_ERRCNT_MAX_LEVEL_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_214C_DTOP_P0_REG_TMDS_CNT_RANGE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2150_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2150)
    #define HD21MAC_CFG_2150_DTOP_P0_REG_ERRCNT_MAX_LEVEL_OV Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2160_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2160)
    #define HD21MAC_CFG_2160_DTOP_P0_REG_TST_BUS_RPT1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2160_DTOP_P0_REG_DEC20_TST_BUS_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2164_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2164)
    #define HD21MAC_CFG_2164_DTOP_P0_REG_TST_BUS_RPT0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2168_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2168)
    #define HD21MAC_CFG_2168_DTOP_P0_REG_ERRLOG_MSB_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_216C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x216C)
    #define HD21MAC_CFG_216C_DTOP_P0_REG_ERRLOG_MSB_1 Fld(16,0,AC_FULLW10)//[15:0]

    //Page HDMI21_MAC_10
#define HD21MAC_CFG_2170_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2170)
    #define HD21MAC_CFG_2170_DTOP_P0_REG_ERRLOG_MSB_2 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2174_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2174)
    #define HD21MAC_CFG_2174_DTOP_P0_REG_ERRLOG_LSB_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2178_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2178)
    #define HD21MAC_CFG_2178_DTOP_P0_REG_ERRLOG_LSB_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_217C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x217C)
    #define HD21MAC_CFG_217C_DTOP_P0_REG_LFSR_NUM Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_217C_DTOP_P0_REG_ERRLOG_LSB_2 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2180_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2180)
    #define HD21MAC_CFG_2180_DTOP_P0_REG_LFSR_RR_MD Fld(2,9,AC_MSKB1)//[10:9]
    #define HD21MAC_CFG_2180_DTOP_P0_REG_MHL30_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2180_DTOP_P0_REG_CP_STM_ID Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_2180_DTOP_P0_REG_CP_S_BIT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2180_DTOP_P0_REG_CP_VLD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2180_DTOP_P0_REG_CP_UPDATE_FRZE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2180_DTOP_P0_REG_LFSR_OFF Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2184_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2184)
    #define HD21MAC_CFG_2184_DTOP_P0_REG_MHL30_SM_ERR_CHK_BUS1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2188_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2188)
    #define HD21MAC_CFG_2188_DTOP_P0_REG_MHL30_SM_ERR_CHK_BUS0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_218C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x218C)
    #define HD21MAC_CFG_218C_DTOP_P0_REG_STATE_CUR Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_218C_DTOP_P0_REG_STATE_NXT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_218C_DTOP_P0_REG_STATE_NXT2 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_218C_DTOP_P0_REG_SM_RR_MUST_EQ_4 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_218C_DTOP_P0_REG_SM_PL_LIMIT_OFF Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_218C_DTOP_P0_REG_MHL30_SM_IDLE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_218C_DTOP_P0_REG_CLR_ERR_CHK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2190_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2190)
    #define HD21MAC_CFG_2190_DTOP_P0_REG_HDR_EXT2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2190_DTOP_P0_REG_HDR_EXT3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2194_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2194)
    #define HD21MAC_CFG_2194_DTOP_P0_REG_HDR_EXT0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2194_DTOP_P0_REG_HDR_EXT1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2198_DTOP_P0 (HDMI2P1_MAC_BASE + 0x2198)
    #define HD21MAC_CFG_2198_DTOP_P0_REG_STM_CTR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2198_DTOP_P0_REG_STM_CTR3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_219C_DTOP_P0 (HDMI2P1_MAC_BASE + 0x219C)
    #define HD21MAC_CFG_219C_DTOP_P0_REG_STM_CTR0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_219C_DTOP_P0_REG_STM_CTR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_21A0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21A0)
    #define HD21MAC_CFG_21A0_DTOP_P0_REG_IPT_CTR6 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_21A0_DTOP_P0_REG_IPT_CTR7 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_21A4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21A4)
    #define HD21MAC_CFG_21A4_DTOP_P0_REG_IPT_CTR4 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_21A4_DTOP_P0_REG_IPT_CTR5 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_21A8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21A8)
    #define HD21MAC_CFG_21A8_DTOP_P0_REG_IPT_CTR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_21A8_DTOP_P0_REG_IPT_CTR3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_21AC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21AC)
    #define HD21MAC_CFG_21AC_DTOP_P0_REG_IPT_CTR0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_21AC_DTOP_P0_REG_IPT_CTR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_21B0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21B0)
    #define HD21MAC_CFG_21B0_DTOP_P0_REG_CP_CRC2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_21B0_DTOP_P0_REG_CP_CRC3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_21B4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21B4)
    #define HD21MAC_CFG_21B4_DTOP_P0_REG_CP_CRC0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_21B4_DTOP_P0_REG_CP_CRC1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_21B8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21B8)
    #define HD21MAC_CFG_21B8_DTOP_P0_REG_RX_CRC_VLU1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_21BC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21BC)
    #define HD21MAC_CFG_21BC_DTOP_P0_REG_RX_CRC_VLU0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_21C0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21C0)
    #define HD21MAC_CFG_21C0_DTOP_P0_REG_CRC_VLU_CLR Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_21C0_DTOP_P0_REG_RX_CRC_CMP_EQ Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_21C0_DTOP_P0_REG_CRC_INV_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_21C4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21C4)
    #define HD21MAC_CFG_21C4_DTOP_P0_REG_LNK2PIX_AT_CHK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_21C4_DTOP_P0_REG_MHL30_CP_AS_VLD_PL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_21C4_DTOP_P0_REG_MHL30_CTL_SWH Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_21C4_DTOP_P0_REG_MHL30_BLK_SWH Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_21C4_DTOP_P0_REG_MHL30_VDO_SWH Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_21C4_DTOP_P0_REG_MHL30_CH_02_SWH Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_21C4_DTOP_P0_REG_MHL30_VGB_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_21C4_DTOP_P0_REG_MHL30_VGB_FORCE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_21C8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21C8)
    #define HD21MAC_CFG_21C8_DTOP_P0_REG_PIX_CNT_INI Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_21C8_DTOP_P0_REG_RST_PIX_RD Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_21C8_DTOP_P0_REG_AV_LNK_FCNT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_21CC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21CC)
    #define HD21MAC_CFG_21CC_DTOP_P0_REG_AV_LNK_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_21D0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21D0)
    #define HD21MAC_CFG_21D0_DTOP_P0_REG_AV_LNK_FIX_L Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_21D0_DTOP_P0_REG_AV_LNK_FIX_H Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_21D4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21D4)
    #define HD21MAC_CFG_21D4_DTOP_P0_REG_AV_LNK_RDM_ON Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_21D4_DTOP_P0_REG_AV_LNK_PAT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_21D4_DTOP_P0_REG_AV_LNK_DURAT Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_21D8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21D8)
    #define HD21MAC_CFG_21D8_DTOP_P0_REG_AV_LNK_DURAT_DIS Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_21D8_DTOP_P0_REG_AV_LNK_BIST_VGB_AS_DAT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_21D8_DTOP_P0_REG_AV_LNK_LFSR_INI_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_21D8_DTOP_P0_REG_AV_LNK_STAT_STOP Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_21D8_DTOP_P0_REG_AV_LNK_STAT_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_21D8_DTOP_P0_REG_AV_LNK_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_21DC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21DC)
    #define HD21MAC_CFG_21DC_DTOP_P0_REG_MHL3_DUMY0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_21E0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21E0)
    #define HD21MAC_CFG_21E0_DTOP_P0_REG_ERROR_THRESHOLD_CH0 Fld(15,0,AC_MSKW10)//[14:0]
#define HD21MAC_CFG_21E4_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21E4)
    #define HD21MAC_CFG_21E4_DTOP_P0_REG_ERROR_THRESHOLD_CH1 Fld(15,0,AC_MSKW10)//[14:0]
#define HD21MAC_CFG_21E8_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21E8)
    #define HD21MAC_CFG_21E8_DTOP_P0_REG_ERROR_THRESHOLD_CH2 Fld(15,0,AC_MSKW10)//[14:0]
#define HD21MAC_CFG_21EC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x21EC)
    #define HD21MAC_CFG_21EC_DTOP_P0_REG_EN_EQ_ISLAND_DETECT_AND Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_21EC_DTOP_P0_REG_EN_EQ_ISLAND_DETECT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_21EC_DTOP_P0_REG_POST_EQ_ERROR_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_2200_RSV_P0 (HDMI2P1_MAC_BASE + 0x2200)
    #define HD21MAC_CFG_2200_RSV_P0_REG_NO_INPUT_RST_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2200_RSV_P0_REG_POWERSAVE_FSM_PAUSE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2200_RSV_P0_REG_POWERSAVE_FSM_RST Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2200_RSV_P0_REG_POWER_SAVING_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2204_RSV_P0 (HDMI2P1_MAC_BASE + 0x2204)
    #define HD21MAC_CFG_2204_RSV_P0_REG_POWER_SAVING_MODE_BUF Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2204_RSV_P0_REG_CLK_FLAG_STABLE_FORCE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2204_RSV_P0_REG_LEARN_STABLE_FORCE Fld(1,5,AC_MSKB0)//[5:5]
#define HD21MAC_CFG_2208_RSV_P0 (HDMI2P1_MAC_BASE + 0x2208)
    #define HD21MAC_CFG_2208_RSV_P0_REG_V_FRONT_ON_NUM Fld(12,4,AC_MSKW10)//[15:4]
    #define HD21MAC_CFG_2208_RSV_P0_REG_V_BACK_OFF_NUM Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_220C_RSV_P0 (HDMI2P1_MAC_BASE + 0x220C)
    #define HD21MAC_CFG_220C_RSV_P0_REG_PS_VDEP_CONTINUOUS_NUM Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_220C_RSV_P0_REG_PS_VDE_UNSTABLE_THD Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2210_RSV_P0 (HDMI2P1_MAC_BASE + 0x2210)
    #define HD21MAC_CFG_2210_RSV_P0_REG_PS_DEP_CONTINUOUS_NUM Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2210_RSV_P0_REG_PS_VDEP_CHANGE_TOL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2210_RSV_P0_REG_PS_DEP_CHANGE_TOL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2210_RSV_P0_REG_PS_UNSTABLE_THD Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2214_RSV_P0 (HDMI2P1_MAC_BASE + 0x2214)
    #define HD21MAC_CFG_2214_RSV_P0_REG_DIS_PS_EQ_DONE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2214_RSV_P0_REG_VDE_PS_FSM_STATUS Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_2214_RSV_P0_REG_VDE_STABLE_IRQ_CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2214_RSV_P0_REG_PS_VDEP_FSM_PAUSE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2214_RSV_P0_REG_PS_VDEP_FSM_RST Fld(1,5,AC_MSKB0)//[5:5]
#define HD21MAC_CFG_2218_RSV_P0 (HDMI2P1_MAC_BASE + 0x2218)
    #define HD21MAC_CFG_2218_RSV_P0_REG_DE_PS_FSM_STATUS Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_2218_RSV_P0_REG_DE_STABLE_IRQ_CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2218_RSV_P0_REG_PS_DEP_CH_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_2218_RSV_P0_REG_PS_BIG_DE_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2218_RSV_P0_REG_PS_DEP_FSM_PAUSE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2218_RSV_P0_REG_PS_DEP_FSM_RST Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2218_RSV_P0_REG_PS_DEP_TIMEOUT_TH Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_221C_RSV_P0 (HDMI2P1_MAC_BASE + 0x221C)
    #define HD21MAC_CFG_221C_RSV_P0_REG_VDE_PERIOD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2220_RSV_P0 (HDMI2P1_MAC_BASE + 0x2220)
    #define HD21MAC_CFG_2220_RSV_P0_REG_DE_PERIOD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2228_RSV_P0 (HDMI2P1_MAC_BASE + 0x2228)
    #define HD21MAC_CFG_2228_RSV_P0_REG_SEL_ISLAND_LEARN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2228_RSV_P0_REG_SEL_HDMI_LEARN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2228_RSV_P0_REG_SEL_CTL3_LEARN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2228_RSV_P0_REG_SEL_HSYNC_LEARN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2228_RSV_P0_REG_SEL_VSYNC_LEARN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2228_RSV_P0_REG_CYCL_NON_SAVING Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2228_RSV_P0_REG_STAYIN_SAVING Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_222C_RSV_P0 (HDMI2P1_MAC_BASE + 0x222C)
    #define HD21MAC_CFG_222C_RSV_P0_REG_OVRIDE_SAVINGON_FOR_DEC Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2230_RSV_P0 (HDMI2P1_MAC_BASE + 0x2230)
    #define HD21MAC_CFG_2230_RSV_P0_REG_VDE_BACK_END Fld(12,4,AC_MSKW10)//[15:4]
    #define HD21MAC_CFG_2230_RSV_P0_REG_VDE_FRONT_START Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2234_RSV_P0 (HDMI2P1_MAC_BASE + 0x2234)
    #define HD21MAC_CFG_2234_RSV_P0_REG_V_DEC_DEPEND_CH2_OFF_NUM Fld(12,4,AC_MSKW10)//[15:4]
    #define HD21MAC_CFG_2234_RSV_P0_REG_V_DEC_DEPEND_CH2_ON_NUM Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_223C_RSV_P0 (HDMI2P1_MAC_BASE + 0x223C)
    #define HD21MAC_CFG_223C_RSV_P0_REG_PS_REASEVED_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2240_RSV_P0 (HDMI2P1_MAC_BASE + 0x2240)
    #define HD21MAC_CFG_2240_RSV_P0_REG_POWER_TEST_BUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2244_RSV_P0 (HDMI2P1_MAC_BASE + 0x2244)
    #define HD21MAC_CFG_2244_RSV_P0_REG_POWER_TEST_BUS_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2248_RSV_P0 (HDMI2P1_MAC_BASE + 0x2248)
    #define HD21MAC_CFG_2248_RSV_P0_REG_WAIT_CLOCK_STATE Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2248_RSV_P0_REG_WAIT_TO_STATE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2248_RSV_P0_REG_SOFT_STATE Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2248_RSV_P0_REG_SAVING_ON_STATE Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_224C_RSV_P0 (HDMI2P1_MAC_BASE + 0x224C)
    #define HD21MAC_CFG_224C_RSV_P0_REG_PS_READ_ONLY_RESERVED_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2250_RSV_P0 (HDMI2P1_MAC_BASE + 0x2250)
    #define HD21MAC_CFG_2250_RSV_P0_REG_PS_READ_ONLY_RESERVED_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2254_RSV_P0 (HDMI2P1_MAC_BASE + 0x2254)
    #define HD21MAC_CFG_2254_RSV_P0_REG_PS_READ_ONLY_RESERVED_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2258_RSV_P0 (HDMI2P1_MAC_BASE + 0x2258)
    #define HD21MAC_CFG_2258_RSV_P0_REG_PS_READ_ONLY_RESERVED_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_225C_RSV_P0 (HDMI2P1_MAC_BASE + 0x225C)
    #define HD21MAC_CFG_225C_RSV_P0_REG_PS_REASEVED_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2260_RSV_P0 (HDMI2P1_MAC_BASE + 0x2260)
    #define HD21MAC_CFG_2260_RSV_P0_REG_PS_REASEVED_4 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2264_RSV_P0 (HDMI2P1_MAC_BASE + 0x2264)
    #define HD21MAC_CFG_2264_RSV_P0_REG_PS_REASEVED_5 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2268_RSV_P0 (HDMI2P1_MAC_BASE + 0x2268)
    #define HD21MAC_CFG_2268_RSV_P0_REG_PS_REASEVED_6 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_226C_RSV_P0 (HDMI2P1_MAC_BASE + 0x226C)
    #define HD21MAC_CFG_226C_RSV_P0_REG_PS_REASEVED_7 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2270_RSV_P0 (HDMI2P1_MAC_BASE + 0x2270)
    #define HD21MAC_CFG_2270_RSV_P0_REG_PS_REASEVED_8 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2274_RSV_P0 (HDMI2P1_MAC_BASE + 0x2274)
    #define HD21MAC_CFG_2274_RSV_P0_REG_PS_REASEVED_9 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2278_RSV_P0 (HDMI2P1_MAC_BASE + 0x2278)
    #define HD21MAC_CFG_2278_RSV_P0_REG_PS_REASEVED_A Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_227C_RSV_P0 (HDMI2P1_MAC_BASE + 0x227C)
    #define HD21MAC_CFG_227C_RSV_P0_REG_PS_REASEVED_B Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2604_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2604)
    #define HD21MAC_CFG_2604_PKT1_P0_REG_VBI_PKT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_HBR_PKT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_GM_PKT Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_DSD_PKT Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_ACP_PKT Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_ISRC1_PKT Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_ISRC2_PKT Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_NULL_PKT Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_VS_PKT Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_ACR_PKT Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_ASAMPLE_PKT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_GCP_PKT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_AVI_PKT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_SPD_PKT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_AUI_PKT Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2604_PKT1_P0_REG_MPEG_PKT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2608_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2608)
    #define HD21MAC_CFG_2608_PKT1_P0_REG_RSV_PKT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_HDR_PKT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_ASP_LAYOUT Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_VCLK_STABLE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_CTS_FIFO_OVF Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_CTS_FIFO_UDF Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_CTS_FIFO_FULL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_CTS_FIFO_EMPTY Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_VCLK_BIG_CHG Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_CTSN_OV_RANGE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_PIX_DE_CNT_DIFF Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_FLAT_ASMP_RCVD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_AFIFO34_FULL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_AFIFO34_EMPTY Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_AFIFO12_FULL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2608_PKT1_P0_REG_AFIFO12_EMPTY Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_260C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x260C)
    #define HD21MAC_CFG_260C_PKT1_P0_REG_HDMI_PKT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2610_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2610)
    #define HD21MAC_CFG_2610_PKT1_P0_REG_ADJUST_WR_DISABLE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_PKT_VALID_ARB_ERR Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_PKT_VALID_ERR Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_SHORT_ISLAND_ERR Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_ASP_PRSNT_BIT_ERR Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_AFIFO12_OVER Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_AFIFO12_UNDER Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_DC_FIFO_UDF Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_DC_FIFO_OVF Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_AS_PBIT_ERR Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_ASAMPLE_ERR Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_UNSUPPKT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_CHECKSUM_ERR Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_BCHPRTY_ERR Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2610_PKT1_P0_REG_BCHERR_CORRECTED Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2614_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2614)
    #define HD21MAC_CFG_2614_PKT1_P0_REG_DIS_PKTS_0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2614_PKT1_P0_REG_CTS_FIFO_BYPASS Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2614_PKT1_P0_REG_RESET_CTS_FIFO Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2614_PKT1_P0_REG_DIS_BCHCHK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2614_PKT1_P0_REG_DIS_CHKSUM Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2614_PKT1_P0_REG_EN_USPPKT Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2614_PKT1_P0_REG_DIS_BCHCORR Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2618_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2618)
    #define HD21MAC_CFG_2618_PKT1_P0_REG_VIDEO_BLANK_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2618_PKT1_P0_REG_GCP_OUT_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2618_PKT1_P0_REG_EN_AVMUTE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2618_PKT1_P0_REG_VMUTEBLANK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2618_PKT1_P0_REG_MHL3_HBR_HDR1_CHK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2618_PKT1_P0_REG_MHL3_HBR_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2618_PKT1_P0_REG_EN_DST Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2618_PKT1_P0_REG_EN_HBR Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2618_PKT1_P0_REG_DIS_PKTS_1 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_261C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x261C)
    #define HD21MAC_CFG_261C_PKT1_P0_REG_UPDATE_LMT_CTSN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_EN_CTSN_FILTER Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_GMP_OUT_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_GMP_OUT_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_MANUAL_VS_POL Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_VS_POL_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_CD_ZERO_UPDATE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_WP_AUTO_ADJUST Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_MANUAL_AP_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_MANUAL_ADJUST_PHASE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_DIS_NO_GCP_QUIT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_MANUAL_COLOR_DEPTH Fld(2,3,AC_MSKB0)//[4:3]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_EN_DF_ADJUST Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_AUTO_RST_DC_FIFO Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_261C_PKT1_P0_REG_EN_DEEP_COLOR Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2620_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2620)
    #define HD21MAC_CFG_2620_PKT1_P0_REG_RESERVED1 Fld(6,10,AC_MSKB1)//[15:10]
    #define HD21MAC_CFG_2620_PKT1_P0_REG_DC_ENG_REPLACE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2620_PKT1_P0_REG_MHL_LINK_MODE_MUST_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2620_PKT1_P0_REG_MHL_LINK_MODE_MUST_SW Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2620_PKT1_P0_REG_MHL_LINK_MODE_MUST_SW_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2620_PKT1_P0_REG_RCV_GCP_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2620_PKT1_P0_REG_FORCE_YCBCR_BLACK Fld(2,3,AC_MSKB0)//[4:3]
    #define HD21MAC_CFG_2620_PKT1_P0_REG_INT_CLR_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2620_PKT1_P0_REG_CTSN_OUT2REG_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2624_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2624)
    #define HD21MAC_CFG_2624_PKT1_P0_REG_N_LMT_1 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2624_PKT1_P0_REG_CTS_LMT_1 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2624_PKT1_P0_REG_HDMI_TMC Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2628_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2628)
    #define HD21MAC_CFG_2628_PKT1_P0_REG_CTS_LMT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_262C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x262C)
    #define HD21MAC_CFG_262C_PKT1_P0_REG_N_LMT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2630_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2630)
    #define HD21MAC_CFG_2630_PKT1_P0_REG_VLD_N_RANGE Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2630_PKT1_P0_REG_VLD_CTS_RANGE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2634_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2634)
    #define HD21MAC_CFG_2634_PKT1_P0_REG_CMPVAL50 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2638_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2638)
    #define HD21MAC_CFG_2638_PKT1_P0_REG_CMPVAL100 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_263C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x263C)
    #define HD21MAC_CFG_263C_PKT1_P0_REG_CMPVAL200 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2640_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2640)
    #define HD21MAC_CFG_2640_PKT1_P0_REG_PKT_TYPE Fld(8,0,AC_FULLB0)//[7:0]

    //Page HDMI21_MAC_11
#define HD21MAC_CFG_2644_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2644)
    #define HD21MAC_CFG_2644_PKT1_P0_REG_AUPLL_LOCK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2644_PKT1_P0_REG_FIN Fld(2,13,AC_MSKB1)//[14:13]
    #define HD21MAC_CFG_2644_PKT1_P0_REG_CNT_VAL Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_2648_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2648)
    #define HD21MAC_CFG_2648_PKT1_P0_REG_CTS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_264C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x264C)
    #define HD21MAC_CFG_264C_PKT1_P0_REG_N_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2650_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2650)
    #define HD21MAC_CFG_2650_PKT1_P0_REG_N_1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2650_PKT1_P0_REG_CTS_1 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2654_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2654)
    #define HD21MAC_CFG_2654_PKT1_P0_REG_GCONTROL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2658_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2658)
    #define HD21MAC_CFG_2658_PKT1_P0_REG_ACP_HDR1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_265C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x265C)
    #define HD21MAC_CFG_265C_PKT1_P0_REG_ACP_PB1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_265C_PKT1_P0_REG_ACP_PB0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2660_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2660)
    #define HD21MAC_CFG_2660_PKT1_P0_REG_ACP_PB3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2660_PKT1_P0_REG_ACP_PB2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2664_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2664)
    #define HD21MAC_CFG_2664_PKT1_P0_REG_ACP_PB5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2664_PKT1_P0_REG_ACP_PB4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2668_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2668)
    #define HD21MAC_CFG_2668_PKT1_P0_REG_ACP_PB7 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2668_PKT1_P0_REG_ACP_PB6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_266C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x266C)
    #define HD21MAC_CFG_266C_PKT1_P0_REG_ACP_PB9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_266C_PKT1_P0_REG_ACP_PB8 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2670_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2670)
    #define HD21MAC_CFG_2670_PKT1_P0_REG_ACP_PB11 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2670_PKT1_P0_REG_ACP_PB10 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2674_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2674)
    #define HD21MAC_CFG_2674_PKT1_P0_REG_ACP_PB13 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2674_PKT1_P0_REG_ACP_PB12 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2678_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2678)
    #define HD21MAC_CFG_2678_PKT1_P0_REG_ACP_PB15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2678_PKT1_P0_REG_ACP_PB14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_267C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x267C)
    #define HD21MAC_CFG_267C_PKT1_P0_REG_GBD_HDR2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_267C_PKT1_P0_REG_ISRC1_HDR1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2680_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2680)
    #define HD21MAC_CFG_2680_PKT1_P0_REG_ISRC_PB1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2680_PKT1_P0_REG_ISRC_PB0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2684_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2684)
    #define HD21MAC_CFG_2684_PKT1_P0_REG_ISRC_PB3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2684_PKT1_P0_REG_ISRC_PB2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2688_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2688)
    #define HD21MAC_CFG_2688_PKT1_P0_REG_ISRC_PB5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2688_PKT1_P0_REG_ISRC_PB4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_268C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x268C)
    #define HD21MAC_CFG_268C_PKT1_P0_REG_ISRC_PB7 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_268C_PKT1_P0_REG_ISRC_PB6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2690_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2690)
    #define HD21MAC_CFG_2690_PKT1_P0_REG_ISRC_PB9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2690_PKT1_P0_REG_ISRC_PB8 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2694_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2694)
    #define HD21MAC_CFG_2694_PKT1_P0_REG_ISRC_PB11 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2694_PKT1_P0_REG_ISRC_PB10 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2698_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2698)
    #define HD21MAC_CFG_2698_PKT1_P0_REG_ISRC_PB13 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2698_PKT1_P0_REG_ISRC_PB12 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_269C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x269C)
    #define HD21MAC_CFG_269C_PKT1_P0_REG_ISRC_PB15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_269C_PKT1_P0_REG_ISRC_PB14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26A0_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26A0)
    #define HD21MAC_CFG_26A0_PKT1_P0_REG_ISRC_PB17 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26A0_PKT1_P0_REG_ISRC_PB16 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26A4_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26A4)
    #define HD21MAC_CFG_26A4_PKT1_P0_REG_ISRC_PB19 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26A4_PKT1_P0_REG_ISRC_PB18 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26A8_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26A8)
    #define HD21MAC_CFG_26A8_PKT1_P0_REG_ISRC_PB21 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26A8_PKT1_P0_REG_ISRC_PB20 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26AC_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26AC)
    #define HD21MAC_CFG_26AC_PKT1_P0_REG_ISRC_PB23 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26AC_PKT1_P0_REG_ISRC_PB22 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26B0_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26B0)
    #define HD21MAC_CFG_26B0_PKT1_P0_REG_ISRC_PB25 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26B0_PKT1_P0_REG_ISRC_PB24 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26B4_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26B4)
    #define HD21MAC_CFG_26B4_PKT1_P0_REG_ISRC_PB27 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26B4_PKT1_P0_REG_ISRC_PB26 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26B8_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26B8)
    #define HD21MAC_CFG_26B8_PKT1_P0_REG_ISRC_PB29 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26B8_PKT1_P0_REG_ISRC_PB28 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26BC_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26BC)
    #define HD21MAC_CFG_26BC_PKT1_P0_REG_ISRC_PB31 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26BC_PKT1_P0_REG_ISRC_PB30 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26C0_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26C0)
    #define HD21MAC_CFG_26C0_PKT1_P0_REG_VS_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26C0_PKT1_P0_REG_VS_HDR0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26C4_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26C4)
    #define HD21MAC_CFG_26C4_PKT1_P0_REG_VS_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26C8_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26C8)
    #define HD21MAC_CFG_26C8_PKT1_P0_REG_VS_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26C8_PKT1_P0_REG_VS_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26CC_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26CC)
    #define HD21MAC_CFG_26CC_PKT1_P0_REG_VS_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26CC_PKT1_P0_REG_VS_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26D0_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26D0)
    #define HD21MAC_CFG_26D0_PKT1_P0_REG_VS_IF6 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26D0_PKT1_P0_REG_VS_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26D4_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26D4)
    #define HD21MAC_CFG_26D4_PKT1_P0_REG_VS_IF8 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26D4_PKT1_P0_REG_VS_IF7 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26D8_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26D8)
    #define HD21MAC_CFG_26D8_PKT1_P0_REG_VS_IF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26D8_PKT1_P0_REG_VS_IF9 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26DC_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26DC)
    #define HD21MAC_CFG_26DC_PKT1_P0_REG_VS_IF12 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26DC_PKT1_P0_REG_VS_IF11 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26E0_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26E0)
    #define HD21MAC_CFG_26E0_PKT1_P0_REG_VS_IF14 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26E0_PKT1_P0_REG_VS_IF13 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26E4_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26E4)
    #define HD21MAC_CFG_26E4_PKT1_P0_REG_VS_IF16 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26E4_PKT1_P0_REG_VS_IF15 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26E8_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26E8)
    #define HD21MAC_CFG_26E8_PKT1_P0_REG_VS_IF18 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26E8_PKT1_P0_REG_VS_IF17 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26EC_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26EC)
    #define HD21MAC_CFG_26EC_PKT1_P0_REG_VS_IF20 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26EC_PKT1_P0_REG_VS_IF19 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26F0_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26F0)
    #define HD21MAC_CFG_26F0_PKT1_P0_REG_VS_IF22 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26F0_PKT1_P0_REG_VS_IF21 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26F4_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26F4)
    #define HD21MAC_CFG_26F4_PKT1_P0_REG_VS_IF24 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26F4_PKT1_P0_REG_VS_IF23 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26F8_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26F8)
    #define HD21MAC_CFG_26F8_PKT1_P0_REG_VS_IF26 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26F8_PKT1_P0_REG_VS_IF25 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_26FC_PKT1_P0 (HDMI2P1_MAC_BASE + 0x26FC)
    #define HD21MAC_CFG_26FC_PKT1_P0_REG_VS_IF28 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_26FC_PKT1_P0_REG_VS_IF27 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2700_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2700)
    #define HD21MAC_CFG_2700_PKT1_P0_REG_AVI_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2700_PKT1_P0_REG_AVI_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2704_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2704)
    #define HD21MAC_CFG_2704_PKT1_P0_REG_AVI_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2704_PKT1_P0_REG_AVI_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2708_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2708)
    #define HD21MAC_CFG_2708_PKT1_P0_REG_AVI_IF6 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2708_PKT1_P0_REG_AVI_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_270C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x270C)
    #define HD21MAC_CFG_270C_PKT1_P0_REG_AVI_IF8 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_270C_PKT1_P0_REG_AVI_IF7 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2710_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2710)
    #define HD21MAC_CFG_2710_PKT1_P0_REG_AVI_IF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2710_PKT1_P0_REG_AVI_IF9 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2714_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2714)
    #define HD21MAC_CFG_2714_PKT1_P0_REG_AVI_IF12 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2714_PKT1_P0_REG_AVI_IF11 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2718_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2718)
    #define HD21MAC_CFG_2718_PKT1_P0_REG_AVI_VERSION Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2718_PKT1_P0_REG_AVI_IF13 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_271C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x271C)
    #define HD21MAC_CFG_271C_PKT1_P0_REG_SPD_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_271C_PKT1_P0_REG_SPD_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2720_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2720)
    #define HD21MAC_CFG_2720_PKT1_P0_REG_SPD_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2720_PKT1_P0_REG_SPD_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2724_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2724)
    #define HD21MAC_CFG_2724_PKT1_P0_REG_SPD_IF6 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2724_PKT1_P0_REG_SPD_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2728_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2728)
    #define HD21MAC_CFG_2728_PKT1_P0_REG_SPD_IF8 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2728_PKT1_P0_REG_SPD_IF7 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_272C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x272C)
    #define HD21MAC_CFG_272C_PKT1_P0_REG_SPD_IF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_272C_PKT1_P0_REG_SPD_IF9 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2730_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2730)
    #define HD21MAC_CFG_2730_PKT1_P0_REG_SPD_IF12 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2730_PKT1_P0_REG_SPD_IF11 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2734_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2734)
    #define HD21MAC_CFG_2734_PKT1_P0_REG_SPD_IF14 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2734_PKT1_P0_REG_SPD_IF13 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2738_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2738)
    #define HD21MAC_CFG_2738_PKT1_P0_REG_SPD_IF16 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2738_PKT1_P0_REG_SPD_IF15 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_273C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x273C)
    #define HD21MAC_CFG_273C_PKT1_P0_REG_SPD_IF18 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_273C_PKT1_P0_REG_SPD_IF17 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2740_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2740)
    #define HD21MAC_CFG_2740_PKT1_P0_REG_SPD_IF20 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2740_PKT1_P0_REG_SPD_IF19 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2744_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2744)
    #define HD21MAC_CFG_2744_PKT1_P0_REG_SPD_IF22 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2744_PKT1_P0_REG_SPD_IF21 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2748_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2748)
    #define HD21MAC_CFG_2748_PKT1_P0_REG_SPD_IF24 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2748_PKT1_P0_REG_SPD_IF23 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_274C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x274C)
    #define HD21MAC_CFG_274C_PKT1_P0_REG_SPD_IF25 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2750_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2750)
    #define HD21MAC_CFG_2750_PKT1_P0_REG_AU_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2750_PKT1_P0_REG_AU_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2754_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2754)
    #define HD21MAC_CFG_2754_PKT1_P0_REG_AU_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2754_PKT1_P0_REG_AU_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2758_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2758)
    #define HD21MAC_CFG_2758_PKT1_P0_REG_AU_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_275C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x275C)
    #define HD21MAC_CFG_275C_PKT1_P0_REG_MPEG_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_275C_PKT1_P0_REG_MPEG_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2760_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2760)
    #define HD21MAC_CFG_2760_PKT1_P0_REG_MPEG_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2760_PKT1_P0_REG_MPEG_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2764_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2764)
    #define HD21MAC_CFG_2764_PKT1_P0_REG_MPEG_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2768_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2768)
    #define HD21MAC_CFG_2768_PKT1_P0_REG_HDMI_CS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_276C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x276C)
    #define HD21MAC_CFG_276C_PKT1_P0_REG_HDMI_CS_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2770_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2770)
    #define HD21MAC_CFG_2770_PKT1_P0_REG_HDMI_CS_2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2774_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2774)
    #define HD21MAC_CFG_2774_PKT1_P0_REG_ODD_CK_GATE_OFFSET Fld(13,0,AC_MSKW10)//[12:0]
    #define HD21MAC_CFG_2774_PKT1_P0_REG_ODD_CK_GATE_OV Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2774_PKT1_P0_REG_ODD_CK_GATE_OVE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2774_PKT1_P0_REG_EHTT_GATE_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2778_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2778)
    #define HD21MAC_CFG_2778_PKT1_P0_REG_DC_REP_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2778_PKT1_P0_REG_ODD_CK_GATE_SFT_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2778_PKT1_P0_REG_4X_CK_GATE_OVE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2778_PKT1_P0_REG_4X_CK_GATE_OV Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2778_PKT1_P0_REG_4X_CK_GATE_OFFSET Fld(4,12,AC_MSKB1)//[15:12]
#define HD21MAC_CFG_277C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x277C)
    #define HD21MAC_CFG_277C_PKT1_P0_REG_PKT_RST Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_277C_PKT1_P0_REG_PKT_VALID_DELAY_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_277C_PKT1_P0_REG_FRAME_RP_VAL Fld(3,3,AC_MSKB0)//[5:3]
    #define HD21MAC_CFG_277C_PKT1_P0_REG_HPLL_LOCK_RAW Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_277C_PKT1_P0_REG_AT_MULT_PP_CHK_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_277C_PKT1_P0_REG_HPLL_LOCK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2780_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2780)
    #define HD21MAC_CFG_2780_PKT1_P0_REG_INT_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2784_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2784)
    #define HD21MAC_CFG_2784_PKT1_P0_REG_INT_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2788_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2788)
    #define HD21MAC_CFG_2788_PKT1_P0_REG_INT_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_278C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x278C)
    #define HD21MAC_CFG_278C_PKT1_P0_REG_INT_CLR Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2790_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2790)
    #define HD21MAC_CFG_2790_PKT1_P0_REG_HDMI_AU_FIFO_MUTE_EN Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2790_PKT1_P0_REG_FRAME_RP_MODE Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2790_PKT1_P0_REG_AUDIO_MODE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2794_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2794)
    #define HD21MAC_CFG_2794_PKT1_P0_REG_PIX_DE_CNT Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_2798_PKT1_P0 (HDMI2P1_MAC_BASE + 0x2798)
    #define HD21MAC_CFG_2798_PKT1_P0_REG_HPLL_TEST_IN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_279C_PKT1_P0 (HDMI2P1_MAC_BASE + 0x279C)
    #define HD21MAC_CFG_279C_PKT1_P0_REG_420_AVG_OV_VALUE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_279C_PKT1_P0_REG_420_AVG_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_279C_PKT1_P0_REG_420_TO_SC_OV_VALUE Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_279C_PKT1_P0_REG_420_TO_SC_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_279C_PKT1_P0_REG_422_TO_SC_OV_VALUE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_279C_PKT1_P0_REG_422_TO_SC_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_279C_PKT1_P0_REG_CTS_N_CAL_8P_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_279C_PKT1_P0_REG_CTS_DIV2_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_279C_PKT1_P0_REG_CTS_N_CAL_8P_MODE Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_279C_PKT1_P0_REG_HPLL_PDIV_B Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_2808_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2808)
    #define HD21MAC_CFG_2808_PKT2_P0_REG_420_TRANSFORM_FSM_RST Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_2830_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2830)
    #define HD21MAC_CFG_2830_PKT2_P0_REG_VLD_N_RANGE_EXT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2830_PKT2_P0_REG_VLD_CTS_RANGE_EXT Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2880_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2880)
    #define HD21MAC_CFG_2880_PKT2_P0_REG_SD_CONTROL2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2880_PKT2_P0_REG_SD_CONTROL1 Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_2880_PKT2_P0_REG_HDMI_SD_PIX_CLK_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2880_PKT2_P0_REG_FORCE_422TO444 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2880_PKT2_P0_REG_BYPASS_422TO444 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2884_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2884)
    #define HD21MAC_CFG_2884_PKT2_P0_REG_SD_RESERVED2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2888_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2888)
    #define HD21MAC_CFG_2888_PKT2_P0_REG_CTS_FRAC_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_288C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x288C)
    #define HD21MAC_CFG_288C_PKT2_P0_REG_N_FRAC_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2890_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2890)
    #define HD21MAC_CFG_2890_PKT2_P0_REG_CTSN_LK_TH Fld(3,0,AC_MSKB0)//[2:0]
    #define HD21MAC_CFG_2890_PKT2_P0_REG_CTSN_LK_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2890_PKT2_P0_REG_PKT_FAIL_RST_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2890_PKT2_P0_REG_PKT_FAIL_RST_OVE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2890_PKT2_P0_REG_PKT_8P_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2890_PKT2_P0_REG_PKT_CYC_CNT_NOT_FULL_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2890_PKT2_P0_REG_HDMI_RX2TX_PKT_DATA_PIPE_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_2890_PKT2_P0_REG_HDMI_AUD_STAT_ORI Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2894_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2894)
    #define HD21MAC_CFG_2894_PKT2_P0_REG_RD_POINT Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2894_PKT2_P0_REG_WR_POINT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2894_PKT2_P0_REG_SD_RESERVED3 Fld(6,2,AC_MSKB0)//[7:2]
    #define HD21MAC_CFG_2894_PKT2_P0_REG_AVG_FIFO_EMPTY_FLAG Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2894_PKT2_P0_REG_AVG_FIFO_FULL_FLAG Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2898_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2898)
    #define HD21MAC_CFG_2898_PKT2_P0_REG_HDMI2_IRQ_MASK_13 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2898_PKT2_P0_REG_HDMI2_IRQ_STATUS_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2898_PKT2_P0_REG_HDMI2_IRQ_MASK Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2898_PKT2_P0_REG_HDMI2_INT_STATUS Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_289C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x289C)
    #define HD21MAC_CFG_289C_PKT2_P0_REG_HDMI2_IRQ_CLEAR7 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_289C_PKT2_P0_REG_HDMI2_IRQ_CLEAR6 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_289C_PKT2_P0_REG_HDMI2_IRQ_CLEAR5 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_289C_PKT2_P0_REG_HDMI2_IRQ_CLEAR4 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_289C_PKT2_P0_REG_HDMI2_IRQ_CLEAR3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_289C_PKT2_P0_REG_HDMI2_IRQ_CLEAR2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_289C_PKT2_P0_REG_HDMI2_IRQ_CLEAR1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_289C_PKT2_P0_REG_HDMI2_IRQ_CLEAR0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_289C_PKT2_P0_REG_HDMI2_IRQ_FORCE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_28A0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28A0)
    #define HD21MAC_CFG_28A0_PKT2_P0_REG_PKT_VALID_ERR_MASK Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_28BC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28BC)
    #define HD21MAC_CFG_28BC_PKT2_P0_REG_PIX_REP_HTOTAL_CNT_HOLD Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_28C0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28C0)
    #define HD21MAC_CFG_28C0_PKT2_P0_REG_PIX_VTOTAL_CNT_HOLD Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_28C4_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28C4)
    #define HD21MAC_CFG_28C4_PKT2_P0_REG_PIX_VDE_CNT_HOLD Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_28C8_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28C8)
    #define HD21MAC_CFG_28C8_PKT2_P0_REG_PIX_HTOTAL_CNT_HOLD Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_28CC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28CC)
    #define HD21MAC_CFG_28CC_PKT2_P0_REG_PIXCLK_CMPVAL50 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_28D0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28D0)
    #define HD21MAC_CFG_28D0_PKT2_P0_REG_PIXCLK_CMPVAL100 Fld(16,0,AC_FULLW10)//[15:0]

    //Page HDMI21_MAC_12
#define HD21MAC_CFG_28D4_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28D4)
    #define HD21MAC_CFG_28D4_PKT2_P0_REG_PIXCLK_CMPVAL200 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_28D8_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28D8)
    #define HD21MAC_CFG_28D8_PKT2_P0_REG_PIXCLK_FIN Fld(2,13,AC_MSKB1)//[14:13]
    #define HD21MAC_CFG_28D8_PKT2_P0_REG_PIXCLK_CNT_VAL Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_28DC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28DC)
    #define HD21MAC_CFG_28DC_PKT2_P0_REG_RX2TX_PKT_BYPASS_RD_PTR Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_28DC_PKT2_P0_REG_RX2TX_PKT_BYPASS_WR_PTR Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_28E0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28E0)
    #define HD21MAC_CFG_28E0_PKT2_P0_REG_RX2TX_PKT_BYPASS_FIFO_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_28E0_PKT2_P0_REG_RX2TX_PKT_BYPASS_FIFO_RD_PTR_INIT Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_28E0_PKT2_P0_REG_RX2TX_PKT_BYPASS_FIFO_WR_PTR_INIT Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_28E4_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28E4)
    #define HD21MAC_CFG_28E4_PKT2_P0_REG_RX2TX_PKT_BYPASS_FIFO_FULL_DIFF Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_28E8_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28E8)
    #define HD21MAC_CFG_28E8_PKT2_P0_REG_DC_FIFO_READ_SHIFT_PROT Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_28E8_PKT2_P0_REG_DC_FIFO_WRITE_SHIFT_PROT Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_28E8_PKT2_P0_REG_DC_FIFO_EMPTY_DIFF Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_28E8_PKT2_P0_REG_DC_FIFO_FULL_DIFF Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_28FC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x28FC)
    #define HD21MAC_CFG_28FC_PKT2_P0_REG_AVI_IF14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2900_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2900)
    #define HD21MAC_CFG_2900_PKT2_P0_REG_VBI_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2900_PKT2_P0_REG_VBI_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2904_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2904)
    #define HD21MAC_CFG_2904_PKT2_P0_REG_VBI_PB01 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2904_PKT2_P0_REG_VBI_PB00 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2908_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2908)
    #define HD21MAC_CFG_2908_PKT2_P0_REG_VBI_PB03 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2908_PKT2_P0_REG_VBI_PB02 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_290C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x290C)
    #define HD21MAC_CFG_290C_PKT2_P0_REG_VBI_PB05 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_290C_PKT2_P0_REG_VBI_PB04 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2910_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2910)
    #define HD21MAC_CFG_2910_PKT2_P0_REG_VBI_PB07 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2910_PKT2_P0_REG_VBI_PB06 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2914_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2914)
    #define HD21MAC_CFG_2914_PKT2_P0_REG_VBI_PB09 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2914_PKT2_P0_REG_VBI_PB08 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2918_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2918)
    #define HD21MAC_CFG_2918_PKT2_P0_REG_VBI_PB11 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2918_PKT2_P0_REG_VBI_PB10 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_291C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x291C)
    #define HD21MAC_CFG_291C_PKT2_P0_REG_VBI_PB13 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_291C_PKT2_P0_REG_VBI_PB12 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2920_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2920)
    #define HD21MAC_CFG_2920_PKT2_P0_REG_VBI_PB15 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2920_PKT2_P0_REG_VBI_PB14 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2924_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2924)
    #define HD21MAC_CFG_2924_PKT2_P0_REG_VBI_PB17 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2924_PKT2_P0_REG_VBI_PB16 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2928_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2928)
    #define HD21MAC_CFG_2928_PKT2_P0_REG_VBI_PB19 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2928_PKT2_P0_REG_VBI_PB18 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_292C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x292C)
    #define HD21MAC_CFG_292C_PKT2_P0_REG_VBI_PB21 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_292C_PKT2_P0_REG_VBI_PB20 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2930_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2930)
    #define HD21MAC_CFG_2930_PKT2_P0_REG_VBI_PB23 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2930_PKT2_P0_REG_VBI_PB22 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2934_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2934)
    #define HD21MAC_CFG_2934_PKT2_P0_REG_VBI_PB25 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2934_PKT2_P0_REG_VBI_PB24 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2938_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2938)
    #define HD21MAC_CFG_2938_PKT2_P0_REG_VBI_PB27 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2938_PKT2_P0_REG_VBI_PB26 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_293C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x293C)
    #define HD21MAC_CFG_293C_PKT2_P0_REG_VBI_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2940_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2940)
    #define HD21MAC_CFG_2940_PKT2_P0_REG_AUDIO_AVMUTE_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2940_PKT2_P0_REG_AUDIO_BLOCK_START_MUX_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2940_PKT2_P0_REG_AUDIO_8CH_CH_STATUS_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_2940_PKT2_P0_REG_MHL_CBUS_AUDIO_AVMUTE_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2940_PKT2_P0_REG_CK_LOSE_AVMUTE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2940_PKT2_P0_REG_HDMI_AVMUTE_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2940_PKT2_P0_REG_PORT_SEL_DIFF_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2940_PKT2_P0_REG_PKT_PORT_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_2940_PKT2_P0_REG_DVI_PORT_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_2944_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2944)
    #define HD21MAC_CFG_2944_PKT2_P0_SW_RST Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_2948_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2948)
    #define HD21MAC_CFG_2948_PKT2_P0_REG_TMUX_SEL2 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_294C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x294C)
    #define HD21MAC_CFG_294C_PKT2_P0_REG_DELAY_1T_ALIGNMENT_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_294C_PKT2_P0_REG_DITH_SEED_RST Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_294C_PKT2_P0_REG_DVI_ROUND_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_294C_PKT2_P0_REG_DITH_SEL_DVI Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_2950_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2950)
    #define HD21MAC_CFG_2950_PKT2_P0_REG_AVG_BYPASS Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2950_PKT2_P0_REG_AVG_MODE Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_2950_PKT2_P0_REG_AVG_CTRL_CASE Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_2954_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2954)
    #define HD21MAC_CFG_2954_PKT2_P0_REG_HDMI_420_SW_MODE Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_VSYNC_CLEAR_MODE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_FINAL_LINE_MODE Fld(2,9,AC_MSKB1)//[10:9]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_420_TRANSFORM_PIX_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_CBCR_SWAP Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_HDMI_20_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_420_TRANSFORM_BYPASS Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_420_TRANSFORM_FSM_RST Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_420_TRANSFORM_VDE_POL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_420_TRANSFORM_HSYNC_POL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_420_TRANSFORM_VSYNC_POL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2954_PKT2_P0_REG_420_TRANSFORM_SWAP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2958_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2958)
    #define HD21MAC_CFG_2958_PKT2_P0_REG_FIFO_WR_PTR Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_295C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x295C)
    #define HD21MAC_CFG_295C_PKT2_P0_REG_FIFO_RD_PTR Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_2960_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2960)
    #define HD21MAC_CFG_2960_PKT2_P0_REG_HTOTAL_STABLE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2960_PKT2_P0_REG_HTOTAL Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_2964_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2964)
    #define HD21MAC_CFG_2964_PKT2_P0_REG_DE_TOTAL_STABLE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2964_PKT2_P0_REG_DE_TOTAL Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_2968_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2968)
    #define HD21MAC_CFG_2968_PKT2_P0_REG_RX2TX_PKT_BYPASS_FIFO_BIST_FAIL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2968_PKT2_P0_REG_420_TRANS_BIST_FAIL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2968_PKT2_P0_REG_420_TRANSFORM_FSM_STATE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_296C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x296C)
    #define HD21MAC_CFG_296C_PKT2_P0_REG_AUD_HEAD_VALID_SEL Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_2970_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2970)
    #define HD21MAC_CFG_2970_PKT2_P0_REG_AUD_HEAD_RSV_PKT_TYPE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2978_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2978)
    #define HD21MAC_CFG_2978_PKT2_P0_REG_VBI_PKT_TYPE Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2978_PKT2_P0_REG_DISCHKSUM_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_2978_PKT2_P0_REG_DIS_RSV_PKT Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2978_PKT2_P0_REG_DIS_HDR_PKT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2978_PKT2_P0_REG_DIS_VBI_PKT Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_297C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x297C)
    #define HD21MAC_CFG_297C_PKT2_P0_REG_RSV_PKT_TYPE Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_297C_PKT2_P0_REG_HDR_PKT_TYPE Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2980_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2980)
    #define HD21MAC_CFG_2980_PKT2_P0_REG_HDR_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2980_PKT2_P0_REG_HDR_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2984_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2984)
    #define HD21MAC_CFG_2984_PKT2_P0_REG_HDR_PB01 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2984_PKT2_P0_REG_HDR_PB00 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2988_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2988)
    #define HD21MAC_CFG_2988_PKT2_P0_REG_HDR_PB03 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2988_PKT2_P0_REG_HDR_PB02 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_298C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x298C)
    #define HD21MAC_CFG_298C_PKT2_P0_REG_HDR_PB05 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_298C_PKT2_P0_REG_HDR_PB04 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2990_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2990)
    #define HD21MAC_CFG_2990_PKT2_P0_REG_HDR_PB07 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2990_PKT2_P0_REG_HDR_PB06 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2994_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2994)
    #define HD21MAC_CFG_2994_PKT2_P0_REG_HDR_PB09 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2994_PKT2_P0_REG_HDR_PB08 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2998_PKT2_P0 (HDMI2P1_MAC_BASE + 0x2998)
    #define HD21MAC_CFG_2998_PKT2_P0_REG_HDR_PB11 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2998_PKT2_P0_REG_HDR_PB10 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_299C_PKT2_P0 (HDMI2P1_MAC_BASE + 0x299C)
    #define HD21MAC_CFG_299C_PKT2_P0_REG_HDR_PB13 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_299C_PKT2_P0_REG_HDR_PB12 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29A0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29A0)
    #define HD21MAC_CFG_29A0_PKT2_P0_REG_HDR_PB15 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29A0_PKT2_P0_REG_HDR_PB14 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29A4_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29A4)
    #define HD21MAC_CFG_29A4_PKT2_P0_REG_HDR_PB17 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29A4_PKT2_P0_REG_HDR_PB16 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29A8_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29A8)
    #define HD21MAC_CFG_29A8_PKT2_P0_REG_HDR_PB19 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29A8_PKT2_P0_REG_HDR_PB18 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29AC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29AC)
    #define HD21MAC_CFG_29AC_PKT2_P0_REG_HDR_PB21 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29AC_PKT2_P0_REG_HDR_PB20 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29B0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29B0)
    #define HD21MAC_CFG_29B0_PKT2_P0_REG_HDR_PB23 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29B0_PKT2_P0_REG_HDR_PB22 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29B4_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29B4)
    #define HD21MAC_CFG_29B4_PKT2_P0_REG_HDR_PB25 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29B4_PKT2_P0_REG_HDR_PB24 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29B8_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29B8)
    #define HD21MAC_CFG_29B8_PKT2_P0_REG_HDR_PB27 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29B8_PKT2_P0_REG_HDR_PB26 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29BC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29BC)
    #define HD21MAC_CFG_29BC_PKT2_P0_REG_HDR_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_29C0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29C0)
    #define HD21MAC_CFG_29C0_PKT2_P0_REG_RSV_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29C0_PKT2_P0_REG_RSV_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29C4_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29C4)
    #define HD21MAC_CFG_29C4_PKT2_P0_REG_RSV_PB01 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29C4_PKT2_P0_REG_RSV_PB00 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29C8_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29C8)
    #define HD21MAC_CFG_29C8_PKT2_P0_REG_RSV_PB03 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29C8_PKT2_P0_REG_RSV_PB02 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29CC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29CC)
    #define HD21MAC_CFG_29CC_PKT2_P0_REG_RSV_PB05 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29CC_PKT2_P0_REG_RSV_PB04 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29D0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29D0)
    #define HD21MAC_CFG_29D0_PKT2_P0_REG_RSV_PB07 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29D0_PKT2_P0_REG_RSV_PB06 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29D4_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29D4)
    #define HD21MAC_CFG_29D4_PKT2_P0_REG_RSV_PB09 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29D4_PKT2_P0_REG_RSV_PB08 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29D8_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29D8)
    #define HD21MAC_CFG_29D8_PKT2_P0_REG_RSV_PB11 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29D8_PKT2_P0_REG_RSV_PB10 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29DC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29DC)
    #define HD21MAC_CFG_29DC_PKT2_P0_REG_RSV_PB13 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29DC_PKT2_P0_REG_RSV_PB12 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29E0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29E0)
    #define HD21MAC_CFG_29E0_PKT2_P0_REG_RSV_PB15 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29E0_PKT2_P0_REG_RSV_PB14 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29E4_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29E4)
    #define HD21MAC_CFG_29E4_PKT2_P0_REG_RSV_PB17 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29E4_PKT2_P0_REG_RSV_PB16 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29E8_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29E8)
    #define HD21MAC_CFG_29E8_PKT2_P0_REG_RSV_PB19 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29E8_PKT2_P0_REG_RSV_PB18 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29EC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29EC)
    #define HD21MAC_CFG_29EC_PKT2_P0_REG_RSV_PB21 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29EC_PKT2_P0_REG_RSV_PB20 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29F0_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29F0)
    #define HD21MAC_CFG_29F0_PKT2_P0_REG_RSV_PB23 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29F0_PKT2_P0_REG_RSV_PB22 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29F4_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29F4)
    #define HD21MAC_CFG_29F4_PKT2_P0_REG_RSV_PB25 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29F4_PKT2_P0_REG_RSV_PB24 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29F8_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29F8)
    #define HD21MAC_CFG_29F8_PKT2_P0_REG_RSV_PB27 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_29F8_PKT2_P0_REG_RSV_PB26 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_29FC_PKT2_P0 (HDMI2P1_MAC_BASE + 0x29FC)
    #define HD21MAC_CFG_29FC_PKT2_P0_REG_RSV_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2A00_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A00)
    #define HD21MAC_CFG_2A00_PKT3_P0_REG_VSIF_HDR2_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A00_PKT3_P0_REG_VSIF_HDR1_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A04_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A04)
    #define HD21MAC_CFG_2A04_PKT3_P0_REG_VSIF_PB01_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A04_PKT3_P0_REG_VSIF_PB00_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A08_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A08)
    #define HD21MAC_CFG_2A08_PKT3_P0_REG_VSIF_PB03_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A08_PKT3_P0_REG_VSIF_PB02_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A0C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A0C)
    #define HD21MAC_CFG_2A0C_PKT3_P0_REG_VSIF_PB05_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A0C_PKT3_P0_REG_VSIF_PB04_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A10_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A10)
    #define HD21MAC_CFG_2A10_PKT3_P0_REG_VSIF_PB07_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A10_PKT3_P0_REG_VSIF_PB06_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A14_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A14)
    #define HD21MAC_CFG_2A14_PKT3_P0_REG_VSIF_PB09_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A14_PKT3_P0_REG_VSIF_PB08_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A18_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A18)
    #define HD21MAC_CFG_2A18_PKT3_P0_REG_VSIF_PB11_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A18_PKT3_P0_REG_VSIF_PB10_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A1C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A1C)
    #define HD21MAC_CFG_2A1C_PKT3_P0_REG_VSIF_PB13_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A1C_PKT3_P0_REG_VSIF_PB12_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A20_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A20)
    #define HD21MAC_CFG_2A20_PKT3_P0_REG_VSIF_PB15_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A20_PKT3_P0_REG_VSIF_PB14_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A24_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A24)
    #define HD21MAC_CFG_2A24_PKT3_P0_REG_VSIF_PB17_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A24_PKT3_P0_REG_VSIF_PB16_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A28_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A28)
    #define HD21MAC_CFG_2A28_PKT3_P0_REG_VSIF_PB19_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A28_PKT3_P0_REG_VSIF_PB18_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A2C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A2C)
    #define HD21MAC_CFG_2A2C_PKT3_P0_REG_VSIF_PB21_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A2C_PKT3_P0_REG_VSIF_PB20_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A30_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A30)
    #define HD21MAC_CFG_2A30_PKT3_P0_REG_VSIF_PB23_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A30_PKT3_P0_REG_VSIF_PB22_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A34_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A34)
    #define HD21MAC_CFG_2A34_PKT3_P0_REG_VSIF_PB25_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A34_PKT3_P0_REG_VSIF_PB24_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A38_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A38)
    #define HD21MAC_CFG_2A38_PKT3_P0_REG_VSIF_PB27_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A38_PKT3_P0_REG_VSIF_PB26_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A3C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A3C)
    #define HD21MAC_CFG_2A3C_PKT3_P0_REG_VSIF_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2A40_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A40)
    #define HD21MAC_CFG_2A40_PKT3_P0_REG_VSIF_HDR2_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A40_PKT3_P0_REG_VSIF_HDR1_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A44_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A44)
    #define HD21MAC_CFG_2A44_PKT3_P0_REG_VSIF_PB01_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A44_PKT3_P0_REG_VSIF_PB00_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A48_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A48)
    #define HD21MAC_CFG_2A48_PKT3_P0_REG_VSIF_PB03_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A48_PKT3_P0_REG_VSIF_PB02_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A4C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A4C)
    #define HD21MAC_CFG_2A4C_PKT3_P0_REG_VSIF_PB05_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A4C_PKT3_P0_REG_VSIF_PB04_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A50_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A50)
    #define HD21MAC_CFG_2A50_PKT3_P0_REG_VSIF_PB07_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A50_PKT3_P0_REG_VSIF_PB06_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A54_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A54)
    #define HD21MAC_CFG_2A54_PKT3_P0_REG_VSIF_PB09_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A54_PKT3_P0_REG_VSIF_PB08_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A58_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A58)
    #define HD21MAC_CFG_2A58_PKT3_P0_REG_VSIF_PB11_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A58_PKT3_P0_REG_VSIF_PB10_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A5C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A5C)
    #define HD21MAC_CFG_2A5C_PKT3_P0_REG_VSIF_PB13_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A5C_PKT3_P0_REG_VSIF_PB12_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A60_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A60)
    #define HD21MAC_CFG_2A60_PKT3_P0_REG_VSIF_PB15_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A60_PKT3_P0_REG_VSIF_PB14_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A64_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A64)
    #define HD21MAC_CFG_2A64_PKT3_P0_REG_VSIF_PB17_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A64_PKT3_P0_REG_VSIF_PB16_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A68_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A68)
    #define HD21MAC_CFG_2A68_PKT3_P0_REG_VSIF_PB19_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A68_PKT3_P0_REG_VSIF_PB18_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A6C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A6C)
    #define HD21MAC_CFG_2A6C_PKT3_P0_REG_VSIF_PB21_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A6C_PKT3_P0_REG_VSIF_PB20_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A70_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A70)
    #define HD21MAC_CFG_2A70_PKT3_P0_REG_VSIF_PB23_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A70_PKT3_P0_REG_VSIF_PB22_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A74_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A74)
    #define HD21MAC_CFG_2A74_PKT3_P0_REG_VSIF_PB25_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A74_PKT3_P0_REG_VSIF_PB24_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A78_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A78)
    #define HD21MAC_CFG_2A78_PKT3_P0_REG_VSIF_PB27_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A78_PKT3_P0_REG_VSIF_PB26_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A7C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A7C)
    #define HD21MAC_CFG_2A7C_PKT3_P0_REG_VSIF_INT_EN Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A7C_PKT3_P0_REG_VSIF_INT_EN_4 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2A7C_PKT3_P0_REG_VSIF_PKT_TYPE Fld(8,8,AC_FULLB1)//[15:8]

    //Page HDMI21_MAC_13
#define HD21MAC_CFG_2A80_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A80)
    #define HD21MAC_CFG_2A80_PKT3_P0_REG_VSIF_HDR2_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A80_PKT3_P0_REG_VSIF_HDR1_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A84_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A84)
    #define HD21MAC_CFG_2A84_PKT3_P0_REG_VSIF_PB01_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A84_PKT3_P0_REG_VSIF_PB00_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A88_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A88)
    #define HD21MAC_CFG_2A88_PKT3_P0_REG_VSIF_PB03_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A88_PKT3_P0_REG_VSIF_PB02_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A8C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A8C)
    #define HD21MAC_CFG_2A8C_PKT3_P0_REG_VSIF_PB05_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A8C_PKT3_P0_REG_VSIF_PB04_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A90_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A90)
    #define HD21MAC_CFG_2A90_PKT3_P0_REG_VSIF_PB07_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A90_PKT3_P0_REG_VSIF_PB06_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A94_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A94)
    #define HD21MAC_CFG_2A94_PKT3_P0_REG_VSIF_PB09_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A94_PKT3_P0_REG_VSIF_PB08_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A98_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A98)
    #define HD21MAC_CFG_2A98_PKT3_P0_REG_VSIF_PB11_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A98_PKT3_P0_REG_VSIF_PB10_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2A9C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2A9C)
    #define HD21MAC_CFG_2A9C_PKT3_P0_REG_VSIF_PB13_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2A9C_PKT3_P0_REG_VSIF_PB12_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AA0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AA0)
    #define HD21MAC_CFG_2AA0_PKT3_P0_REG_VSIF_PB15_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AA0_PKT3_P0_REG_VSIF_PB14_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AA4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AA4)
    #define HD21MAC_CFG_2AA4_PKT3_P0_REG_VSIF_PB17_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AA4_PKT3_P0_REG_VSIF_PB16_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AA8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AA8)
    #define HD21MAC_CFG_2AA8_PKT3_P0_REG_VSIF_PB19_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AA8_PKT3_P0_REG_VSIF_PB18_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AAC_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AAC)
    #define HD21MAC_CFG_2AAC_PKT3_P0_REG_VSIF_PB21_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AAC_PKT3_P0_REG_VSIF_PB20_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AB0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AB0)
    #define HD21MAC_CFG_2AB0_PKT3_P0_REG_VSIF_PB23_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AB0_PKT3_P0_REG_VSIF_PB22_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AB4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AB4)
    #define HD21MAC_CFG_2AB4_PKT3_P0_REG_VSIF_PB25_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AB4_PKT3_P0_REG_VSIF_PB24_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AB8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AB8)
    #define HD21MAC_CFG_2AB8_PKT3_P0_REG_VSIF_PB27_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AB8_PKT3_P0_REG_VSIF_PB26_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2ABC_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2ABC)
    #define HD21MAC_CFG_2ABC_PKT3_P0_REG_VSIF_CNT Fld(4,0,AC_MSKB0)//[3:0]
    #define HD21MAC_CFG_2ABC_PKT3_P0_REG_VSIF_NUM_INT Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2ABC_PKT3_P0_REG_NO_VSIF_FCNT Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_2ABC_PKT3_P0_REG_EDR_Q_RANGE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2ABC_PKT3_P0_REG_SET_DOLBY_EDR11 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2ABC_PKT3_P0_REG_CLR_DOLBY_EDR11 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2ABC_PKT3_P0_REG_SET_DOLBY_EDR Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2ABC_PKT3_P0_REG_CLR_DOLBY_EDR Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2AC0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AC0)
    #define HD21MAC_CFG_2AC0_PKT3_P0_REG_VSIF_HDR2_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AC0_PKT3_P0_REG_VSIF_HDR1_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AC4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AC4)
    #define HD21MAC_CFG_2AC4_PKT3_P0_REG_VSIF_PB01_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AC4_PKT3_P0_REG_VSIF_PB00_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AC8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AC8)
    #define HD21MAC_CFG_2AC8_PKT3_P0_REG_VSIF_PB03_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AC8_PKT3_P0_REG_VSIF_PB02_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2ACC_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2ACC)
    #define HD21MAC_CFG_2ACC_PKT3_P0_REG_VSIF_PB05_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2ACC_PKT3_P0_REG_VSIF_PB04_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AD0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AD0)
    #define HD21MAC_CFG_2AD0_PKT3_P0_REG_VSIF_PB07_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AD0_PKT3_P0_REG_VSIF_PB06_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AD4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AD4)
    #define HD21MAC_CFG_2AD4_PKT3_P0_REG_VSIF_PB09_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AD4_PKT3_P0_REG_VSIF_PB08_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AD8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AD8)
    #define HD21MAC_CFG_2AD8_PKT3_P0_REG_VSIF_PB11_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AD8_PKT3_P0_REG_VSIF_PB10_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2ADC_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2ADC)
    #define HD21MAC_CFG_2ADC_PKT3_P0_REG_VSIF_PB13_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2ADC_PKT3_P0_REG_VSIF_PB12_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AE0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AE0)
    #define HD21MAC_CFG_2AE0_PKT3_P0_REG_VSIF_PB15_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AE0_PKT3_P0_REG_VSIF_PB14_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AE4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AE4)
    #define HD21MAC_CFG_2AE4_PKT3_P0_REG_VSIF_PB17_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AE4_PKT3_P0_REG_VSIF_PB16_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AE8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AE8)
    #define HD21MAC_CFG_2AE8_PKT3_P0_REG_VSIF_PB19_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AE8_PKT3_P0_REG_VSIF_PB18_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AEC_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AEC)
    #define HD21MAC_CFG_2AEC_PKT3_P0_REG_VSIF_PB21_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AEC_PKT3_P0_REG_VSIF_PB20_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AF0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AF0)
    #define HD21MAC_CFG_2AF0_PKT3_P0_REG_VSIF_PB23_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AF0_PKT3_P0_REG_VSIF_PB22_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AF4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AF4)
    #define HD21MAC_CFG_2AF4_PKT3_P0_REG_VSIF_PB25_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AF4_PKT3_P0_REG_VSIF_PB24_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AF8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AF8)
    #define HD21MAC_CFG_2AF8_PKT3_P0_REG_VSIF_PB27_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2AF8_PKT3_P0_REG_VSIF_PB26_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2AFC_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2AFC)
    #define HD21MAC_CFG_2AFC_PKT3_P0_REG_VSIF_VERSION Fld(7,0,AC_MSKB0)//[6:0]
    #define HD21MAC_CFG_2AFC_PKT3_P0_REG_VSIF_CHG_DIS Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2AFC_PKT3_P0_REG_VSIF_CHG_CLR Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2AFC_PKT3_P0_REG_VSIF_AWS_SHIFT Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2AFC_PKT3_P0_REG_VSIF_FUL_SHIFT_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2AFC_PKT3_P0_REG_VSIF_DIS_PKT Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2AFC_PKT3_P0_REG_CLR_VSIF_CNT Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2AFC_PKT3_P0_REG_VSIF_VER2_CLR_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2AFC_PKT3_P0_REG_VDE_END_CLR_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2B00_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B00)
    #define HD21MAC_CFG_2B00_PKT3_P0_REG_AM_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B00_PKT3_P0_REG_AM_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B04_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B04)
    #define HD21MAC_CFG_2B04_PKT3_P0_REG_AM_PB01 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B04_PKT3_P0_REG_AM_PB00 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B08_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B08)
    #define HD21MAC_CFG_2B08_PKT3_P0_REG_AM_PB03 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B08_PKT3_P0_REG_AM_PB02 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B0C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B0C)
    #define HD21MAC_CFG_2B0C_PKT3_P0_REG_AM_PB05 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B0C_PKT3_P0_REG_AM_PB04 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B10_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B10)
    #define HD21MAC_CFG_2B10_PKT3_P0_REG_AM_PB07 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B10_PKT3_P0_REG_AM_PB06 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B14_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B14)
    #define HD21MAC_CFG_2B14_PKT3_P0_REG_AM_PB09 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B14_PKT3_P0_REG_AM_PB08 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B18_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B18)
    #define HD21MAC_CFG_2B18_PKT3_P0_REG_AM_PB11 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B18_PKT3_P0_REG_AM_PB10 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B1C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B1C)
    #define HD21MAC_CFG_2B1C_PKT3_P0_REG_AM_PB13 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B1C_PKT3_P0_REG_AM_PB12 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B20_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B20)
    #define HD21MAC_CFG_2B20_PKT3_P0_REG_AM_PB15 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B20_PKT3_P0_REG_AM_PB14 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B24_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B24)
    #define HD21MAC_CFG_2B24_PKT3_P0_REG_AM_PB17 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B24_PKT3_P0_REG_AM_PB16 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B28_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B28)
    #define HD21MAC_CFG_2B28_PKT3_P0_REG_AM_PB19 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2B28_PKT3_P0_REG_AM_PB18 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_2B38_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B38)
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_AM_PKT_TYPE Fld(6,0,AC_MSKB0)//[5:0]
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_DIS_AM_PKT Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_AUD_PKT_BPS Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_DSD_MS_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_ASP_MS_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_DSD_3D_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_ASP_3D_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_AUD_32CH_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_AUD_32CH_OV Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2B38_PKT3_P0_REG_AUD_3D_PRD Fld(2,14,AC_MSKB1)//[15:14]
#define HD21MAC_CFG_2B3C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B3C)
    #define HD21MAC_CFG_2B3C_PKT3_P0_REG_AM_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2B40_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B40)
    #define HD21MAC_CFG_2B40_PKT3_P0_REG_SUPPORT_PKT_HEADER_L Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2B40_PKT3_P0_REG_SUPPORT_PKT_HEADER_H Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2B44_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B44)
    #define HD21MAC_CFG_2B44_PKT3_P0_REG_VSP_HDR_VERSION_DIFF_OVE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2B44_PKT3_P0_REG_VSP_HDR_VERSION_DIFF_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2B48_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B48)
    #define HD21MAC_CFG_2B48_PKT3_P0_REG_AUDIO_IF02 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2B48_PKT3_P0_REG_AUDIO_IF01 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2B4C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B4C)
    #define HD21MAC_CFG_2B4C_PKT3_P0_REG_AUDIO_IF04 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2B4C_PKT3_P0_REG_AUDIO_IF03 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2B50_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B50)
    #define HD21MAC_CFG_2B50_PKT3_P0_REG_AUDIO_IF06 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2B50_PKT3_P0_REG_AUDIO_IF05 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2B54_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B54)
    #define HD21MAC_CFG_2B54_PKT3_P0_REG_AUDIO_IF08 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2B54_PKT3_P0_REG_AUDIO_IF07 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2B58_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B58)
    #define HD21MAC_CFG_2B58_PKT3_P0_REG_AUDIO_IF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2B58_PKT3_P0_REG_AUDIO_IF09 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2B68_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B68)
    #define HD21MAC_CFG_2B68_PKT3_P0_REG_ASP_PKT_VALID_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2B68_PKT3_P0_REG_AMP_PKT_VALID_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2B68_PKT3_P0_REG_ACR_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2B68_PKT3_P0_REG_ACP_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2B6C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B6C)
    #define HD21MAC_CFG_2B6C_PKT3_P0_REG_GBD_PKT_VALID_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2B6C_PKT3_P0_REG_EMP_PKT_VALID_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2B6C_PKT3_P0_REG_AVI_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2B6C_PKT3_P0_REG_AUDIF_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2B70_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B70)
    #define HD21MAC_CFG_2B70_PKT3_P0_REG_ISRC2_PKT_VALID_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2B70_PKT3_P0_REG_ISRC1_PKT_VALID_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2B70_PKT3_P0_REG_HDR_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2B70_PKT3_P0_REG_GCP_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2B74_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B74)
    #define HD21MAC_CFG_2B74_PKT3_P0_REG_VBI_PKT_VALID_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2B74_PKT3_P0_REG_SPD_PKT_VALID_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2B74_PKT3_P0_REG_RSV_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2B74_PKT3_P0_REG_MPEG_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2B78_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B78)
    #define HD21MAC_CFG_2B78_PKT3_P0_REG_VSP_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2B78_PKT3_P0_REG_VSIF_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2B7C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B7C)
    #define HD21MAC_CFG_2B7C_PKT3_P0_REG_HDMIRX21_RX2TX_MTW_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2B80_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B80)
    #define HD21MAC_CFG_2B80_PKT3_P0_REG_SRC_FIELD_INV Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2B80_PKT3_P0_REG_SRC_FIELD_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2B80_PKT3_P0_REG_SRC_DET_I_MD_DET_CONDI_EN Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_2B80_PKT3_P0_REG_SRC_H_POL_OVE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2B80_PKT3_P0_REG_SRC_H_POL_OV Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2B80_PKT3_P0_REG_SRC_V_POL_OVE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2B80_PKT3_P0_REG_SRC_V_POL_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2B80_PKT3_P0_REG_SRC_DET_PIX_PER_CYCLE Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_2B80_PKT3_P0_REG_SRC_DET_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_2B84_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B84)
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_SRC_DET_I_MD_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_SRC_FIELD_NON_MATCH Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_HS_POL Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_VS_POL Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_TIMING_DET_STATUS_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_SC_H_POL_OVE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_SC_H_POL_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_SC_DET_PIX_PER_CYCLE Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_SC_DET_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_SRC_DET_NO_SIGNAL_OVE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2B84_PKT3_P0_REG_SRC_DET_NO_SIGNAL_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2B88_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B88)
    #define HD21MAC_CFG_2B88_PKT3_P0_REG_TIMING_DET_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2B8C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B8C)
    #define HD21MAC_CFG_2B8C_PKT3_P0_REG_TIMING_DET_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2B90_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B90)
    #define HD21MAC_CFG_2B90_PKT3_P0_REG_TIMING_DET_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2B94_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B94)
    #define HD21MAC_CFG_2B94_PKT3_P0_REG_TIMING_DET_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2B98_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B98)
    #define HD21MAC_CFG_2B98_PKT3_P0_REG_TIMING_DET_HS_LENGTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2B9C_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2B9C)
    #define HD21MAC_CFG_2B9C_PKT3_P0_REG_TIMING_DET_VS_LENGTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2BA0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BA0)
    #define HD21MAC_CFG_2BA0_PKT3_P0_REG_TIMING_DET_H_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2BA4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BA4)
    #define HD21MAC_CFG_2BA4_PKT3_P0_REG_TIMING_DET_V_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2BA8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BA8)
    #define HD21MAC_CFG_2BA8_PKT3_P0_REG_TIMING_DET_IRQ_STATUS Fld(16,0,AC_FULLW10)//[15:0]
    #define HD21MAC_CFG_2BA8_PKT3_P0_REG_TIMING_DET_IRQ_HTOTAL_STABLE_STATUS Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_2BAC_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BAC)
    #define HD21MAC_CFG_2BAC_PKT3_P0_REG_TIMING_DET_IRQ_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2BB0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BB0)
    #define HD21MAC_CFG_2BB0_PKT3_P0_REG_TIMING_DET_IRQ_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2BC0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BC0)
    #define HD21MAC_CFG_2BC0_PKT3_P0_REG_VSIF_VID_PB2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2BC0_PKT3_P0_REG_VSIF_VID_PB1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2BC4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BC4)
    #define HD21MAC_CFG_2BC4_PKT3_P0_REG_AUD_MASK_EVENT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2BC4_PKT3_P0_REG_AUD_MASK_EVENT_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2BC4_PKT3_P0_REG_AUD_MASK_OVE Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2BC4_PKT3_P0_REG_AUD_MASK_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2BC4_PKT3_P0_REG_DIS_ALLM_TIMEOUT_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2BC4_PKT3_P0_REG_CLR_ALLM_MODE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2BC4_PKT3_P0_REG_SET_ALLM_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2BC4_PKT3_P0_REG_DIS_ALLM_VSIF_VID Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2BC4_PKT3_P0_REG_VSIF_VID_PB3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2BC8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BC8)
    #define HD21MAC_CFG_2BC8_PKT3_P0_REG_VMUTE_CONDI Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2BCC_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BCC)
    #define HD21MAC_CFG_2BCC_PKT3_P0_REG_H_WIN_PARA_SEL Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_2BCC_PKT3_P0_REG_H_WIN_PARA Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_2BD0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BD0)
    #define HD21MAC_CFG_2BD0_PKT3_P0_REG_DC_READ_PTR_START_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2BD0_PKT3_P0_REG_DC_MODE_CHANGE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2BD0_PKT3_P0_REG_DC_DE_STABLE_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2BD0_PKT3_P0_REG_HV_RPLC_CFG Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2BD4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BD4)
    #define HD21MAC_CFG_2BD4_PKT3_P0_REG_TMDS_PTR_GRAY Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2BD4_PKT3_P0_REG_PIX_PTR_GRAY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2BD4_PKT3_P0_REG_TMDS_PTR_NEXT_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2BD4_PKT3_P0_REG_PIX_PTR_NEXT_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2BD8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BD8)
    #define HD21MAC_CFG_2BD8_PKT3_P0_REG_PHASE_DIFF Fld(3,13,AC_MSKB1)//[15:13]
    #define HD21MAC_CFG_2BD8_PKT3_P0_REG_TMDS_S Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_2BDC_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BDC)
    #define HD21MAC_CFG_2BDC_PKT3_P0_REG_PIX_PTR_GRAY_S1_W Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2BDC_PKT3_P0_REG_TMDS_PTR_GRAY_BUF Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2BDC_PKT3_P0_REG_TMDS_PTR_GRAY_S1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2BDC_PKT3_P0_REG_PIX_PTR_GRAY_BUF Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2BE0_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BE0)
    #define HD21MAC_CFG_2BE0_PKT3_P0_REG_TMDS_PTR_A1_GRAY Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2BE0_PKT3_P0_REG_TMDS_PTR_D1_GRAY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2BE0_PKT3_P0_REG_PIX_PTR_A1_GRAY Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2BE0_PKT3_P0_REG_PIX_PTR_D1_GRAY Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2BE4_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BE4)
    #define HD21MAC_CFG_2BE4_PKT3_P0_REG_TMDS_PTR_A2_GRAY Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2BE4_PKT3_P0_REG_TMDS_PTR_D2_GRAY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2BE4_PKT3_P0_REG_PIX_PTR_A2_GRAY Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2BE4_PKT3_P0_REG_PIX_PTR_D2_GRAY Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2BE8_PKT3_P0 (HDMI2P1_MAC_BASE + 0x2BE8)
    #define HD21MAC_CFG_2BE8_PKT3_P0_REG_TMDS_PTR_A3_GRAY Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2BE8_PKT3_P0_REG_TMDS_PTR_D3_GRAY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2BE8_PKT3_P0_REG_PIX_PTR_A3_GRAY Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2BE8_PKT3_P0_REG_PIX_PTR_D3_GRAY Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2C00_EM_P0 (HDMI2P1_MAC_BASE + 0x2C00)
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_HDR_TY3_TAG_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_HDR_TY2_TAG_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_HDR_TY1_TAG_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_HDR_DATA_SET_LENGTH_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_HDR_NEW_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_HDR_END_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_HDR_SEQUENCE_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_HDR_LAST_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_HDR_FIRST_MASK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_VENDOR_LAST_MASK Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_VENDOR_NEW_MASK Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_VENDOR_END_MASK Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_VENDOR_SEQUENCE_MASK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_VENDOR_FIRST_MASK Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_SEQUENCE_MASK Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2C00_EM_P0_REG_EMP_FIRST_MASK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2C04_EM_P0 (HDMI2P1_MAC_BASE + 0x2C04)
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_HDR_ENABLE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_VIDEO_TIMING_DATA_SET_LENGTH_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_VIDEO_TIMING_END_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_VIDEO_TIMING_NEW_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_VIDEO_TIMING_SEQUENCE_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_VIDEO_TIMING_LAST_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_VIDEO_TIMING_FIRST_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_DSC_DATA_SET_LENGTH_MASK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_DSC_NEW_MASK Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_DSC_END_MASK Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_DSC_SEQUENCE_MASK Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_DSC_LAST_MASK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_DSC_FIRST_MASK Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2C04_EM_P0_REG_EMP_HDR_TY4_TAG_MASK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2C08_EM_P0 (HDMI2P1_MAC_BASE + 0x2C08)
    #define HD21MAC_CFG_2C08_EM_P0_REG_EMP_SW_RESET Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2C08_EM_P0_REG_EMP_TIMER_PULSE_ENABLE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2C08_EM_P0_REG_DSC_ERROR_FILTER_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2C08_EM_P0_REG_DSC_END_LINE_PULSE_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2C08_EM_P0_REG_DSC_SEQUENCE_NUMBER_EVENT_BUF_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2C08_EM_P0_REG_DSC_INTERRUPT_EVENT_BUF_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2C08_EM_P0_REG_DSC_FIRST_EVENT_BUF_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2C08_EM_P0_REG_DSC_SEQUENCE_EVENT_BUF_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2C08_EM_P0_REG_DSC_LAST_EVENT_BUF_MASK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2C08_EM_P0_REG_ALL_OUTVALID Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2C08_EM_P0_REG_EMP_FVA_ENABLE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2C08_EM_P0_REG_EMP_VENDOR_ENABLE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2C08_EM_P0_REG_EMP_VRR_ENABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2C08_EM_P0_REG_EMP_DSC_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2C0C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C0C)
    #define HD21MAC_CFG_2C0C_EM_P0_REG_EMP_SEQUENCE Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C0C_EM_P0_REG_ORGANIZATION_ID Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C10_EM_P0 (HDMI2P1_MAC_BASE + 0x2C10)
    #define HD21MAC_CFG_2C10_EM_P0_REG_DATA_SET_TAG Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C14_EM_P0 (HDMI2P1_MAC_BASE + 0x2C14)
    #define HD21MAC_CFG_2C14_EM_P0_REG_ORGANIZATION_ID_TAG_SELECT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2C14_EM_P0_REG_HCATIVE_BYTE_SWAP Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2C14_EM_P0_REG_END_LINE_PULSE_SELECT_MTW Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2C14_EM_P0_REG_GENERAL_EMP_UPDATE_PULSE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2C14_EM_P0_REG_END_LINE_DECREASE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2C14_EM_P0_REG_LINE_EXTENDTION Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2C14_EM_P0_REG_EMP_VS_F Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2C14_EM_P0_REG_EMP_VS_R Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2C18_EM_P0 (HDMI2P1_MAC_BASE + 0x2C18)
    #define HD21MAC_CFG_2C18_EM_P0_REG_HDMI_IRQ_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C1C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C1C)
    #define HD21MAC_CFG_2C1C_EM_P0_REG_HDMI_IRQ_STATUS_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C20_EM_P0 (HDMI2P1_MAC_BASE + 0x2C20)
    #define HD21MAC_CFG_2C20_EM_P0_REG_INT_MASK Fld(16,0,AC_FULLW10)//[15:0]

    //Page HDMI21_MAC_14
#define HD21MAC_CFG_2C24_EM_P0 (HDMI2P1_MAC_BASE + 0x2C24)
    #define HD21MAC_CFG_2C24_EM_P0_REG_INT_MASK_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C28_EM_P0 (HDMI2P1_MAC_BASE + 0x2C28)
    #define HD21MAC_CFG_2C28_EM_P0_REG_INT_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C2C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C2C)
    #define HD21MAC_CFG_2C2C_EM_P0_REG_INT_FORCE_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C30_EM_P0 (HDMI2P1_MAC_BASE + 0x2C30)
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR15 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR14 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR13 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR12 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR11 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR10 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR9 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR8 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR7 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR6 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR5 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR4 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2C30_EM_P0_REG_HDMI2_IRQ_CLEAR0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2C34_EM_P0 (HDMI2P1_MAC_BASE + 0x2C34)
    #define HD21MAC_CFG_2C34_EM_P0_REG_EMP_PKT_HDR_B0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C34_EM_P0_REG_M_CONST_RSTZ Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2C34_EM_P0_REG_HDMI2_IRQ_CLEAR20 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2C34_EM_P0_REG_HDMI2_IRQ_CLEAR19 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2C34_EM_P0_REG_HDMI2_IRQ_CLEAR18 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2C34_EM_P0_REG_HDMI2_IRQ_CLEAR17 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2C34_EM_P0_REG_HDMI2_IRQ_CLEAR16 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2C38_EM_P0 (HDMI2P1_MAC_BASE + 0x2C38)
    #define HD21MAC_CFG_2C38_EM_P0_REG_COMPRESSED_VIDEO_EMPS_ORGANIZATION_ID Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C38_EM_P0_REG_VENDOR_SPECIFIC_ORGANIZATION_ID Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C3C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C3C)
    #define HD21MAC_CFG_2C3C_EM_P0_REG_VIDEO_TIMING_METADATA_ORGANIZATION_ID Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C3C_EM_P0_REG_HDR_DYNAMIC_METADATA_ORGANIZATION_ID Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C40_EM_P0 (HDMI2P1_MAC_BASE + 0x2C40)
    #define HD21MAC_CFG_2C40_EM_P0_REG_DSC_OTHER_DATA_SET_TAG Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C44_EM_P0 (HDMI2P1_MAC_BASE + 0x2C44)
    #define HD21MAC_CFG_2C44_EM_P0_REG_VIDEO_TIMING_OTHER_DATA_SET_TAG Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C48_EM_P0 (HDMI2P1_MAC_BASE + 0x2C48)
    #define HD21MAC_CFG_2C48_EM_P0_REG_EMP_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C4C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C4C)
    #define HD21MAC_CFG_2C4C_EM_P0_REG_EMP_PKT_TYPE Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C4C_EM_P0_REG_DIS_EMP_PKT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2C50_EM_P0 (HDMI2P1_MAC_BASE + 0x2C50)
    #define HD21MAC_CFG_2C50_EM_P0_REG_ORGANIZATION_ID_SECOND Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C50_EM_P0_REG_ORGANIZATION_ID_FIRST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C54_EM_P0 (HDMI2P1_MAC_BASE + 0x2C54)
    #define HD21MAC_CFG_2C54_EM_P0_REG_ORGANIZATION_ID_FORTH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C54_EM_P0_REG_ORGANIZATION_ID_THIRD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C58_EM_P0 (HDMI2P1_MAC_BASE + 0x2C58)
    #define HD21MAC_CFG_2C58_EM_P0_REG_DATA_SET_TAG_FIRST Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C5C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C5C)
    #define HD21MAC_CFG_2C5C_EM_P0_REG_DATA_SET_TAG_SECOND Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C60_EM_P0 (HDMI2P1_MAC_BASE + 0x2C60)
    #define HD21MAC_CFG_2C60_EM_P0_REG_DATA_SET_TAG_THIRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C64_EM_P0 (HDMI2P1_MAC_BASE + 0x2C64)
    #define HD21MAC_CFG_2C64_EM_P0_REG_DATA_SET_TAG_FORTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2C68_EM_P0 (HDMI2P1_MAC_BASE + 0x2C68)
    #define HD21MAC_CFG_2C68_EM_P0_REG_NO_VIDEO_TIMING_CNT Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2C68_EM_P0_REG_NO_VENDOR_CNT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2C68_EM_P0_REG_NO_HDR_CNT Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2C68_EM_P0_REG_NO_DSC_CNT Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2C6C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C6C)
    #define HD21MAC_CFG_2C6C_EM_P0_REG_VIDEO_TIME_OUT_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2C6C_EM_P0_REG_VENDOR_TIME_OUT_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2C6C_EM_P0_REG_HDR_TIME_OUT_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2C6C_EM_P0_REG_DSC_TIME_OUT_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2C70_EM_P0 (HDMI2P1_MAC_BASE + 0x2C70)
    #define HD21MAC_CFG_2C70_EM_P0_REG_EMP_TIMER_SELECT Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_2C70_EM_P0_REG_END_LINE_TIMER_BASED_CNT Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_2C74_EM_P0 (HDMI2P1_MAC_BASE + 0x2C74)
    #define HD21MAC_CFG_2C74_EM_P0_REG_DSC_PB1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C74_EM_P0_REG_DSC_PB0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C78_EM_P0 (HDMI2P1_MAC_BASE + 0x2C78)
    #define HD21MAC_CFG_2C78_EM_P0_REG_DSC_PB3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C78_EM_P0_REG_DSC_PB2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C7C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C7C)
    #define HD21MAC_CFG_2C7C_EM_P0_REG_DSC_PB5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C7C_EM_P0_REG_DSC_PB4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C80_EM_P0 (HDMI2P1_MAC_BASE + 0x2C80)
    #define HD21MAC_CFG_2C80_EM_P0_REG_VENDOR_MD1_FIRST Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C80_EM_P0_REG_VENDOR_MD0_FIRST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C84_EM_P0 (HDMI2P1_MAC_BASE + 0x2C84)
    #define HD21MAC_CFG_2C84_EM_P0_REG_VENDOR_MD0_SECOND Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C84_EM_P0_REG_VENDOR_MD2_FIRST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C88_EM_P0 (HDMI2P1_MAC_BASE + 0x2C88)
    #define HD21MAC_CFG_2C88_EM_P0_REG_VENDOR_MD2_SECOND Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C88_EM_P0_REG_VENDOR_MD1_SECOND Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C8C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C8C)
    #define HD21MAC_CFG_2C8C_EM_P0_REG_VENDOR_MD1_THIRD Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C8C_EM_P0_REG_VENDOR_MD0_THIRD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C90_EM_P0 (HDMI2P1_MAC_BASE + 0x2C90)
    #define HD21MAC_CFG_2C90_EM_P0_REG_VENDOR_MD0_FORTH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C90_EM_P0_REG_VENDOR_MD2_THIRD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C94_EM_P0 (HDMI2P1_MAC_BASE + 0x2C94)
    #define HD21MAC_CFG_2C94_EM_P0_REG_VENDOR_MD2_FORTH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2C94_EM_P0_REG_VENDOR_MD1_FORTH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2C98_EM_P0 (HDMI2P1_MAC_BASE + 0x2C98)
    #define HD21MAC_CFG_2C98_EM_P0_REG_FAPA_1_ENABLE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2C98_EM_P0_REG_SEQUENCE_OFF Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2C98_EM_P0_REG_EMP_VIDEO_TIMING_FILTER Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2C98_EM_P0_REG_EMP_HDR_FILTER_TYPE4 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2C98_EM_P0_REG_EMP_HDR_FILTER_TYPE3 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2C98_EM_P0_REG_EMP_HDR_FILTER_TYPE2 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2C98_EM_P0_REG_EMP_HDR_FILTER_TYPE1 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2C98_EM_P0_REG_EMP_HDR_FILTER_TYPE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2C98_EM_P0_REG_EMP_DSC_FILTER Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2C98_EM_P0_REG_EMP_VENDOR_FILTER Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2C9C_EM_P0 (HDMI2P1_MAC_BASE + 0x2C9C)
    #define HD21MAC_CFG_2C9C_EM_P0_REG_END_LINE_CNT Fld(14,2,AC_MSKW10)//[15:2]
#define HD21MAC_CFG_2CA0_EM_P0 (HDMI2P1_MAC_BASE + 0x2CA0)
    #define HD21MAC_CFG_2CA0_EM_P0_REG_BASE_VFRONT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CA0_EM_P0_REG_FVA_FACTOR_M1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2CA0_EM_P0_REG_RB Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2CA0_EM_P0_REG_M_CONST Fld(1,2,AC_MSKB0)//[2:2]
#define HD21MAC_CFG_2CA4_EM_P0 (HDMI2P1_MAC_BASE + 0x2CA4)
    #define HD21MAC_CFG_2CA4_EM_P0_REG_BASE_REFRESH_RATE Fld(10,6,AC_MSKW10)//[15:6]
    #define HD21MAC_CFG_2CA4_EM_P0_REG_EMP_DSC_ENABLE_OVE_SELECT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2CA4_EM_P0_REG_EMP_DSC_ENABLE_OVE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2CA4_EM_P0_REG_DSC_PPS_LAST_PACKET_UPDATE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2CA4_EM_P0_REG_DSC_PPS_END_LINE_UPDATE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2CA4_EM_P0_REG_DSC_END_LINE_PULSE Fld(1,1,AC_MSKB0)//[1:1]
#define HD21MAC_CFG_2CA8_EM_P0 (HDMI2P1_MAC_BASE + 0x2CA8)
    #define HD21MAC_CFG_2CA8_EM_P0_REG_EMP_HFRONT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2CAC_EM_P0 (HDMI2P1_MAC_BASE + 0x2CAC)
    #define HD21MAC_CFG_2CAC_EM_P0_REG_EMP_HSYNC Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2CB0_EM_P0 (HDMI2P1_MAC_BASE + 0x2CB0)
    #define HD21MAC_CFG_2CB0_EM_P0_REG_EMP_HBACK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2CB4_EM_P0 (HDMI2P1_MAC_BASE + 0x2CB4)
    #define HD21MAC_CFG_2CB4_EM_P0_REG_EMP_HCATIVE_BYTE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2CB8_EM_P0 (HDMI2P1_MAC_BASE + 0x2CB8)
    #define HD21MAC_CFG_2CB8_EM_P0_REG_DSC_PB6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CBC_EM_P0 (HDMI2P1_MAC_BASE + 0x2CBC)
    #define HD21MAC_CFG_2CBC_EM_P0_REG_DSC_HB1_LAST Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CBC_EM_P0_REG_DSC_HB1_FIRST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CC0_EM_P0 (HDMI2P1_MAC_BASE + 0x2CC0)
    #define HD21MAC_CFG_2CC0_EM_P0_REG_PB27 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CC0_EM_P0_REG_PB26 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CC4_EM_P0 (HDMI2P1_MAC_BASE + 0x2CC4)
    #define HD21MAC_CFG_2CC4_EM_P0_REG_PB25 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CC4_EM_P0_REG_PB24 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CC8_EM_P0 (HDMI2P1_MAC_BASE + 0x2CC8)
    #define HD21MAC_CFG_2CC8_EM_P0_REG_PB23 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CC8_EM_P0_REG_PB22 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CCC_EM_P0 (HDMI2P1_MAC_BASE + 0x2CCC)
    #define HD21MAC_CFG_2CCC_EM_P0_REG_PB21 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CCC_EM_P0_REG_PB20 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CD0_EM_P0 (HDMI2P1_MAC_BASE + 0x2CD0)
    #define HD21MAC_CFG_2CD0_EM_P0_REG_PB19 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CD0_EM_P0_REG_PB18 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CD4_EM_P0 (HDMI2P1_MAC_BASE + 0x2CD4)
    #define HD21MAC_CFG_2CD4_EM_P0_REG_PB17 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CD4_EM_P0_REG_PB16 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CD8_EM_P0 (HDMI2P1_MAC_BASE + 0x2CD8)
    #define HD21MAC_CFG_2CD8_EM_P0_REG_PB15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CD8_EM_P0_REG_PB14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CDC_EM_P0 (HDMI2P1_MAC_BASE + 0x2CDC)
    #define HD21MAC_CFG_2CDC_EM_P0_REG_PB13 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CDC_EM_P0_REG_PB12 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CE0_EM_P0 (HDMI2P1_MAC_BASE + 0x2CE0)
    #define HD21MAC_CFG_2CE0_EM_P0_REG_PB11 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CE0_EM_P0_REG_PB10 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CE4_EM_P0 (HDMI2P1_MAC_BASE + 0x2CE4)
    #define HD21MAC_CFG_2CE4_EM_P0_REG_PB9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CE4_EM_P0_REG_PB8 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CE8_EM_P0 (HDMI2P1_MAC_BASE + 0x2CE8)
    #define HD21MAC_CFG_2CE8_EM_P0_REG_PB7 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CE8_EM_P0_REG_PB6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CEC_EM_P0 (HDMI2P1_MAC_BASE + 0x2CEC)
    #define HD21MAC_CFG_2CEC_EM_P0_REG_PB5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CEC_EM_P0_REG_PB4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CF0_EM_P0 (HDMI2P1_MAC_BASE + 0x2CF0)
    #define HD21MAC_CFG_2CF0_EM_P0_REG_PB3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CF0_EM_P0_REG_PB2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CF4_EM_P0 (HDMI2P1_MAC_BASE + 0x2CF4)
    #define HD21MAC_CFG_2CF4_EM_P0_REG_PB1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CF4_EM_P0_REG_PB0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CF8_EM_P0 (HDMI2P1_MAC_BASE + 0x2CF8)
    #define HD21MAC_CFG_2CF8_EM_P0_REG_HB0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CF8_EM_P0_REG_HB1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2CFC_EM_P0 (HDMI2P1_MAC_BASE + 0x2CFC)
    #define HD21MAC_CFG_2CFC_EM_P0_REG_HB2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2CFC_EM_P0_REG_PACKET_VALID Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2D00_EM_P0 (HDMI2P1_MAC_BASE + 0x2D00)
    #define HD21MAC_CFG_2D00_EM_P0_REG_PPS_127 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D00_EM_P0_REG_PPS_126 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D04_EM_P0 (HDMI2P1_MAC_BASE + 0x2D04)
    #define HD21MAC_CFG_2D04_EM_P0_REG_PPS_125 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D04_EM_P0_REG_PPS_124 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D08_EM_P0 (HDMI2P1_MAC_BASE + 0x2D08)
    #define HD21MAC_CFG_2D08_EM_P0_REG_PPS_123 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D08_EM_P0_REG_PPS_122 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D0C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D0C)
    #define HD21MAC_CFG_2D0C_EM_P0_REG_PPS_121 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D0C_EM_P0_REG_PPS_120 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D10_EM_P0 (HDMI2P1_MAC_BASE + 0x2D10)
    #define HD21MAC_CFG_2D10_EM_P0_REG_PPS_119 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D10_EM_P0_REG_PPS_118 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D14_EM_P0 (HDMI2P1_MAC_BASE + 0x2D14)
    #define HD21MAC_CFG_2D14_EM_P0_REG_PPS_117 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D14_EM_P0_REG_PPS_116 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D18_EM_P0 (HDMI2P1_MAC_BASE + 0x2D18)
    #define HD21MAC_CFG_2D18_EM_P0_REG_PPS_115 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D18_EM_P0_REG_PPS_114 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D1C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D1C)
    #define HD21MAC_CFG_2D1C_EM_P0_REG_PPS_113 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D1C_EM_P0_REG_PPS_112 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D20_EM_P0 (HDMI2P1_MAC_BASE + 0x2D20)
    #define HD21MAC_CFG_2D20_EM_P0_REG_PPS_111 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D20_EM_P0_REG_PPS_110 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D24_EM_P0 (HDMI2P1_MAC_BASE + 0x2D24)
    #define HD21MAC_CFG_2D24_EM_P0_REG_PPS_109 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D24_EM_P0_REG_PPS_108 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D28_EM_P0 (HDMI2P1_MAC_BASE + 0x2D28)
    #define HD21MAC_CFG_2D28_EM_P0_REG_PPS_107 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D28_EM_P0_REG_PPS_106 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D2C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D2C)
    #define HD21MAC_CFG_2D2C_EM_P0_REG_PPS_105 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D2C_EM_P0_REG_PPS_104 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D30_EM_P0 (HDMI2P1_MAC_BASE + 0x2D30)
    #define HD21MAC_CFG_2D30_EM_P0_REG_PPS_103 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D30_EM_P0_REG_PPS_102 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D34_EM_P0 (HDMI2P1_MAC_BASE + 0x2D34)
    #define HD21MAC_CFG_2D34_EM_P0_REG_PPS_101 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D34_EM_P0_REG_PPS_100 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D38_EM_P0 (HDMI2P1_MAC_BASE + 0x2D38)
    #define HD21MAC_CFG_2D38_EM_P0_REG_PPS_99 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D38_EM_P0_REG_PPS_98 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D3C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D3C)
    #define HD21MAC_CFG_2D3C_EM_P0_REG_PPS_97 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D3C_EM_P0_REG_PPS_96 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D40_EM_P0 (HDMI2P1_MAC_BASE + 0x2D40)
    #define HD21MAC_CFG_2D40_EM_P0_REG_PPS_95 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D40_EM_P0_REG_PPS_94 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D44_EM_P0 (HDMI2P1_MAC_BASE + 0x2D44)
    #define HD21MAC_CFG_2D44_EM_P0_REG_PPS_93 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D44_EM_P0_REG_PPS_92 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D48_EM_P0 (HDMI2P1_MAC_BASE + 0x2D48)
    #define HD21MAC_CFG_2D48_EM_P0_REG_PPS_91 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D48_EM_P0_REG_PPS_90 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D4C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D4C)
    #define HD21MAC_CFG_2D4C_EM_P0_REG_PPS_89 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D4C_EM_P0_REG_PPS_88 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D50_EM_P0 (HDMI2P1_MAC_BASE + 0x2D50)
    #define HD21MAC_CFG_2D50_EM_P0_REG_PPS_87 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D50_EM_P0_REG_PPS_86 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D54_EM_P0 (HDMI2P1_MAC_BASE + 0x2D54)
    #define HD21MAC_CFG_2D54_EM_P0_REG_PPS_85 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D54_EM_P0_REG_PPS_84 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D58_EM_P0 (HDMI2P1_MAC_BASE + 0x2D58)
    #define HD21MAC_CFG_2D58_EM_P0_REG_PPS_83 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D58_EM_P0_REG_PPS_82 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D5C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D5C)
    #define HD21MAC_CFG_2D5C_EM_P0_REG_PPS_81 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D5C_EM_P0_REG_PPS_80 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D60_EM_P0 (HDMI2P1_MAC_BASE + 0x2D60)
    #define HD21MAC_CFG_2D60_EM_P0_REG_PPS_79 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D60_EM_P0_REG_PPS_78 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D64_EM_P0 (HDMI2P1_MAC_BASE + 0x2D64)
    #define HD21MAC_CFG_2D64_EM_P0_REG_PPS_77 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D64_EM_P0_REG_PPS_76 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D68_EM_P0 (HDMI2P1_MAC_BASE + 0x2D68)
    #define HD21MAC_CFG_2D68_EM_P0_REG_PPS_75 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D68_EM_P0_REG_PPS_74 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D6C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D6C)
    #define HD21MAC_CFG_2D6C_EM_P0_REG_PPS_73 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D6C_EM_P0_REG_PPS_72 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D70_EM_P0 (HDMI2P1_MAC_BASE + 0x2D70)
    #define HD21MAC_CFG_2D70_EM_P0_REG_PPS_71 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D70_EM_P0_REG_PPS_70 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D74_EM_P0 (HDMI2P1_MAC_BASE + 0x2D74)
    #define HD21MAC_CFG_2D74_EM_P0_REG_PPS_69 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D74_EM_P0_REG_PPS_68 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D78_EM_P0 (HDMI2P1_MAC_BASE + 0x2D78)
    #define HD21MAC_CFG_2D78_EM_P0_REG_PPS_67 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D78_EM_P0_REG_PPS_66 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D7C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D7C)
    #define HD21MAC_CFG_2D7C_EM_P0_REG_PPS_65 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D7C_EM_P0_REG_PPS_64 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D80_EM_P0 (HDMI2P1_MAC_BASE + 0x2D80)
    #define HD21MAC_CFG_2D80_EM_P0_REG_PPS_63 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D80_EM_P0_REG_PPS_62 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D84_EM_P0 (HDMI2P1_MAC_BASE + 0x2D84)
    #define HD21MAC_CFG_2D84_EM_P0_REG_PPS_61 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D84_EM_P0_REG_PPS_60 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D88_EM_P0 (HDMI2P1_MAC_BASE + 0x2D88)
    #define HD21MAC_CFG_2D88_EM_P0_REG_PPS_59 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D88_EM_P0_REG_PPS_58 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D8C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D8C)
    #define HD21MAC_CFG_2D8C_EM_P0_REG_PPS_57 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D8C_EM_P0_REG_PPS_56 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D90_EM_P0 (HDMI2P1_MAC_BASE + 0x2D90)
    #define HD21MAC_CFG_2D90_EM_P0_REG_PPS_55 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D90_EM_P0_REG_PPS_54 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D94_EM_P0 (HDMI2P1_MAC_BASE + 0x2D94)
    #define HD21MAC_CFG_2D94_EM_P0_REG_PPS_53 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D94_EM_P0_REG_PPS_52 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D98_EM_P0 (HDMI2P1_MAC_BASE + 0x2D98)
    #define HD21MAC_CFG_2D98_EM_P0_REG_PPS_51 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D98_EM_P0_REG_PPS_50 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2D9C_EM_P0 (HDMI2P1_MAC_BASE + 0x2D9C)
    #define HD21MAC_CFG_2D9C_EM_P0_REG_PPS_49 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2D9C_EM_P0_REG_PPS_48 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DA0_EM_P0 (HDMI2P1_MAC_BASE + 0x2DA0)
    #define HD21MAC_CFG_2DA0_EM_P0_REG_PPS_47 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DA0_EM_P0_REG_PPS_46 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DA4_EM_P0 (HDMI2P1_MAC_BASE + 0x2DA4)
    #define HD21MAC_CFG_2DA4_EM_P0_REG_PPS_45 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DA4_EM_P0_REG_PPS_44 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DA8_EM_P0 (HDMI2P1_MAC_BASE + 0x2DA8)
    #define HD21MAC_CFG_2DA8_EM_P0_REG_PPS_43 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DA8_EM_P0_REG_PPS_42 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DAC_EM_P0 (HDMI2P1_MAC_BASE + 0x2DAC)
    #define HD21MAC_CFG_2DAC_EM_P0_REG_PPS_41 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DAC_EM_P0_REG_PPS_40 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DB0_EM_P0 (HDMI2P1_MAC_BASE + 0x2DB0)
    #define HD21MAC_CFG_2DB0_EM_P0_REG_PPS_39 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DB0_EM_P0_REG_PPS_38 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DB4_EM_P0 (HDMI2P1_MAC_BASE + 0x2DB4)
    #define HD21MAC_CFG_2DB4_EM_P0_REG_PPS_37 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DB4_EM_P0_REG_PPS_36 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DB8_EM_P0 (HDMI2P1_MAC_BASE + 0x2DB8)
    #define HD21MAC_CFG_2DB8_EM_P0_REG_PPS_35 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DB8_EM_P0_REG_PPS_34 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DBC_EM_P0 (HDMI2P1_MAC_BASE + 0x2DBC)
    #define HD21MAC_CFG_2DBC_EM_P0_REG_PPS_33 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DBC_EM_P0_REG_PPS_32 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DC0_EM_P0 (HDMI2P1_MAC_BASE + 0x2DC0)
    #define HD21MAC_CFG_2DC0_EM_P0_REG_PPS_31 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DC0_EM_P0_REG_PPS_30 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DC4_EM_P0 (HDMI2P1_MAC_BASE + 0x2DC4)
    #define HD21MAC_CFG_2DC4_EM_P0_REG_PPS_29 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DC4_EM_P0_REG_PPS_28 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DC8_EM_P0 (HDMI2P1_MAC_BASE + 0x2DC8)
    #define HD21MAC_CFG_2DC8_EM_P0_REG_PPS_27 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DC8_EM_P0_REG_PPS_26 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DCC_EM_P0 (HDMI2P1_MAC_BASE + 0x2DCC)
    #define HD21MAC_CFG_2DCC_EM_P0_REG_PPS_25 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DCC_EM_P0_REG_PPS_24 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DD0_EM_P0 (HDMI2P1_MAC_BASE + 0x2DD0)
    #define HD21MAC_CFG_2DD0_EM_P0_REG_PPS_23 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DD0_EM_P0_REG_PPS_22 Fld(8,0,AC_FULLB0)//[7:0]

    //Page HDMI21_MAC_15
#define HD21MAC_CFG_2DD4_EM_P0 (HDMI2P1_MAC_BASE + 0x2DD4)
    #define HD21MAC_CFG_2DD4_EM_P0_REG_PPS_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DD4_EM_P0_REG_PPS_20 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DD8_EM_P0 (HDMI2P1_MAC_BASE + 0x2DD8)
    #define HD21MAC_CFG_2DD8_EM_P0_REG_PPS_19 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DD8_EM_P0_REG_PPS_18 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DDC_EM_P0 (HDMI2P1_MAC_BASE + 0x2DDC)
    #define HD21MAC_CFG_2DDC_EM_P0_REG_PPS_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DDC_EM_P0_REG_PPS_16 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DE0_EM_P0 (HDMI2P1_MAC_BASE + 0x2DE0)
    #define HD21MAC_CFG_2DE0_EM_P0_REG_PPS_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DE0_EM_P0_REG_PPS_14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DE4_EM_P0 (HDMI2P1_MAC_BASE + 0x2DE4)
    #define HD21MAC_CFG_2DE4_EM_P0_REG_PPS_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DE4_EM_P0_REG_PPS_12 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DE8_EM_P0 (HDMI2P1_MAC_BASE + 0x2DE8)
    #define HD21MAC_CFG_2DE8_EM_P0_REG_PPS_11 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DE8_EM_P0_REG_PPS_10 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DEC_EM_P0 (HDMI2P1_MAC_BASE + 0x2DEC)
    #define HD21MAC_CFG_2DEC_EM_P0_REG_PPS_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DEC_EM_P0_REG_PPS_8 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DF0_EM_P0 (HDMI2P1_MAC_BASE + 0x2DF0)
    #define HD21MAC_CFG_2DF0_EM_P0_REG_PPS_7 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DF0_EM_P0_REG_PPS_6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DF4_EM_P0 (HDMI2P1_MAC_BASE + 0x2DF4)
    #define HD21MAC_CFG_2DF4_EM_P0_REG_PPS_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DF4_EM_P0_REG_PPS_4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DF8_EM_P0 (HDMI2P1_MAC_BASE + 0x2DF8)
    #define HD21MAC_CFG_2DF8_EM_P0_REG_PPS_3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DF8_EM_P0_REG_PPS_2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2DFC_EM_P0 (HDMI2P1_MAC_BASE + 0x2DFC)
    #define HD21MAC_CFG_2DFC_EM_P0_REG_PPS_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2DFC_EM_P0_REG_PPS_0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2E14_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E14)
    #define HD21MAC_CFG_2E14_PLL_TOP_P0_REG_PHASE_LOCK_THRESH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2E14_PLL_TOP_P0_REG_PRD_LOCK_THRESH Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2E14_PLL_TOP_P0_REG_PRD_STABLE_THRESH Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2E18_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E18)
    #define HD21MAC_CFG_2E18_PLL_TOP_P0_REG_LIMIT_D5D6D7_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E1C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E1C)
    #define HD21MAC_CFG_2E1C_PLL_TOP_P0_REG_LIMIT_D5D6D7_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2E20_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E20)
    #define HD21MAC_CFG_2E20_PLL_TOP_P0_REG_LIMIT_D5D6D7_RK_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E24_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E24)
    #define HD21MAC_CFG_2E24_PLL_TOP_P0_REG_LIMIT_D5D6D7_RK_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2E28_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E28)
    #define HD21MAC_CFG_2E28_PLL_TOP_P0_REG_LIMIT_LPLL_OFFSET Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E2C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E2C)
    #define HD21MAC_CFG_2E2C_PLL_TOP_P0_REG_P_GAIN_PHASE Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2E2C_PLL_TOP_P0_REG_I_GAIN_PHASE Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2E2C_PLL_TOP_P0_REG_P_GAIN_PRD Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_2E2C_PLL_TOP_P0_REG_I_GAIN_PRD Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2E30_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E30)
    #define HD21MAC_CFG_2E30_PLL_TOP_P0_REG_OVS_FRAME_DIV Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2E30_PLL_TOP_P0_REG_IVS_FRAME_DIV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2E30_PLL_TOP_P0_REG_P_GAIN_PHASE_ZERO Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2E30_PLL_TOP_P0_REG_I_GAIN_PHASE_ZERO Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2E30_PLL_TOP_P0_REG_P_GAIN_PRD_ZERO Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2E30_PLL_TOP_P0_REG_I_GAIN_PRD_ZERO Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2E30_PLL_TOP_P0_REG_FRAME_LPLL_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2E30_PLL_TOP_P0_REG_FPLL_MODE Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_2E34_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E34)
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_SSC_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_NON_STABLE_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_NO_SIGNAL_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_NON_STABLE_OV Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_NO_SIGNAL_OV Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_OVE_STATUS_IN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_EN_2_LIMIT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_FORCE_PHASE_CLOSE_DONE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_FORCE_PHASE_REDUCE_DONE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_FORCE_PRD_LOCK_DONE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2E34_PLL_TOP_P0_REG_FORCE_PRD_STABLE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2E38_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E38)
    #define HD21MAC_CFG_2E38_PLL_TOP_P0_REG_EXT_OVS_FRAME_DIV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2E38_PLL_TOP_P0_REG_EXT_IVS_FRAME_DIV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2E3C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E3C)
    #define HD21MAC_CFG_2E3C_PLL_TOP_P0_REG_PLL_SET_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E40_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E40)
    #define HD21MAC_CFG_2E40_PLL_TOP_P0_REG_PLL_SET_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2E44_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E44)
    #define HD21MAC_CFG_2E44_PLL_TOP_P0_REG_PHASE_DIF Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E48_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E48)
    #define HD21MAC_CFG_2E48_PLL_TOP_P0_REG_PHASE_UP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2E4C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E4C)
    #define HD21MAC_CFG_2E4C_PLL_TOP_P0_REG_PRD_DIF Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E50_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E50)
    #define HD21MAC_CFG_2E50_PLL_TOP_P0_REG_PRD_UP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2E58_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E58)
    #define HD21MAC_CFG_2E58_PLL_TOP_P0_REG_LPLL_TESTD Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_2E58_PLL_TOP_P0_REG_EN_FB_RETIME Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2E58_PLL_TOP_P0_REG_EN_OUTCLK_2CHIP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2E5C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E5C)
    #define HD21MAC_CFG_2E5C_PLL_TOP_P0_REG_LPLL_STEP Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_2E60_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E60)
    #define HD21MAC_CFG_2E60_PLL_TOP_P0_REG_LPLL_SPAN Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_2E64_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E64)
    #define HD21MAC_CFG_2E64_PLL_TOP_P0_REG_IDCLK_DIV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E68_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E68)
    #define HD21MAC_CFG_2E68_PLL_TOP_P0_REG_IDCLK_DIV_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2E6C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E6C)
    #define HD21MAC_CFG_2E6C_PLL_TOP_P0_REG_ODCLK_DIV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E70_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E70)
    #define HD21MAC_CFG_2E70_PLL_TOP_P0_REG_ODCLK_DIV_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2E74_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E74)
    #define HD21MAC_CFG_2E74_PLL_TOP_P0_REG_FIX_DEC_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2E74_PLL_TOP_P0_REG_DEC_V_LIMIT Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_2E78_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E78)
    #define HD21MAC_CFG_2E78_PLL_TOP_P0_REG_INC_V_LIMIT Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_2E7C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E7C)
    #define HD21MAC_CFG_2E7C_PLL_TOP_P0_REG_REDUCE_DONE_THRESH Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2E7C_PLL_TOP_P0_REG_PHASE_CLOSE_THRESH Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_2E80_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E80)
    #define HD21MAC_CFG_2E80_PLL_TOP_P0_REG_HIS_CNT_HIGH_THRESH Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_2E80_PLL_TOP_P0_REG_HIS_CNT_LOW_THRESH Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_2E84_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E84)
    #define HD21MAC_CFG_2E84_PLL_TOP_P0_REG_IVS_PRD_VALUE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E88_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E88)
    #define HD21MAC_CFG_2E88_PLL_TOP_P0_REG_IVS_PRD_VALUE_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2E8C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E8C)
    #define HD21MAC_CFG_2E8C_PLL_TOP_P0_REG_OVS_PRD_VALUE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2E90_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E90)
    #define HD21MAC_CFG_2E90_PLL_TOP_P0_REG_OVS_PRD_VALUE_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2E98_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E98)
    #define HD21MAC_CFG_2E98_PLL_TOP_P0_REG_FIX_V_DEC Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2E98_PLL_TOP_P0_REG_FIX_V_TOTAL Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_2E9C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2E9C)
    #define HD21MAC_CFG_2E9C_PLL_TOP_P0_REG_FIX_H_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_2EA0_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2EA0)
    #define HD21MAC_CFG_2EA0_PLL_TOP_P0_REG_PLL_SET_USING_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2EA4_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2EA4)
    #define HD21MAC_CFG_2EA4_PLL_TOP_P0_REG_PLL_SET_USING_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2EA8_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2EA8)
    #define HD21MAC_CFG_2EA8_PLL_TOP_P0_REG_PHASE_LOCK_DONE Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2EA8_PLL_TOP_P0_REG_PHASE_REDUCE_DONE Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_2EA8_PLL_TOP_P0_REG_PRD_LOCK_DONE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2EA8_PLL_TOP_P0_REG_IVS_PRD_STABLE Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2EA8_PLL_TOP_P0_REG_OVS_PRD_STABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2EA8_PLL_TOP_P0_REG_CS_STATE Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_2EAC_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2EAC)
    #define HD21MAC_CFG_2EAC_PLL_TOP_P0_REG_ERR_UP_INV Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2EAC_PLL_TOP_P0_REG_PH_UP_INV Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2EAC_PLL_TOP_P0_REG_PH_HALF_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2EAC_PLL_TOP_P0_REG_STATUS_DEBUG Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_2EBC_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2EBC)
    #define HD21MAC_CFG_2EBC_PLL_TOP_P0_REG_RST_MODULE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2F80_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2F80)
    #define HD21MAC_CFG_2F80_PLL_TOP_P0_REG_SDM_SET_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2F84_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2F84)
    #define HD21MAC_CFG_2F84_PLL_TOP_P0_REG_SDM_SET_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2F88_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2F88)
    #define HD21MAC_CFG_2F88_PLL_TOP_P0_REG_SDM_SET_LIMIT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2F8C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2F8C)
    #define HD21MAC_CFG_2F8C_PLL_TOP_P0_REG_SDM_SET_LIMIT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2F90_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2F90)
    #define HD21MAC_CFG_2F90_PLL_TOP_P0_REG_SDM_SET_LIMIT_FAST_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2F94_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2F94)
    #define HD21MAC_CFG_2F94_PLL_TOP_P0_REG_SDM_SET_LIMIT_FAST_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2F98_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2F98)
    #define HD21MAC_CFG_2F98_PLL_TOP_P0_REG_SDM_P_GAIN Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_2F98_PLL_TOP_P0_REG_SDM_I_GAIN Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_2F9C_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2F9C)
    #define HD21MAC_CFG_2F9C_PLL_TOP_P0_REG_SLD_CYC Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2FA8_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FA8)
    #define HD21MAC_CFG_2FA8_PLL_TOP_P0_REG_GCR_TMDSPLL_LOOPDIV_SECOND Fld(8,7,AC_MSKW10)//[14:7]
    #define HD21MAC_CFG_2FA8_PLL_TOP_P0_REG_PD_TMDSPLL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_2FA8_PLL_TOP_P0_REG_GCP_TMDSPLL_PORST Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_2FA8_PLL_TOP_P0_REG_GCP_TMDSPLL_EXTAL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2FA8_PLL_TOP_P0_REG_EN_TMDSPLL_TEST Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2FA8_PLL_TOP_P0_REG_EN_TMDSPLL_PRDT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2FA8_PLL_TOP_P0_REG_EN_TMDSPLL_PRDT Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2FA8_PLL_TOP_P0_REG_EN_OV_TMDSPLL_CP_SW Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_2FAC_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FAC)
    #define HD21MAC_CFG_2FAC_PLL_TOP_P0_REG_EN_CLKO_TMDS Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_2FAC_PLL_TOP_P0_REG_EN_CLKO_PIX Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2FAC_PLL_TOP_P0_REG_GCR_TMDSPLL_OUTPUT_DIV Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_2FB0_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FB0)
    #define HD21MAC_CFG_2FB0_PLL_TOP_P0_REG_TEST_TMDSPLL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2FB4_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FB4)
    #define HD21MAC_CFG_2FB4_PLL_TOP_P0_REG_RO_TMDSPLL_LOCK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2FB4_PLL_TOP_P0_REG_GCR_TMDS_CP_SW Fld(2,11,AC_MSKB1)//[12:11]
    #define HD21MAC_CFG_2FB4_PLL_TOP_P0_REG_GCR_TMDSPLL_ICTRL Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_2FB4_PLL_TOP_P0_REG_GCR_TMDSPLL_LOOPDIV_FIRST Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_2FB4_PLL_TOP_P0_REG_TMDS_POST_DIV Fld(4,2,AC_MSKB0)//[5:2]
    #define HD21MAC_CFG_2FB4_PLL_TOP_P0_REG_GCR_TMDSPLL_INPUT_DIV Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_2FB8_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FB8)
    #define HD21MAC_CFG_2FB8_PLL_TOP_P0_REG_RSV_OV Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_2FB8_PLL_TOP_P0_REG_SW_FREQ_SETTING Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_2FBC_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FBC)
    #define HD21MAC_CFG_2FBC_PLL_TOP_P0_REG_ATOP_TMDS_POST_DIV_RPT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_2FBC_PLL_TOP_P0_REG_HW_CKG_DIV_8_4_2_AUTO Fld(3,13,AC_MSKB1)//[15:13]
#define HD21MAC_CFG_2FC0_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FC0)
    #define HD21MAC_CFG_2FC0_PLL_TOP_P0_REG_FSYNC_RESET_THRESH Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_2FC0_PLL_TOP_P0_REG_FSYNC_RESET_2T_FLAG Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_2FC0_PLL_TOP_P0_REG_CLR_FSYNC_RESET_2T_FLAG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_2FC0_PLL_TOP_P0_REG_EN_PLL_FSYNC_RESET Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2FC0_PLL_TOP_P0_REG_PRD_LOCK_THRESH_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2FC0_PLL_TOP_P0_REG_VTT_PLL_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2FC0_PLL_TOP_P0_REG_EN_CLK_DIV Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2FC4_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FC4)
    #define HD21MAC_CFG_2FC4_PLL_TOP_P0_REG_LPLL1_TEST_V2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2FC8_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FC8)
    #define HD21MAC_CFG_2FC8_PLL_TOP_P0_REG_IDCLK_DIV_PRD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2FCC_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FCC)
    #define HD21MAC_CFG_2FCC_PLL_TOP_P0_REG_IDCLK_DIV_PRD_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2FD0_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FD0)
    #define HD21MAC_CFG_2FD0_PLL_TOP_P0_REG_ODCLK_DIV_PRD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2FD4_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FD4)
    #define HD21MAC_CFG_2FD4_PLL_TOP_P0_REG_ODCLK_DIV_PRD_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_2FD8_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FD8)
    #define HD21MAC_CFG_2FD8_PLL_TOP_P0_REG_SRC_VTT Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_2FDC_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FDC)
    #define HD21MAC_CFG_2FDC_PLL_TOP_P0_REG_SRC_HTT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_2FE0_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FE0)
    #define HD21MAC_CFG_2FE0_PLL_TOP_P0_REG_PIX_RATE_MIN Fld(10,0,AC_MSKW10)//[9:0]
    #define HD21MAC_CFG_2FE0_PLL_TOP_P0_REG_LOC_VTT_FIX_CAL_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_2FE0_PLL_TOP_P0_REG_IVS_THRESH_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_2FE0_PLL_TOP_P0_REG_V_OFFSET_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_2FE0_PLL_TOP_P0_REG_P_RATE_RDY Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2FE0_PLL_TOP_P0_REG_P_RATE_FUNC_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2FEC_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FEC)
    #define HD21MAC_CFG_2FEC_PLL_TOP_P0_REG_SELF_DET_TH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2FF0_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FF0)
    #define HD21MAC_CFG_2FF0_PLL_TOP_P0_REG_IVS_PRD_RPT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_2FF4_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FF4)
    #define HD21MAC_CFG_2FF4_PLL_TOP_P0_REG_FPLL_GAT_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_2FF4_PLL_TOP_P0_REG_IVS_PRD_RPT_1 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_2FF8_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FF8)
    #define HD21MAC_CFG_2FF8_PLL_TOP_P0_REG_F_RPT_CNT Fld(12,0,AC_MSKW10)//[11:0]
    #define HD21MAC_CFG_2FF8_PLL_TOP_P0_REG_PHASE_LOCK_THRESH_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_2FF8_PLL_TOP_P0_REG_F_RPT_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_2FF8_PLL_TOP_P0_REG_SPREADER_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_2FFC_PLL_TOP_P0 (HDMI2P1_MAC_BASE + 0x2FFC)
    #define HD21MAC_CFG_2FFC_PLL_TOP_P0_REG_DB_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define HD21MAC_CFG_2FFC_PLL_TOP_P0_REG_SW_TRIG_DB_LOAD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_2FFC_PLL_TOP_P0_REG_SW_TRIG_CLR_FIX_VTT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_2FFC_PLL_TOP_P0_REG_FIX_POSI_LD Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_2FFC_PLL_TOP_P0_REG_TGEN_SRC_SEL Fld(1,8,AC_MSKB1)//[8:8]
#define HD21MAC_CFG_3000_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3000)
    #define HD21MAC_CFG_3000_SVCE_P0_REG_SW_RST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3004_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3004)
    #define HD21MAC_CFG_3004_SVCE_P0_REG_PATH2P_RPLC Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3004_SVCE_P0_REG_VDO2P_REPLACE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3004_SVCE_P0_REG_DIS_DE_PROT Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3004_SVCE_P0_REG_AWS_SYNC Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3004_SVCE_P0_REG_OUTPUT_FORMAT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3004_SVCE_P0_REG_INPUT_FORMAT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3004_SVCE_P0_REG_CFG_PPS_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3004_SVCE_P0_REG_PATH8P_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3008_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3008)
    #define HD21MAC_CFG_3008_SVCE_P0_REG_CHUNK_SIZE_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_300C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x300C)
    #define HD21MAC_CFG_300C_SVCE_P0_REG_CHUNK_SIZE_OV Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3010_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3010)
    #define HD21MAC_CFG_3010_SVCE_P0_REG_FEED_PIC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3014_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3014)
    #define HD21MAC_CFG_3014_SVCE_P0_REG_FEED_SLICE_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3018_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3018)
    #define HD21MAC_CFG_3018_SVCE_P0_REG_FEED_CHUNK_SIZE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_301C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x301C)
    #define HD21MAC_CFG_301C_SVCE_P0_REG_FEED_BPP Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_3020_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3020)
    #define HD21MAC_CFG_3020_SVCE_P0_REG_FEED_BPC_OV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_3020_SVCE_P0_REG_FEED_DIV2EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3024_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3024)
    #define HD21MAC_CFG_3024_SVCE_P0_REG_CLR_FEED_FIFO_FLAG Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3028_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3028)
    #define HD21MAC_CFG_3028_SVCE_P0_REG_FEED_FIFO_FULL_LAT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_302C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x302C)
    #define HD21MAC_CFG_302C_SVCE_P0_REG_FEED_FIFO_RST_MODE Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_3030_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3030)
    #define HD21MAC_CFG_3030_SVCE_P0_REG_CHUNK_SIZE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3034_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3034)
    #define HD21MAC_CFG_3034_SVCE_P0_REG_SN_LEAD_CFG Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_3034_SVCE_P0_REG_SLICE_NUM Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_3040_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3040)
    #define HD21MAC_CFG_3040_SVCE_P0_REG_DVI_ROUND_EN_OV Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3040_SVCE_P0_REG_DITH_SEL_DVI_OV Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21MAC_CFG_3040_SVCE_P0_REG_DITH_SEED_RST_OV Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3040_SVCE_P0_REG_DIS_FULL_BLACK_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3040_SVCE_P0_REG_AVI_IF5_OV Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_3040_SVCE_P0_REG_FORCE_YCBCR_BLACK_OV Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_3040_SVCE_P0_REG_VIDEO_BLANK_TST_OV Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3040_SVCE_P0_REG_YCBCR444_DC_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3040_SVCE_P0_REG_YCBCR422_DC_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3040_SVCE_P0_REG_YCBCR420_DC_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3044_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3044)
    #define HD21MAC_CFG_3044_SVCE_P0_REG_DITHER_CFG_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3044_SVCE_P0_REG_DITHER_IF_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3044_SVCE_P0_REG_DITHER_IF_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3048_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3048)
    #define HD21MAC_CFG_3048_SVCE_P0_REG_VS_RST_RCV_FIFO_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_304C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x304C)
    #define HD21MAC_CFG_304C_SVCE_P0_REG_TGEN_DB_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_304C_SVCE_P0_REG_TGEN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3050_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3050)
    #define HD21MAC_CFG_3050_SVCE_P0_REG_TGEN_SET_READY Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3054_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3054)
    #define HD21MAC_CFG_3054_SVCE_P0_REG_TGEN_CLR_CNT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3058_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3058)
    #define HD21MAC_CFG_3058_SVCE_P0_REG_HREF_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_305C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x305C)
    #define HD21MAC_CFG_305C_SVCE_P0_REG_VREF_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3060_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3060)
    #define HD21MAC_CFG_3060_SVCE_P0_REG_HREF_FORCE Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_3064_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3064)
    #define HD21MAC_CFG_3064_SVCE_P0_REG_VREF_FORCE Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_3068_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3068)
    #define HD21MAC_CFG_3068_SVCE_P0_REG_SYNPLL_REF_HS_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_306C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x306C)
    #define HD21MAC_CFG_306C_SVCE_P0_REG_TGEN_VRR_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3070_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3070)
    #define HD21MAC_CFG_3070_SVCE_P0_REG_TGEN_DE_SFT_PROT_OPT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_3070_SVCE_P0_REG_TGEN_DE_SFT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3074_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3074)
    #define HD21MAC_CFG_3074_SVCE_P0_REG_TGEN_DE_SFT_CNT Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_3078_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3078)
    #define HD21MAC_CFG_3078_SVCE_P0_REG_DSC_HS_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3078_SVCE_P0_REG_DSC_ACK_SEL Fld(3,11,AC_MSKB1)//[13:11]
    #define HD21MAC_CFG_3078_SVCE_P0_REG_PRE_ACK Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_3078_SVCE_P0_REG_DSC_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3080_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3080)
    #define HD21MAC_CFG_3080_SVCE_P0_REG_TG_HTT Fld(14,0,AC_MSKW10)//[13:0]

    //Page HDMI21_MAC_16
#define HD21MAC_CFG_3084_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3084)
    #define HD21MAC_CFG_3084_SVCE_P0_REG_TG_HS_ED Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_3088_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3088)
    #define HD21MAC_CFG_3088_SVCE_P0_REG_TG_H_BP_ED Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_308C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x308C)
    #define HD21MAC_CFG_308C_SVCE_P0_REG_TG_H_DE Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_3090_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3090)
    #define HD21MAC_CFG_3090_SVCE_P0_REG_TG_VTT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_3094_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3094)
    #define HD21MAC_CFG_3094_SVCE_P0_REG_TG_VS_ED Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_3098_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3098)
    #define HD21MAC_CFG_3098_SVCE_P0_REG_TG_V_BP_ED Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_309C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x309C)
    #define HD21MAC_CFG_309C_SVCE_P0_REG_TG_V_DE Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_30A0_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30A0)
    #define HD21MAC_CFG_30A0_SVCE_P0_REG_PATGEN_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_30A0_SVCE_P0_REG_PATGEN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_30A4_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30A4)
    #define HD21MAC_CFG_30A4_SVCE_P0_REG_PATGEN_PRG_RGB Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_30A8_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30A8)
    #define HD21MAC_CFG_30A8_SVCE_P0_REG_CLR_RCV_FIFO_FLAG Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_30AC_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30AC)
    #define HD21MAC_CFG_30AC_SVCE_P0_REG_RCV_FIFO_FULL_LAT Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_30AC_SVCE_P0_REG_RCV_FIFO_EMPTY_LAT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_30C0_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30C0)
    #define HD21MAC_CFG_30C0_SVCE_P0_REG_FEED_DEBUG_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_30C4_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30C4)
    #define HD21MAC_CFG_30C4_SVCE_P0_REG_FEED_DEBUG_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_30C8_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30C8)
    #define HD21MAC_CFG_30C8_SVCE_P0_REG_RCV_DEBUG_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_30CC_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30CC)
    #define HD21MAC_CFG_30CC_SVCE_P0_REG_RCV_DEBUG_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_30D0_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30D0)
    #define HD21MAC_CFG_30D0_SVCE_P0_REG_DSCD_DEBUG_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_30D4_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30D4)
    #define HD21MAC_CFG_30D4_SVCE_P0_REG_DSCD_DEBUG_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_30DC_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30DC)
    #define HD21MAC_CFG_30DC_SVCE_P0_REG_BIST_FAIL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_30E0_SVCE_P0 (HDMI2P1_MAC_BASE + 0x30E0)
    #define HD21MAC_CFG_30E0_SVCE_P0_REG_TESTBUS_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_3100_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3100)
    #define HD21MAC_CFG_3100_SVCE_P0_REG_DSCD_RESERVE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3104_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3104)
    #define HD21MAC_CFG_3104_SVCE_P0_REG_DSCD_RESERVE_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3108_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3108)
    #define HD21MAC_CFG_3108_SVCE_P0_REG_DSCD_RESERVE_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_310C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x310C)
    #define HD21MAC_CFG_310C_SVCE_P0_REG_DSCD_RESERVE_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3110_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3110)
    #define HD21MAC_CFG_3110_SVCE_P0_REG_DSCD_RESERVE_4 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3114_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3114)
    #define HD21MAC_CFG_3114_SVCE_P0_REG_DSCD_RESERVE_5 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3118_SVCE_P0 (HDMI2P1_MAC_BASE + 0x3118)
    #define HD21MAC_CFG_3118_SVCE_P0_REG_DSCD_RESERVE_6 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_311C_SVCE_P0 (HDMI2P1_MAC_BASE + 0x311C)
    #define HD21MAC_CFG_311C_SVCE_P0_REG_DSCD_RESERVE_7 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3200_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3200)
    #define HD21MAC_CFG_3200_FRL_TOP_P1_REG_TESTBUS_SEL Fld(7,0,AC_MSKB0)//[6:0]
#define HD21MAC_CFG_3204_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3204)
    #define HD21MAC_CFG_3204_FRL_TOP_P1_REG_WB_DET_USER_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3208_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3208)
    #define HD21MAC_CFG_3208_FRL_TOP_P1_REG_WB_DET_USER_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_320C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x320C)
    #define HD21MAC_CFG_320C_FRL_TOP_P1_REG_WB_DET_UNLOCK_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_320C_FRL_TOP_P1_REG_WB_DET_LOCK_TH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3210_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3210)
    #define HD21MAC_CFG_3210_FRL_TOP_P1_REG_WB_DET_FSM_PAUSE_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3210_FRL_TOP_P1_REG_WB_DET_FSM_PAUSE_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3210_FRL_TOP_P1_REG_WB_DET_FSM_PAUSE_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3210_FRL_TOP_P1_REG_WB_DET_FSM_PAUSE_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3210_FRL_TOP_P1_REG_WB_DET_FSM_RST_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3210_FRL_TOP_P1_REG_WB_DET_FSM_RST_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3210_FRL_TOP_P1_REG_WB_DET_FSM_RST_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3210_FRL_TOP_P1_REG_WB_DET_FSM_RST_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3214_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3214)
    #define HD21MAC_CFG_3214_FRL_TOP_P1_REG_WB_DET_SFT_OV_EN_L1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3214_FRL_TOP_P1_REG_WB_DET_SFT_OV_VALUE_L1 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3214_FRL_TOP_P1_REG_WB_DET_SFT_OV_EN_L0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3214_FRL_TOP_P1_REG_WB_DET_SFT_OV_VALUE_L0 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_3218_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3218)
    #define HD21MAC_CFG_3218_FRL_TOP_P1_REG_WB_DET_SFT_OV_EN_L3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3218_FRL_TOP_P1_REG_WB_DET_SFT_OV_VALUE_L3 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3218_FRL_TOP_P1_REG_WB_DET_SFT_OV_EN_L2 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3218_FRL_TOP_P1_REG_WB_DET_SFT_OV_VALUE_L2 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_321C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x321C)
    #define HD21MAC_CFG_321C_FRL_TOP_P1_REG_TEST_PATH_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_321C_FRL_TOP_P1_REG_WB_DET_CODE_BIT_REVERSE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3220_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3220)
    #define HD21MAC_CFG_3220_FRL_TOP_P1_REG_WB_DET_SFT_STS_L1 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3220_FRL_TOP_P1_REG_WB_DET_SFT_STS_L0 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_3224_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3224)
    #define HD21MAC_CFG_3224_FRL_TOP_P1_REG_WB_DET_SFT_STS_L3 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3224_FRL_TOP_P1_REG_WB_DET_SFT_STS_L2 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_3228_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3228)
    #define HD21MAC_CFG_3228_FRL_TOP_P1_REG_WB_DET_CNT_STS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3228_FRL_TOP_P1_REG_WB_DET_CNT_STS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_322C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x322C)
    #define HD21MAC_CFG_322C_FRL_TOP_P1_REG_WB_DET_CNT_STS_L3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_322C_FRL_TOP_P1_REG_WB_DET_CNT_STS_L2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3230_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3230)
    #define HD21MAC_CFG_3230_FRL_TOP_P1_REG_WB_DET_FSM_STS_L3 Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_3230_FRL_TOP_P1_REG_WB_DET_FSM_STS_L2 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_3230_FRL_TOP_P1_REG_WB_DET_FSM_STS_L1 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_3230_FRL_TOP_P1_REG_WB_DET_FSM_STS_L0 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3234_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3234)
    #define HD21MAC_CFG_3234_FRL_TOP_P1_REG_WB_DET_SFT_BUF_STS_L1 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3234_FRL_TOP_P1_REG_WB_DET_SFT_BUF_STS_L0 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_3238_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3238)
    #define HD21MAC_CFG_3238_FRL_TOP_P1_REG_WB_DET_SFT_BUF_STS_L3 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3238_FRL_TOP_P1_REG_WB_DET_SFT_BUF_STS_L2 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_323C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x323C)
    #define HD21MAC_CFG_323C_FRL_TOP_P1_REG_WB_DET_LOSE_IRQ_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_323C_FRL_TOP_P1_REG_WB_DET_LOSE_IRQ_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_323C_FRL_TOP_P1_REG_WB_DET_LOSE_IRQ_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_323C_FRL_TOP_P1_REG_WB_DET_LOSE_IRQ_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_323C_FRL_TOP_P1_REG_WB_DET_LOSE_IRQ_CLR_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_323C_FRL_TOP_P1_REG_WB_DET_LOSE_IRQ_CLR_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_323C_FRL_TOP_P1_REG_WB_DET_LOSE_IRQ_CLR_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_323C_FRL_TOP_P1_REG_WB_DET_LOSE_IRQ_CLR_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3240_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3240)
    #define HD21MAC_CFG_3240_FRL_TOP_P1_REG_IGNORE_1816B_ERROR_IN_TRAIN_PERIOD Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3240_FRL_TOP_P1_REG_MASK_SCDC_TO_CLR_ERROR_CNT Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3240_FRL_TOP_P1_REG_ERROR_CNT_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_3240_FRL_TOP_P1_REG_RD_ERR_CNT_THR Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_3240_FRL_TOP_P1_REG_RD_ERR_INIT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3240_FRL_TOP_P1_REG_EN_16B_OUT_INV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3240_FRL_TOP_P1_REG_EN_18B_IN_INV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3244_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3244)
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_RED_CNT_CLR_L3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_RED_CNT_CLR_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_RED_CNT_CLR_L1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_RED_CNT_CLR_L0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_RMD_CNT_CLR_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_RMD_CNT_CLR_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_RMD_CNT_CLR_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_RMD_CNT_CLR_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_CLR_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_CLR_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_CLR_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3244_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_CLR_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3248_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3248)
    #define HD21MAC_CFG_3248_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_324C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x324C)
    #define HD21MAC_CFG_324C_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3250_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3250)
    #define HD21MAC_CFG_3250_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3254_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3254)
    #define HD21MAC_CFG_3254_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3258_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3258)
    #define HD21MAC_CFG_3258_FRL_TOP_P1_REG_18B16B_RMD_CNT_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_325C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x325C)
    #define HD21MAC_CFG_325C_FRL_TOP_P1_REG_18B16B_RMD_CNT_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3260_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3260)
    #define HD21MAC_CFG_3260_FRL_TOP_P1_REG_18B16B_RMD_CNT_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3264_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3264)
    #define HD21MAC_CFG_3264_FRL_TOP_P1_REG_18B16B_RMD_CNT_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3268_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3268)
    #define HD21MAC_CFG_3268_FRL_TOP_P1_REG_18B16B_RED_CNT_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_326C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x326C)
    #define HD21MAC_CFG_326C_FRL_TOP_P1_REG_18B16B_RED_CNT_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3270_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3270)
    #define HD21MAC_CFG_3270_FRL_TOP_P1_REG_18B16B_RED_CNT_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3274_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3274)
    #define HD21MAC_CFG_3274_FRL_TOP_P1_REG_18B16B_RED_CNT_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3278_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3278)
    #define HD21MAC_CFG_3278_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_VLD_TO_SCDC_CLR_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3278_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_VLD_TO_SCDC_CLR_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3278_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_VLD_TO_SCDC_CLR_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3278_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_VLD_TO_SCDC_CLR_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3278_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_TO_SCDC_CLR_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3278_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_TO_SCDC_CLR_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3278_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_TO_SCDC_CLR_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3278_FRL_TOP_P1_REG_18B16B_SYMBOL_ERROR_CNT_TO_SCDC_CLR_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3280_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3280)
    #define HD21MAC_CFG_3280_FRL_TOP_P1_REG_LFSR_SEED_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3284_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3284)
    #define HD21MAC_CFG_3284_FRL_TOP_P1_REG_LFSR_SEED_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3288_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3288)
    #define HD21MAC_CFG_3288_FRL_TOP_P1_REG_LFSR_SEED_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_328C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x328C)
    #define HD21MAC_CFG_328C_FRL_TOP_P1_REG_LFSR_SEED_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3294_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3294)
    #define HD21MAC_CFG_3294_FRL_TOP_P1_REG_INTERLANESKEW_LANE0_CATCH Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_3294_FRL_TOP_P1_REG_INTERLANESKEW_FORCE_SYMBOL_LOCK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3294_FRL_TOP_P1_REG_INTERLANESKEW_LOSELOCK_THR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3298_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3298)
    #define HD21MAC_CFG_3298_FRL_TOP_P1_REG_INTERLANESKEW_RPTR_OV_EN_L3 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3298_FRL_TOP_P1_REG_INTERLANESKEW_RPTR_OV_EN_L2 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3298_FRL_TOP_P1_REG_INTERLANESKEW_RPTR_OV_EN_L1 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3298_FRL_TOP_P1_REG_INTERLANESKEW_RPTR_OV_L3 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_3298_FRL_TOP_P1_REG_INTERLANESKEW_RPTR_OV_L2 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_3298_FRL_TOP_P1_REG_INTERLANESKEW_RPTR_OV_L1 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_329C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x329C)
    #define HD21MAC_CFG_329C_FRL_TOP_P1_REG_INTERLANESKEW_RPTR_L2 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_329C_FRL_TOP_P1_REG_INTERLANESKEW_RPTR_L1 Fld(5,3,AC_MSKB0)//[7:3]
    #define HD21MAC_CFG_329C_FRL_TOP_P1_REG_INTERLANESKEW_LOCK Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_329C_FRL_TOP_P1_REG_INTERLANESKEW_UNLOCK_IRQ Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_329C_FRL_TOP_P1_REG_INTERLANESKEW_UNLOCK_IRQ_CLR Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_32A0_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32A0)
    #define HD21MAC_CFG_32A0_FRL_TOP_P1_REG_SHIFT_CNT_TOL Fld(4,0,AC_MSKB0)//[3:0]
    #define HD21MAC_CFG_32A0_FRL_TOP_P1_REG_INTERLANESKEW_RPTR_L3 Fld(5,8,AC_MSKB1)//[12:8]
#define HD21MAC_CFG_32A8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32A8)
    #define HD21MAC_CFG_32A8_FRL_TOP_P1_REG_SR_SSB_CHECK_TIME Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_32A8_FRL_TOP_P1_REG_SR_SSB_32_PERIOD_OK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_32A8_FRL_TOP_P1_REG_FEC_ENGINE_BYPASS Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_32A8_FRL_TOP_P1_REG_SR_SSB_CHECK_OK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_32A8_FRL_TOP_P1_REG_FEC_DEC_BITERR_ADDED Fld(5,4,AC_MSKW10)//[8:4]
    #define HD21MAC_CFG_32A8_FRL_TOP_P1_REG_FEC_DEC_ERROR_AUTO_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_32A8_FRL_TOP_P1_REG_FEC_DEC_OUT_MODE Fld(2,1,AC_MSKB0)//[2:1]
    #define HD21MAC_CFG_32A8_FRL_TOP_P1_REG_FEC_DEC_ALWAYS_FIX Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_32AC_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32AC)
    #define HD21MAC_CFG_32AC_FRL_TOP_P1_REG_FEC_DEC_BLOCK_WINDOW Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32B0_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32B0)
    #define HD21MAC_CFG_32B0_FRL_TOP_P1_REG_FEC_ERROR_CNT_TO_SCDC_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_32B0_FRL_TOP_P1_REG_SR_SSB_DELAY Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_32B4_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32B4)
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALID_SCDC_CLR_L3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALID_SCDC_CLR_L2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALID_SCDC_CLR_L1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALID_SCDC_CLR_L0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_SCDC_CLR_L3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_SCDC_CLR_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_SCDC_CLR_L1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_SCDC_CLR_L0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_CLR_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_CLR_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_CLR_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_CLR_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RESET_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RESET_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RESET_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_32B4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RESET_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_32B8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32B8)
    #define HD21MAC_CFG_32B8_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_SEL_L3 Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_32B8_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_SEL_L2 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_32B8_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_SEL_L1 Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_32B8_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_SEL_L0 Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_32C0_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32C0)
    #define HD21MAC_CFG_32C0_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_0_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32C4_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32C4)
    #define HD21MAC_CFG_32C4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_1_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32C8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32C8)
    #define HD21MAC_CFG_32C8_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_0_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32CC_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32CC)
    #define HD21MAC_CFG_32CC_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_1_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32D0_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32D0)
    #define HD21MAC_CFG_32D0_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_0_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32D4_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32D4)
    #define HD21MAC_CFG_32D4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_1_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32D8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32D8)
    #define HD21MAC_CFG_32D8_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_0_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32DC_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32DC)
    #define HD21MAC_CFG_32DC_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_RAW_VALUE_1_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32E0_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32E0)
    #define HD21MAC_CFG_32E0_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32E4_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32E4)
    #define HD21MAC_CFG_32E4_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32E8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32E8)
    #define HD21MAC_CFG_32E8_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32EC_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32EC)
    #define HD21MAC_CFG_32EC_FRL_TOP_P1_REG_FEC_DEC_ERROR_CNT_VALUE_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_32F0_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32F0)
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOSE_LOCK_IRQ_CLR_L3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOSE_LOCK_IRQ_CLR_L2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOSE_LOCK_IRQ_CLR_L1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOSE_LOCK_IRQ_CLR_L0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOSE_LOCK_IRQ_L3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOSE_LOCK_IRQ_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOSE_LOCK_IRQ_L1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOSE_LOCK_IRQ_L0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOCK_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOCK_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOCK_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_LOCK_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_MASK_SYMBOL_LOCK_IN_TRAIN_SEQ Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_TRAINING_EN_VALUE_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_TRAINING_EN_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_32F0_FRL_TOP_P1_REG_SYMBOL_ERROR_INCLUDE_RD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_32F4_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32F4)
    #define HD21MAC_CFG_32F4_FRL_TOP_P1_REG_SYMBOL_UNLOCK_THR Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_32F4_FRL_TOP_P1_REG_SYMBOL_LOCK_THR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_32F8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x32F8)
    #define HD21MAC_CFG_32F8_FRL_TOP_P1_REG_SYMBOL_UNLOCK_THR_NORMAL Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_32F8_FRL_TOP_P1_REG_SYMBOL_LOCK_THR_NORMAL Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3300_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3300)
    #define HD21MAC_CFG_3300_FRL_TOP_P1_REG_LANE_LINK_QUALITY_ERROR_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3304_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3304)
    #define HD21MAC_CFG_3304_FRL_TOP_P1_REG_LANE_LINK_QUALITY_ERROR_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3308_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3308)
    #define HD21MAC_CFG_3308_FRL_TOP_P1_REG_LANE_LINK_QUALITY_ERROR_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_330C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x330C)
    #define HD21MAC_CFG_330C_FRL_TOP_P1_REG_LANE_LINK_QUALITY_ERROR_L3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3310_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3310)
    #define HD21MAC_CFG_3310_FRL_TOP_P1_REG_LANE_LINK_QUALITY_ERROR_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3310_FRL_TOP_P1_REG_LANE_LINK_QUALITY_ERROR_CLR_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3310_FRL_TOP_P1_REG_LANE_LINK_QUALITY_ERROR_CLR_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3310_FRL_TOP_P1_REG_LANE_LINK_QUALITY_ERROR_CLR_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3310_FRL_TOP_P1_REG_LANE_LINK_QUALITY_ERROR_CLR_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3314_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3314)
    #define HD21MAC_CFG_3314_FRL_TOP_P1_REG_FEC_HW_RESET Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3318_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3318)
    #define HD21MAC_CFG_3318_FRL_TOP_P1_REG_SR_SSB_PERIOD_L0 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_331C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x331C)
    #define HD21MAC_CFG_331C_FRL_TOP_P1_REG_SR_SSB_PERIOD_L1 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_3320_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3320)
    #define HD21MAC_CFG_3320_FRL_TOP_P1_REG_SR_SSB_PERIOD_L2 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_3324_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3324)
    #define HD21MAC_CFG_3324_FRL_TOP_P1_REG_SR_SSB_PERIOD_L3 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_3340_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3340)
    #define HD21MAC_CFG_3340_FRL_TOP_P1_REG_BIST_FALI_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3344_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3344)
    #define HD21MAC_CFG_3344_FRL_TOP_P1_REG_BIST_FALI_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3348_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3348)
    #define HD21MAC_CFG_3348_FRL_TOP_P1_REG_TESTBUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_334C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x334C)
    #define HD21MAC_CFG_334C_FRL_TOP_P1_REG_TESTBUS_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3380_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3380)
    #define HD21MAC_CFG_3380_FRL_TOP_P1_REG_18B16B_SR_P_0 Fld(16,0,AC_FULLW10)//[15:0]

    //Page HDMI21_MAC_17
#define HD21MAC_CFG_3384_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3384)
    #define HD21MAC_CFG_3384_FRL_TOP_P1_REG_18B16B_SR_P_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3388_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3388)
    #define HD21MAC_CFG_3388_FRL_TOP_P1_REG_18B16B_SR_N_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_338C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x338C)
    #define HD21MAC_CFG_338C_FRL_TOP_P1_REG_18B16B_SR_N_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3390_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3390)
    #define HD21MAC_CFG_3390_FRL_TOP_P1_REG_18B16B_SSB_P_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3394_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3394)
    #define HD21MAC_CFG_3394_FRL_TOP_P1_REG_18B16B_SSB_P_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3398_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x3398)
    #define HD21MAC_CFG_3398_FRL_TOP_P1_REG_18B16B_SSB_N_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_339C_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x339C)
    #define HD21MAC_CFG_339C_FRL_TOP_P1_REG_18B16B_SSB_N_1 Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_33C0_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33C0)
    #define HD21MAC_CFG_33C0_FRL_TOP_P1_REG_RESERVED_R_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33C4_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33C4)
    #define HD21MAC_CFG_33C4_FRL_TOP_P1_REG_RESERVED_R_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33C8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33C8)
    #define HD21MAC_CFG_33C8_FRL_TOP_P1_REG_RESERVED_R_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33CC_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33CC)
    #define HD21MAC_CFG_33CC_FRL_TOP_P1_REG_RESERVED_R_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33D0_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33D0)
    #define HD21MAC_CFG_33D0_FRL_TOP_P1_REG_RESERVED_RW_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33D4_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33D4)
    #define HD21MAC_CFG_33D4_FRL_TOP_P1_REG_RESERVED_RW_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33D8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33D8)
    #define HD21MAC_CFG_33D8_FRL_TOP_P1_REG_RESERVED_RW_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33DC_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33DC)
    #define HD21MAC_CFG_33DC_FRL_TOP_P1_REG_RESERVED_RW_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33E8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33E8)
    #define HD21MAC_CFG_33E8_FRL_TOP_P1_REG_SW_RESET_WHEN_TRAINING_BEGIN_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33EC_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33EC)
    #define HD21MAC_CFG_33EC_FRL_TOP_P1_REG_SW_RESET_WHEN_TRAINING_BEGIN_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33F0_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33F0)
    #define HD21MAC_CFG_33F0_FRL_TOP_P1_REG_SW_RESET_WHEN_TRAINING_BEGIN_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33F4_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33F4)
    #define HD21MAC_CFG_33F4_FRL_TOP_P1_REG_SW_RESET_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33F8_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33F8)
    #define HD21MAC_CFG_33F8_FRL_TOP_P1_REG_SW_RESET_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_33FC_FRL_TOP_P1 (HDMI2P1_MAC_BASE + 0x33FC)
    #define HD21MAC_CFG_33FC_FRL_TOP_P1_REG_SW_RESET_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3400_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3400)
    #define HD21MAC_CFG_3400_FRL_DEC_P1_REG_FRL_DECODE_ERROR_MASK Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3400_FRL_DEC_P1_REG_FRL_LANE_NUM_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3400_FRL_DEC_P1_REG_FRL_LANE_NUM Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3404_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3404)
    #define HD21MAC_CFG_3404_FRL_DEC_P1_REG_TESTBUS_MUX Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3404_FRL_DEC_P1_REG_BYPASS_SSB_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3404_FRL_DEC_P1_REG_FRL_TMDS_CLK_CTRL_RST Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3408_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3408)
    #define HD21MAC_CFG_3408_FRL_DEC_P1_REG_TYPE_DETECT_L_OFFSET Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3408_FRL_DEC_P1_REG_FRL_DECODE_RESET Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3408_FRL_DEC_P1_REG_FRL_DECODE_RESERVED_RESET Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_3408_FRL_DEC_P1_REG_FRL_DECODE_TIMING_DETECT_RESET Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3408_FRL_DEC_P1_REG_FRL_DECODE_SRAM_RESET Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3408_FRL_DEC_P1_REG_FRL_DECODE_DEPACKER_RESET Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3408_FRL_DEC_P1_REG_FRL_DECODE_TYPE_DETECT_RESET Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_340C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x340C)
    #define HD21MAC_CFG_340C_FRL_DEC_P1_REG_FRL_SRAM_RST_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_340C_FRL_DEC_P1_REG_FRL_SRAM_SW_RST Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_340C_FRL_DEC_P1_REG_FRL_SRAM_EMPTY_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_340C_FRL_DEC_P1_REG_FRL_SRAM_EMPTY Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_340C_FRL_DEC_P1_REG_FRL_SRAM_FULL_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_340C_FRL_DEC_P1_REG_FRL_SRAM_FULL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3410_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3410)
    #define HD21MAC_CFG_3410_FRL_DEC_P1_REG_FRL_SRAM_READ_START Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3414_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3414)
    #define HD21MAC_CFG_3414_FRL_DEC_P1_REG_VTYPE_401_CNT_THRD Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3414_FRL_DEC_P1_REG_ISLAND_PREAMBLE Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_3414_FRL_DEC_P1_REG_VIDEO_PREAMBLE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3418_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3418)
    #define HD21MAC_CFG_3418_FRL_DEC_P1_REG_TMDS_DEPACKER_VIDEO_GB_VALUE_MASK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3440_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3440)
    #define HD21MAC_CFG_3440_FRL_DEC_P1_REG_FRL_TIMING_DETECT_VTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3444_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3444)
    #define HD21MAC_CFG_3444_FRL_DEC_P1_REG_FRL_TIMING_DETECT_HTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3448_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3448)
    #define HD21MAC_CFG_3448_FRL_DEC_P1_REG_FRL_TIMING_DETECT_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_344C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x344C)
    #define HD21MAC_CFG_344C_FRL_DEC_P1_REG_FRL_TIMING_DETECT_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3450_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3450)
    #define HD21MAC_CFG_3450_FRL_DEC_P1_REG_FRL_TIMING_DETECT_V_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3454_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3454)
    #define HD21MAC_CFG_3454_FRL_DEC_P1_REG_FRL_TIMING_DETECT_VSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3458_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3458)
    #define HD21MAC_CFG_3458_FRL_DEC_P1_REG_FRL_TIMING_DETECT_V_BACK_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_345C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x345C)
    #define HD21MAC_CFG_345C_FRL_DEC_P1_REG_FRL_TIMING_DETECT_H_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3460_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3460)
    #define HD21MAC_CFG_3460_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_VTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3464_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3464)
    #define HD21MAC_CFG_3464_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_HTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3468_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3468)
    #define HD21MAC_CFG_3468_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_346C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x346C)
    #define HD21MAC_CFG_346C_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3470_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3470)
    #define HD21MAC_CFG_3470_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_V_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3474_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3474)
    #define HD21MAC_CFG_3474_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_VSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3478_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3478)
    #define HD21MAC_CFG_3478_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_V_BACK_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_347C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x347C)
    #define HD21MAC_CFG_347C_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_H_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3480_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3480)
    #define HD21MAC_CFG_3480_FRL_DEC_P1_REG_FRL_TIMING_DETECT_HSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3484_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3484)
    #define HD21MAC_CFG_3484_FRL_DEC_P1_REG_FRL_TIMING_DETECT_H_BACK_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3488_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3488)
    #define HD21MAC_CFG_3488_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_VDE_STABLE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3488_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_HDE_STABLE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3488_FRL_DEC_P1_REG_FRL_TIMING_DETECT_VDE_STABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3488_FRL_DEC_P1_REG_FRL_TIMING_DETECT_HDE_STABLE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_348C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x348C)
    #define HD21MAC_CFG_348C_FRL_DEC_P1_REG_FRL_VIDEO_HDE_CNT_STABLE_CNT_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3490_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3490)
    #define HD21MAC_CFG_3490_FRL_DEC_P1_REG_FRL_VIDEO_VDE_CNT_STABLE_CNT_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3494_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3494)
    #define HD21MAC_CFG_3494_FRL_DEC_P1_REG_TMDS_VIDEO_HDE_CNT_STABLE_CNT_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3498_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3498)
    #define HD21MAC_CFG_3498_FRL_DEC_P1_REG_TMDS_VIDEO_VDE_CNT_STABLE_CNT_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_34A0_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x34A0)
    #define HD21MAC_CFG_34A0_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_HSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_34A4_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x34A4)
    #define HD21MAC_CFG_34A4_FRL_DEC_P1_REG_TMDS_TIMING_DETECT_H_BACK_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_34A8_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x34A8)
    #define HD21MAC_CFG_34A8_FRL_DEC_P1_REG_FRL_HDE_CNT_STABLE_EQ_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_34AC_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x34AC)
    #define HD21MAC_CFG_34AC_FRL_DEC_P1_REG_TMDS_HDE_CNT_STABLE_EQ_THRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_34C0_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x34C0)
    #define HD21MAC_CFG_34C0_FRL_DEC_P1_REG_HV_REGEN_V_VRR_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_34C0_FRL_DEC_P1_REG_HV_REGEN_V_FRONT_SYNC_MUX Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_34C0_FRL_DEC_P1_REG_HSYNC_REGEN_MUX Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_34C0_FRL_DEC_P1_REG_HV_REGEN_H_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_34C0_FRL_DEC_P1_REG_HV_REGEN_V_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_34C4_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x34C4)
    #define HD21MAC_CFG_34C4_FRL_DEC_P1_REG_HV_REGEN_V_FRONT_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_34C8_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x34C8)
    #define HD21MAC_CFG_34C8_FRL_DEC_P1_REG_HV_REGEN_V_SYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_34CC_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x34CC)
    #define HD21MAC_CFG_34CC_FRL_DEC_P1_REG_HV_REGEN_H_FRONT_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_34D0_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x34D0)
    #define HD21MAC_CFG_34D0_FRL_DEC_P1_REG_HV_REGEN_H_SYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3500_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3500)
    #define HD21MAC_CFG_3500_FRL_DEC_P1_REG_FRL_DECODE_IRQ_STATUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3504_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3504)
    #define HD21MAC_CFG_3504_FRL_DEC_P1_REG_FRL_DECODE_IRQ_STATUS_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3508_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3508)
    #define HD21MAC_CFG_3508_FRL_DEC_P1_REG_FRL_DECODE_IRQ_FINAL_STATUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_350C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x350C)
    #define HD21MAC_CFG_350C_FRL_DEC_P1_REG_FRL_DECODE_IRQ_FINAL_STATUS_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3510_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3510)
    #define HD21MAC_CFG_3510_FRL_DEC_P1_REG_FRL_DECODE_IRQ_CLR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3514_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3514)
    #define HD21MAC_CFG_3514_FRL_DEC_P1_REG_FRL_DECODE_IRQ_CLR_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3518_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3518)
    #define HD21MAC_CFG_3518_FRL_DEC_P1_REG_FRL_DECODE_IRQ_MASK_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_351C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x351C)
    #define HD21MAC_CFG_351C_FRL_DEC_P1_REG_FRL_DECODE_IRQ_MASK_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3520_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3520)
    #define HD21MAC_CFG_3520_FRL_DEC_P1_REG_FRL_DECODE_IRQ_FORCE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3524_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3524)
    #define HD21MAC_CFG_3524_FRL_DEC_P1_REG_FRL_DECODE_IRQ_FORCE_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3540_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3540)
    #define HD21MAC_CFG_3540_FRL_DEC_P1_REG_CTSN_SYNTH_RING_CNT_PERIOD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3544_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3544)
    #define HD21MAC_CFG_3544_FRL_DEC_P1_REG_CTSN_SYNTH_RING_CNT_PERIOD_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_3548_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3548)
    #define HD21MAC_CFG_3548_FRL_DEC_P1_REG_CTSN_SYNTH_RING_CNT_SIZE Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3548_FRL_DEC_P1_REG_CTSN_SYNTH_REFRESH_RATIO_MUX Fld(2,1,AC_MSKB0)//[2:1]
    #define HD21MAC_CFG_3548_FRL_DEC_P1_REG_CTSN_SYNTH_CNT_EN_START_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_354C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x354C)
    #define HD21MAC_CFG_354C_FRL_DEC_P1_REG_CTSN_SYNTH_CNT_FAST_DIV_VAL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_354C_FRL_DEC_P1_REG_CTSN_SYNTH_RATIO_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_354C_FRL_DEC_P1_REG_CTSN_SYNTH_RATIO_OVE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3550_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3550)
    #define HD21MAC_CFG_3550_FRL_DEC_P1_REG_CTSN_SYNTH_PERIOD_OV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3554_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3554)
    #define HD21MAC_CFG_3554_FRL_DEC_P1_REG_CTSN_SYNTH_PERIOD_OV_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_3558_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3558)
    #define HD21MAC_CFG_3558_FRL_DEC_P1_REG_CTSN_SYNTH_ADD_OV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_355C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x355C)
    #define HD21MAC_CFG_355C_FRL_DEC_P1_REG_CTSN_SYNTH_ADD_OV_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_3560_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3560)
    #define HD21MAC_CFG_3560_FRL_DEC_P1_REG_CTSN_SYNTH_STABLE_PERIOD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3564_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3564)
    #define HD21MAC_CFG_3564_FRL_DEC_P1_REG_CTSN_SYNTH_BIG_CHG_PERIOD_THR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3568_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3568)
    #define HD21MAC_CFG_3568_FRL_DEC_P1_REG_CTSN_SYNTH_BIG_CHG_PERIOD_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3568_FRL_DEC_P1_REG_CTSN_SYNTH_BIG_CHG_PERIOD_THR_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_356C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x356C)
    #define HD21MAC_CFG_356C_FRL_DEC_P1_REG_CTSN_SYNTH_BIG_CHG_ADD_THR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3570_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3570)
    #define HD21MAC_CFG_3570_FRL_DEC_P1_REG_CTSN_SYNTH_BIG_CHG_ADD_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3570_FRL_DEC_P1_REG_CTSN_SYNTH_BIG_CHG_ADD_THR_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_3574_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3574)
    #define HD21MAC_CFG_3574_FRL_DEC_P1_REG_CTSN_SYNTH_BIG_CHG_RECORD_PERIOD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3578_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3578)
    #define HD21MAC_CFG_3578_FRL_DEC_P1_REG_CTSN_SYNTH_TMDS_CNT_DIFF_PERIOD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_357C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x357C)
    #define HD21MAC_CFG_357C_FRL_DEC_P1_REG_CTSN_SYNTH_TMDS_CNT_DIFF_CLEAR Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_357C_FRL_DEC_P1_REG_CTSN_SYNTH_TMDS_CNT_DIFF_MODE Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_357C_FRL_DEC_P1_REG_CTSN_SYNTH_TMDS_CNT_DIFF_PERIOD_1 Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_3580_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3580)
    #define HD21MAC_CFG_3580_FRL_DEC_P1_REG_CLK_TMDS_DE_JITTER_EN_OV Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3580_FRL_DEC_P1_REG_CLK_TMDS_DE_JITTER_EN_OVE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3580_FRL_DEC_P1_REG_CTSN_SYNTH_CNT_RST_OVE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3580_FRL_DEC_P1_REG_CTSN_SYNTH_CNT_RST_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3584_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3584)
    #define HD21MAC_CFG_3584_FRL_DEC_P1_REG_CTSN_SYNTH_TMDS_DIFF_CUR_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_3584_FRL_DEC_P1_REG_CTSN_SYNTH_CNT_EN_START_MODE Fld(2,4,AC_MSKB0)//[5:4]
#define HD21MAC_CFG_3588_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3588)
    #define HD21MAC_CFG_3588_FRL_DEC_P1_REG_CTSN_SYNTH_RING_CNT_SWITCH_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_358C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x358C)
    #define HD21MAC_CFG_358C_FRL_DEC_P1_REG_CTSN_SYNTH_RING_CNT_SWITCH_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_3590_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3590)
    #define HD21MAC_CFG_3590_FRL_DEC_P1_REG_CTSN_SYNTH_BIG_CHG_INCREASE_NUM Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3590_FRL_DEC_P1_REG_CTSN_SYNTH_BIG_CHG_NUM Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3594_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3594)
    #define HD21MAC_CFG_3594_FRL_DEC_P1_REG_CTSN_SYNTH_MAX_TMDS_CURRENT_LEAD Fld(3,1,AC_MSKB0)//[3:1]
    #define HD21MAC_CFG_3594_FRL_DEC_P1_REG_CLK_TMDS_DE_JITTER_EN_HW Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3598_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x3598)
    #define HD21MAC_CFG_3598_FRL_DEC_P1_REG_CTSN_SYNTH_MAX_TMDS_DIFF_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_359C_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x359C)
    #define HD21MAC_CFG_359C_FRL_DEC_P1_REG_CTSN_SYNTH_MAX_TMDS_DIFF_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_35A0_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35A0)
    #define HD21MAC_CFG_35A0_FRL_DEC_P1_REG_CTSN_SYNTH_STAT_TMDS_DIFF_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_35A4_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35A4)
    #define HD21MAC_CFG_35A4_FRL_DEC_P1_REG_CTSN_SYNTH_STAT_TMDS_DIFF_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_35A8_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35A8)
    #define HD21MAC_CFG_35A8_FRL_DEC_P1_REG_CTSN_SYNTH_MAX_STAT_TMDS_DIFF_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_35AC_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35AC)
    #define HD21MAC_CFG_35AC_FRL_DEC_P1_REG_CTSN_SYNTH_MAX_STAT_TMDS_DIFF_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_35B0_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35B0)
    #define HD21MAC_CFG_35B0_FRL_DEC_P1_REG_CTSN_SYNTH_MAX_TMDS_CURRENT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_35B4_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35B4)
    #define HD21MAC_CFG_35B4_FRL_DEC_P1_REG_CTSN_SYNTH_MAX_TMDS_CURRENT_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_35B8_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35B8)
    #define HD21MAC_CFG_35B8_FRL_DEC_P1_REG_CTSN_SYNTH_MIN_TMDS_CURRENT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_35BC_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35BC)
    #define HD21MAC_CFG_35BC_FRL_DEC_P1_REG_CTSN_SYNTH_MIN_TMDS_CURRENT_1 Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_35C0_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35C0)
    #define HD21MAC_CFG_35C0_FRL_DEC_P1_REG_FRL_HSYNC_POLARITY_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_35C0_FRL_DEC_P1_REG_FRL_VSYNC_POLARITY_INV Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_35C0_FRL_DEC_P1_REG_FRL_HSYNC_POLARITY_DETECT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_35C0_FRL_DEC_P1_REG_FRL_VSYNC_POLARITY_DETECT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_35C0_FRL_DEC_P1_REG_TMDS_HSYNC_POLARITY_SW Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_35C0_FRL_DEC_P1_REG_TMDS_VSYNC_POLARITY_SW Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_35C4_FRL_DEC_P1 (HDMI2P1_MAC_BASE + 0x35C4)
    #define HD21MAC_CFG_35C4_FRL_DEC_P1_REG_FRL_DEPACK_BUG_EN Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_3600_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3600)
    #define HD21MAC_CFG_3600_DTOP_P1_REG_SW_RESERVED1 Fld(9,7,AC_MSKW10)//[15:7]
    #define HD21MAC_CFG_3600_DTOP_P1_REG_BOUNDARY_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3600_DTOP_P1_REG_ACCU_ERR_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3600_DTOP_P1_REG_EQ_NEW_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3600_DTOP_P1_REG_SW_RESERVED0 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3604_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3604)
    #define HD21MAC_CFG_3604_DTOP_P1_REG_PHR_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3608_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3608)
    #define HD21MAC_CFG_3608_DTOP_P1_REG_PHG_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_360C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x360C)
    #define HD21MAC_CFG_360C_DTOP_P1_REG_PHB_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3610_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3610)
    #define HD21MAC_CFG_3610_DTOP_P1_REG_TMUX_SEL2 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_3610_DTOP_P1_REG_SCMB_STATUS Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3610_DTOP_P1_REG_ACCLSB16BIT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3610_DTOP_P1_REG_ACC8LSB_EXT_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3610_DTOP_P1_REG_ACC8LSB_SELECT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3614_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3614)
    #define HD21MAC_CFG_3614_DTOP_P1_RESERVED_05_15 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_FIFO_EMPTY_STS_CH0 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_FIFO_FULL_STS_CH0 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_EMPTY_IRQ_STS_CH0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_FULL_IRQ_STS_CH0 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_FIFO_RPTR_STS_CH0 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_FIFO_WPTR_STS_CH0 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_FULL_IRQ_CLR_CH0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_EMPTY_IRQ_CLR_CH0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_FIFO_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_8BTO10B_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3614_DTOP_P1_REG_DELAY_1T_ALIGNMENT_STATUS Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3618_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3618)
    #define HD21MAC_CFG_3618_DTOP_P1_RESERVED_06_15 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3618_DTOP_P1_REG_FIFO_EMPTY_STS_CH1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3618_DTOP_P1_REG_FIFO_FULL_STS_CH1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3618_DTOP_P1_REG_EMPTY_IRQ_STS_CH1 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3618_DTOP_P1_REG_FULL_IRQ_STS_CH1 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3618_DTOP_P1_REG_FIFO_RPTR_STS_CH1 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_3618_DTOP_P1_REG_FIFO_WPTR_STS_CH1 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_3618_DTOP_P1_REG_FULL_IRQ_CLR_CH1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3618_DTOP_P1_REG_EMPTY_IRQ_CLR_CH1 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3618_DTOP_P1_RESERVED_06_00 Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_361C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x361C)
    #define HD21MAC_CFG_361C_DTOP_P1_REG_DVIR_RD_ONLY_RESERVED Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_361C_DTOP_P1_REG_DVI_ERSTR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3620_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3620)
    #define HD21MAC_CFG_3620_DTOP_P1_REG_DVIG_RD_ONLY_RESERVED Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3620_DTOP_P1_REG_DVI_ERSTG Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3624_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3624)
    #define HD21MAC_CFG_3624_DTOP_P1_REG_DVIB_RD_ONLY_RESERVED Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3624_DTOP_P1_REG_DVI_ERSTB Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3628_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3628)
    #define HD21MAC_CFG_3628_DTOP_P1_REG_DVI_RESERVED_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3628_DTOP_P1_REG_DVI_PHASE_THD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_362C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x362C)
    #define HD21MAC_CFG_362C_DTOP_P1_REG_DVI_PH_CH_SEL Fld(2,0,AC_MSKB0)//[1:0]
    #define HD21MAC_CFG_362C_DTOP_P1_REG_DVI_RDST Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_362C_DTOP_P1_REG_DVI_ERRD Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_362C_DTOP_P1_REG_DVI_RESERVED_0 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_362C_DTOP_P1_REG_DVI_ERTH Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3630_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3630)
    #define HD21MAC_CFG_3630_DTOP_P1_REG_DVI_INIT_VALUE Fld(5,0,AC_MSKB0)//[4:0]
    #define HD21MAC_CFG_3630_DTOP_P1_REG_DVI_ENSTRCTRL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3630_DTOP_P1_REG_DVI_ENFALLEDGE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3630_DTOP_P1_REG_DVI_PM_SWAP Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3630_DTOP_P1_REG_SFTERFIL Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3630_DTOP_P1_REG_DVI_OVRIDE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3630_DTOP_P1_REG_DVI_RESERVED_1 Fld(6,10,AC_MSKB1)//[15:10]
#define HD21MAC_CFG_3634_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3634)
    #define HD21MAC_CFG_3634_DTOP_P1_REG_DVI_RESERVED_10 Fld(3,0,AC_MSKB0)//[2:0]
    #define HD21MAC_CFG_3634_DTOP_P1_REG_DET_CLK_CNT Fld(13,3,AC_MSKW10)//[15:3]
#define HD21MAC_CFG_3638_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3638)
    #define HD21MAC_CFG_3638_DTOP_P1_REG_DVI_RESERVED_3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3638_DTOP_P1_REG_DVI_RESERVED_2 Fld(4,0,AC_MSKB0)//[3:0]
    #define HD21MAC_CFG_3638_DTOP_P1_REG_AUTO_CLR_ENZ Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3638_DTOP_P1_REG_DVI_RBSWAP Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3638_DTOP_P1_REG_DVI_GATEODCLK Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3638_DTOP_P1_REG_DVI_DELOCKEN Fld(1,7,AC_MSKB0)//[7:7]

    //Page HDMI21_MAC_18
#define HD21MAC_CFG_363C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x363C)
    #define HD21MAC_CFG_363C_DTOP_P1_REG_SET_CMPVALUE43_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_363C_DTOP_P1_REG_SET_CMPVALUE43_RESERVED Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_363C_DTOP_P1_REG_SET_CMPVALUE43 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_3640_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3640)
    #define HD21MAC_CFG_3640_DTOP_P1_REG_SET_CMPVALUE85_RESERVED Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_3640_DTOP_P1_REG_SET_CMPVALUE85 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_3644_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3644)
    #define HD21MAC_CFG_3644_DTOP_P1_REG_SET_CMPVALUE170_RESERVED Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_3644_DTOP_P1_REG_SET_CMPVALUE170 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_3648_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3648)
    #define HD21MAC_CFG_3648_DTOP_P1_REG_COMP_TOL_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3648_DTOP_P1_REG_COMP_TOL Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_3648_DTOP_P1_REG_SET_CMPVALUE Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_364C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x364C)
    #define HD21MAC_CFG_364C_DTOP_P1_REG_SET_CMPVALUE2_RESERVED Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_364C_DTOP_P1_REG_ENLARGE_COM_TOL Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_364C_DTOP_P1_REG_SET_CMPVALUE2 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_3650_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3650)
    #define HD21MAC_CFG_3650_DTOP_P1_REG_DVT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3654_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3654)
    #define HD21MAC_CFG_3654_DTOP_P1_REG_WDT_WIDTH Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3654_DTOP_P1_REG_WDT_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3654_DTOP_P1_REG_WDT_TESTMD Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3654_DTOP_P1_REG_DVT_PH Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3654_DTOP_P1_REG_CH_PH64 Fld(3,11,AC_MSKB1)//[13:11]
    #define HD21MAC_CFG_3654_DTOP_P1_REG_OV_EQ_DONE_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3654_DTOP_P1_REG_OV_EQ_DONE_VALUE Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_3658_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3658)
    #define HD21MAC_CFG_3658_DTOP_P1_REG_DVI_RPT_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_365C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x365C)
    #define HD21MAC_CFG_365C_DTOP_P1_REG_DVI_RPT_STATUS1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3660_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3660)
    #define HD21MAC_CFG_3660_DTOP_P1_REG_DBG_RPT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3664_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3664)
    #define HD21MAC_CFG_3664_DTOP_P1_REG_DBG_GP0_TST Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3664_DTOP_P1_REG_ALIGN_DEAD_PROT Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3664_DTOP_P1_REG_SELF_TEST_SMALL_DE_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3664_DTOP_P1_REG_SELF_TEST_CH_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_3664_DTOP_P1_REG_DBG_TST Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3668_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3668)
    #define HD21MAC_CFG_3668_DTOP_P1_RESERVED_1A_15 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3668_DTOP_P1_REG_FIFO_EMPTY_STS_CH2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3668_DTOP_P1_REG_FIFO_FULL_STS_CH2 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3668_DTOP_P1_REG_EMPTY_IRQ_STS_CH2 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3668_DTOP_P1_REG_FULL_IRQ_STS_CH2 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3668_DTOP_P1_REG_FIFO_RPTR_STS_CH2 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_3668_DTOP_P1_REG_FIFO_WPTR_STS_CH2 Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21MAC_CFG_3668_DTOP_P1_REG_FULL_IRQ_CLR_CH2 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3668_DTOP_P1_REG_EMPTY_IRQ_CLR_CH2 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3668_DTOP_P1_RESERVED_1A_00 Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_366C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x366C)
    #define HD21MAC_CFG_366C_DTOP_P1_REG_DVI_RESERVED_5 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3670_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3670)
    #define HD21MAC_CFG_3670_DTOP_P1_REG_VCLK_UNSTABLE_TIMES Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21MAC_CFG_3670_DTOP_P1_REG_VCLK_STABLE_TIMES Fld(7,0,AC_MSKB0)//[6:0]
#define HD21MAC_CFG_3674_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3674)
    #define HD21MAC_CFG_3674_DTOP_P1_REG_DVI_RESERVED_12 Fld(7,9,AC_MSKB1)//[15:9]
    #define HD21MAC_CFG_3674_DTOP_P1_REG_REF_CNT_NUM_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3674_DTOP_P1_REG_VCLK_CHK_RANGE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3678_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3678)
    #define HD21MAC_CFG_3678_DTOP_P1_REG_VS_RPT_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3678_DTOP_P1_REG_VS_RPT_INTERVAL Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21MAC_CFG_3678_DTOP_P1_REG_FORCE_DEC_MD Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_3678_DTOP_P1_REG_DVI_RESERVED_6 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3678_DTOP_P1_REG_VFILTER_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3678_DTOP_P1_REG_TIMER_V_DIV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_367C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x367C)
    #define HD21MAC_CFG_367C_DTOP_P1_REG_CK_STABLE_NUM Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_367C_DTOP_P1_REG_CK_UNSTABLE_NUM Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_367C_DTOP_P1_REG_CK_FSM_RST Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_367C_DTOP_P1_REG_CK_FSM_PAUSE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_367C_DTOP_P1_REG_CK_RISE_IRQ_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_367C_DTOP_P1_REG_CK_FALL_IRQ_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_367C_DTOP_P1_REG_CK_STABLE_SEL_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_3680_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3680)
    #define HD21MAC_CFG_3680_DTOP_P1_REG_MANUAL_EQUALIZER_0 Fld(2,0,AC_MSKB0)//[1:0]
    #define HD21MAC_CFG_3680_DTOP_P1_REG_MANUAL_EQUALIZER_1 Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_3680_DTOP_P1_REG_MANUAL_EQUALIZER_2 Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_3680_DTOP_P1_REG_DVI_RESERVED_13 Fld(10,6,AC_MSKW10)//[15:6]
#define HD21MAC_CFG_3684_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3684)
    #define HD21MAC_CFG_3684_DTOP_P1_REG_EQ_RESERVED_0 Fld(11,5,AC_MSKW10)//[15:5]
    #define HD21MAC_CFG_3684_DTOP_P1_REG_CK_UNSTABLE_FLAG_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3684_DTOP_P1_REG_TMDS_CK_FALL_IRQ_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3684_DTOP_P1_REG_TMDS_CK_RISE_IRQ_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3684_DTOP_P1_REG_CK_STABLE_GATE_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3684_DTOP_P1_REG_VCLK_STABLE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_368C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x368C)
    #define HD21MAC_CFG_368C_DTOP_P1_REG_SW_RESET Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_368C_DTOP_P1_REG_ENABLE_AUTO_RUN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_368C_DTOP_P1_REG_DVI_RESERVED_14 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_368C_DTOP_P1_REG_DVI_RD_ONLY_RESERVED0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3698_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3698)
    #define HD21MAC_CFG_3698_DTOP_P1_REG_DVI_RD_ONLY_RESERVED1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_369C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x369C)
    #define HD21MAC_CFG_369C_DTOP_P1_REG_MHL_HW_MODE_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_369C_DTOP_P1_REG_DYNAMIC_SEQ_ALIGN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_369C_DTOP_P1_REG_RST_MHL_SEQ_CHK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_369C_DTOP_P1_REG_REF_WBDRY_RDY Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_369C_DTOP_P1_REG_MHL_PACK_PIX_MD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_369C_DTOP_P1_REG_MHL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_36A0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36A0)
    #define HD21MAC_CFG_36A0_DTOP_P1_REG_MHL_RSV Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_36A4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36A4)
    #define HD21MAC_CFG_36A4_DTOP_P1_REG_CSYNC_CFG0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_36A4_DTOP_P1_REG_DVI_RESERVED_7 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_36A8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36A8)
    #define HD21MAC_CFG_36A8_DTOP_P1_REG_CSYNC_CFG2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_36A8_DTOP_P1_REG_CSYNC_CFG1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_36AC_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36AC)
    #define HD21MAC_CFG_36AC_DTOP_P1_REG_PH_ALIGN_EVER_OV Fld(1,7,AC_MSKB0)//[7:7]
#define HD21MAC_CFG_36B0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36B0)
    #define HD21MAC_CFG_36B0_DTOP_P1_REG_DEC_HDCP_TSTBUS_SEL Fld(4,12,AC_MSKB1)//[15:12]
#define HD21MAC_CFG_36B4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36B4)
    #define HD21MAC_CFG_36B4_DTOP_P1_REG_RCV_GCP_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_36B4_DTOP_P1_REG_BCHPRTY_ERR Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_36B4_DTOP_P1_REG_BCHERR_CORRECTED Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_36B4_DTOP_P1_REG_DIS_BCHCORR Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_36B4_DTOP_P1_REG_AVMUTE_DISBCHCHK Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_36B4_DTOP_P1_REG_AVMUTE_OVERRIDE_DATA Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_36B4_DTOP_P1_REG_AVMUTE_OVERRIDE_TRIGGER Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_36B4_DTOP_P1_REG_AVMUTE_DIS Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_36B4_DTOP_P1_REG_AVMUTE_RST Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_36B8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36B8)
    #define HD21MAC_CFG_36B8_DTOP_P1_REG_DVI_RESERVED_8 Fld(10,6,AC_MSKW10)//[15:6]
    #define HD21MAC_CFG_36B8_DTOP_P1_REG_REVERSE_DEC Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_36B8_DTOP_P1_REG_REVERSE_DATA Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_36B8_DTOP_P1_REG_FRAME_CLR_AUTO Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_36BC_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36BC)
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_DE_STABLE_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_CK_STABLE_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_RESERVED Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_FSM_STATUS Fld(3,10,AC_MSKB1)//[12:10]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_EQ_CNT_STATUS Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_UNSTABLE_RST Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_LARGE_DE_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_ENV_VLD_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_ENV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_FOREVER Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_PAUSE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_36BC_DTOP_P1_REG_AUTO_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_36C0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36C0)
    #define HD21MAC_CFG_36C0_DTOP_P1_REG_AUTO_EQ_50MHZ_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_36C0_DTOP_P1_REG_AUTO_EQ_100MHZ_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_36C0_DTOP_P1_REG_AUTO_EQ_NUM Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_36C0_DTOP_P1_REG_RESERVED_DVI4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_36C4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36C4)
    #define HD21MAC_CFG_36C4_DTOP_P1_REG_DEP_FILTER_LEN Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_36C4_DTOP_P1_REG_DEP_RESERVED_1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_36C4_DTOP_P1_REG_DE_FSM_STATUS Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_36C4_DTOP_P1_REG_DEP_RESERVED_0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_36C4_DTOP_P1_REG_DEP_FSM_PAUSE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_36C4_DTOP_P1_REG_DEP_FSM_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_36C4_DTOP_P1_REG_DE_FILTER_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_36C8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36C8)
    #define HD21MAC_CFG_36C8_DTOP_P1_REG_DEP_CONTINUOUS_NUM Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_36C8_DTOP_P1_REG_DEP_CHANGE_TOL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_36C8_DTOP_P1_REG_DEP_TIMEOUT_TH Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_36C8_DTOP_P1_REG_DEP_SMALL_DE_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_36C8_DTOP_P1_REG_DEP_DE_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_36C8_DTOP_P1_REG_DEP_CH_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_36CC_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36CC)
    #define HD21MAC_CFG_36CC_DTOP_P1_REG_DE_RD_ONLY_RESERVED Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_36CC_DTOP_P1_REG_DE_PERIOD Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_36D0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36D0)
    #define HD21MAC_CFG_36D0_DTOP_P1_REG_SELF_TEST_RD_ONLY_RESERVED1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_36D4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36D4)
    #define HD21MAC_CFG_36D4_DTOP_P1_REG_STEERCTRL_CUR2 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_36D4_DTOP_P1_REG_STEERCTRL_CUR1 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_36D4_DTOP_P1_REG_STEERCTRL_CUR0 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_36D4_DTOP_P1_REG_DECSTATE_CHK Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_36E8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36E8)
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_SCMB_FLG_ERR Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_WB_TIMER_TH Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_SCMB_EN_BOTH Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_WB_SCMB_AUTO Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_ALIGN_SRC_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_KW_DLY_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_WB_RST Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_DEC2HDCP_SRC_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_WB2ALN_SRC_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_DIS_SSCP_ONLY Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_DIS_CH_INFO Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_36E8_DTOP_P1_REG_SCMB_FLG_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_36EC_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36EC)
    #define HD21MAC_CFG_36EC_DTOP_P1_REG_ADCDVI_IRQ_MASK Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_36EC_DTOP_P1_REG_ADCDVI_IRQ_STATUS_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_36EC_DTOP_P1_REG_ADCDVI_IRQ_STATUS_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_36EC_DTOP_P1_REG_ADCDVI_IRQ_STATUS_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_36EC_DTOP_P1_REG_ADCDVI_IRQ_STATUS_4 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_36EC_DTOP_P1_REG_ADCDVI_IRQ_STATUS_3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_36EC_DTOP_P1_REG_ADCDVI_IRQ_STATUS_2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_36EC_DTOP_P1_REG_ADCDVI_IRQ_STATUS_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_36EC_DTOP_P1_REG_ADCDVI_IRQ_STATUS_0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_36F0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36F0)
    #define HD21MAC_CFG_36F0_DTOP_P1_REG_ADCDVI_IRQ_CLR_7 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_36F0_DTOP_P1_REG_ADCDVI_IRQ_CLR_6 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_36F0_DTOP_P1_REG_ADCDVI_IRQ_CLR_5 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_36F0_DTOP_P1_REG_ADCDVI_IRQ_CLR_4 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_36F0_DTOP_P1_REG_ADCDVI_IRQ_CLR_3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_36F0_DTOP_P1_REG_ADCDVI_IRQ_CLR_2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_36F0_DTOP_P1_REG_ADCDVI_IRQ_CLR_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_36F0_DTOP_P1_REG_ADCDVI_IRQ_CLR_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_36F0_DTOP_P1_REG_ADCDVI_IRQ_FORCE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_36F4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36F4)
    #define HD21MAC_CFG_36F4_DTOP_P1_REG_ADCDVI_IRQ_CLR_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_36F8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x36F8)
    #define HD21MAC_CFG_36F8_DTOP_P1_REG_MAC_RST Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_3700_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3700)
    #define HD21MAC_CFG_3700_DTOP_P1_REG_SW_CLR_ERR_CNT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3700_DTOP_P1_REG_SW_PROBE_ADR Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3700_DTOP_P1_REG_CHANNEL_SWAP Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3700_DTOP_P1_REG_PIX_SWAP Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3700_DTOP_P1_REG_FORCE_HDMIDET_OFF Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3700_DTOP_P1_REG_SW_PROBE_ON Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3700_DTOP_P1_REG_LOG_TYP Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3700_DTOP_P1_REG_HDMI20_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3700_DTOP_P1_REG_SW_HDE_ON Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3700_DTOP_P1_REG_FSM_ERR_CLEAR Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3704_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3704)
    #define HD21MAC_CFG_3704_DTOP_P1_REG_SW_HDE_LENGTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3708_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3708)
    #define HD21MAC_CFG_3708_DTOP_P1_REG_LFSR_SEED_CH0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_370C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x370C)
    #define HD21MAC_CFG_370C_DTOP_P1_REG_LFSR_SEED_CH1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3710_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3710)
    #define HD21MAC_CFG_3710_DTOP_P1_REG_LFSR_SEED_CH2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3714_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3714)
    #define HD21MAC_CFG_3714_DTOP_P1_REG_LOG_ERRNO Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3718_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3718)
    #define HD21MAC_CFG_3718_DTOP_P1_REG_LOG_HLOC Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_371C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x371C)
    #define HD21MAC_CFG_371C_DTOP_P1_REG_LOG_VLOC Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3720_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3720)
    #define HD21MAC_CFG_3720_DTOP_P1_REG_FSM_ERRCNT_MSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3724_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3724)
    #define HD21MAC_CFG_3724_DTOP_P1_REG_FSM_ERRCNT_LSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3728_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3728)
    #define HD21MAC_CFG_3728_DTOP_P1_REG_ERR_WADR_MSB Fld(6,0,AC_MSKB0)//[5:0]
    #define HD21MAC_CFG_3728_DTOP_P1_REG_ERRLOG_BIST_FAIL_MSB Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3728_DTOP_P1_REG_FSM_ERR_FLAG_MSB Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_372C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x372C)
    #define HD21MAC_CFG_372C_DTOP_P1_REG_ERR_WADR_LSB Fld(6,0,AC_MSKB0)//[5:0]
    #define HD21MAC_CFG_372C_DTOP_P1_REG_ERRLOG_BIST_FAIL_LSB Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_372C_DTOP_P1_REG_FSM_ERR_FLAG_LSB Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_3730_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3730)
    #define HD21MAC_CFG_3730_DTOP_P1_REG_ERR_HLOC_MSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3734_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3734)
    #define HD21MAC_CFG_3734_DTOP_P1_REG_ERR_HLOC_LSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3738_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3738)
    #define HD21MAC_CFG_3738_DTOP_P1_REG_ERR_VLOC_MSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_373C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x373C)
    #define HD21MAC_CFG_373C_DTOP_P1_REG_ERR_VLOC_LSB Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3740_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3740)
    #define HD21MAC_CFG_3740_DTOP_P1_REG_TMDS_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3740_DTOP_P1_REG_DATA_SWAP Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3740_DTOP_P1_REG_ERR_NOT_INC_WBNG Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3740_DTOP_P1_REG_ERR_STATUS_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3740_DTOP_P1_REG_ERR_STATUS_LD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3740_DTOP_P1_REG_ERR_CHANNEL_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3744_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3744)
    #define HD21MAC_CFG_3744_DTOP_P1_REG_SCV_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3744_DTOP_P1_REG_TERC4_CNT Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3748_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3748)
    #define HD21MAC_CFG_3748_DTOP_P1_REG_UNSCMB_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3748_DTOP_P1_REG_DIS_DC_BALANCE_COUNT Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3748_DTOP_P1_REG_DIS_SCDC_ERRCNT_CLR Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3748_DTOP_P1_REG_DEC_ERROR_CH2 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3748_DTOP_P1_REG_DEC_ERROR_CH1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3748_DTOP_P1_REG_DEC_ERROR_CH0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3748_DTOP_P1_REG_DEC_ERR_CLR_CH2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3748_DTOP_P1_REG_DEC_ERR_CLR_CH1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3748_DTOP_P1_REG_DEC_ERR_CLR_CH0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_374C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x374C)
    #define HD21MAC_CFG_374C_DTOP_P1_REG_ERRCNT_MAX_LEVEL_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_374C_DTOP_P1_REG_TMDS_CNT_RANGE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3750_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3750)
    #define HD21MAC_CFG_3750_DTOP_P1_REG_ERRCNT_MAX_LEVEL_OV Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3760_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3760)
    #define HD21MAC_CFG_3760_DTOP_P1_REG_TST_BUS_RPT1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3760_DTOP_P1_REG_DEC20_TST_BUS_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3764_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3764)
    #define HD21MAC_CFG_3764_DTOP_P1_REG_TST_BUS_RPT0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3768_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3768)
    #define HD21MAC_CFG_3768_DTOP_P1_REG_ERRLOG_MSB_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_376C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x376C)
    #define HD21MAC_CFG_376C_DTOP_P1_REG_ERRLOG_MSB_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3770_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3770)
    #define HD21MAC_CFG_3770_DTOP_P1_REG_ERRLOG_MSB_2 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3774_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3774)
    #define HD21MAC_CFG_3774_DTOP_P1_REG_ERRLOG_LSB_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3778_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3778)
    #define HD21MAC_CFG_3778_DTOP_P1_REG_ERRLOG_LSB_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_377C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x377C)
    #define HD21MAC_CFG_377C_DTOP_P1_REG_LFSR_NUM Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_377C_DTOP_P1_REG_ERRLOG_LSB_2 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3780_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3780)
    #define HD21MAC_CFG_3780_DTOP_P1_REG_LFSR_RR_MD Fld(2,9,AC_MSKB1)//[10:9]
    #define HD21MAC_CFG_3780_DTOP_P1_REG_MHL30_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3780_DTOP_P1_REG_CP_STM_ID Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_3780_DTOP_P1_REG_CP_S_BIT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3780_DTOP_P1_REG_CP_VLD Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3780_DTOP_P1_REG_CP_UPDATE_FRZE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3780_DTOP_P1_REG_LFSR_OFF Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3784_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3784)
    #define HD21MAC_CFG_3784_DTOP_P1_REG_MHL30_SM_ERR_CHK_BUS1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3788_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3788)
    #define HD21MAC_CFG_3788_DTOP_P1_REG_MHL30_SM_ERR_CHK_BUS0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_378C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x378C)
    #define HD21MAC_CFG_378C_DTOP_P1_REG_STATE_CUR Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_378C_DTOP_P1_REG_STATE_NXT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_378C_DTOP_P1_REG_STATE_NXT2 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_378C_DTOP_P1_REG_SM_RR_MUST_EQ_4 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_378C_DTOP_P1_REG_SM_PL_LIMIT_OFF Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_378C_DTOP_P1_REG_MHL30_SM_IDLE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_378C_DTOP_P1_REG_CLR_ERR_CHK Fld(1,0,AC_MSKB0)//[0:0]

    //Page HDMI21_MAC_19
#define HD21MAC_CFG_3790_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3790)
    #define HD21MAC_CFG_3790_DTOP_P1_REG_HDR_EXT2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3790_DTOP_P1_REG_HDR_EXT3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3794_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3794)
    #define HD21MAC_CFG_3794_DTOP_P1_REG_HDR_EXT0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3794_DTOP_P1_REG_HDR_EXT1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3798_DTOP_P1 (HDMI2P1_MAC_BASE + 0x3798)
    #define HD21MAC_CFG_3798_DTOP_P1_REG_STM_CTR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3798_DTOP_P1_REG_STM_CTR3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_379C_DTOP_P1 (HDMI2P1_MAC_BASE + 0x379C)
    #define HD21MAC_CFG_379C_DTOP_P1_REG_STM_CTR0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_379C_DTOP_P1_REG_STM_CTR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_37A0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37A0)
    #define HD21MAC_CFG_37A0_DTOP_P1_REG_IPT_CTR6 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_37A0_DTOP_P1_REG_IPT_CTR7 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_37A4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37A4)
    #define HD21MAC_CFG_37A4_DTOP_P1_REG_IPT_CTR4 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_37A4_DTOP_P1_REG_IPT_CTR5 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_37A8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37A8)
    #define HD21MAC_CFG_37A8_DTOP_P1_REG_IPT_CTR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_37A8_DTOP_P1_REG_IPT_CTR3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_37AC_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37AC)
    #define HD21MAC_CFG_37AC_DTOP_P1_REG_IPT_CTR0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_37AC_DTOP_P1_REG_IPT_CTR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_37B0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37B0)
    #define HD21MAC_CFG_37B0_DTOP_P1_REG_CP_CRC2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_37B0_DTOP_P1_REG_CP_CRC3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_37B4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37B4)
    #define HD21MAC_CFG_37B4_DTOP_P1_REG_CP_CRC0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_37B4_DTOP_P1_REG_CP_CRC1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_37B8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37B8)
    #define HD21MAC_CFG_37B8_DTOP_P1_REG_RX_CRC_VLU1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_37BC_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37BC)
    #define HD21MAC_CFG_37BC_DTOP_P1_REG_RX_CRC_VLU0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_37C0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37C0)
    #define HD21MAC_CFG_37C0_DTOP_P1_REG_CRC_VLU_CLR Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_37C0_DTOP_P1_REG_RX_CRC_CMP_EQ Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_37C0_DTOP_P1_REG_CRC_INV_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_37C4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37C4)
    #define HD21MAC_CFG_37C4_DTOP_P1_REG_LNK2PIX_AT_CHK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_37C4_DTOP_P1_REG_MHL30_CP_AS_VLD_PL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_37C4_DTOP_P1_REG_MHL30_CTL_SWH Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_37C4_DTOP_P1_REG_MHL30_BLK_SWH Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_37C4_DTOP_P1_REG_MHL30_VDO_SWH Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_37C4_DTOP_P1_REG_MHL30_CH_02_SWH Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_37C4_DTOP_P1_REG_MHL30_VGB_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_37C4_DTOP_P1_REG_MHL30_VGB_FORCE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_37C8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37C8)
    #define HD21MAC_CFG_37C8_DTOP_P1_REG_PIX_CNT_INI Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_37C8_DTOP_P1_REG_RST_PIX_RD Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_37C8_DTOP_P1_REG_AV_LNK_FCNT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_37CC_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37CC)
    #define HD21MAC_CFG_37CC_DTOP_P1_REG_AV_LNK_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_37D0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37D0)
    #define HD21MAC_CFG_37D0_DTOP_P1_REG_AV_LNK_FIX_L Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_37D0_DTOP_P1_REG_AV_LNK_FIX_H Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_37D4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37D4)
    #define HD21MAC_CFG_37D4_DTOP_P1_REG_AV_LNK_RDM_ON Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_37D4_DTOP_P1_REG_AV_LNK_PAT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_37D4_DTOP_P1_REG_AV_LNK_DURAT Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_37D8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37D8)
    #define HD21MAC_CFG_37D8_DTOP_P1_REG_AV_LNK_DURAT_DIS Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_37D8_DTOP_P1_REG_AV_LNK_BIST_VGB_AS_DAT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_37D8_DTOP_P1_REG_AV_LNK_LFSR_INI_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_37D8_DTOP_P1_REG_AV_LNK_STAT_STOP Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_37D8_DTOP_P1_REG_AV_LNK_STAT_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_37D8_DTOP_P1_REG_AV_LNK_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_37DC_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37DC)
    #define HD21MAC_CFG_37DC_DTOP_P1_REG_MHL3_DUMY0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_37E0_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37E0)
    #define HD21MAC_CFG_37E0_DTOP_P1_REG_ERROR_THRESHOLD_CH0 Fld(15,0,AC_MSKW10)//[14:0]
#define HD21MAC_CFG_37E4_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37E4)
    #define HD21MAC_CFG_37E4_DTOP_P1_REG_ERROR_THRESHOLD_CH1 Fld(15,0,AC_MSKW10)//[14:0]
#define HD21MAC_CFG_37E8_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37E8)
    #define HD21MAC_CFG_37E8_DTOP_P1_REG_ERROR_THRESHOLD_CH2 Fld(15,0,AC_MSKW10)//[14:0]
#define HD21MAC_CFG_37EC_DTOP_P1 (HDMI2P1_MAC_BASE + 0x37EC)
    #define HD21MAC_CFG_37EC_DTOP_P1_REG_EN_EQ_ISLAND_DETECT_AND Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_37EC_DTOP_P1_REG_EN_EQ_ISLAND_DETECT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_37EC_DTOP_P1_REG_POST_EQ_ERROR_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3800_RSV_P1 (HDMI2P1_MAC_BASE + 0x3800)
    #define HD21MAC_CFG_3800_RSV_P1_REG_NO_INPUT_RST_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3800_RSV_P1_REG_POWERSAVE_FSM_PAUSE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3800_RSV_P1_REG_POWERSAVE_FSM_RST Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3800_RSV_P1_REG_POWER_SAVING_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3804_RSV_P1 (HDMI2P1_MAC_BASE + 0x3804)
    #define HD21MAC_CFG_3804_RSV_P1_REG_POWER_SAVING_MODE_BUF Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3804_RSV_P1_REG_CLK_FLAG_STABLE_FORCE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3804_RSV_P1_REG_LEARN_STABLE_FORCE Fld(1,5,AC_MSKB0)//[5:5]
#define HD21MAC_CFG_3808_RSV_P1 (HDMI2P1_MAC_BASE + 0x3808)
    #define HD21MAC_CFG_3808_RSV_P1_REG_V_FRONT_ON_NUM Fld(12,4,AC_MSKW10)//[15:4]
    #define HD21MAC_CFG_3808_RSV_P1_REG_V_BACK_OFF_NUM Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_380C_RSV_P1 (HDMI2P1_MAC_BASE + 0x380C)
    #define HD21MAC_CFG_380C_RSV_P1_REG_PS_VDEP_CONTINUOUS_NUM Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_380C_RSV_P1_REG_PS_VDE_UNSTABLE_THD Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3810_RSV_P1 (HDMI2P1_MAC_BASE + 0x3810)
    #define HD21MAC_CFG_3810_RSV_P1_REG_PS_DEP_CONTINUOUS_NUM Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_3810_RSV_P1_REG_PS_VDEP_CHANGE_TOL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_3810_RSV_P1_REG_PS_DEP_CHANGE_TOL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_3810_RSV_P1_REG_PS_UNSTABLE_THD Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3814_RSV_P1 (HDMI2P1_MAC_BASE + 0x3814)
    #define HD21MAC_CFG_3814_RSV_P1_REG_DIS_PS_EQ_DONE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3814_RSV_P1_REG_VDE_PS_FSM_STATUS Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_3814_RSV_P1_REG_VDE_STABLE_IRQ_CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3814_RSV_P1_REG_PS_VDEP_FSM_PAUSE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3814_RSV_P1_REG_PS_VDEP_FSM_RST Fld(1,5,AC_MSKB0)//[5:5]
#define HD21MAC_CFG_3818_RSV_P1 (HDMI2P1_MAC_BASE + 0x3818)
    #define HD21MAC_CFG_3818_RSV_P1_REG_DE_PS_FSM_STATUS Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_3818_RSV_P1_REG_DE_STABLE_IRQ_CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3818_RSV_P1_REG_PS_DEP_CH_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_3818_RSV_P1_REG_PS_BIG_DE_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3818_RSV_P1_REG_PS_DEP_FSM_PAUSE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3818_RSV_P1_REG_PS_DEP_FSM_RST Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3818_RSV_P1_REG_PS_DEP_TIMEOUT_TH Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_381C_RSV_P1 (HDMI2P1_MAC_BASE + 0x381C)
    #define HD21MAC_CFG_381C_RSV_P1_REG_VDE_PERIOD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3820_RSV_P1 (HDMI2P1_MAC_BASE + 0x3820)
    #define HD21MAC_CFG_3820_RSV_P1_REG_DE_PERIOD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3828_RSV_P1 (HDMI2P1_MAC_BASE + 0x3828)
    #define HD21MAC_CFG_3828_RSV_P1_REG_SEL_ISLAND_LEARN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3828_RSV_P1_REG_SEL_HDMI_LEARN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3828_RSV_P1_REG_SEL_CTL3_LEARN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3828_RSV_P1_REG_SEL_HSYNC_LEARN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3828_RSV_P1_REG_SEL_VSYNC_LEARN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3828_RSV_P1_REG_CYCL_NON_SAVING Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3828_RSV_P1_REG_STAYIN_SAVING Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_382C_RSV_P1 (HDMI2P1_MAC_BASE + 0x382C)
    #define HD21MAC_CFG_382C_RSV_P1_REG_OVRIDE_SAVINGON_FOR_DEC Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3830_RSV_P1 (HDMI2P1_MAC_BASE + 0x3830)
    #define HD21MAC_CFG_3830_RSV_P1_REG_VDE_BACK_END Fld(12,4,AC_MSKW10)//[15:4]
    #define HD21MAC_CFG_3830_RSV_P1_REG_VDE_FRONT_START Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3834_RSV_P1 (HDMI2P1_MAC_BASE + 0x3834)
    #define HD21MAC_CFG_3834_RSV_P1_REG_V_DEC_DEPEND_CH2_OFF_NUM Fld(12,4,AC_MSKW10)//[15:4]
    #define HD21MAC_CFG_3834_RSV_P1_REG_V_DEC_DEPEND_CH2_ON_NUM Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_383C_RSV_P1 (HDMI2P1_MAC_BASE + 0x383C)
    #define HD21MAC_CFG_383C_RSV_P1_REG_PS_REASEVED_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3840_RSV_P1 (HDMI2P1_MAC_BASE + 0x3840)
    #define HD21MAC_CFG_3840_RSV_P1_REG_POWER_TEST_BUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3844_RSV_P1 (HDMI2P1_MAC_BASE + 0x3844)
    #define HD21MAC_CFG_3844_RSV_P1_REG_POWER_TEST_BUS_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3848_RSV_P1 (HDMI2P1_MAC_BASE + 0x3848)
    #define HD21MAC_CFG_3848_RSV_P1_REG_WAIT_CLOCK_STATE Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3848_RSV_P1_REG_WAIT_TO_STATE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3848_RSV_P1_REG_SOFT_STATE Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3848_RSV_P1_REG_SAVING_ON_STATE Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_384C_RSV_P1 (HDMI2P1_MAC_BASE + 0x384C)
    #define HD21MAC_CFG_384C_RSV_P1_REG_PS_READ_ONLY_RESERVED_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3850_RSV_P1 (HDMI2P1_MAC_BASE + 0x3850)
    #define HD21MAC_CFG_3850_RSV_P1_REG_PS_READ_ONLY_RESERVED_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3854_RSV_P1 (HDMI2P1_MAC_BASE + 0x3854)
    #define HD21MAC_CFG_3854_RSV_P1_REG_PS_READ_ONLY_RESERVED_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3858_RSV_P1 (HDMI2P1_MAC_BASE + 0x3858)
    #define HD21MAC_CFG_3858_RSV_P1_REG_PS_READ_ONLY_RESERVED_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_385C_RSV_P1 (HDMI2P1_MAC_BASE + 0x385C)
    #define HD21MAC_CFG_385C_RSV_P1_REG_PS_REASEVED_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3860_RSV_P1 (HDMI2P1_MAC_BASE + 0x3860)
    #define HD21MAC_CFG_3860_RSV_P1_REG_PS_REASEVED_4 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3864_RSV_P1 (HDMI2P1_MAC_BASE + 0x3864)
    #define HD21MAC_CFG_3864_RSV_P1_REG_PS_REASEVED_5 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3868_RSV_P1 (HDMI2P1_MAC_BASE + 0x3868)
    #define HD21MAC_CFG_3868_RSV_P1_REG_PS_REASEVED_6 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_386C_RSV_P1 (HDMI2P1_MAC_BASE + 0x386C)
    #define HD21MAC_CFG_386C_RSV_P1_REG_PS_REASEVED_7 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3870_RSV_P1 (HDMI2P1_MAC_BASE + 0x3870)
    #define HD21MAC_CFG_3870_RSV_P1_REG_PS_REASEVED_8 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3874_RSV_P1 (HDMI2P1_MAC_BASE + 0x3874)
    #define HD21MAC_CFG_3874_RSV_P1_REG_PS_REASEVED_9 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3878_RSV_P1 (HDMI2P1_MAC_BASE + 0x3878)
    #define HD21MAC_CFG_3878_RSV_P1_REG_PS_REASEVED_A Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_387C_RSV_P1 (HDMI2P1_MAC_BASE + 0x387C)
    #define HD21MAC_CFG_387C_RSV_P1_REG_PS_REASEVED_B Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C04_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C04)
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_VBI_PKT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_HBR_PKT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_GM_PKT Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_DSD_PKT Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_ACP_PKT Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_ISRC1_PKT Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_ISRC2_PKT Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_NULL_PKT Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_VS_PKT Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_ACR_PKT Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_ASAMPLE_PKT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_GCP_PKT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_AVI_PKT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_SPD_PKT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_AUI_PKT Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3C04_PKT1_P1_REG_MPEG_PKT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3C08_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C08)
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_RSV_PKT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_HDR_PKT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_ASP_LAYOUT Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_VCLK_STABLE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_CTS_FIFO_OVF Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_CTS_FIFO_UDF Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_CTS_FIFO_FULL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_CTS_FIFO_EMPTY Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_VCLK_BIG_CHG Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_CTSN_OV_RANGE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_PIX_DE_CNT_DIFF Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_FLAT_ASMP_RCVD Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_AFIFO34_FULL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_AFIFO34_EMPTY Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_AFIFO12_FULL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3C08_PKT1_P1_REG_AFIFO12_EMPTY Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3C0C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C0C)
    #define HD21MAC_CFG_3C0C_PKT1_P1_REG_HDMI_PKT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C10_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C10)
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_ADJUST_WR_DISABLE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_PKT_VALID_ARB_ERR Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_PKT_VALID_ERR Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_SHORT_ISLAND_ERR Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_ASP_PRSNT_BIT_ERR Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_AFIFO12_OVER Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_AFIFO12_UNDER Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_DC_FIFO_UDF Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_DC_FIFO_OVF Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_AS_PBIT_ERR Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_ASAMPLE_ERR Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_UNSUPPKT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_CHECKSUM_ERR Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_BCHPRTY_ERR Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3C10_PKT1_P1_REG_BCHERR_CORRECTED Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3C14_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C14)
    #define HD21MAC_CFG_3C14_PKT1_P1_REG_DIS_PKTS_0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C14_PKT1_P1_REG_CTS_FIFO_BYPASS Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3C14_PKT1_P1_REG_RESET_CTS_FIFO Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3C14_PKT1_P1_REG_DIS_BCHCHK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3C14_PKT1_P1_REG_DIS_CHKSUM Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3C14_PKT1_P1_REG_EN_USPPKT Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3C14_PKT1_P1_REG_DIS_BCHCORR Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3C18_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C18)
    #define HD21MAC_CFG_3C18_PKT1_P1_REG_VIDEO_BLANK_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3C18_PKT1_P1_REG_GCP_OUT_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3C18_PKT1_P1_REG_EN_AVMUTE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3C18_PKT1_P1_REG_VMUTEBLANK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3C18_PKT1_P1_REG_MHL3_HBR_HDR1_CHK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3C18_PKT1_P1_REG_MHL3_HBR_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3C18_PKT1_P1_REG_EN_DST Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3C18_PKT1_P1_REG_EN_HBR Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3C18_PKT1_P1_REG_DIS_PKTS_1 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_3C1C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C1C)
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_UPDATE_LMT_CTSN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_EN_CTSN_FILTER Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_GMP_OUT_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_GMP_OUT_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_MANUAL_VS_POL Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_VS_POL_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_CD_ZERO_UPDATE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_WP_AUTO_ADJUST Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_MANUAL_AP_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_MANUAL_ADJUST_PHASE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_DIS_NO_GCP_QUIT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_MANUAL_COLOR_DEPTH Fld(2,3,AC_MSKB0)//[4:3]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_EN_DF_ADJUST Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_AUTO_RST_DC_FIFO Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3C1C_PKT1_P1_REG_EN_DEEP_COLOR Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3C20_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C20)
    #define HD21MAC_CFG_3C20_PKT1_P1_REG_RESERVED1 Fld(6,10,AC_MSKB1)//[15:10]
    #define HD21MAC_CFG_3C20_PKT1_P1_REG_DC_ENG_REPLACE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3C20_PKT1_P1_REG_MHL_LINK_MODE_MUST_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3C20_PKT1_P1_REG_MHL_LINK_MODE_MUST_SW Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3C20_PKT1_P1_REG_MHL_LINK_MODE_MUST_SW_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3C20_PKT1_P1_REG_RCV_GCP_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3C20_PKT1_P1_REG_FORCE_YCBCR_BLACK Fld(2,3,AC_MSKB0)//[4:3]
    #define HD21MAC_CFG_3C20_PKT1_P1_REG_INT_CLR_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3C20_PKT1_P1_REG_CTSN_OUT2REG_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3C24_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C24)
    #define HD21MAC_CFG_3C24_PKT1_P1_REG_N_LMT_1 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_3C24_PKT1_P1_REG_CTS_LMT_1 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_3C24_PKT1_P1_REG_HDMI_TMC Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C28_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C28)
    #define HD21MAC_CFG_3C28_PKT1_P1_REG_CTS_LMT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C2C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C2C)
    #define HD21MAC_CFG_3C2C_PKT1_P1_REG_N_LMT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C30_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C30)
    #define HD21MAC_CFG_3C30_PKT1_P1_REG_VLD_N_RANGE Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C30_PKT1_P1_REG_VLD_CTS_RANGE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C34_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C34)
    #define HD21MAC_CFG_3C34_PKT1_P1_REG_CMPVAL50 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C38_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C38)
    #define HD21MAC_CFG_3C38_PKT1_P1_REG_CMPVAL100 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C3C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C3C)
    #define HD21MAC_CFG_3C3C_PKT1_P1_REG_CMPVAL200 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C40_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C40)
    #define HD21MAC_CFG_3C40_PKT1_P1_REG_PKT_TYPE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C44_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C44)
    #define HD21MAC_CFG_3C44_PKT1_P1_REG_AUPLL_LOCK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3C44_PKT1_P1_REG_FIN Fld(2,13,AC_MSKB1)//[14:13]
    #define HD21MAC_CFG_3C44_PKT1_P1_REG_CNT_VAL Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_3C48_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C48)
    #define HD21MAC_CFG_3C48_PKT1_P1_REG_CTS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C4C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C4C)
    #define HD21MAC_CFG_3C4C_PKT1_P1_REG_N_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C50_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C50)
    #define HD21MAC_CFG_3C50_PKT1_P1_REG_N_1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_3C50_PKT1_P1_REG_CTS_1 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3C54_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C54)
    #define HD21MAC_CFG_3C54_PKT1_P1_REG_GCONTROL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3C58_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C58)
    #define HD21MAC_CFG_3C58_PKT1_P1_REG_ACP_HDR1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C5C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C5C)
    #define HD21MAC_CFG_3C5C_PKT1_P1_REG_ACP_PB1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C5C_PKT1_P1_REG_ACP_PB0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C60_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C60)
    #define HD21MAC_CFG_3C60_PKT1_P1_REG_ACP_PB3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C60_PKT1_P1_REG_ACP_PB2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C64_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C64)
    #define HD21MAC_CFG_3C64_PKT1_P1_REG_ACP_PB5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C64_PKT1_P1_REG_ACP_PB4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C68_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C68)
    #define HD21MAC_CFG_3C68_PKT1_P1_REG_ACP_PB7 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C68_PKT1_P1_REG_ACP_PB6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C6C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C6C)
    #define HD21MAC_CFG_3C6C_PKT1_P1_REG_ACP_PB9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C6C_PKT1_P1_REG_ACP_PB8 Fld(8,0,AC_FULLB0)//[7:0]

    //Page HDMI21_MAC_20
#define HD21MAC_CFG_3C70_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C70)
    #define HD21MAC_CFG_3C70_PKT1_P1_REG_ACP_PB11 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C70_PKT1_P1_REG_ACP_PB10 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C74_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C74)
    #define HD21MAC_CFG_3C74_PKT1_P1_REG_ACP_PB13 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C74_PKT1_P1_REG_ACP_PB12 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C78_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C78)
    #define HD21MAC_CFG_3C78_PKT1_P1_REG_ACP_PB15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C78_PKT1_P1_REG_ACP_PB14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C7C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C7C)
    #define HD21MAC_CFG_3C7C_PKT1_P1_REG_GBD_HDR2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C7C_PKT1_P1_REG_ISRC1_HDR1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C80_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C80)
    #define HD21MAC_CFG_3C80_PKT1_P1_REG_ISRC_PB1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C80_PKT1_P1_REG_ISRC_PB0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C84_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C84)
    #define HD21MAC_CFG_3C84_PKT1_P1_REG_ISRC_PB3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C84_PKT1_P1_REG_ISRC_PB2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C88_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C88)
    #define HD21MAC_CFG_3C88_PKT1_P1_REG_ISRC_PB5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C88_PKT1_P1_REG_ISRC_PB4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C8C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C8C)
    #define HD21MAC_CFG_3C8C_PKT1_P1_REG_ISRC_PB7 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C8C_PKT1_P1_REG_ISRC_PB6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C90_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C90)
    #define HD21MAC_CFG_3C90_PKT1_P1_REG_ISRC_PB9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C90_PKT1_P1_REG_ISRC_PB8 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C94_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C94)
    #define HD21MAC_CFG_3C94_PKT1_P1_REG_ISRC_PB11 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C94_PKT1_P1_REG_ISRC_PB10 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C98_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C98)
    #define HD21MAC_CFG_3C98_PKT1_P1_REG_ISRC_PB13 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C98_PKT1_P1_REG_ISRC_PB12 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3C9C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3C9C)
    #define HD21MAC_CFG_3C9C_PKT1_P1_REG_ISRC_PB15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3C9C_PKT1_P1_REG_ISRC_PB14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CA0_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CA0)
    #define HD21MAC_CFG_3CA0_PKT1_P1_REG_ISRC_PB17 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CA0_PKT1_P1_REG_ISRC_PB16 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CA4_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CA4)
    #define HD21MAC_CFG_3CA4_PKT1_P1_REG_ISRC_PB19 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CA4_PKT1_P1_REG_ISRC_PB18 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CA8_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CA8)
    #define HD21MAC_CFG_3CA8_PKT1_P1_REG_ISRC_PB21 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CA8_PKT1_P1_REG_ISRC_PB20 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CAC_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CAC)
    #define HD21MAC_CFG_3CAC_PKT1_P1_REG_ISRC_PB23 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CAC_PKT1_P1_REG_ISRC_PB22 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CB0_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CB0)
    #define HD21MAC_CFG_3CB0_PKT1_P1_REG_ISRC_PB25 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CB0_PKT1_P1_REG_ISRC_PB24 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CB4_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CB4)
    #define HD21MAC_CFG_3CB4_PKT1_P1_REG_ISRC_PB27 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CB4_PKT1_P1_REG_ISRC_PB26 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CB8_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CB8)
    #define HD21MAC_CFG_3CB8_PKT1_P1_REG_ISRC_PB29 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CB8_PKT1_P1_REG_ISRC_PB28 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CBC_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CBC)
    #define HD21MAC_CFG_3CBC_PKT1_P1_REG_ISRC_PB31 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CBC_PKT1_P1_REG_ISRC_PB30 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CC0_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CC0)
    #define HD21MAC_CFG_3CC0_PKT1_P1_REG_VS_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CC0_PKT1_P1_REG_VS_HDR0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CC4_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CC4)
    #define HD21MAC_CFG_3CC4_PKT1_P1_REG_VS_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CC8_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CC8)
    #define HD21MAC_CFG_3CC8_PKT1_P1_REG_VS_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CC8_PKT1_P1_REG_VS_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CCC_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CCC)
    #define HD21MAC_CFG_3CCC_PKT1_P1_REG_VS_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CCC_PKT1_P1_REG_VS_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CD0_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CD0)
    #define HD21MAC_CFG_3CD0_PKT1_P1_REG_VS_IF6 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CD0_PKT1_P1_REG_VS_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CD4_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CD4)
    #define HD21MAC_CFG_3CD4_PKT1_P1_REG_VS_IF8 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CD4_PKT1_P1_REG_VS_IF7 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CD8_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CD8)
    #define HD21MAC_CFG_3CD8_PKT1_P1_REG_VS_IF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CD8_PKT1_P1_REG_VS_IF9 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CDC_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CDC)
    #define HD21MAC_CFG_3CDC_PKT1_P1_REG_VS_IF12 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CDC_PKT1_P1_REG_VS_IF11 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CE0_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CE0)
    #define HD21MAC_CFG_3CE0_PKT1_P1_REG_VS_IF14 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CE0_PKT1_P1_REG_VS_IF13 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CE4_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CE4)
    #define HD21MAC_CFG_3CE4_PKT1_P1_REG_VS_IF16 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CE4_PKT1_P1_REG_VS_IF15 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CE8_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CE8)
    #define HD21MAC_CFG_3CE8_PKT1_P1_REG_VS_IF18 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CE8_PKT1_P1_REG_VS_IF17 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CEC_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CEC)
    #define HD21MAC_CFG_3CEC_PKT1_P1_REG_VS_IF20 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CEC_PKT1_P1_REG_VS_IF19 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CF0_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CF0)
    #define HD21MAC_CFG_3CF0_PKT1_P1_REG_VS_IF22 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CF0_PKT1_P1_REG_VS_IF21 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CF4_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CF4)
    #define HD21MAC_CFG_3CF4_PKT1_P1_REG_VS_IF24 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CF4_PKT1_P1_REG_VS_IF23 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CF8_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CF8)
    #define HD21MAC_CFG_3CF8_PKT1_P1_REG_VS_IF26 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CF8_PKT1_P1_REG_VS_IF25 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3CFC_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3CFC)
    #define HD21MAC_CFG_3CFC_PKT1_P1_REG_VS_IF28 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3CFC_PKT1_P1_REG_VS_IF27 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D00_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D00)
    #define HD21MAC_CFG_3D00_PKT1_P1_REG_AVI_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D00_PKT1_P1_REG_AVI_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D04_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D04)
    #define HD21MAC_CFG_3D04_PKT1_P1_REG_AVI_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D04_PKT1_P1_REG_AVI_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D08_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D08)
    #define HD21MAC_CFG_3D08_PKT1_P1_REG_AVI_IF6 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D08_PKT1_P1_REG_AVI_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D0C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D0C)
    #define HD21MAC_CFG_3D0C_PKT1_P1_REG_AVI_IF8 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D0C_PKT1_P1_REG_AVI_IF7 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D10_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D10)
    #define HD21MAC_CFG_3D10_PKT1_P1_REG_AVI_IF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D10_PKT1_P1_REG_AVI_IF9 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D14_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D14)
    #define HD21MAC_CFG_3D14_PKT1_P1_REG_AVI_IF12 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D14_PKT1_P1_REG_AVI_IF11 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D18_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D18)
    #define HD21MAC_CFG_3D18_PKT1_P1_REG_AVI_VERSION Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D18_PKT1_P1_REG_AVI_IF13 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D1C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D1C)
    #define HD21MAC_CFG_3D1C_PKT1_P1_REG_SPD_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D1C_PKT1_P1_REG_SPD_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D20_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D20)
    #define HD21MAC_CFG_3D20_PKT1_P1_REG_SPD_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D20_PKT1_P1_REG_SPD_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D24_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D24)
    #define HD21MAC_CFG_3D24_PKT1_P1_REG_SPD_IF6 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D24_PKT1_P1_REG_SPD_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D28_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D28)
    #define HD21MAC_CFG_3D28_PKT1_P1_REG_SPD_IF8 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D28_PKT1_P1_REG_SPD_IF7 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D2C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D2C)
    #define HD21MAC_CFG_3D2C_PKT1_P1_REG_SPD_IF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D2C_PKT1_P1_REG_SPD_IF9 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D30_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D30)
    #define HD21MAC_CFG_3D30_PKT1_P1_REG_SPD_IF12 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D30_PKT1_P1_REG_SPD_IF11 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D34_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D34)
    #define HD21MAC_CFG_3D34_PKT1_P1_REG_SPD_IF14 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D34_PKT1_P1_REG_SPD_IF13 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D38_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D38)
    #define HD21MAC_CFG_3D38_PKT1_P1_REG_SPD_IF16 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D38_PKT1_P1_REG_SPD_IF15 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D3C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D3C)
    #define HD21MAC_CFG_3D3C_PKT1_P1_REG_SPD_IF18 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D3C_PKT1_P1_REG_SPD_IF17 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D40_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D40)
    #define HD21MAC_CFG_3D40_PKT1_P1_REG_SPD_IF20 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D40_PKT1_P1_REG_SPD_IF19 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D44_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D44)
    #define HD21MAC_CFG_3D44_PKT1_P1_REG_SPD_IF22 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D44_PKT1_P1_REG_SPD_IF21 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D48_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D48)
    #define HD21MAC_CFG_3D48_PKT1_P1_REG_SPD_IF24 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D48_PKT1_P1_REG_SPD_IF23 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D4C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D4C)
    #define HD21MAC_CFG_3D4C_PKT1_P1_REG_SPD_IF25 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D50_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D50)
    #define HD21MAC_CFG_3D50_PKT1_P1_REG_AU_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D50_PKT1_P1_REG_AU_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D54_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D54)
    #define HD21MAC_CFG_3D54_PKT1_P1_REG_AU_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D54_PKT1_P1_REG_AU_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D58_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D58)
    #define HD21MAC_CFG_3D58_PKT1_P1_REG_AU_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D5C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D5C)
    #define HD21MAC_CFG_3D5C_PKT1_P1_REG_MPEG_IF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D5C_PKT1_P1_REG_MPEG_IF1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D60_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D60)
    #define HD21MAC_CFG_3D60_PKT1_P1_REG_MPEG_IF4 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D60_PKT1_P1_REG_MPEG_IF3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D64_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D64)
    #define HD21MAC_CFG_3D64_PKT1_P1_REG_MPEG_IF5 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D68_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D68)
    #define HD21MAC_CFG_3D68_PKT1_P1_REG_HDMI_CS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3D6C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D6C)
    #define HD21MAC_CFG_3D6C_PKT1_P1_REG_HDMI_CS_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3D70_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D70)
    #define HD21MAC_CFG_3D70_PKT1_P1_REG_HDMI_CS_2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3D74_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D74)
    #define HD21MAC_CFG_3D74_PKT1_P1_REG_ODD_CK_GATE_OFFSET Fld(13,0,AC_MSKW10)//[12:0]
    #define HD21MAC_CFG_3D74_PKT1_P1_REG_ODD_CK_GATE_OV Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3D74_PKT1_P1_REG_ODD_CK_GATE_OVE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3D74_PKT1_P1_REG_EHTT_GATE_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_3D78_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D78)
    #define HD21MAC_CFG_3D78_PKT1_P1_REG_DC_REP_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3D78_PKT1_P1_REG_ODD_CK_GATE_SFT_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3D78_PKT1_P1_REG_4X_CK_GATE_OVE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3D78_PKT1_P1_REG_4X_CK_GATE_OV Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3D78_PKT1_P1_REG_4X_CK_GATE_OFFSET Fld(4,12,AC_MSKB1)//[15:12]
#define HD21MAC_CFG_3D7C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D7C)
    #define HD21MAC_CFG_3D7C_PKT1_P1_REG_PKT_RST Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D7C_PKT1_P1_REG_PKT_VALID_DELAY_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3D7C_PKT1_P1_REG_FRAME_RP_VAL Fld(3,3,AC_MSKB0)//[5:3]
    #define HD21MAC_CFG_3D7C_PKT1_P1_REG_HPLL_LOCK_RAW Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3D7C_PKT1_P1_REG_AT_MULT_PP_CHK_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3D7C_PKT1_P1_REG_HPLL_LOCK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3D80_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D80)
    #define HD21MAC_CFG_3D80_PKT1_P1_REG_INT_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3D84_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D84)
    #define HD21MAC_CFG_3D84_PKT1_P1_REG_INT_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3D88_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D88)
    #define HD21MAC_CFG_3D88_PKT1_P1_REG_INT_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3D8C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D8C)
    #define HD21MAC_CFG_3D8C_PKT1_P1_REG_INT_CLR Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3D90_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D90)
    #define HD21MAC_CFG_3D90_PKT1_P1_REG_HDMI_AU_FIFO_MUTE_EN Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3D90_PKT1_P1_REG_FRAME_RP_MODE Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_3D90_PKT1_P1_REG_AUDIO_MODE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3D94_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D94)
    #define HD21MAC_CFG_3D94_PKT1_P1_REG_PIX_DE_CNT Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_3D98_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D98)
    #define HD21MAC_CFG_3D98_PKT1_P1_REG_HPLL_TEST_IN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3D9C_PKT1_P1 (HDMI2P1_MAC_BASE + 0x3D9C)
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_420_AVG_OV_VALUE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_420_AVG_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_420_TO_SC_OV_VALUE Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_420_TO_SC_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_422_TO_SC_OV_VALUE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_422_TO_SC_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_CTS_N_CAL_8P_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_CTS_DIV2_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_CTS_N_CAL_8P_MODE Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_3D9C_PKT1_P1_REG_HPLL_PDIV_B Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_3E08_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E08)
    #define HD21MAC_CFG_3E08_PKT2_P1_REG_420_TRANSFORM_FSM_RST Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_3E30_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E30)
    #define HD21MAC_CFG_3E30_PKT2_P1_REG_VLD_N_RANGE_EXT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3E30_PKT2_P1_REG_VLD_CTS_RANGE_EXT Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3E80_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E80)
    #define HD21MAC_CFG_3E80_PKT2_P1_REG_SD_CONTROL2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3E80_PKT2_P1_REG_SD_CONTROL1 Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_3E80_PKT2_P1_REG_HDMI_SD_PIX_CLK_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3E80_PKT2_P1_REG_FORCE_422TO444 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3E80_PKT2_P1_REG_BYPASS_422TO444 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3E84_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E84)
    #define HD21MAC_CFG_3E84_PKT2_P1_REG_SD_RESERVED2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3E88_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E88)
    #define HD21MAC_CFG_3E88_PKT2_P1_REG_CTS_FRAC_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3E8C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E8C)
    #define HD21MAC_CFG_3E8C_PKT2_P1_REG_N_FRAC_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3E90_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E90)
    #define HD21MAC_CFG_3E90_PKT2_P1_REG_CTSN_LK_TH Fld(3,0,AC_MSKB0)//[2:0]
    #define HD21MAC_CFG_3E90_PKT2_P1_REG_CTSN_LK_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3E90_PKT2_P1_REG_PKT_FAIL_RST_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3E90_PKT2_P1_REG_PKT_FAIL_RST_OVE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3E90_PKT2_P1_REG_PKT_8P_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3E90_PKT2_P1_REG_PKT_CYC_CNT_NOT_FULL_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3E90_PKT2_P1_REG_HDMI_RX2TX_PKT_DATA_PIPE_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_3E90_PKT2_P1_REG_HDMI_AUD_STAT_ORI Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_3E94_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E94)
    #define HD21MAC_CFG_3E94_PKT2_P1_REG_RD_POINT Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_3E94_PKT2_P1_REG_WR_POINT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_3E94_PKT2_P1_REG_SD_RESERVED3 Fld(6,2,AC_MSKB0)//[7:2]
    #define HD21MAC_CFG_3E94_PKT2_P1_REG_AVG_FIFO_EMPTY_FLAG Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3E94_PKT2_P1_REG_AVG_FIFO_FULL_FLAG Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3E98_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E98)
    #define HD21MAC_CFG_3E98_PKT2_P1_REG_HDMI2_IRQ_MASK Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_3E98_PKT2_P1_REG_HDMI2_INT_STATUS Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3E9C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3E9C)
    #define HD21MAC_CFG_3E9C_PKT2_P1_REG_HDMI2_IRQ_CLEAR7 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3E9C_PKT2_P1_REG_HDMI2_IRQ_CLEAR6 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3E9C_PKT2_P1_REG_HDMI2_IRQ_CLEAR5 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3E9C_PKT2_P1_REG_HDMI2_IRQ_CLEAR4 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3E9C_PKT2_P1_REG_HDMI2_IRQ_CLEAR3 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3E9C_PKT2_P1_REG_HDMI2_IRQ_CLEAR2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3E9C_PKT2_P1_REG_HDMI2_IRQ_CLEAR1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3E9C_PKT2_P1_REG_HDMI2_IRQ_CLEAR0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3E9C_PKT2_P1_REG_HDMI2_IRQ_FORCE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3EA0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EA0)
    #define HD21MAC_CFG_3EA0_PKT2_P1_REG_PKT_VALID_ERR_MASK Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_3EBC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EBC)
    #define HD21MAC_CFG_3EBC_PKT2_P1_REG_PIX_REP_HTOTAL_CNT_HOLD Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_3EC0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EC0)
    #define HD21MAC_CFG_3EC0_PKT2_P1_REG_PIX_VTOTAL_CNT_HOLD Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_3EC4_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EC4)
    #define HD21MAC_CFG_3EC4_PKT2_P1_REG_PIX_VDE_CNT_HOLD Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_3EC8_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EC8)
    #define HD21MAC_CFG_3EC8_PKT2_P1_REG_PIX_HTOTAL_CNT_HOLD Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_3ECC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3ECC)
    #define HD21MAC_CFG_3ECC_PKT2_P1_REG_PIXCLK_CMPVAL50 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3ED0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3ED0)
    #define HD21MAC_CFG_3ED0_PKT2_P1_REG_PIXCLK_CMPVAL100 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3ED4_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3ED4)
    #define HD21MAC_CFG_3ED4_PKT2_P1_REG_PIXCLK_CMPVAL200 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3ED8_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3ED8)
    #define HD21MAC_CFG_3ED8_PKT2_P1_REG_PIXCLK_FIN Fld(2,13,AC_MSKB1)//[14:13]
    #define HD21MAC_CFG_3ED8_PKT2_P1_REG_PIXCLK_CNT_VAL Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_3EDC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EDC)
    #define HD21MAC_CFG_3EDC_PKT2_P1_REG_RX2TX_PKT_BYPASS_RD_PTR Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3EDC_PKT2_P1_REG_RX2TX_PKT_BYPASS_WR_PTR Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_3EE0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EE0)
    #define HD21MAC_CFG_3EE0_PKT2_P1_REG_RX2TX_PKT_BYPASS_FIFO_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3EE0_PKT2_P1_REG_RX2TX_PKT_BYPASS_FIFO_RD_PTR_INIT Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21MAC_CFG_3EE0_PKT2_P1_REG_RX2TX_PKT_BYPASS_FIFO_WR_PTR_INIT Fld(6,0,AC_MSKB0)//[5:0]
#define HD21MAC_CFG_3EE4_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EE4)
    #define HD21MAC_CFG_3EE4_PKT2_P1_REG_RX2TX_PKT_BYPASS_FIFO_FULL_DIFF Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3EE8_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EE8)
    #define HD21MAC_CFG_3EE8_PKT2_P1_REG_DC_FIFO_READ_SHIFT_PROT Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_3EE8_PKT2_P1_REG_DC_FIFO_WRITE_SHIFT_PROT Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_3EE8_PKT2_P1_REG_DC_FIFO_EMPTY_DIFF Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_3EE8_PKT2_P1_REG_DC_FIFO_FULL_DIFF Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3EFC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3EFC)
    #define HD21MAC_CFG_3EFC_PKT2_P1_REG_AVI_IF14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3F00_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F00)
    #define HD21MAC_CFG_3F00_PKT2_P1_REG_VBI_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F00_PKT2_P1_REG_VBI_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F04_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F04)
    #define HD21MAC_CFG_3F04_PKT2_P1_REG_VBI_PB01 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F04_PKT2_P1_REG_VBI_PB00 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F08_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F08)
    #define HD21MAC_CFG_3F08_PKT2_P1_REG_VBI_PB03 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F08_PKT2_P1_REG_VBI_PB02 Fld(8,8,AC_FULLB1)//[15:8]

    //Page HDMI21_MAC_21
#define HD21MAC_CFG_3F0C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F0C)
    #define HD21MAC_CFG_3F0C_PKT2_P1_REG_VBI_PB05 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F0C_PKT2_P1_REG_VBI_PB04 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F10_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F10)
    #define HD21MAC_CFG_3F10_PKT2_P1_REG_VBI_PB07 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F10_PKT2_P1_REG_VBI_PB06 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F14_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F14)
    #define HD21MAC_CFG_3F14_PKT2_P1_REG_VBI_PB09 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F14_PKT2_P1_REG_VBI_PB08 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F18_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F18)
    #define HD21MAC_CFG_3F18_PKT2_P1_REG_VBI_PB11 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F18_PKT2_P1_REG_VBI_PB10 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F1C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F1C)
    #define HD21MAC_CFG_3F1C_PKT2_P1_REG_VBI_PB13 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F1C_PKT2_P1_REG_VBI_PB12 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F20_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F20)
    #define HD21MAC_CFG_3F20_PKT2_P1_REG_VBI_PB15 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F20_PKT2_P1_REG_VBI_PB14 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F24_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F24)
    #define HD21MAC_CFG_3F24_PKT2_P1_REG_VBI_PB17 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F24_PKT2_P1_REG_VBI_PB16 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F28_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F28)
    #define HD21MAC_CFG_3F28_PKT2_P1_REG_VBI_PB19 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F28_PKT2_P1_REG_VBI_PB18 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F2C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F2C)
    #define HD21MAC_CFG_3F2C_PKT2_P1_REG_VBI_PB21 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F2C_PKT2_P1_REG_VBI_PB20 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F30_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F30)
    #define HD21MAC_CFG_3F30_PKT2_P1_REG_VBI_PB23 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F30_PKT2_P1_REG_VBI_PB22 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F34_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F34)
    #define HD21MAC_CFG_3F34_PKT2_P1_REG_VBI_PB25 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F34_PKT2_P1_REG_VBI_PB24 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F38_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F38)
    #define HD21MAC_CFG_3F38_PKT2_P1_REG_VBI_PB27 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F38_PKT2_P1_REG_VBI_PB26 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F3C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F3C)
    #define HD21MAC_CFG_3F3C_PKT2_P1_REG_VBI_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3F40_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F40)
    #define HD21MAC_CFG_3F40_PKT2_P1_REG_AUDIO_AVMUTE_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_3F40_PKT2_P1_REG_AUDIO_BLOCK_START_MUX_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3F40_PKT2_P1_REG_AUDIO_8CH_CH_STATUS_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_3F40_PKT2_P1_REG_MHL_CBUS_AUDIO_AVMUTE_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3F40_PKT2_P1_REG_CK_LOSE_AVMUTE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_3F40_PKT2_P1_REG_HDMI_AVMUTE_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_3F40_PKT2_P1_REG_PORT_SEL_DIFF_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3F40_PKT2_P1_REG_PKT_PORT_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_3F40_PKT2_P1_REG_DVI_PORT_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_3F44_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F44)
    #define HD21MAC_CFG_3F44_PKT2_P1_SW_RST Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_3F48_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F48)
    #define HD21MAC_CFG_3F48_PKT2_P1_REG_TMUX_SEL2 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3F4C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F4C)
    #define HD21MAC_CFG_3F4C_PKT2_P1_REG_DELAY_1T_ALIGNMENT_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3F4C_PKT2_P1_REG_DITH_SEED_RST Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3F4C_PKT2_P1_REG_DVI_ROUND_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3F4C_PKT2_P1_REG_DITH_SEL_DVI Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3F50_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F50)
    #define HD21MAC_CFG_3F50_PKT2_P1_REG_AVG_BYPASS Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3F50_PKT2_P1_REG_AVG_MODE Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_3F50_PKT2_P1_REG_AVG_CTRL_CASE Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_3F54_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F54)
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_HDMI_420_SW_MODE Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_VSYNC_CLEAR_MODE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_FINAL_LINE_MODE Fld(2,9,AC_MSKB1)//[10:9]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_420_TRANSFORM_PIX_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_CBCR_SWAP Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_HDMI_20_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_420_TRANSFORM_BYPASS Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_420_TRANSFORM_FSM_RST Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_420_TRANSFORM_VDE_POL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_420_TRANSFORM_HSYNC_POL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_420_TRANSFORM_VSYNC_POL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_3F54_PKT2_P1_REG_420_TRANSFORM_SWAP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_3F58_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F58)
    #define HD21MAC_CFG_3F58_PKT2_P1_REG_FIFO_WR_PTR Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_3F5C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F5C)
    #define HD21MAC_CFG_3F5C_PKT2_P1_REG_FIFO_RD_PTR Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_3F60_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F60)
    #define HD21MAC_CFG_3F60_PKT2_P1_REG_HTOTAL_STABLE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3F60_PKT2_P1_REG_HTOTAL Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_3F64_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F64)
    #define HD21MAC_CFG_3F64_PKT2_P1_REG_DE_TOTAL_STABLE Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_3F64_PKT2_P1_REG_DE_TOTAL Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_3F68_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F68)
    #define HD21MAC_CFG_3F68_PKT2_P1_REG_RX2TX_PKT_BYPASS_FIFO_BIST_FAIL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_3F68_PKT2_P1_REG_420_TRANS_BIST_FAIL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_3F68_PKT2_P1_REG_420_TRANSFORM_FSM_STATE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_3F6C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F6C)
    #define HD21MAC_CFG_3F6C_PKT2_P1_REG_AUD_HEAD_VALID_SEL Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_3F70_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F70)
    #define HD21MAC_CFG_3F70_PKT2_P1_REG_AUD_HEAD_RSV_PKT_TYPE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_3F78_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F78)
    #define HD21MAC_CFG_3F78_PKT2_P1_REG_VBI_PKT_TYPE Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F78_PKT2_P1_REG_DISCHKSUM_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_3F78_PKT2_P1_REG_DIS_RSV_PKT Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_3F78_PKT2_P1_REG_DIS_HDR_PKT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_3F78_PKT2_P1_REG_DIS_VBI_PKT Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_3F7C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F7C)
    #define HD21MAC_CFG_3F7C_PKT2_P1_REG_RSV_PKT_TYPE Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F7C_PKT2_P1_REG_HDR_PKT_TYPE Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F80_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F80)
    #define HD21MAC_CFG_3F80_PKT2_P1_REG_HDR_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F80_PKT2_P1_REG_HDR_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F84_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F84)
    #define HD21MAC_CFG_3F84_PKT2_P1_REG_HDR_PB01 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F84_PKT2_P1_REG_HDR_PB00 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F88_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F88)
    #define HD21MAC_CFG_3F88_PKT2_P1_REG_HDR_PB03 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F88_PKT2_P1_REG_HDR_PB02 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F8C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F8C)
    #define HD21MAC_CFG_3F8C_PKT2_P1_REG_HDR_PB05 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F8C_PKT2_P1_REG_HDR_PB04 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F90_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F90)
    #define HD21MAC_CFG_3F90_PKT2_P1_REG_HDR_PB07 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F90_PKT2_P1_REG_HDR_PB06 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F94_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F94)
    #define HD21MAC_CFG_3F94_PKT2_P1_REG_HDR_PB09 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F94_PKT2_P1_REG_HDR_PB08 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F98_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F98)
    #define HD21MAC_CFG_3F98_PKT2_P1_REG_HDR_PB11 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F98_PKT2_P1_REG_HDR_PB10 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3F9C_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3F9C)
    #define HD21MAC_CFG_3F9C_PKT2_P1_REG_HDR_PB13 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3F9C_PKT2_P1_REG_HDR_PB12 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FA0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FA0)
    #define HD21MAC_CFG_3FA0_PKT2_P1_REG_HDR_PB15 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FA0_PKT2_P1_REG_HDR_PB14 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FA4_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FA4)
    #define HD21MAC_CFG_3FA4_PKT2_P1_REG_HDR_PB17 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FA4_PKT2_P1_REG_HDR_PB16 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FA8_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FA8)
    #define HD21MAC_CFG_3FA8_PKT2_P1_REG_HDR_PB19 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FA8_PKT2_P1_REG_HDR_PB18 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FAC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FAC)
    #define HD21MAC_CFG_3FAC_PKT2_P1_REG_HDR_PB21 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FAC_PKT2_P1_REG_HDR_PB20 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FB0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FB0)
    #define HD21MAC_CFG_3FB0_PKT2_P1_REG_HDR_PB23 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FB0_PKT2_P1_REG_HDR_PB22 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FB4_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FB4)
    #define HD21MAC_CFG_3FB4_PKT2_P1_REG_HDR_PB25 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FB4_PKT2_P1_REG_HDR_PB24 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FB8_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FB8)
    #define HD21MAC_CFG_3FB8_PKT2_P1_REG_HDR_PB27 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FB8_PKT2_P1_REG_HDR_PB26 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FBC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FBC)
    #define HD21MAC_CFG_3FBC_PKT2_P1_REG_HDR_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_3FC0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FC0)
    #define HD21MAC_CFG_3FC0_PKT2_P1_REG_RSV_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FC0_PKT2_P1_REG_RSV_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FC4_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FC4)
    #define HD21MAC_CFG_3FC4_PKT2_P1_REG_RSV_PB01 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FC4_PKT2_P1_REG_RSV_PB00 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FC8_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FC8)
    #define HD21MAC_CFG_3FC8_PKT2_P1_REG_RSV_PB03 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FC8_PKT2_P1_REG_RSV_PB02 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FCC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FCC)
    #define HD21MAC_CFG_3FCC_PKT2_P1_REG_RSV_PB05 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FCC_PKT2_P1_REG_RSV_PB04 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FD0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FD0)
    #define HD21MAC_CFG_3FD0_PKT2_P1_REG_RSV_PB07 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FD0_PKT2_P1_REG_RSV_PB06 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FD4_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FD4)
    #define HD21MAC_CFG_3FD4_PKT2_P1_REG_RSV_PB09 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FD4_PKT2_P1_REG_RSV_PB08 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FD8_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FD8)
    #define HD21MAC_CFG_3FD8_PKT2_P1_REG_RSV_PB11 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FD8_PKT2_P1_REG_RSV_PB10 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FDC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FDC)
    #define HD21MAC_CFG_3FDC_PKT2_P1_REG_RSV_PB13 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FDC_PKT2_P1_REG_RSV_PB12 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FE0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FE0)
    #define HD21MAC_CFG_3FE0_PKT2_P1_REG_RSV_PB15 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FE0_PKT2_P1_REG_RSV_PB14 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FE4_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FE4)
    #define HD21MAC_CFG_3FE4_PKT2_P1_REG_RSV_PB17 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FE4_PKT2_P1_REG_RSV_PB16 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FE8_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FE8)
    #define HD21MAC_CFG_3FE8_PKT2_P1_REG_RSV_PB19 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FE8_PKT2_P1_REG_RSV_PB18 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FEC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FEC)
    #define HD21MAC_CFG_3FEC_PKT2_P1_REG_RSV_PB21 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FEC_PKT2_P1_REG_RSV_PB20 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FF0_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FF0)
    #define HD21MAC_CFG_3FF0_PKT2_P1_REG_RSV_PB23 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FF0_PKT2_P1_REG_RSV_PB22 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FF4_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FF4)
    #define HD21MAC_CFG_3FF4_PKT2_P1_REG_RSV_PB25 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FF4_PKT2_P1_REG_RSV_PB24 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FF8_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FF8)
    #define HD21MAC_CFG_3FF8_PKT2_P1_REG_RSV_PB27 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_3FF8_PKT2_P1_REG_RSV_PB26 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_3FFC_PKT2_P1 (HDMI2P1_MAC_BASE + 0x3FFC)
    #define HD21MAC_CFG_3FFC_PKT2_P1_REG_RSV_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4000_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4000)
    #define HD21MAC_CFG_4000_PKT3_P1_REG_VSIF_HDR2_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4000_PKT3_P1_REG_VSIF_HDR1_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4004_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4004)
    #define HD21MAC_CFG_4004_PKT3_P1_REG_VSIF_PB01_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4004_PKT3_P1_REG_VSIF_PB00_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4008_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4008)
    #define HD21MAC_CFG_4008_PKT3_P1_REG_VSIF_PB03_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4008_PKT3_P1_REG_VSIF_PB02_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_400C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x400C)
    #define HD21MAC_CFG_400C_PKT3_P1_REG_VSIF_PB05_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_400C_PKT3_P1_REG_VSIF_PB04_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4010_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4010)
    #define HD21MAC_CFG_4010_PKT3_P1_REG_VSIF_PB07_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4010_PKT3_P1_REG_VSIF_PB06_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4014_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4014)
    #define HD21MAC_CFG_4014_PKT3_P1_REG_VSIF_PB09_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4014_PKT3_P1_REG_VSIF_PB08_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4018_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4018)
    #define HD21MAC_CFG_4018_PKT3_P1_REG_VSIF_PB11_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4018_PKT3_P1_REG_VSIF_PB10_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_401C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x401C)
    #define HD21MAC_CFG_401C_PKT3_P1_REG_VSIF_PB13_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_401C_PKT3_P1_REG_VSIF_PB12_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4020_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4020)
    #define HD21MAC_CFG_4020_PKT3_P1_REG_VSIF_PB15_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4020_PKT3_P1_REG_VSIF_PB14_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4024_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4024)
    #define HD21MAC_CFG_4024_PKT3_P1_REG_VSIF_PB17_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4024_PKT3_P1_REG_VSIF_PB16_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4028_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4028)
    #define HD21MAC_CFG_4028_PKT3_P1_REG_VSIF_PB19_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4028_PKT3_P1_REG_VSIF_PB18_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_402C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x402C)
    #define HD21MAC_CFG_402C_PKT3_P1_REG_VSIF_PB21_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_402C_PKT3_P1_REG_VSIF_PB20_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4030_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4030)
    #define HD21MAC_CFG_4030_PKT3_P1_REG_VSIF_PB23_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4030_PKT3_P1_REG_VSIF_PB22_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4034_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4034)
    #define HD21MAC_CFG_4034_PKT3_P1_REG_VSIF_PB25_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4034_PKT3_P1_REG_VSIF_PB24_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4038_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4038)
    #define HD21MAC_CFG_4038_PKT3_P1_REG_VSIF_PB27_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4038_PKT3_P1_REG_VSIF_PB26_0 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_403C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x403C)
    #define HD21MAC_CFG_403C_PKT3_P1_REG_VSIF_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4040_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4040)
    #define HD21MAC_CFG_4040_PKT3_P1_REG_VSIF_HDR2_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4040_PKT3_P1_REG_VSIF_HDR1_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4044_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4044)
    #define HD21MAC_CFG_4044_PKT3_P1_REG_VSIF_PB01_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4044_PKT3_P1_REG_VSIF_PB00_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4048_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4048)
    #define HD21MAC_CFG_4048_PKT3_P1_REG_VSIF_PB03_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4048_PKT3_P1_REG_VSIF_PB02_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_404C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x404C)
    #define HD21MAC_CFG_404C_PKT3_P1_REG_VSIF_PB05_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_404C_PKT3_P1_REG_VSIF_PB04_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4050_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4050)
    #define HD21MAC_CFG_4050_PKT3_P1_REG_VSIF_PB07_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4050_PKT3_P1_REG_VSIF_PB06_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4054_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4054)
    #define HD21MAC_CFG_4054_PKT3_P1_REG_VSIF_PB09_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4054_PKT3_P1_REG_VSIF_PB08_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4058_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4058)
    #define HD21MAC_CFG_4058_PKT3_P1_REG_VSIF_PB11_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4058_PKT3_P1_REG_VSIF_PB10_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_405C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x405C)
    #define HD21MAC_CFG_405C_PKT3_P1_REG_VSIF_PB13_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_405C_PKT3_P1_REG_VSIF_PB12_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4060_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4060)
    #define HD21MAC_CFG_4060_PKT3_P1_REG_VSIF_PB15_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4060_PKT3_P1_REG_VSIF_PB14_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4064_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4064)
    #define HD21MAC_CFG_4064_PKT3_P1_REG_VSIF_PB17_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4064_PKT3_P1_REG_VSIF_PB16_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4068_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4068)
    #define HD21MAC_CFG_4068_PKT3_P1_REG_VSIF_PB19_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4068_PKT3_P1_REG_VSIF_PB18_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_406C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x406C)
    #define HD21MAC_CFG_406C_PKT3_P1_REG_VSIF_PB21_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_406C_PKT3_P1_REG_VSIF_PB20_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4070_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4070)
    #define HD21MAC_CFG_4070_PKT3_P1_REG_VSIF_PB23_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4070_PKT3_P1_REG_VSIF_PB22_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4074_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4074)
    #define HD21MAC_CFG_4074_PKT3_P1_REG_VSIF_PB25_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4074_PKT3_P1_REG_VSIF_PB24_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4078_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4078)
    #define HD21MAC_CFG_4078_PKT3_P1_REG_VSIF_PB27_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4078_PKT3_P1_REG_VSIF_PB26_1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_407C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x407C)
    #define HD21MAC_CFG_407C_PKT3_P1_REG_VSIF_INT_EN Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_407C_PKT3_P1_REG_VSIF_PKT_TYPE Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4080_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4080)
    #define HD21MAC_CFG_4080_PKT3_P1_REG_VSIF_HDR2_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4080_PKT3_P1_REG_VSIF_HDR1_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4084_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4084)
    #define HD21MAC_CFG_4084_PKT3_P1_REG_VSIF_PB01_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4084_PKT3_P1_REG_VSIF_PB00_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4088_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4088)
    #define HD21MAC_CFG_4088_PKT3_P1_REG_VSIF_PB03_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4088_PKT3_P1_REG_VSIF_PB02_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_408C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x408C)
    #define HD21MAC_CFG_408C_PKT3_P1_REG_VSIF_PB05_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_408C_PKT3_P1_REG_VSIF_PB04_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4090_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4090)
    #define HD21MAC_CFG_4090_PKT3_P1_REG_VSIF_PB07_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4090_PKT3_P1_REG_VSIF_PB06_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4094_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4094)
    #define HD21MAC_CFG_4094_PKT3_P1_REG_VSIF_PB09_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4094_PKT3_P1_REG_VSIF_PB08_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4098_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4098)
    #define HD21MAC_CFG_4098_PKT3_P1_REG_VSIF_PB11_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4098_PKT3_P1_REG_VSIF_PB10_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_409C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x409C)
    #define HD21MAC_CFG_409C_PKT3_P1_REG_VSIF_PB13_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_409C_PKT3_P1_REG_VSIF_PB12_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40A0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40A0)
    #define HD21MAC_CFG_40A0_PKT3_P1_REG_VSIF_PB15_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40A0_PKT3_P1_REG_VSIF_PB14_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40A4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40A4)
    #define HD21MAC_CFG_40A4_PKT3_P1_REG_VSIF_PB17_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40A4_PKT3_P1_REG_VSIF_PB16_2 Fld(8,8,AC_FULLB1)//[15:8]

    //Page HDMI21_MAC_22
#define HD21MAC_CFG_40A8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40A8)
    #define HD21MAC_CFG_40A8_PKT3_P1_REG_VSIF_PB19_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40A8_PKT3_P1_REG_VSIF_PB18_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40AC_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40AC)
    #define HD21MAC_CFG_40AC_PKT3_P1_REG_VSIF_PB21_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40AC_PKT3_P1_REG_VSIF_PB20_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40B0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40B0)
    #define HD21MAC_CFG_40B0_PKT3_P1_REG_VSIF_PB23_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40B0_PKT3_P1_REG_VSIF_PB22_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40B4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40B4)
    #define HD21MAC_CFG_40B4_PKT3_P1_REG_VSIF_PB25_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40B4_PKT3_P1_REG_VSIF_PB24_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40B8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40B8)
    #define HD21MAC_CFG_40B8_PKT3_P1_REG_VSIF_PB27_2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40B8_PKT3_P1_REG_VSIF_PB26_2 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40BC_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40BC)
    #define HD21MAC_CFG_40BC_PKT3_P1_REG_VSIF_CNT Fld(4,0,AC_MSKB0)//[3:0]
    #define HD21MAC_CFG_40BC_PKT3_P1_REG_VSIF_NUM_INT Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_40BC_PKT3_P1_REG_NO_VSIF_FCNT Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_40BC_PKT3_P1_REG_EDR_Q_RANGE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_40BC_PKT3_P1_REG_SET_DOLBY_EDR11 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_40BC_PKT3_P1_REG_CLR_DOLBY_EDR11 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_40BC_PKT3_P1_REG_SET_DOLBY_EDR Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_40BC_PKT3_P1_REG_CLR_DOLBY_EDR Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_40C0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40C0)
    #define HD21MAC_CFG_40C0_PKT3_P1_REG_VSIF_HDR2_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40C0_PKT3_P1_REG_VSIF_HDR1_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40C4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40C4)
    #define HD21MAC_CFG_40C4_PKT3_P1_REG_VSIF_PB01_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40C4_PKT3_P1_REG_VSIF_PB00_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40C8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40C8)
    #define HD21MAC_CFG_40C8_PKT3_P1_REG_VSIF_PB03_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40C8_PKT3_P1_REG_VSIF_PB02_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40CC_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40CC)
    #define HD21MAC_CFG_40CC_PKT3_P1_REG_VSIF_PB05_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40CC_PKT3_P1_REG_VSIF_PB04_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40D0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40D0)
    #define HD21MAC_CFG_40D0_PKT3_P1_REG_VSIF_PB07_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40D0_PKT3_P1_REG_VSIF_PB06_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40D4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40D4)
    #define HD21MAC_CFG_40D4_PKT3_P1_REG_VSIF_PB09_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40D4_PKT3_P1_REG_VSIF_PB08_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40D8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40D8)
    #define HD21MAC_CFG_40D8_PKT3_P1_REG_VSIF_PB11_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40D8_PKT3_P1_REG_VSIF_PB10_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40DC_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40DC)
    #define HD21MAC_CFG_40DC_PKT3_P1_REG_VSIF_PB13_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40DC_PKT3_P1_REG_VSIF_PB12_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40E0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40E0)
    #define HD21MAC_CFG_40E0_PKT3_P1_REG_VSIF_PB15_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40E0_PKT3_P1_REG_VSIF_PB14_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40E4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40E4)
    #define HD21MAC_CFG_40E4_PKT3_P1_REG_VSIF_PB17_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40E4_PKT3_P1_REG_VSIF_PB16_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40E8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40E8)
    #define HD21MAC_CFG_40E8_PKT3_P1_REG_VSIF_PB19_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40E8_PKT3_P1_REG_VSIF_PB18_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40EC_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40EC)
    #define HD21MAC_CFG_40EC_PKT3_P1_REG_VSIF_PB21_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40EC_PKT3_P1_REG_VSIF_PB20_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40F0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40F0)
    #define HD21MAC_CFG_40F0_PKT3_P1_REG_VSIF_PB23_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40F0_PKT3_P1_REG_VSIF_PB22_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40F4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40F4)
    #define HD21MAC_CFG_40F4_PKT3_P1_REG_VSIF_PB25_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40F4_PKT3_P1_REG_VSIF_PB24_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40F8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40F8)
    #define HD21MAC_CFG_40F8_PKT3_P1_REG_VSIF_PB27_3 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_40F8_PKT3_P1_REG_VSIF_PB26_3 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_40FC_PKT3_P1 (HDMI2P1_MAC_BASE + 0x40FC)
    #define HD21MAC_CFG_40FC_PKT3_P1_REG_VSIF_VERSION Fld(7,0,AC_MSKB0)//[6:0]
    #define HD21MAC_CFG_40FC_PKT3_P1_REG_VSIF_CHG_DIS Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_40FC_PKT3_P1_REG_VSIF_CHG_CLR Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_40FC_PKT3_P1_REG_VSIF_AWS_SHIFT Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_40FC_PKT3_P1_REG_VSIF_FUL_SHIFT_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_40FC_PKT3_P1_REG_VSIF_DIS_PKT Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_40FC_PKT3_P1_REG_CLR_VSIF_CNT Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_40FC_PKT3_P1_REG_VSIF_VER2_CLR_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_40FC_PKT3_P1_REG_VDE_END_CLR_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_4100_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4100)
    #define HD21MAC_CFG_4100_PKT3_P1_REG_AM_HDR2 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4100_PKT3_P1_REG_AM_HDR1 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4104_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4104)
    #define HD21MAC_CFG_4104_PKT3_P1_REG_AM_PB01 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4104_PKT3_P1_REG_AM_PB00 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4108_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4108)
    #define HD21MAC_CFG_4108_PKT3_P1_REG_AM_PB03 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4108_PKT3_P1_REG_AM_PB02 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_410C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x410C)
    #define HD21MAC_CFG_410C_PKT3_P1_REG_AM_PB05 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_410C_PKT3_P1_REG_AM_PB04 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4110_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4110)
    #define HD21MAC_CFG_4110_PKT3_P1_REG_AM_PB07 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4110_PKT3_P1_REG_AM_PB06 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4114_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4114)
    #define HD21MAC_CFG_4114_PKT3_P1_REG_AM_PB09 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4114_PKT3_P1_REG_AM_PB08 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4118_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4118)
    #define HD21MAC_CFG_4118_PKT3_P1_REG_AM_PB11 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4118_PKT3_P1_REG_AM_PB10 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_411C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x411C)
    #define HD21MAC_CFG_411C_PKT3_P1_REG_AM_PB13 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_411C_PKT3_P1_REG_AM_PB12 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4120_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4120)
    #define HD21MAC_CFG_4120_PKT3_P1_REG_AM_PB15 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4120_PKT3_P1_REG_AM_PB14 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4124_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4124)
    #define HD21MAC_CFG_4124_PKT3_P1_REG_AM_PB17 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4124_PKT3_P1_REG_AM_PB16 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4128_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4128)
    #define HD21MAC_CFG_4128_PKT3_P1_REG_AM_PB19 Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_4128_PKT3_P1_REG_AM_PB18 Fld(8,8,AC_FULLB1)//[15:8]
#define HD21MAC_CFG_4138_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4138)
    #define HD21MAC_CFG_4138_PKT3_P1_REG_AM_PKT_TYPE Fld(6,0,AC_MSKB0)//[5:0]
    #define HD21MAC_CFG_4138_PKT3_P1_REG_DIS_AM_PKT Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_4138_PKT3_P1_REG_AUD_PKT_BPS Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_4138_PKT3_P1_REG_DSD_MS_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4138_PKT3_P1_REG_ASP_MS_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4138_PKT3_P1_REG_DSD_3D_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_4138_PKT3_P1_REG_ASP_3D_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_4138_PKT3_P1_REG_AUD_32CH_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_4138_PKT3_P1_REG_AUD_32CH_OV Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_4138_PKT3_P1_REG_AUD_3D_PRD Fld(2,14,AC_MSKB1)//[15:14]
#define HD21MAC_CFG_413C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x413C)
    #define HD21MAC_CFG_413C_PKT3_P1_REG_AM_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4140_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4140)
    #define HD21MAC_CFG_4140_PKT3_P1_REG_SUPPORT_PKT_HEADER_L Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4140_PKT3_P1_REG_SUPPORT_PKT_HEADER_H Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4144_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4144)
    #define HD21MAC_CFG_4144_PKT3_P1_REG_VSP_HDR_VERSION_DIFF_OVE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4144_PKT3_P1_REG_VSP_HDR_VERSION_DIFF_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4148_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4148)
    #define HD21MAC_CFG_4148_PKT3_P1_REG_AUDIO_IF02 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4148_PKT3_P1_REG_AUDIO_IF01 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_414C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x414C)
    #define HD21MAC_CFG_414C_PKT3_P1_REG_AUDIO_IF04 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_414C_PKT3_P1_REG_AUDIO_IF03 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4150_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4150)
    #define HD21MAC_CFG_4150_PKT3_P1_REG_AUDIO_IF06 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4150_PKT3_P1_REG_AUDIO_IF05 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4154_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4154)
    #define HD21MAC_CFG_4154_PKT3_P1_REG_AUDIO_IF08 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4154_PKT3_P1_REG_AUDIO_IF07 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4158_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4158)
    #define HD21MAC_CFG_4158_PKT3_P1_REG_AUDIO_IF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4158_PKT3_P1_REG_AUDIO_IF09 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4168_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4168)
    #define HD21MAC_CFG_4168_PKT3_P1_REG_ASP_PKT_VALID_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_4168_PKT3_P1_REG_AMP_PKT_VALID_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_4168_PKT3_P1_REG_ACR_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_4168_PKT3_P1_REG_ACP_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_416C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x416C)
    #define HD21MAC_CFG_416C_PKT3_P1_REG_GBD_PKT_VALID_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_416C_PKT3_P1_REG_EMP_PKT_VALID_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_416C_PKT3_P1_REG_AVI_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_416C_PKT3_P1_REG_AUDIF_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_4170_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4170)
    #define HD21MAC_CFG_4170_PKT3_P1_REG_ISRC2_PKT_VALID_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_4170_PKT3_P1_REG_ISRC1_PKT_VALID_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_4170_PKT3_P1_REG_HDR_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_4170_PKT3_P1_REG_GCP_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_4174_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4174)
    #define HD21MAC_CFG_4174_PKT3_P1_REG_VBI_PKT_VALID_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_4174_PKT3_P1_REG_SPD_PKT_VALID_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_4174_PKT3_P1_REG_RSV_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_4174_PKT3_P1_REG_MPEG_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_4178_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4178)
    #define HD21MAC_CFG_4178_PKT3_P1_REG_VSP_PKT_VALID_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_4178_PKT3_P1_REG_VSIF_PKT_VALID_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_417C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x417C)
    #define HD21MAC_CFG_417C_PKT3_P1_REG_HDMIRX21_RX2TX_MTW_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4180_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4180)
    #define HD21MAC_CFG_4180_PKT3_P1_REG_SRC_FIELD_INV Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_4180_PKT3_P1_REG_SRC_FIELD_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_4180_PKT3_P1_REG_SRC_DET_I_MD_DET_CONDI_EN Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_4180_PKT3_P1_REG_SRC_H_POL_OVE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_4180_PKT3_P1_REG_SRC_H_POL_OV Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_4180_PKT3_P1_REG_SRC_V_POL_OVE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4180_PKT3_P1_REG_SRC_V_POL_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4180_PKT3_P1_REG_SRC_DET_PIX_PER_CYCLE Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_4180_PKT3_P1_REG_SRC_DET_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_4184_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4184)
    #define HD21MAC_CFG_4184_PKT3_P1_REG_SRC_DET_I_MD_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_SRC_FIELD_NON_MATCH Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_HS_POL Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_VS_POL Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_TIMING_DET_STATUS_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_SC_H_POL_OVE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_SC_H_POL_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_SC_DET_PIX_PER_CYCLE Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_SC_DET_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_SRC_DET_NO_SIGNAL_OVE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4184_PKT3_P1_REG_SRC_DET_NO_SIGNAL_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4188_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4188)
    #define HD21MAC_CFG_4188_PKT3_P1_REG_TIMING_DET_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_418C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x418C)
    #define HD21MAC_CFG_418C_PKT3_P1_REG_TIMING_DET_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4190_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4190)
    #define HD21MAC_CFG_4190_PKT3_P1_REG_TIMING_DET_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4194_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4194)
    #define HD21MAC_CFG_4194_PKT3_P1_REG_TIMING_DET_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4198_PKT3_P1 (HDMI2P1_MAC_BASE + 0x4198)
    #define HD21MAC_CFG_4198_PKT3_P1_REG_TIMING_DET_HS_LENGTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_419C_PKT3_P1 (HDMI2P1_MAC_BASE + 0x419C)
    #define HD21MAC_CFG_419C_PKT3_P1_REG_TIMING_DET_VS_LENGTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_41A0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41A0)
    #define HD21MAC_CFG_41A0_PKT3_P1_REG_TIMING_DET_H_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_41A4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41A4)
    #define HD21MAC_CFG_41A4_PKT3_P1_REG_TIMING_DET_V_FRONT_PORCH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_41A8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41A8)
    #define HD21MAC_CFG_41A8_PKT3_P1_REG_TIMING_DET_IRQ_STATUS Fld(16,0,AC_FULLW10)//[15:0]
    #define HD21MAC_CFG_2BA8_PKT3_P1_REG_TIMING_DET_IRQ_HTOTAL_STABLE_STATUS Fld(1,4,AC_MSKB0)//[4:4]
#define HD21MAC_CFG_41AC_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41AC)
    #define HD21MAC_CFG_41AC_PKT3_P1_REG_TIMING_DET_IRQ_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_41B0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41B0)
    #define HD21MAC_CFG_41B0_PKT3_P1_REG_TIMING_DET_IRQ_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_41C0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41C0)
    #define HD21MAC_CFG_41C0_PKT3_P1_REG_VSIF_VID_PB2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_41C0_PKT3_P1_REG_VSIF_VID_PB1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_41C4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41C4)
    #define HD21MAC_CFG_41C4_PKT3_P1_REG_AUD_MASK_EVENT Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_41C4_PKT3_P1_REG_AUD_MASK_EVENT_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_41C4_PKT3_P1_REG_AUD_MASK_OVE Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_41C4_PKT3_P1_REG_AUD_MASK_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_41C4_PKT3_P1_REG_DIS_ALLM_TIMEOUT_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_41C4_PKT3_P1_REG_CLR_ALLM_MODE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_41C4_PKT3_P1_REG_SET_ALLM_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_41C4_PKT3_P1_REG_DIS_ALLM_VSIF_VID Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_41C4_PKT3_P1_REG_VSIF_VID_PB3 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_41C8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41C8)
    #define HD21MAC_CFG_41C8_PKT3_P1_REG_VMUTE_CONDI Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_41CC_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41CC)
    #define HD21MAC_CFG_41CC_PKT3_P1_REG_H_WIN_PARA_SEL Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_41CC_PKT3_P1_REG_H_WIN_PARA Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_41D0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41D0)
    #define HD21MAC_CFG_41D0_PKT3_P1_REG_DC_READ_PTR_START_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_41D0_PKT3_P1_REG_DC_MODE_CHANGE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_41D0_PKT3_P1_REG_DC_DE_STABLE_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_41D0_PKT3_P1_REG_HV_RPLC_CFG Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_41D4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41D4)
    #define HD21MAC_CFG_41D4_PKT3_P1_REG_TMDS_PTR_GRAY Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_41D4_PKT3_P1_REG_PIX_PTR_GRAY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_41D4_PKT3_P1_REG_TMDS_PTR_NEXT_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_41D4_PKT3_P1_REG_PIX_PTR_NEXT_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_41D8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41D8)
    #define HD21MAC_CFG_41D8_PKT3_P1_REG_PHASE_DIFF Fld(3,13,AC_MSKB1)//[15:13]
    #define HD21MAC_CFG_41D8_PKT3_P1_REG_TMDS_S Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_41DC_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41DC)
    #define HD21MAC_CFG_41DC_PKT3_P1_REG_PIX_PTR_GRAY_S1_W Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_41DC_PKT3_P1_REG_TMDS_PTR_GRAY_BUF Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_41DC_PKT3_P1_REG_TMDS_PTR_GRAY_S1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_41DC_PKT3_P1_REG_PIX_PTR_GRAY_BUF Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_41E0_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41E0)
    #define HD21MAC_CFG_41E0_PKT3_P1_REG_TMDS_PTR_A1_GRAY Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_41E0_PKT3_P1_REG_TMDS_PTR_D1_GRAY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_41E0_PKT3_P1_REG_PIX_PTR_A1_GRAY Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_41E0_PKT3_P1_REG_PIX_PTR_D1_GRAY Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_41E4_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41E4)
    #define HD21MAC_CFG_41E4_PKT3_P1_REG_TMDS_PTR_A2_GRAY Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_41E4_PKT3_P1_REG_TMDS_PTR_D2_GRAY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_41E4_PKT3_P1_REG_PIX_PTR_A2_GRAY Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_41E4_PKT3_P1_REG_PIX_PTR_D2_GRAY Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_41E8_PKT3_P1 (HDMI2P1_MAC_BASE + 0x41E8)
    #define HD21MAC_CFG_41E8_PKT3_P1_REG_TMDS_PTR_A3_GRAY Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_41E8_PKT3_P1_REG_TMDS_PTR_D3_GRAY Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_41E8_PKT3_P1_REG_PIX_PTR_A3_GRAY Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_41E8_PKT3_P1_REG_PIX_PTR_D3_GRAY Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_4200_EM_P1 (HDMI2P1_MAC_BASE + 0x4200)
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_HDR_TY3_TAG_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_HDR_TY2_TAG_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_HDR_TY1_TAG_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_HDR_DATA_SET_LENGTH_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_HDR_NEW_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_HDR_END_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_HDR_SEQUENCE_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_HDR_LAST_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_HDR_FIRST_MASK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_VENDOR_LAST_MASK Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_VENDOR_NEW_MASK Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_VENDOR_END_MASK Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_VENDOR_SEQUENCE_MASK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_VENDOR_FIRST_MASK Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_SEQUENCE_MASK Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4200_EM_P1_REG_EMP_FIRST_MASK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4204_EM_P1 (HDMI2P1_MAC_BASE + 0x4204)
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_HDR_ENABLE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_VIDEO_TIMING_DATA_SET_LENGTH_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_VIDEO_TIMING_END_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_VIDEO_TIMING_NEW_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_VIDEO_TIMING_SEQUENCE_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_VIDEO_TIMING_LAST_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_VIDEO_TIMING_FIRST_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_DSC_DATA_SET_LENGTH_MASK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_DSC_NEW_MASK Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_DSC_END_MASK Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_DSC_SEQUENCE_MASK Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_DSC_LAST_MASK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_DSC_FIRST_MASK Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4204_EM_P1_REG_EMP_HDR_TY4_TAG_MASK Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4208_EM_P1 (HDMI2P1_MAC_BASE + 0x4208)
    #define HD21MAC_CFG_4208_EM_P1_REG_EMP_SW_RESET Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_4208_EM_P1_REG_EMP_TIMER_PULSE_ENABLE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_4208_EM_P1_REG_DSC_ERROR_FILTER_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_4208_EM_P1_REG_DSC_END_LINE_PULSE_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_4208_EM_P1_REG_DSC_SEQUENCE_NUMBER_EVENT_BUF_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_4208_EM_P1_REG_DSC_INTERRUPT_EVENT_BUF_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_4208_EM_P1_REG_DSC_FIRST_EVENT_BUF_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4208_EM_P1_REG_DSC_SEQUENCE_EVENT_BUF_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4208_EM_P1_REG_DSC_LAST_EVENT_BUF_MASK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_4208_EM_P1_REG_ALL_OUTVALID Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_4208_EM_P1_REG_EMP_FVA_ENABLE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4208_EM_P1_REG_EMP_VENDOR_ENABLE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4208_EM_P1_REG_EMP_VRR_ENABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4208_EM_P1_REG_EMP_DSC_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_420C_EM_P1 (HDMI2P1_MAC_BASE + 0x420C)
    #define HD21MAC_CFG_420C_EM_P1_REG_EMP_SEQUENCE Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_420C_EM_P1_REG_ORGANIZATION_ID Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4210_EM_P1 (HDMI2P1_MAC_BASE + 0x4210)
    #define HD21MAC_CFG_4210_EM_P1_REG_DATA_SET_TAG Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4214_EM_P1 (HDMI2P1_MAC_BASE + 0x4214)
    #define HD21MAC_CFG_4214_EM_P1_REG_ORGANIZATION_ID_TAG_SELECT Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_4214_EM_P1_REG_HCATIVE_BYTE_SWAP Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_4214_EM_P1_REG_END_LINE_PULSE_SELECT_MTW Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_4214_EM_P1_REG_GENERAL_EMP_UPDATE_PULSE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_4214_EM_P1_REG_END_LINE_DECREASE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4214_EM_P1_REG_LINE_EXTENDTION Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4214_EM_P1_REG_EMP_VS_F Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4214_EM_P1_REG_EMP_VS_R Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4218_EM_P1 (HDMI2P1_MAC_BASE + 0x4218)
    #define HD21MAC_CFG_4218_EM_P1_REG_HDMI_IRQ_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_421C_EM_P1 (HDMI2P1_MAC_BASE + 0x421C)
    #define HD21MAC_CFG_421C_EM_P1_REG_HDMI_IRQ_STATUS_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4220_EM_P1 (HDMI2P1_MAC_BASE + 0x4220)
    #define HD21MAC_CFG_4220_EM_P1_REG_INT_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4224_EM_P1 (HDMI2P1_MAC_BASE + 0x4224)
    #define HD21MAC_CFG_4224_EM_P1_REG_INT_MASK_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4228_EM_P1 (HDMI2P1_MAC_BASE + 0x4228)
    #define HD21MAC_CFG_4228_EM_P1_REG_INT_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_422C_EM_P1 (HDMI2P1_MAC_BASE + 0x422C)
    #define HD21MAC_CFG_422C_EM_P1_REG_INT_FORCE_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4230_EM_P1 (HDMI2P1_MAC_BASE + 0x4230)
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR15 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR14 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR13 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR12 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR11 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR10 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR9 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR8 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR7 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR6 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR5 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR4 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4230_EM_P1_REG_HDMI2_IRQ_CLEAR0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4234_EM_P1 (HDMI2P1_MAC_BASE + 0x4234)
    #define HD21MAC_CFG_4234_EM_P1_REG_EMP_PKT_HDR_B0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4234_EM_P1_REG_M_CONST_RSTZ Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_4234_EM_P1_REG_HDMI2_IRQ_CLEAR20 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_4234_EM_P1_REG_HDMI2_IRQ_CLEAR19 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4234_EM_P1_REG_HDMI2_IRQ_CLEAR18 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4234_EM_P1_REG_HDMI2_IRQ_CLEAR17 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4234_EM_P1_REG_HDMI2_IRQ_CLEAR16 Fld(1,0,AC_MSKB0)//[0:0]

    //Page HDMI21_MAC_23
#define HD21MAC_CFG_4238_EM_P1 (HDMI2P1_MAC_BASE + 0x4238)
    #define HD21MAC_CFG_4238_EM_P1_REG_COMPRESSED_VIDEO_EMPS_ORGANIZATION_ID Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4238_EM_P1_REG_VENDOR_SPECIFIC_ORGANIZATION_ID Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_423C_EM_P1 (HDMI2P1_MAC_BASE + 0x423C)
    #define HD21MAC_CFG_423C_EM_P1_REG_VIDEO_TIMING_METADATA_ORGANIZATION_ID Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_423C_EM_P1_REG_HDR_DYNAMIC_METADATA_ORGANIZATION_ID Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4240_EM_P1 (HDMI2P1_MAC_BASE + 0x4240)
    #define HD21MAC_CFG_4240_EM_P1_REG_DSC_OTHER_DATA_SET_TAG Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4244_EM_P1 (HDMI2P1_MAC_BASE + 0x4244)
    #define HD21MAC_CFG_4244_EM_P1_REG_VIDEO_TIMING_OTHER_DATA_SET_TAG Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4248_EM_P1 (HDMI2P1_MAC_BASE + 0x4248)
    #define HD21MAC_CFG_4248_EM_P1_REG_EMP_PKT_DIFF_EN Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_424C_EM_P1 (HDMI2P1_MAC_BASE + 0x424C)
    #define HD21MAC_CFG_424C_EM_P1_REG_EMP_PKT_TYPE Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_424C_EM_P1_REG_DIS_EMP_PKT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4250_EM_P1 (HDMI2P1_MAC_BASE + 0x4250)
    #define HD21MAC_CFG_4250_EM_P1_REG_ORGANIZATION_ID_SECOND Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4250_EM_P1_REG_ORGANIZATION_ID_FIRST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4254_EM_P1 (HDMI2P1_MAC_BASE + 0x4254)
    #define HD21MAC_CFG_4254_EM_P1_REG_ORGANIZATION_ID_FORTH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4254_EM_P1_REG_ORGANIZATION_ID_THIRD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4258_EM_P1 (HDMI2P1_MAC_BASE + 0x4258)
    #define HD21MAC_CFG_4258_EM_P1_REG_DATA_SET_TAG_FIRST Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_425C_EM_P1 (HDMI2P1_MAC_BASE + 0x425C)
    #define HD21MAC_CFG_425C_EM_P1_REG_DATA_SET_TAG_SECOND Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4260_EM_P1 (HDMI2P1_MAC_BASE + 0x4260)
    #define HD21MAC_CFG_4260_EM_P1_REG_DATA_SET_TAG_THIRD Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4264_EM_P1 (HDMI2P1_MAC_BASE + 0x4264)
    #define HD21MAC_CFG_4264_EM_P1_REG_DATA_SET_TAG_FORTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4268_EM_P1 (HDMI2P1_MAC_BASE + 0x4268)
    #define HD21MAC_CFG_4268_EM_P1_REG_NO_VIDEO_TIMING_CNT Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_4268_EM_P1_REG_NO_VENDOR_CNT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_4268_EM_P1_REG_NO_HDR_CNT Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_4268_EM_P1_REG_NO_DSC_CNT Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_426C_EM_P1 (HDMI2P1_MAC_BASE + 0x426C)
    #define HD21MAC_CFG_426C_EM_P1_REG_VIDEO_TIME_OUT_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_426C_EM_P1_REG_VENDOR_TIME_OUT_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_426C_EM_P1_REG_HDR_TIME_OUT_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_426C_EM_P1_REG_DSC_TIME_OUT_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4270_EM_P1 (HDMI2P1_MAC_BASE + 0x4270)
    #define HD21MAC_CFG_4270_EM_P1_REG_EMP_TIMER_SELECT Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21MAC_CFG_4270_EM_P1_REG_END_LINE_TIMER_BASED_CNT Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_4274_EM_P1 (HDMI2P1_MAC_BASE + 0x4274)
    #define HD21MAC_CFG_4274_EM_P1_REG_DSC_PB1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4274_EM_P1_REG_DSC_PB0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4278_EM_P1 (HDMI2P1_MAC_BASE + 0x4278)
    #define HD21MAC_CFG_4278_EM_P1_REG_DSC_PB3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4278_EM_P1_REG_DSC_PB2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_427C_EM_P1 (HDMI2P1_MAC_BASE + 0x427C)
    #define HD21MAC_CFG_427C_EM_P1_REG_DSC_PB5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_427C_EM_P1_REG_DSC_PB4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4280_EM_P1 (HDMI2P1_MAC_BASE + 0x4280)
    #define HD21MAC_CFG_4280_EM_P1_REG_VENDOR_MD1_FIRST Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4280_EM_P1_REG_VENDOR_MD0_FIRST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4284_EM_P1 (HDMI2P1_MAC_BASE + 0x4284)
    #define HD21MAC_CFG_4284_EM_P1_REG_VENDOR_MD0_SECOND Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4284_EM_P1_REG_VENDOR_MD2_FIRST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4288_EM_P1 (HDMI2P1_MAC_BASE + 0x4288)
    #define HD21MAC_CFG_4288_EM_P1_REG_VENDOR_MD2_SECOND Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4288_EM_P1_REG_VENDOR_MD1_SECOND Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_428C_EM_P1 (HDMI2P1_MAC_BASE + 0x428C)
    #define HD21MAC_CFG_428C_EM_P1_REG_VENDOR_MD1_THIRD Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_428C_EM_P1_REG_VENDOR_MD0_THIRD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4290_EM_P1 (HDMI2P1_MAC_BASE + 0x4290)
    #define HD21MAC_CFG_4290_EM_P1_REG_VENDOR_MD0_FORTH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4290_EM_P1_REG_VENDOR_MD2_THIRD Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4294_EM_P1 (HDMI2P1_MAC_BASE + 0x4294)
    #define HD21MAC_CFG_4294_EM_P1_REG_VENDOR_MD2_FORTH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4294_EM_P1_REG_VENDOR_MD1_FORTH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4298_EM_P1 (HDMI2P1_MAC_BASE + 0x4298)
    #define HD21MAC_CFG_4298_EM_P1_REG_FAPA_1_ENABLE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4298_EM_P1_REG_SEQUENCE_OFF Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4298_EM_P1_REG_EMP_VIDEO_TIMING_FILTER Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_4298_EM_P1_REG_EMP_HDR_FILTER_TYPE4 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_4298_EM_P1_REG_EMP_HDR_FILTER_TYPE3 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_4298_EM_P1_REG_EMP_HDR_FILTER_TYPE2 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_4298_EM_P1_REG_EMP_HDR_FILTER_TYPE1 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4298_EM_P1_REG_EMP_HDR_FILTER_TYPE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4298_EM_P1_REG_EMP_DSC_FILTER Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4298_EM_P1_REG_EMP_VENDOR_FILTER Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_429C_EM_P1 (HDMI2P1_MAC_BASE + 0x429C)
    #define HD21MAC_CFG_429C_EM_P1_REG_END_LINE_CNT Fld(14,2,AC_MSKW10)//[15:2]
#define HD21MAC_CFG_42A0_EM_P1 (HDMI2P1_MAC_BASE + 0x42A0)
    #define HD21MAC_CFG_42A0_EM_P1_REG_BASE_VFRONT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42A0_EM_P1_REG_FVA_FACTOR_M1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_42A0_EM_P1_REG_RB Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_42A0_EM_P1_REG_M_CONST Fld(1,2,AC_MSKB0)//[2:2]
#define HD21MAC_CFG_42A4_EM_P1 (HDMI2P1_MAC_BASE + 0x42A4)
    #define HD21MAC_CFG_42A4_EM_P1_REG_BASE_REFRESH_RATE Fld(10,6,AC_MSKW10)//[15:6]
    #define HD21MAC_CFG_42A4_EM_P1_REG_EMP_DSC_ENABLE_OVE_SELECT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_42A4_EM_P1_REG_EMP_DSC_ENABLE_OVE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_42A4_EM_P1_REG_DSC_PPS_LAST_PACKET_UPDATE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_42A4_EM_P1_REG_DSC_PPS_END_LINE_UPDATE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_42A4_EM_P1_REG_DSC_END_LINE_PULSE Fld(1,1,AC_MSKB0)//[1:1]
#define HD21MAC_CFG_42A8_EM_P1 (HDMI2P1_MAC_BASE + 0x42A8)
    #define HD21MAC_CFG_42A8_EM_P1_REG_EMP_HFRONT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_42AC_EM_P1 (HDMI2P1_MAC_BASE + 0x42AC)
    #define HD21MAC_CFG_42AC_EM_P1_REG_EMP_HSYNC Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_42B0_EM_P1 (HDMI2P1_MAC_BASE + 0x42B0)
    #define HD21MAC_CFG_42B0_EM_P1_REG_EMP_HBACK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_42B4_EM_P1 (HDMI2P1_MAC_BASE + 0x42B4)
    #define HD21MAC_CFG_42B4_EM_P1_REG_EMP_HCATIVE_BYTE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_42B8_EM_P1 (HDMI2P1_MAC_BASE + 0x42B8)
    #define HD21MAC_CFG_42B8_EM_P1_REG_DSC_PB6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42BC_EM_P1 (HDMI2P1_MAC_BASE + 0x42BC)
    #define HD21MAC_CFG_42BC_EM_P1_REG_DSC_HB1_LAST Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42BC_EM_P1_REG_DSC_HB1_FIRST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42C0_EM_P1 (HDMI2P1_MAC_BASE + 0x42C0)
    #define HD21MAC_CFG_42C0_EM_P1_REG_PB27 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42C0_EM_P1_REG_PB26 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42C4_EM_P1 (HDMI2P1_MAC_BASE + 0x42C4)
    #define HD21MAC_CFG_42C4_EM_P1_REG_PB25 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42C4_EM_P1_REG_PB24 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42C8_EM_P1 (HDMI2P1_MAC_BASE + 0x42C8)
    #define HD21MAC_CFG_42C8_EM_P1_REG_PB23 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42C8_EM_P1_REG_PB22 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42CC_EM_P1 (HDMI2P1_MAC_BASE + 0x42CC)
    #define HD21MAC_CFG_42CC_EM_P1_REG_PB21 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42CC_EM_P1_REG_PB20 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42D0_EM_P1 (HDMI2P1_MAC_BASE + 0x42D0)
    #define HD21MAC_CFG_42D0_EM_P1_REG_PB19 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42D0_EM_P1_REG_PB18 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42D4_EM_P1 (HDMI2P1_MAC_BASE + 0x42D4)
    #define HD21MAC_CFG_42D4_EM_P1_REG_PB17 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42D4_EM_P1_REG_PB16 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42D8_EM_P1 (HDMI2P1_MAC_BASE + 0x42D8)
    #define HD21MAC_CFG_42D8_EM_P1_REG_PB15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42D8_EM_P1_REG_PB14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42DC_EM_P1 (HDMI2P1_MAC_BASE + 0x42DC)
    #define HD21MAC_CFG_42DC_EM_P1_REG_PB13 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42DC_EM_P1_REG_PB12 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42E0_EM_P1 (HDMI2P1_MAC_BASE + 0x42E0)
    #define HD21MAC_CFG_42E0_EM_P1_REG_PB11 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42E0_EM_P1_REG_PB10 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42E4_EM_P1 (HDMI2P1_MAC_BASE + 0x42E4)
    #define HD21MAC_CFG_42E4_EM_P1_REG_PB9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42E4_EM_P1_REG_PB8 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42E8_EM_P1 (HDMI2P1_MAC_BASE + 0x42E8)
    #define HD21MAC_CFG_42E8_EM_P1_REG_PB7 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42E8_EM_P1_REG_PB6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42EC_EM_P1 (HDMI2P1_MAC_BASE + 0x42EC)
    #define HD21MAC_CFG_42EC_EM_P1_REG_PB5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42EC_EM_P1_REG_PB4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42F0_EM_P1 (HDMI2P1_MAC_BASE + 0x42F0)
    #define HD21MAC_CFG_42F0_EM_P1_REG_PB3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42F0_EM_P1_REG_PB2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42F4_EM_P1 (HDMI2P1_MAC_BASE + 0x42F4)
    #define HD21MAC_CFG_42F4_EM_P1_REG_PB1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42F4_EM_P1_REG_PB0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42F8_EM_P1 (HDMI2P1_MAC_BASE + 0x42F8)
    #define HD21MAC_CFG_42F8_EM_P1_REG_HB0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42F8_EM_P1_REG_HB1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_42FC_EM_P1 (HDMI2P1_MAC_BASE + 0x42FC)
    #define HD21MAC_CFG_42FC_EM_P1_REG_HB2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_42FC_EM_P1_REG_PACKET_VALID Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4300_EM_P1 (HDMI2P1_MAC_BASE + 0x4300)
    #define HD21MAC_CFG_4300_EM_P1_REG_PPS_127 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4300_EM_P1_REG_PPS_126 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4304_EM_P1 (HDMI2P1_MAC_BASE + 0x4304)
    #define HD21MAC_CFG_4304_EM_P1_REG_PPS_125 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4304_EM_P1_REG_PPS_124 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4308_EM_P1 (HDMI2P1_MAC_BASE + 0x4308)
    #define HD21MAC_CFG_4308_EM_P1_REG_PPS_123 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4308_EM_P1_REG_PPS_122 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_430C_EM_P1 (HDMI2P1_MAC_BASE + 0x430C)
    #define HD21MAC_CFG_430C_EM_P1_REG_PPS_121 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_430C_EM_P1_REG_PPS_120 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4310_EM_P1 (HDMI2P1_MAC_BASE + 0x4310)
    #define HD21MAC_CFG_4310_EM_P1_REG_PPS_119 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4310_EM_P1_REG_PPS_118 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4314_EM_P1 (HDMI2P1_MAC_BASE + 0x4314)
    #define HD21MAC_CFG_4314_EM_P1_REG_PPS_117 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4314_EM_P1_REG_PPS_116 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4318_EM_P1 (HDMI2P1_MAC_BASE + 0x4318)
    #define HD21MAC_CFG_4318_EM_P1_REG_PPS_115 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4318_EM_P1_REG_PPS_114 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_431C_EM_P1 (HDMI2P1_MAC_BASE + 0x431C)
    #define HD21MAC_CFG_431C_EM_P1_REG_PPS_113 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_431C_EM_P1_REG_PPS_112 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4320_EM_P1 (HDMI2P1_MAC_BASE + 0x4320)
    #define HD21MAC_CFG_4320_EM_P1_REG_PPS_111 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4320_EM_P1_REG_PPS_110 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4324_EM_P1 (HDMI2P1_MAC_BASE + 0x4324)
    #define HD21MAC_CFG_4324_EM_P1_REG_PPS_109 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4324_EM_P1_REG_PPS_108 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4328_EM_P1 (HDMI2P1_MAC_BASE + 0x4328)
    #define HD21MAC_CFG_4328_EM_P1_REG_PPS_107 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4328_EM_P1_REG_PPS_106 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_432C_EM_P1 (HDMI2P1_MAC_BASE + 0x432C)
    #define HD21MAC_CFG_432C_EM_P1_REG_PPS_105 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_432C_EM_P1_REG_PPS_104 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4330_EM_P1 (HDMI2P1_MAC_BASE + 0x4330)
    #define HD21MAC_CFG_4330_EM_P1_REG_PPS_103 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4330_EM_P1_REG_PPS_102 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4334_EM_P1 (HDMI2P1_MAC_BASE + 0x4334)
    #define HD21MAC_CFG_4334_EM_P1_REG_PPS_101 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4334_EM_P1_REG_PPS_100 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4338_EM_P1 (HDMI2P1_MAC_BASE + 0x4338)
    #define HD21MAC_CFG_4338_EM_P1_REG_PPS_99 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4338_EM_P1_REG_PPS_98 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_433C_EM_P1 (HDMI2P1_MAC_BASE + 0x433C)
    #define HD21MAC_CFG_433C_EM_P1_REG_PPS_97 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_433C_EM_P1_REG_PPS_96 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4340_EM_P1 (HDMI2P1_MAC_BASE + 0x4340)
    #define HD21MAC_CFG_4340_EM_P1_REG_PPS_95 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4340_EM_P1_REG_PPS_94 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4344_EM_P1 (HDMI2P1_MAC_BASE + 0x4344)
    #define HD21MAC_CFG_4344_EM_P1_REG_PPS_93 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4344_EM_P1_REG_PPS_92 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4348_EM_P1 (HDMI2P1_MAC_BASE + 0x4348)
    #define HD21MAC_CFG_4348_EM_P1_REG_PPS_91 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4348_EM_P1_REG_PPS_90 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_434C_EM_P1 (HDMI2P1_MAC_BASE + 0x434C)
    #define HD21MAC_CFG_434C_EM_P1_REG_PPS_89 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_434C_EM_P1_REG_PPS_88 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4350_EM_P1 (HDMI2P1_MAC_BASE + 0x4350)
    #define HD21MAC_CFG_4350_EM_P1_REG_PPS_87 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4350_EM_P1_REG_PPS_86 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4354_EM_P1 (HDMI2P1_MAC_BASE + 0x4354)
    #define HD21MAC_CFG_4354_EM_P1_REG_PPS_85 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4354_EM_P1_REG_PPS_84 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4358_EM_P1 (HDMI2P1_MAC_BASE + 0x4358)
    #define HD21MAC_CFG_4358_EM_P1_REG_PPS_83 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4358_EM_P1_REG_PPS_82 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_435C_EM_P1 (HDMI2P1_MAC_BASE + 0x435C)
    #define HD21MAC_CFG_435C_EM_P1_REG_PPS_81 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_435C_EM_P1_REG_PPS_80 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4360_EM_P1 (HDMI2P1_MAC_BASE + 0x4360)
    #define HD21MAC_CFG_4360_EM_P1_REG_PPS_79 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4360_EM_P1_REG_PPS_78 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4364_EM_P1 (HDMI2P1_MAC_BASE + 0x4364)
    #define HD21MAC_CFG_4364_EM_P1_REG_PPS_77 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4364_EM_P1_REG_PPS_76 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4368_EM_P1 (HDMI2P1_MAC_BASE + 0x4368)
    #define HD21MAC_CFG_4368_EM_P1_REG_PPS_75 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4368_EM_P1_REG_PPS_74 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_436C_EM_P1 (HDMI2P1_MAC_BASE + 0x436C)
    #define HD21MAC_CFG_436C_EM_P1_REG_PPS_73 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_436C_EM_P1_REG_PPS_72 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4370_EM_P1 (HDMI2P1_MAC_BASE + 0x4370)
    #define HD21MAC_CFG_4370_EM_P1_REG_PPS_71 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4370_EM_P1_REG_PPS_70 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4374_EM_P1 (HDMI2P1_MAC_BASE + 0x4374)
    #define HD21MAC_CFG_4374_EM_P1_REG_PPS_69 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4374_EM_P1_REG_PPS_68 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4378_EM_P1 (HDMI2P1_MAC_BASE + 0x4378)
    #define HD21MAC_CFG_4378_EM_P1_REG_PPS_67 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4378_EM_P1_REG_PPS_66 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_437C_EM_P1 (HDMI2P1_MAC_BASE + 0x437C)
    #define HD21MAC_CFG_437C_EM_P1_REG_PPS_65 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_437C_EM_P1_REG_PPS_64 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4380_EM_P1 (HDMI2P1_MAC_BASE + 0x4380)
    #define HD21MAC_CFG_4380_EM_P1_REG_PPS_63 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4380_EM_P1_REG_PPS_62 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4384_EM_P1 (HDMI2P1_MAC_BASE + 0x4384)
    #define HD21MAC_CFG_4384_EM_P1_REG_PPS_61 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4384_EM_P1_REG_PPS_60 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4388_EM_P1 (HDMI2P1_MAC_BASE + 0x4388)
    #define HD21MAC_CFG_4388_EM_P1_REG_PPS_59 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4388_EM_P1_REG_PPS_58 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_438C_EM_P1 (HDMI2P1_MAC_BASE + 0x438C)
    #define HD21MAC_CFG_438C_EM_P1_REG_PPS_57 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_438C_EM_P1_REG_PPS_56 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4390_EM_P1 (HDMI2P1_MAC_BASE + 0x4390)
    #define HD21MAC_CFG_4390_EM_P1_REG_PPS_55 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4390_EM_P1_REG_PPS_54 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4394_EM_P1 (HDMI2P1_MAC_BASE + 0x4394)
    #define HD21MAC_CFG_4394_EM_P1_REG_PPS_53 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4394_EM_P1_REG_PPS_52 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4398_EM_P1 (HDMI2P1_MAC_BASE + 0x4398)
    #define HD21MAC_CFG_4398_EM_P1_REG_PPS_51 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4398_EM_P1_REG_PPS_50 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_439C_EM_P1 (HDMI2P1_MAC_BASE + 0x439C)
    #define HD21MAC_CFG_439C_EM_P1_REG_PPS_49 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_439C_EM_P1_REG_PPS_48 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43A0_EM_P1 (HDMI2P1_MAC_BASE + 0x43A0)
    #define HD21MAC_CFG_43A0_EM_P1_REG_PPS_47 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43A0_EM_P1_REG_PPS_46 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43A4_EM_P1 (HDMI2P1_MAC_BASE + 0x43A4)
    #define HD21MAC_CFG_43A4_EM_P1_REG_PPS_45 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43A4_EM_P1_REG_PPS_44 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43A8_EM_P1 (HDMI2P1_MAC_BASE + 0x43A8)
    #define HD21MAC_CFG_43A8_EM_P1_REG_PPS_43 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43A8_EM_P1_REG_PPS_42 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43AC_EM_P1 (HDMI2P1_MAC_BASE + 0x43AC)
    #define HD21MAC_CFG_43AC_EM_P1_REG_PPS_41 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43AC_EM_P1_REG_PPS_40 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43B0_EM_P1 (HDMI2P1_MAC_BASE + 0x43B0)
    #define HD21MAC_CFG_43B0_EM_P1_REG_PPS_39 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43B0_EM_P1_REG_PPS_38 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43B4_EM_P1 (HDMI2P1_MAC_BASE + 0x43B4)
    #define HD21MAC_CFG_43B4_EM_P1_REG_PPS_37 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43B4_EM_P1_REG_PPS_36 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43B8_EM_P1 (HDMI2P1_MAC_BASE + 0x43B8)
    #define HD21MAC_CFG_43B8_EM_P1_REG_PPS_35 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43B8_EM_P1_REG_PPS_34 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43BC_EM_P1 (HDMI2P1_MAC_BASE + 0x43BC)
    #define HD21MAC_CFG_43BC_EM_P1_REG_PPS_33 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43BC_EM_P1_REG_PPS_32 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43C0_EM_P1 (HDMI2P1_MAC_BASE + 0x43C0)
    #define HD21MAC_CFG_43C0_EM_P1_REG_PPS_31 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43C0_EM_P1_REG_PPS_30 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43C4_EM_P1 (HDMI2P1_MAC_BASE + 0x43C4)
    #define HD21MAC_CFG_43C4_EM_P1_REG_PPS_29 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43C4_EM_P1_REG_PPS_28 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43C8_EM_P1 (HDMI2P1_MAC_BASE + 0x43C8)
    #define HD21MAC_CFG_43C8_EM_P1_REG_PPS_27 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43C8_EM_P1_REG_PPS_26 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43CC_EM_P1 (HDMI2P1_MAC_BASE + 0x43CC)
    #define HD21MAC_CFG_43CC_EM_P1_REG_PPS_25 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43CC_EM_P1_REG_PPS_24 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43D0_EM_P1 (HDMI2P1_MAC_BASE + 0x43D0)
    #define HD21MAC_CFG_43D0_EM_P1_REG_PPS_23 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43D0_EM_P1_REG_PPS_22 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43D4_EM_P1 (HDMI2P1_MAC_BASE + 0x43D4)
    #define HD21MAC_CFG_43D4_EM_P1_REG_PPS_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43D4_EM_P1_REG_PPS_20 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43D8_EM_P1 (HDMI2P1_MAC_BASE + 0x43D8)
    #define HD21MAC_CFG_43D8_EM_P1_REG_PPS_19 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43D8_EM_P1_REG_PPS_18 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43DC_EM_P1 (HDMI2P1_MAC_BASE + 0x43DC)
    #define HD21MAC_CFG_43DC_EM_P1_REG_PPS_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43DC_EM_P1_REG_PPS_16 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43E0_EM_P1 (HDMI2P1_MAC_BASE + 0x43E0)
    #define HD21MAC_CFG_43E0_EM_P1_REG_PPS_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43E0_EM_P1_REG_PPS_14 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43E4_EM_P1 (HDMI2P1_MAC_BASE + 0x43E4)
    #define HD21MAC_CFG_43E4_EM_P1_REG_PPS_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43E4_EM_P1_REG_PPS_12 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43E8_EM_P1 (HDMI2P1_MAC_BASE + 0x43E8)
    #define HD21MAC_CFG_43E8_EM_P1_REG_PPS_11 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43E8_EM_P1_REG_PPS_10 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43EC_EM_P1 (HDMI2P1_MAC_BASE + 0x43EC)
    #define HD21MAC_CFG_43EC_EM_P1_REG_PPS_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43EC_EM_P1_REG_PPS_8 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43F0_EM_P1 (HDMI2P1_MAC_BASE + 0x43F0)
    #define HD21MAC_CFG_43F0_EM_P1_REG_PPS_7 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43F0_EM_P1_REG_PPS_6 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43F4_EM_P1 (HDMI2P1_MAC_BASE + 0x43F4)
    #define HD21MAC_CFG_43F4_EM_P1_REG_PPS_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43F4_EM_P1_REG_PPS_4 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_43F8_EM_P1 (HDMI2P1_MAC_BASE + 0x43F8)
    #define HD21MAC_CFG_43F8_EM_P1_REG_PPS_3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43F8_EM_P1_REG_PPS_2 Fld(8,0,AC_FULLB0)//[7:0]

    //Page HDMI21_MAC_24
#define HD21MAC_CFG_43FC_EM_P1 (HDMI2P1_MAC_BASE + 0x43FC)
    #define HD21MAC_CFG_43FC_EM_P1_REG_PPS_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_43FC_EM_P1_REG_PPS_0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4414_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4414)
    #define HD21MAC_CFG_4414_PLL_TOP_P1_REG_PHASE_LOCK_THRESH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4414_PLL_TOP_P1_REG_PRD_LOCK_THRESH Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_4414_PLL_TOP_P1_REG_PRD_STABLE_THRESH Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_4418_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4418)
    #define HD21MAC_CFG_4418_PLL_TOP_P1_REG_LIMIT_D5D6D7_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_441C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x441C)
    #define HD21MAC_CFG_441C_PLL_TOP_P1_REG_LIMIT_D5D6D7_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4420_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4420)
    #define HD21MAC_CFG_4420_PLL_TOP_P1_REG_LIMIT_D5D6D7_RK_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4424_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4424)
    #define HD21MAC_CFG_4424_PLL_TOP_P1_REG_LIMIT_D5D6D7_RK_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4428_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4428)
    #define HD21MAC_CFG_4428_PLL_TOP_P1_REG_LIMIT_LPLL_OFFSET Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_442C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x442C)
    #define HD21MAC_CFG_442C_PLL_TOP_P1_REG_P_GAIN_PHASE Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_442C_PLL_TOP_P1_REG_I_GAIN_PHASE Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_442C_PLL_TOP_P1_REG_P_GAIN_PRD Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21MAC_CFG_442C_PLL_TOP_P1_REG_I_GAIN_PRD Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_4430_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4430)
    #define HD21MAC_CFG_4430_PLL_TOP_P1_REG_OVS_FRAME_DIV Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_4430_PLL_TOP_P1_REG_IVS_FRAME_DIV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_4430_PLL_TOP_P1_REG_P_GAIN_PHASE_ZERO Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_4430_PLL_TOP_P1_REG_I_GAIN_PHASE_ZERO Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_4430_PLL_TOP_P1_REG_P_GAIN_PRD_ZERO Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_4430_PLL_TOP_P1_REG_I_GAIN_PRD_ZERO Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_4430_PLL_TOP_P1_REG_FRAME_LPLL_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4430_PLL_TOP_P1_REG_FPLL_MODE Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_4434_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4434)
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_SSC_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_NON_STABLE_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_NO_SIGNAL_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_NON_STABLE_OV Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_NO_SIGNAL_OV Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_OVE_STATUS_IN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_EN_2_LIMIT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_FORCE_PHASE_CLOSE_DONE Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_FORCE_PHASE_REDUCE_DONE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_FORCE_PRD_LOCK_DONE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4434_PLL_TOP_P1_REG_FORCE_PRD_STABLE Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4438_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4438)
    #define HD21MAC_CFG_4438_PLL_TOP_P1_REG_EXT_OVS_FRAME_DIV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4438_PLL_TOP_P1_REG_EXT_IVS_FRAME_DIV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_443C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x443C)
    #define HD21MAC_CFG_443C_PLL_TOP_P1_REG_PLL_SET_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4440_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4440)
    #define HD21MAC_CFG_4440_PLL_TOP_P1_REG_PLL_SET_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4444_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4444)
    #define HD21MAC_CFG_4444_PLL_TOP_P1_REG_PHASE_DIF Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4448_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4448)
    #define HD21MAC_CFG_4448_PLL_TOP_P1_REG_PHASE_UP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_444C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x444C)
    #define HD21MAC_CFG_444C_PLL_TOP_P1_REG_PRD_DIF Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4450_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4450)
    #define HD21MAC_CFG_4450_PLL_TOP_P1_REG_PRD_UP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4458_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4458)
    #define HD21MAC_CFG_4458_PLL_TOP_P1_REG_LPLL_TESTD Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21MAC_CFG_4458_PLL_TOP_P1_REG_EN_FB_RETIME Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4458_PLL_TOP_P1_REG_EN_OUTCLK_2CHIP Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_445C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x445C)
    #define HD21MAC_CFG_445C_PLL_TOP_P1_REG_LPLL_STEP Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_4460_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4460)
    #define HD21MAC_CFG_4460_PLL_TOP_P1_REG_LPLL_SPAN Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_4464_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4464)
    #define HD21MAC_CFG_4464_PLL_TOP_P1_REG_IDCLK_DIV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4468_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4468)
    #define HD21MAC_CFG_4468_PLL_TOP_P1_REG_IDCLK_DIV_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_446C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x446C)
    #define HD21MAC_CFG_446C_PLL_TOP_P1_REG_ODCLK_DIV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4470_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4470)
    #define HD21MAC_CFG_4470_PLL_TOP_P1_REG_ODCLK_DIV_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4474_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4474)
    #define HD21MAC_CFG_4474_PLL_TOP_P1_REG_FIX_DEC_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_4474_PLL_TOP_P1_REG_DEC_V_LIMIT Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_4478_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4478)
    #define HD21MAC_CFG_4478_PLL_TOP_P1_REG_INC_V_LIMIT Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_447C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x447C)
    #define HD21MAC_CFG_447C_PLL_TOP_P1_REG_REDUCE_DONE_THRESH Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_447C_PLL_TOP_P1_REG_PHASE_CLOSE_THRESH Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_4480_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4480)
    #define HD21MAC_CFG_4480_PLL_TOP_P1_REG_HIS_CNT_HIGH_THRESH Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21MAC_CFG_4480_PLL_TOP_P1_REG_HIS_CNT_LOW_THRESH Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_4484_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4484)
    #define HD21MAC_CFG_4484_PLL_TOP_P1_REG_IVS_PRD_VALUE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4488_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4488)
    #define HD21MAC_CFG_4488_PLL_TOP_P1_REG_IVS_PRD_VALUE_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_448C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x448C)
    #define HD21MAC_CFG_448C_PLL_TOP_P1_REG_OVS_PRD_VALUE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4490_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4490)
    #define HD21MAC_CFG_4490_PLL_TOP_P1_REG_OVS_PRD_VALUE_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4498_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4498)
    #define HD21MAC_CFG_4498_PLL_TOP_P1_REG_FIX_V_DEC Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_4498_PLL_TOP_P1_REG_FIX_V_TOTAL Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_449C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x449C)
    #define HD21MAC_CFG_449C_PLL_TOP_P1_REG_FIX_H_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_44A0_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x44A0)
    #define HD21MAC_CFG_44A0_PLL_TOP_P1_REG_PLL_SET_USING_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_44A4_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x44A4)
    #define HD21MAC_CFG_44A4_PLL_TOP_P1_REG_PLL_SET_USING_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_44A8_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x44A8)
    #define HD21MAC_CFG_44A8_PLL_TOP_P1_REG_PHASE_LOCK_DONE Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_44A8_PLL_TOP_P1_REG_PHASE_REDUCE_DONE Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21MAC_CFG_44A8_PLL_TOP_P1_REG_PRD_LOCK_DONE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_44A8_PLL_TOP_P1_REG_IVS_PRD_STABLE Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_44A8_PLL_TOP_P1_REG_OVS_PRD_STABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_44A8_PLL_TOP_P1_REG_CS_STATE Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_44AC_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x44AC)
    #define HD21MAC_CFG_44AC_PLL_TOP_P1_REG_ERR_UP_INV Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_44AC_PLL_TOP_P1_REG_PH_UP_INV Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_44AC_PLL_TOP_P1_REG_PH_HALF_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_44AC_PLL_TOP_P1_REG_STATUS_DEBUG Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_44BC_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x44BC)
    #define HD21MAC_CFG_44BC_PLL_TOP_P1_REG_RST_MODULE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4580_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4580)
    #define HD21MAC_CFG_4580_PLL_TOP_P1_REG_SDM_SET_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4584_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4584)
    #define HD21MAC_CFG_4584_PLL_TOP_P1_REG_SDM_SET_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4588_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4588)
    #define HD21MAC_CFG_4588_PLL_TOP_P1_REG_SDM_SET_LIMIT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_458C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x458C)
    #define HD21MAC_CFG_458C_PLL_TOP_P1_REG_SDM_SET_LIMIT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4590_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4590)
    #define HD21MAC_CFG_4590_PLL_TOP_P1_REG_SDM_SET_LIMIT_FAST_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4594_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4594)
    #define HD21MAC_CFG_4594_PLL_TOP_P1_REG_SDM_SET_LIMIT_FAST_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4598_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x4598)
    #define HD21MAC_CFG_4598_PLL_TOP_P1_REG_SDM_P_GAIN Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_4598_PLL_TOP_P1_REG_SDM_I_GAIN Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_459C_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x459C)
    #define HD21MAC_CFG_459C_PLL_TOP_P1_REG_SLD_CYC Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_45A8_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45A8)
    #define HD21MAC_CFG_45A8_PLL_TOP_P1_REG_GCR_TMDSPLL_LOOPDIV_SECOND Fld(8,7,AC_MSKW10)//[14:7]
    #define HD21MAC_CFG_45A8_PLL_TOP_P1_REG_PD_TMDSPLL Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21MAC_CFG_45A8_PLL_TOP_P1_REG_GCP_TMDSPLL_PORST Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21MAC_CFG_45A8_PLL_TOP_P1_REG_GCP_TMDSPLL_EXTAL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_45A8_PLL_TOP_P1_REG_EN_TMDSPLL_TEST Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_45A8_PLL_TOP_P1_REG_EN_TMDSPLL_PRDT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_45A8_PLL_TOP_P1_REG_EN_TMDSPLL_PRDT Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_45A8_PLL_TOP_P1_REG_EN_OV_TMDSPLL_CP_SW Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_45AC_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45AC)
    #define HD21MAC_CFG_45AC_PLL_TOP_P1_REG_EN_CLKO_TMDS Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21MAC_CFG_45AC_PLL_TOP_P1_REG_EN_CLKO_PIX Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_45AC_PLL_TOP_P1_REG_GCR_TMDSPLL_OUTPUT_DIV Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_45B0_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45B0)
    #define HD21MAC_CFG_45B0_PLL_TOP_P1_REG_TEST_TMDSPLL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_45B4_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45B4)
    #define HD21MAC_CFG_45B4_PLL_TOP_P1_REG_RO_TMDSPLL_LOCK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_45B4_PLL_TOP_P1_REG_GCR_TMDS_CP_SW Fld(2,11,AC_MSKB1)//[12:11]
    #define HD21MAC_CFG_45B4_PLL_TOP_P1_REG_GCR_TMDSPLL_ICTRL Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_45B4_PLL_TOP_P1_REG_GCR_TMDSPLL_LOOPDIV_FIRST Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_45B4_PLL_TOP_P1_REG_TMDS_POST_DIV Fld(4,2,AC_MSKB0)//[5:2]
    #define HD21MAC_CFG_45B4_PLL_TOP_P1_REG_GCR_TMDSPLL_INPUT_DIV Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_45B8_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45B8)
    #define HD21MAC_CFG_45B8_PLL_TOP_P1_REG_RSV_OV Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21MAC_CFG_45B8_PLL_TOP_P1_REG_SW_FREQ_SETTING Fld(9,0,AC_MSKW10)//[8:0]
#define HD21MAC_CFG_45BC_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45BC)
    #define HD21MAC_CFG_45BC_PLL_TOP_P1_REG_ATOP_TMDS_POST_DIV_RPT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_45BC_PLL_TOP_P1_REG_HW_CKG_DIV_8_4_2_AUTO Fld(3,13,AC_MSKB1)//[15:13]
#define HD21MAC_CFG_45C0_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45C0)
    #define HD21MAC_CFG_45C0_PLL_TOP_P1_REG_FSYNC_RESET_THRESH Fld(8,0,AC_FULLB0)//[7:0]
    #define HD21MAC_CFG_45C0_PLL_TOP_P1_REG_FSYNC_RESET_2T_FLAG Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_45C0_PLL_TOP_P1_REG_CLR_FSYNC_RESET_2T_FLAG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_45C0_PLL_TOP_P1_REG_EN_PLL_FSYNC_RESET Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_45C0_PLL_TOP_P1_REG_PRD_LOCK_THRESH_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_45C0_PLL_TOP_P1_REG_VTT_PLL_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_45C0_PLL_TOP_P1_REG_EN_CLK_DIV Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_45C4_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45C4)
    #define HD21MAC_CFG_45C4_PLL_TOP_P1_REG_LPLL1_TEST_V2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_45C8_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45C8)
    #define HD21MAC_CFG_45C8_PLL_TOP_P1_REG_IDCLK_DIV_PRD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_45CC_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45CC)
    #define HD21MAC_CFG_45CC_PLL_TOP_P1_REG_IDCLK_DIV_PRD_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_45D0_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45D0)
    #define HD21MAC_CFG_45D0_PLL_TOP_P1_REG_ODCLK_DIV_PRD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_45D4_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45D4)
    #define HD21MAC_CFG_45D4_PLL_TOP_P1_REG_ODCLK_DIV_PRD_1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_45D8_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45D8)
    #define HD21MAC_CFG_45D8_PLL_TOP_P1_REG_SRC_VTT Fld(12,0,AC_MSKW10)//[11:0]
#define HD21MAC_CFG_45DC_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45DC)
    #define HD21MAC_CFG_45DC_PLL_TOP_P1_REG_SRC_HTT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_45E0_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45E0)
    #define HD21MAC_CFG_45E0_PLL_TOP_P1_REG_PIX_RATE_MIN Fld(10,0,AC_MSKW10)//[9:0]
    #define HD21MAC_CFG_45E0_PLL_TOP_P1_REG_LOC_VTT_FIX_CAL_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21MAC_CFG_45E0_PLL_TOP_P1_REG_IVS_THRESH_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_45E0_PLL_TOP_P1_REG_V_OFFSET_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21MAC_CFG_45E0_PLL_TOP_P1_REG_P_RATE_RDY Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_45E0_PLL_TOP_P1_REG_P_RATE_FUNC_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_45EC_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45EC)
    #define HD21MAC_CFG_45EC_PLL_TOP_P1_REG_SELF_DET_TH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_45F0_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45F0)
    #define HD21MAC_CFG_45F0_PLL_TOP_P1_REG_IVS_PRD_RPT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_45F4_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45F4)
    #define HD21MAC_CFG_45F4_PLL_TOP_P1_REG_FPLL_GAT_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_45F4_PLL_TOP_P1_REG_IVS_PRD_RPT_1 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_45F8_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45F8)
    #define HD21MAC_CFG_45F8_PLL_TOP_P1_REG_F_RPT_CNT Fld(12,0,AC_MSKW10)//[11:0]
    #define HD21MAC_CFG_45F8_PLL_TOP_P1_REG_PHASE_LOCK_THRESH_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21MAC_CFG_45F8_PLL_TOP_P1_REG_F_RPT_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_45F8_PLL_TOP_P1_REG_SPREADER_EN Fld(1,15,AC_MSKB1)//[15:15]
#define HD21MAC_CFG_45FC_PLL_TOP_P1 (HDMI2P1_MAC_BASE + 0x45FC)
    #define HD21MAC_CFG_45FC_PLL_TOP_P1_REG_DB_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define HD21MAC_CFG_45FC_PLL_TOP_P1_REG_SW_TRIG_DB_LOAD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_45FC_PLL_TOP_P1_REG_SW_TRIG_CLR_FIX_VTT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_45FC_PLL_TOP_P1_REG_FIX_POSI_LD Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_45FC_PLL_TOP_P1_REG_TGEN_SRC_SEL Fld(1,8,AC_MSKB1)//[8:8]
#define HD21MAC_CFG_4600_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4600)
    #define HD21MAC_CFG_4600_SVCE_P1_REG_SW_RST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_4604_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4604)
    #define HD21MAC_CFG_4604_SVCE_P1_REG_PATH2P_RPLC Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21MAC_CFG_4604_SVCE_P1_REG_VDO2P_REPLACE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_4604_SVCE_P1_REG_DIS_DE_PROT Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4604_SVCE_P1_REG_AWS_SYNC Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4604_SVCE_P1_REG_OUTPUT_FORMAT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4604_SVCE_P1_REG_INPUT_FORMAT Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4604_SVCE_P1_REG_CFG_PPS_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4604_SVCE_P1_REG_PATH8P_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4608_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4608)
    #define HD21MAC_CFG_4608_SVCE_P1_REG_CHUNK_SIZE_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21MAC_CFG_460C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x460C)
    #define HD21MAC_CFG_460C_SVCE_P1_REG_CHUNK_SIZE_OV Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4610_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4610)
    #define HD21MAC_CFG_4610_SVCE_P1_REG_FEED_PIC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4614_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4614)
    #define HD21MAC_CFG_4614_SVCE_P1_REG_FEED_SLICE_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4618_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4618)
    #define HD21MAC_CFG_4618_SVCE_P1_REG_FEED_CHUNK_SIZE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_461C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x461C)
    #define HD21MAC_CFG_461C_SVCE_P1_REG_FEED_BPP Fld(10,0,AC_MSKW10)//[9:0]
#define HD21MAC_CFG_4620_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4620)
    #define HD21MAC_CFG_4620_SVCE_P1_REG_FEED_BPC_OV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_4620_SVCE_P1_REG_FEED_DIV2EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4624_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4624)
    #define HD21MAC_CFG_4624_SVCE_P1_REG_CLR_FEED_FIFO_FLAG Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4628_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4628)
    #define HD21MAC_CFG_4628_SVCE_P1_REG_FEED_FIFO_FULL_LAT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_462C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x462C)
    #define HD21MAC_CFG_462C_SVCE_P1_REG_FEED_FIFO_RST_MODE Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_4630_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4630)
    #define HD21MAC_CFG_4630_SVCE_P1_REG_CHUNK_SIZE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4634_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4634)
    #define HD21MAC_CFG_4634_SVCE_P1_REG_SN_LEAD_CFG Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21MAC_CFG_4634_SVCE_P1_REG_SLICE_NUM Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_4640_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4640)
    #define HD21MAC_CFG_4640_SVCE_P1_REG_DVI_ROUND_EN_OV Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21MAC_CFG_4640_SVCE_P1_REG_DITH_SEL_DVI_OV Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21MAC_CFG_4640_SVCE_P1_REG_DITH_SEED_RST_OV Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21MAC_CFG_4640_SVCE_P1_REG_DIS_FULL_BLACK_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21MAC_CFG_4640_SVCE_P1_REG_AVI_IF5_OV Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21MAC_CFG_4640_SVCE_P1_REG_FORCE_YCBCR_BLACK_OV Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21MAC_CFG_4640_SVCE_P1_REG_VIDEO_BLANK_TST_OV Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21MAC_CFG_4640_SVCE_P1_REG_YCBCR444_DC_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4640_SVCE_P1_REG_YCBCR422_DC_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4640_SVCE_P1_REG_YCBCR420_DC_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4644_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4644)
    #define HD21MAC_CFG_4644_SVCE_P1_REG_DITHER_CFG_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21MAC_CFG_4644_SVCE_P1_REG_DITHER_IF_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_4644_SVCE_P1_REG_DITHER_IF_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4648_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4648)
    #define HD21MAC_CFG_4648_SVCE_P1_REG_VS_RST_RCV_FIFO_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_464C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x464C)
    #define HD21MAC_CFG_464C_SVCE_P1_REG_TGEN_DB_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_464C_SVCE_P1_REG_TGEN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4650_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4650)
    #define HD21MAC_CFG_4650_SVCE_P1_REG_TGEN_SET_READY Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4654_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4654)
    #define HD21MAC_CFG_4654_SVCE_P1_REG_TGEN_CLR_CNT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4658_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4658)
    #define HD21MAC_CFG_4658_SVCE_P1_REG_HREF_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_465C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x465C)
    #define HD21MAC_CFG_465C_SVCE_P1_REG_VREF_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_4660_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4660)
    #define HD21MAC_CFG_4660_SVCE_P1_REG_HREF_FORCE Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_4664_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4664)
    #define HD21MAC_CFG_4664_SVCE_P1_REG_VREF_FORCE Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_4668_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4668)
    #define HD21MAC_CFG_4668_SVCE_P1_REG_SYNPLL_REF_HS_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_466C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x466C)
    #define HD21MAC_CFG_466C_SVCE_P1_REG_TGEN_VRR_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4670_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4670)
    #define HD21MAC_CFG_4670_SVCE_P1_REG_TGEN_DE_SFT_PROT_OPT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21MAC_CFG_4670_SVCE_P1_REG_TGEN_DE_SFT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_4674_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4674)
    #define HD21MAC_CFG_4674_SVCE_P1_REG_TGEN_DE_SFT_CNT Fld(5,0,AC_MSKB0)//[4:0]
#define HD21MAC_CFG_4678_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4678)
    #define HD21MAC_CFG_4678_SVCE_P1_REG_DSC_HS_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21MAC_CFG_4678_SVCE_P1_REG_DSC_ACK_SEL Fld(3,11,AC_MSKB1)//[13:11]
    #define HD21MAC_CFG_4678_SVCE_P1_REG_PRE_ACK Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21MAC_CFG_4678_SVCE_P1_REG_DSC_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define HD21MAC_CFG_4680_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4680)
    #define HD21MAC_CFG_4680_SVCE_P1_REG_TG_HTT Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_4684_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4684)
    #define HD21MAC_CFG_4684_SVCE_P1_REG_TG_HS_ED Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_4688_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4688)
    #define HD21MAC_CFG_4688_SVCE_P1_REG_TG_H_BP_ED Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_468C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x468C)
    #define HD21MAC_CFG_468C_SVCE_P1_REG_TG_H_DE Fld(14,0,AC_MSKW10)//[13:0]
#define HD21MAC_CFG_4690_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4690)
    #define HD21MAC_CFG_4690_SVCE_P1_REG_TG_VTT Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_4694_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4694)
    #define HD21MAC_CFG_4694_SVCE_P1_REG_TG_VS_ED Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_4698_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4698)
    #define HD21MAC_CFG_4698_SVCE_P1_REG_TG_V_BP_ED Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_469C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x469C)
    #define HD21MAC_CFG_469C_SVCE_P1_REG_TG_V_DE Fld(13,0,AC_MSKW10)//[12:0]
#define HD21MAC_CFG_46A0_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46A0)
    #define HD21MAC_CFG_46A0_SVCE_P1_REG_PATGEN_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21MAC_CFG_46A0_SVCE_P1_REG_PATGEN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_46A4_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46A4)
    #define HD21MAC_CFG_46A4_SVCE_P1_REG_PATGEN_PRG_RGB Fld(8,0,AC_FULLB0)//[7:0]
#define HD21MAC_CFG_46A8_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46A8)
    #define HD21MAC_CFG_46A8_SVCE_P1_REG_CLR_RCV_FIFO_FLAG Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_46AC_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46AC)
    #define HD21MAC_CFG_46AC_SVCE_P1_REG_RCV_FIFO_FULL_LAT Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21MAC_CFG_46AC_SVCE_P1_REG_RCV_FIFO_EMPTY_LAT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21MAC_CFG_46C0_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46C0)
    #define HD21MAC_CFG_46C0_SVCE_P1_REG_FEED_DEBUG_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_46C4_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46C4)
    #define HD21MAC_CFG_46C4_SVCE_P1_REG_FEED_DEBUG_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_46C8_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46C8)
    #define HD21MAC_CFG_46C8_SVCE_P1_REG_RCV_DEBUG_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_46CC_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46CC)
    #define HD21MAC_CFG_46CC_SVCE_P1_REG_RCV_DEBUG_1 Fld(16,0,AC_FULLW10)//[15:0]

    //Page HDMI21_MAC_25
#define HD21MAC_CFG_46D0_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46D0)
    #define HD21MAC_CFG_46D0_SVCE_P1_REG_DSCD_DEBUG_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_46D4_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46D4)
    #define HD21MAC_CFG_46D4_SVCE_P1_REG_DSCD_DEBUG_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_46DC_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46DC)
    #define HD21MAC_CFG_46DC_SVCE_P1_REG_BIST_FAIL Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_46E0_SVCE_P1 (HDMI2P1_MAC_BASE + 0x46E0)
    #define HD21MAC_CFG_46E0_SVCE_P1_REG_TESTBUS_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define HD21MAC_CFG_4700_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4700)
    #define HD21MAC_CFG_4700_SVCE_P1_REG_DSCD_RESERVE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4704_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4704)
    #define HD21MAC_CFG_4704_SVCE_P1_REG_DSCD_RESERVE_1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4708_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4708)
    #define HD21MAC_CFG_4708_SVCE_P1_REG_DSCD_RESERVE_2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_470C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x470C)
    #define HD21MAC_CFG_470C_SVCE_P1_REG_DSCD_RESERVE_3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4710_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4710)
    #define HD21MAC_CFG_4710_SVCE_P1_REG_DSCD_RESERVE_4 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4714_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4714)
    #define HD21MAC_CFG_4714_SVCE_P1_REG_DSCD_RESERVE_5 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_4718_SVCE_P1 (HDMI2P1_MAC_BASE + 0x4718)
    #define HD21MAC_CFG_4718_SVCE_P1_REG_DSCD_RESERVE_6 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21MAC_CFG_471C_SVCE_P1 (HDMI2P1_MAC_BASE + 0x471C)
    #define HD21MAC_CFG_471C_SVCE_P1_REG_DSCD_RESERVE_7 Fld(16,0,AC_FULLW10)//[15:0]

#endif //#ifndef _HW_HDMI2P1_MAC_H_
