/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: tenny.liu $
 * $Date: 2015/06/08 $
 * $RCSfile: srm_drvif.h,v $
 * $Revision: #4 $
 *
 *---------------------------------------------------------------------------*/

/** @file sm_drvif.h
 *  Brief of file sm_drvif.h.
 *  Details of file sm_drvif.h (optional).
 */

#ifndef SRM_DRVIF_H
#define SRM_DRVIF_H


//-----------------------------------------------------------------------------
// Include files
//-----------------------------------------------------------------------------

#include "x_typedef.h"


//-----------------------------------------------------------------------------
// Type definitions
//-----------------------------------------------------------------------------

typedef void (*FN_SRN_CALLBACK) (UINT32, UINT32, UINT32, UINT32);
#ifdef CC_MT5881
// Module 
#define SRM_DRV_MDDI                    0
#define SRM_DRV_SCPOS                   1
#define SRM_DRV_VDOIN                   2
#define SRM_DRV_VDEC_MC                 3
#define SRM_DRV_VLD_JPEG                4
#define SRM_DRV_OSD                     5
#define SRM_DRV_MJC                     6

#define SRM_DRV_DMX                     7
#define SRM_DRV_USB                     8
#define SRM_DRV_B2R                     9
#define SRM_DRV_CPU                     10
#define SRM_DRV_GFX_HI                  11
#define SRM_DRV_GFX_LO                  12
#define SRM_DRV_VLD1_JPEG               13
#define SRM_DRV_JPEGDEC                 14
#define SRM_DRV_DSP_1                   15
#define SRM_DRV_DSP_2                   16
#define SRM_DRV_TCM                     17
#define SRM_DRV_IDETEST                 18
#define SRM_DRV_UART                    19
#define SRM_DRV_FCI                     20
#define SRM_DRV_AUD                     21
#define SRM_DRV_8032_R_W                22
#define SRM_DRV_ETH                     23
#define SRM_DRV_GDMA                    24
#define SRM_DRV_MDDI_PIP                25
#define SRM_DRV_DDI                     26
#define SRM_DRV_IMGRZ                   27
#define SRM_DRV_POD                     28
#define SRM_DRV_MMU                     29
#define SRM_DRV_AUD_DSP                 30
#define SRM_DRV_PR_GEN                  31
#define SRM_DRV_TDDC                    32
#define SRM_DRV_USB3                    33
#define SRM_DRV_ETH_CHK_SUM             34
#define SRM_DRV_TOTAL                   35

#else
// Module 
#define SRM_DRV_MDDI                    0
#define SRM_DRV_SCPOS                   1
#define SRM_DRV_VDOIN                   2
#define SRM_DRV_VDEC_MC                 3
#define SRM_DRV_VLD_JPEG                4
#define SRM_DRV_OSD                     5
#define SRM_DRV_MJC                     6

#define SRM_DRV_DMX                     7
#define SRM_DRV_USB                     8
#define SRM_DRV_B2R                     9
#define SRM_DRV_CPU                     10
#define SRM_DRV_GFX_HI                  11
#define SRM_DRV_GFX_LO                  12
#define SRM_DRV_VLD1_JPEG               13
#define SRM_DRV_JPEGDEC                 14
#define SRM_DRV_DSP_1                   15
#define SRM_DRV_DSP_2                   16
#define SRM_DRV_TCM                     17
#define SRM_DRV_IDETEST                 18
#define SRM_DRV_UART                    19
#define SRM_DRV_FCI                     20
#define SRM_DRV_AUD                     21
#define SRM_DRV_MJC_OUT                 22
#define SRM_DRV_ETH                     23
#define SRM_DRV_GDMA                    24
#define SRM_DRV_MDDI_PIP                25
#define SRM_DRV_DDI                     26
#define SRM_DRV_IMGRZ                   27
#define SRM_DRV_POD                     28
#define SRM_DRV_VENC                    29
#define SRM_DRV_3D_GFX                  30
#define SRM_DRV_PR_GEN                  31
#define SRM_DRV_TDDC                    32
#define SRM_DRV_USB3                    33
#define SRM_DRV_ETH_CHK_SUM             34
#define SRM_DRV_SPIS                    35
#define SRM_DRV_TOTAL                   36
#endif
// VGA Bandwidth Issue
#define SRM_VGA_BANDWIDTH_OK            0       // Normal Mode
#define SRM_VGA_BANDWIDTH_FAIL          1       // Display Mode

// SRM Control Feature
#define SRM_BOB_CTRL                    0       // BOB Mode Control
#define SRM_TNR_CTRL                    1       // TNR Mode Control
#define SRM_DISP_CTRL                   2       // Display Mode Control
#define SRM_MUTE_CTRL                   3       // Mute Control
#define SRM_SCALER_WE_CTRL              4       // Scaler Write Enable Control 
#define SRM_MPEG_PIP_CTRL               5       // Deblocking/Half Reference Control
#define SRM_MISC_CTRL                   6       // Misc (Scaler change notify, ...)
#define SRM_MJC_CTRL                    7       // MJC control
#define SRM_MMBUFCHG_CTRL               8       // Multimedia buffer change
#define SRM_TDC_CTRL                           9
#define SRM_FEATURE_CTRL_NS             10

#define SRM_STABLE_CB_NS                9

#define SRM_SRAM_SRC_SD                 0
#define SRM_SRAM_SRC_HD                 1
#define SRM_SRAM_SRC_VGA                2

#define SRM_MISC_NULL                   0
#define SRM_MISC_SCALER_CHANGE          1       // Scaler change notify
#define SRM_MISC_MAX                    SRM_MISC_SCALER_CHANGE

#define SRM_SCPOS_MUTE_OFF              0       // Scaler Mute Off
#define SRM_SCPOS_MUTE_ON               1       // Scaler Mute On
#define SRM_SCPOS_MUTE_MAX              SRM_SCPOS_MUTE_ON

#define SRM_SCPOS_WE_ON                 0       // Normal
#define SRM_SCPOS_WE_OFF                1       // Force Write Enable Off
#define SRM_SCPOS_WE_MAX                SRM_SCPOS_WE_OFF

#ifndef CC_DOWN_BW_WITH_MENU
#define CC_DOWN_BW_WITH_MENU
#endif


// Information Event
#define SRM_SCPOS_EVENT_MASK            (0xFFFF)

#define SRM_SCPOS_EVENT_ONOFF           (1 << 16)
#define SRM_SCPOS_EVENT_SOURCE          (1 << 17)
#define SRM_SCPOS_EVENT_MPEG_SIZE       (1 << 18)
#define SRM_SCPOS_EVENT_SIZE            (1 << 19)
#define SRM_SCPOS_EVENT_OUT_SIZE        (1 << 20)
#define SRM_SCPOS_EVENT_STATUS          (1 << 21)
#define SRM_SCPOS_EVENT_WIDTH           (1 << 22)
//#define SRM_SCPOS_EVENT_UNMUTE          (1 << 22)
#define SRM_SCPOS_EVENT_UNSTABLE        (1 << 23)
#define SRM_SCPOS_EVENT_GAME_MODE       (1 << 24)
#define SRM_SCPOS_EVENT_SCAN_MODE       (1 << 25)
#define SRM_SCPOS_EVENT_ZOOM_MODE       (1 << 26)
#define SRM_SCPOS_EVENT_SRC_RATIO       (1 << 27)
#if defined(CC_DOWN_BW_WITH_MENU)
#define SRM_SCPOS_EVENT_DOWN_PQ_MODE    (1 << 28)
#endif
#define SRM_SCPOS_EVENT_Dot_By_Dot       (1 << 29)
#define SRM_SCPOS_EVENT_MJC_ON_OFF (1<<30)


#define SRM_OSD_EVENT_ONOFF             (1 << 16)
#define SRM_OSD_EVENT_SIZE              (1 << 17)

#define SRM_CTRL_MODE_UNKOWN                    0
#define SRM_CTRL_MODE_NONE                      1
#define SRM_CTRL_MODE_DB_RULE                   2
#define SRM_CTRL_MODE_BONDING_RULE              3

#define SRM_VDP_SD_RESOLUTION                   (720 * 576)
#define SRM_VDP_720HD_RESOLUTION                (1280 * 720)
#define SRM_VDP_1080HD_RESOLUTION               (1920 * 1080)

typedef enum
{
    SRM_TV_MODE_TYPE_NORMAL = 0,
    SRM_TV_MODE_TYPE_PIP,
    SRM_TV_MODE_TYPE_POP,
    SRM_TV_MODE_TYPE_SCART_OUT_ON,
    SRM_TV_MODE_TYPE_SCART_OUT_OFF,
    SRM_TV_MODE_TYPE_LAST_VALID_ENTRY      /* only for counting purpose */
} SRM_TV_MODE_T;

typedef enum
{
    SRM_MM_MODE_TYPE_OFF,
    SRM_MM_MODE_TYPE_VIDEO,// mm playback: disable MJC and enable SCPOS
    SRM_MM_MODE_TYPE_JPEG, // jpeg viewer: disable NR,DI,MJC and enable SCPOS
    SRM_MM_MODE_TYPE_THUMBNAIL
} SRM_MM_MODE_T;

typedef enum
{
    SRM_FREEZE_MODE_SCPOS = 0,
    SRM_FREEZE_MODE_MDDI,
    SRM_FREEZE_MODE_MJC,
    SRM_FREEZE_MODE_MPEG,
    SRM_FREEZE_MODE_LAST_VALID_ENTRY     /* only for counting purpose */
} SRM_FREEZE_MODE_T;

typedef enum
{
    SRM_MM_SIZE_INFO_NULL = 0,
    SRM_MM_SIZE_INFO_SD,
    SRM_MM_SIZE_INFO_720P,
    SRM_MM_SIZE_INFO_1080P,
    SRM_MM_SIZE_INFO_LAST_VALID_ENTRY
} SRM_MM_SIZE_MODE_T;

typedef enum
{
	FBM_MMMODE =0,
	FBM_TVMODE,
	FBM_NETMODE
} FBM_MODE_T;
/** Brief of SRM_VDP_INFO_T
 */
typedef struct 
{
    UINT32 u4Enable;
    UINT32 u4Status;
    UINT32 u4ColorFormat444;
    UINT32 u4VgaTiming;
    UINT32 u4Source;
    UINT32 u4SourceId;
    UINT32 u4MpegResolution;
    UINT32 u4Resolution;
	UINT32 u4InputWidth;
	UINT32 u4InputHeight;
    UINT32 u4Interlace;
    UINT32 u4OutputWidth;
    UINT32 u4OutputHeight;
    UINT32 u4InputSrcWidthRatio;
    UINT32 u4InputSrcHeightRadio;
    UINT32 u4InputFrameRate;

    UINT32 u4NoSignal;
} SRM_VDP_INFO_T;

typedef struct
{
    UINT32 u4Arg1;
    UINT32 u4Arg2;
    UINT32 u4Arg3;
} SRM_VDP_CTRL_PRM_T;

typedef struct
{
    UINT32 u4CtrlMode[SRM_FEATURE_CTRL_NS];
    SRM_VDP_CTRL_PRM_T rPrm[SRM_FEATURE_CTRL_NS];
    SRM_VDP_CTRL_PRM_T rNewPrm[SRM_FEATURE_CTRL_NS];
} SRM_VDP_CRTL_T;

typedef struct
{
    UINT32 u4Valid[SRM_FEATURE_CTRL_NS];
    SRM_VDP_CTRL_PRM_T u4Value[SRM_FEATURE_CTRL_NS];
    SRM_VDP_CTRL_PRM_T u4Mask[SRM_FEATURE_CTRL_NS];
} SRM_CLI_CRTL_T;

typedef UINT32 (*FN_SRN_DB_RULE) (SRM_VDP_INFO_T*, SRM_VDP_CRTL_T*);

typedef struct
{
    UINT32 u4Reserved : 14;
    UINT32 u4TotalFlag : 1;
    UINT32 fg32Bit : 1;
    UINT32 u4GroupId : 8;
    UINT32 u4AgentId : 8;
} SRM_DRAM_MONITER_T;

//-----------------------------------------------------------------------------
// Inter-file functions
//-----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// Public functions
//-----------------------------------------------------------------------------

EXTERN void SRM_Init(void);

EXTERN void SRM_Pause(void);

EXTERN void SRM_Resume(void);

EXTERN void SRM_SendEvent(UINT32 u4Arg1, UINT32 u4Arg2, UINT32 u4Arg3, UINT32 u4Arg4);

EXTERN void SRM_RegisterCB(UINT32 u4Mod, FN_SRN_CALLBACK pfCbFun);

EXTERN void SRM_RegisterStableCB(FN_SRN_CALLBACK pfCbFun);

EXTERN void SRM_DramInit(void);

EXTERN UINT32 SRM_DramMonitor(UINT32 u4Channel, UINT32 u4Mod, UINT32 u4DelayClock, UINT32 u4MonitorDelay);

EXTERN SRM_TV_MODE_T SRM_GetTvMode(void);

EXTERN void SRM_SetTvMode(SRM_TV_MODE_T eMode);

EXTERN SRM_FREEZE_MODE_T SRM_GetFreezeMode(UINT32 u4VdpId);

EXTERN SRM_VDP_INFO_T* SRM_GetVdpInfo(UINT32 u4VdpId);

EXTERN SRM_VDP_CRTL_T* SRM_GetVdpCtrl(UINT32 u4VdpId);

EXTERN UINT32 SRM_CheckVGABandwidth(UINT32 u4ActiveWidth, UINT32 u4ActiveHeight, UINT32 u4ReflashRate);

EXTERN void SRM_QueryStatus(void);

EXTERN void SRM_CStatus(void);//ctc

EXTERN UINT32 SRM_IsEpgMode(VOID);
#if (defined(CC_MT5890)||defined(CC_MT5891)||defined(CC_MT5893)||defined(CC_MT5886)||defined(CC_MT5895)) && defined(CC_SUPPORT_4K2K)  
EXTERN UINT32 SRM_IsMenuListMode(VOID);
#endif

EXTERN UINT32 SRM_IsMainVerticalFull(VOID);

EXTERN UINT32 SRM_IsDualVideo(void);

EXTERN UINT32 SRM_IsPipVideo(void);

EXTERN UINT32 SRM_IsPopVideo(VOID);
EXTERN BOOL SUPPORT_PipPopMode(VOID);
EXTERN UINT32 SRM_IsGameMode(UINT32 u4VdpId);
EXTERN UINT32 VDP_Get121Map(UCHAR ucVdpId);
EXTERN UINT32 SRM_IsScanMode(UINT32 u4VdpId);
EXTERN UINT32 SRM_IsEnterScanMode(UINT32 u4VdpId);

#if defined(CC_DOWN_BW_WITH_MENU)
EXTERN UINT32 SRM_IsDownBWMode(void);
#endif

EXTERN UINT32 SRM_IsPauseMode(void);
EXTERN UINT32 SRM_GetCurrFBMMode(void);
    
EXTERN UINT32 SRM_GetMMSizeMode(UINT32 u4VdpId);

EXTERN UINT32 SRM_ISMMBufChg(UINT32 u4VdpId);

EXTERN VOID SRM_CLRMMBufChg(UINT32 u4VdpId);

#if defined(CC_DTV_HD_DOT_BY_DOT)
EXTERN UINT32 SRM_IsForce2Zoom(void);

EXTERN void SRM_ClrZoomDBDChg(void);

EXTERN UINT32 SRM_IsForce2DotByDot(void);
#endif

EXTERN UINT32 SRM_IsVideoStrictStable(void);

EXTERN UINT32 SRM_IsMainVideoStrictStable(void);

EXTERN UINT32 SRM_IsSubVideoStrictStable(void);

EXTERN UINT32 SRM_IsVideoStable(void);

EXTERN UINT32 SRM_CheckStable(SRM_VDP_INFO_T* prSrmVdpInfo);

EXTERN VOID SRM_LoadRule(FN_SRN_DB_RULE **papfStableRule, UINT32 *pu4StableRuleNs,
                         FN_SRN_DB_RULE **papfNotStableRule, UINT32 *pu4NotStableRuleNs);

EXTERN UINT32 SRM_CheckDisplayMode(UINT32 u4Source, UINT32 u4Resolution,
                                   UINT32 u4InputFrameRate, UINT32 u4VgaTiming,
                                   UINT32 u4Interlace);

EXTERN UINT32 SRM_CheckMddiMode(UINT32 u4Source, UINT32 u4Resolution,
                                UINT32 u4InputFrameRate, UINT32 u4Interlace);

EXTERN UINT32 SRM_SramSetMode(UINT32 u4Mode);

EXTERN UINT32 SRM_SramSetPool(UINT32 u4MainSrc, UINT32 u4POPMode,
                              UINT32 u4MainScaleUp, UINT32 u4SubScaleUp);

EXTERN VOID SRM_SramQuery(VOID);

EXTERN VOID SRM_QuesyFifoStatus(VOID);

EXTERN VOID SRM_ResetFifoStatus(VOID);

EXTERN SRM_MM_MODE_T SRM_GetMmMode(VOID);

EXTERN VOID SRM_SetMmMode(SRM_MM_MODE_T eMode);

EXTERN UINT32 SRM_Is3DModel(VOID);

EXTERN SRM_MM_MODE_T SRM_GetMmModeByPath(UINT32 u4VdpId);
EXTERN VOID SRM_SetMmModeByPath(UINT32 u4VdpId, SRM_MM_MODE_T eMode);

#if defined(CC_MT5399) || defined(CC_MT5398) || defined(CC_MT5880) || defined(CC_MT5882) || defined(CC_MT5890)||defined(CC_MT5865)||defined(CC_MT5891)||defined(CC_MT5893)||defined(CC_MT5886) || defined(CC_MT5863) || defined(CC_MT5895)
EXTERN UINT32 SRM_GetScposMode(UINT32 u4VdpId);
EXTERN UINT32 SRM_GetMddiMode(UINT32 u4VdpId);
EXTERN UINT32 SRM_GetScposHPDSize(UINT32 u4VdpId);
#endif

EXTERN void SRM_CliSetDispMode(UINT32 u4VdpId, UINT32 u4Mode);
EXTERN void SRM_TriggerCliSrm(UINT32 u4VdpId);
EXTERN void SRM_ClearCliSetting(void);
EXTERN UINT32 SRM_IsMJCWidthLimit(VOID);

EXTERN UINT32 SRM_IsSubVideoDisplay(VOID);

UINT32 SRM_IsHybridMode(UINT32 u4VdpId);
UINT8 SRM_DualMode8Bit(void);
SRM_TV_MODE_T SRM_GetApplicationMode(VOID);

EXTERN UINT32 SRM_IsSmallWindow(VOID);

#endif    // SRM_DRVIF_H

