//***************************************************************************
//!file     si_cra_cfg.h
//!brief    Silicon Image Device CRA configuration data.
//
// No part of this work may be reproduced, modified, distributed, 
// transmitted, transcribed, or translated into any language or computer 
// format, in any form or by any means without written permission of 
// Silicon Image, Inc., 1060 East Arques Avenue, Sunnyvale, California 94085
//
// Copyright 2008-2010, Silicon Image, Inc.  All rights reserved.
//***************************************************************************/

#ifndef __SI_CRA_CFG_H__
#define __SI_CRA_CFG_H__
#include "si_common.h"

typedef enum _deviceBusTypes_t
{
    // The following four must remain together because they are used
    // as bus indices for the CraWriteBlockI2c and CraReadBlockI2c functions
    DEV_I2C_0,          // Main I2C bus
    DEV_I2C_1,          // Separate I2C bus
    DEV_I2C_2,          // Separate I2C bus
    DEV_I2C_3,          // Separate I2C bus

    // The following four must remain together because they are used
    // as bus indices for the CraWriteBlockI2c and CraReadBlockI2c functions
    // with the formula offsetBusTypeX - DEV_I2C_OFFSET == DEV_I2C_x
    DEV_I2C_OFFSET,     // Main I2C bus with register offset
    DEV_I2C_1_OFFSET,   // Separate I2C bus
    DEV_I2C_2_OFFSET,   // Separate I2C bus
    DEV_I2C_3_OFFSET,   // Separate I2C bus

    DEV_DDC_0,          // DDC bus for TX 0

    DEV_I2C_ADDR16,     // Main I2C bus, 16 bit register address
} deviceBusTypes_t;

// Actual I2C page addresses for the various devices
// TODO:OEM - If a device ID has been reassigned, update it here AND in
//            the g_siiRegPageBaseReassign[] array
typedef enum _devicePageIds_t
{
    DEV_PAGE_PP_0       = (0xB0),
    DEV_PAGE_IPV        = (0xFA),
    DEV_PAGE_PP_2       = (0x66),
    DEV_PAGE_PP_5       = (0x50),
    DEV_PAGE_PP_6       = (0x52),
    DEV_PAGE_PP_7       = (0x54),
    DEV_PAGE_PP_9       = (0xE2), //0xE0 confilict panel
    DEV_PAGE_PP_A       = (0x64),
    DEV_PAGE_PP_B       = (0x90),
    DEV_PAGE_CBUS       = (0xE6),

    DEV_PAGE_DDC_EDID   = (0xA0),
    DEV_PAGE_DDC_SEGM   = (0x60),
} devicePageIds_t;

// Virtual page addresses.
// Index into pageConfig_t array (shifted left by 8)
typedef enum _SiiRegPageIndex_t
{
    PP_PAGE_0           = 0x0000,   // Port Processor base address
    PP_PAGE_ARC         = PP_PAGE_0,
    PP_PAGE_IPV         = 0x0100,   // IPV
    PP_PAGE_2           = 0x0200,   // RX TMDS
    PP_PAGE_5           = 0x0300,   // PA1
    PP_PAGE_PAUTH1      = 0x0300,   // same as PP_PAGE_5
    PP_PAGE_6           = 0x0400,   // PA2
    PP_PAGE_PAUTH2      = 0x0400,   // same as PP_PAGE_6
    PP_PAGE_7           = 0x0500,   // PA3
    PP_PAGE_PAUTH3      = 0x0500,   // same as PP_PAGE_7
    PP_PAGE_9           = 0x0600,   // NVRAM
    PP_PAGE_EDID        = 0x0600,   // Same as PP_PAGE_9
    PP_PAGE_GPIO        = 0x0600,   // Same as PP_PAGE_9
    PP_PAGE_MHL         = 0x0600,   // Same as PP_PAGE_9
    PP_PAGE_A           = 0x0700,   // RX TMDS
    PP_PAGE_B           = 0x0800,   // TX TMDS
    CBUS_PAGE           = 0x0900,   // CBUS
    TX_PAGE_DDC_EDID    = 0x0A00,   // TX DDC EDID
    TX_PAGE_DDC_SEGM    = 0x0B00,   // TX DDC EDID Segment address

} SiiRegPageIndex_t;

#define SII_CRA_MAX_DEVICE_INSTANCES    1   // Maximum size of instance dimension of address descriptor array
#define SII_CRA_DEVICE_PAGE_COUNT       12  // Number of entries in pageConfig_t array

typedef struct pageConfig
{
    deviceBusTypes_t    busType;    // I2C, Parallel
    int_t               address;    // I2C DEV ID, parallel mem offset
} pageConfig_t;

#endif  // __SI_CRA_CFG_H__
