/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _H_DRV_HDMI2P1_H_
#define _H_DRV_HDMI2P1_H_

#define DEF_HDMI21_PORT_START_INDEX             HDMI_SWITCH_3
#define DEF_HDMI21_PORT_END_INDEX               HDMI_SWITCH_4
#define DEF_HDMI21_FRL_RATE_DOWN_EN           0

#define DEF_HDMI21_MAX_FRL_RATE                 6   // 0: not support FRL;
                                                    // 1: supports 3L3G;
                                                    // 2: supports 3L3G/3L6G;
                                                    // 3: supports 3L3G/3L6G/4L6G;
                                                    // 4: supports 3L3G/3L6G/4L6G/4L8G;
                                                    // 5: supports 3L3G/3L6G/4L6G/4L8G/4L10G;
                                                    // 6: supports 3L3G/3L6G/4L6G/4L8G/4L10G/4L12G;
                                                    // 7~15: reserved;

#define DEF_HDMI21_DSC_MAX_FRL_RATE             6   // 0: not support FRL;
                                                    // 1: supports 3G;
                                                    // 2: supports 3L6G;
                                                    // 3: supports 4L6G;
                                                    // 4: supports 8G;
                                                    // 5: supports 10G;
                                                    // 6: supports 12G;
                                                    // 7~15: reserved;

#define DEF_HDMI21_TIMER_INTERVAL               5       // Enter timer handler every 10ms

#define DEF_HDMI21_WAIT_FRL_RATE_TIMEOUT_TIMER  10000   // FLT flow should be finished in 200ms
#define DEF_HDMI21_FLT_TIMEOUT_TIMER            5000    // FLT flow should be finished in 200ms

#define DEF_HDMI21_WAIT_FRL_RATE_TICK_CNT       (DEF_HDMI21_WAIT_FRL_RATE_TIMEOUT_TIMER/DEF_HDMI21_TIMER_INTERVAL)
#define DEF_HDMI21_FLT_TIMER_TICK_CNT           (DEF_HDMI21_FLT_TIMEOUT_TIMER/DEF_HDMI21_TIMER_INTERVAL)

#define DEF_HDMI21_BG_DUMP_ERROR_STATUS_EN      0

//CTS:CED
#define DEF_HDMI21_SCDC_CED_FIELD_BYTE_NUM      9   // maximum 4 lane (2-byte for each lane) + 1-byte checksum = 9
#define DEF_HDMI21_SCDC_CED_REC_CNT_MAX         10

//CTS:RS
#define DEF_HDMI21_SCDC_RS_ERR_TYPE_NUM         5
#define DEF_HDMI21_SCDC_H50_READ_CNT_LIMIT      4



#define DEF_HDMI21_FLT_FSM_WAIT_PLL             4   // HW internal Training state
                                                    // 0 : IDLE
                                                    // 1 : LTP_34_REQ
                                                    // 2 : LTP_5678_REQ
                                                    // 3 : SW_ST1
                                                    // 4 : WAIT_PLL
                                                    // 5 : WAIT_CAL_FFE
                                                    // 6 : SW_ST2
                                                    // 7 : CHK_FFE_DONE
                                                    // 8 : LTP_E_REQ
                                                    // 9 : WAIT_CHK_DEC
                                                    // 10 : LTP_F_REQ
                                                    // 11 : LTP_0_REQ
                                                    // 12 : WAIT_CHK_SB
                                                    // 13 : CHK_FFE
                                                    // 14 : LTP_E_REQ2
                                                    // 15 : FRL_TRAIN_DONE
#define HDMI21_SUPPORT_VRR
#define HDMI21_SHM_EMP_DMA_MEM_NUM_MAX 3
#define HDMI21_SHM_EMP_DMA_MEM_SIZE 0x1280
///HDMI EMP maxim numbers
#define HDMI21_EM_PACKET_VRR_NUM_MAX 74
#define HDMI21_EM_PACKET_HDR_NUM_MAX 74
#define HDMI21_EMP_ORGANIZATION_ID_OFFSET 5
#define HDMI21_EMP_FIRST_FLAG_OFFSET 1
#define HDMI21_EMP_LAST_FLAG_OFFSET 1
#define HDMI21_EMP_LAST_FLAG_BIT 6
#define HDMI21_EMP_FIRST_FLAG_BIT 7
#define HDMI21_FIRST_HB_PB_SIZE 32
#define HDMI21_EMP_CTA_861_G_HDR_TYPE_OFFSET 10
#define HDMI21_EMP_DOLBY_FIRST_EMP_MD0_MD5 (6)
#define HDMI21_EMP_DOLBY_FIRST_EMP_INFO_SIZE (7)
#define HDMI21_EMP_DOLBY_FIRST_EMP_MD_SIZE (21)
#define HDMI21_EMP_DOLBY_SUBSEQUENT_EMP_MD_SIZE (28)
#define HDMI21_EMP_DOLBY_VSEM_EDR_DATA_OFFSET   (13)
#define HDMI21_SHM_EMP_DMA_MEM_SIZE_MAX (HDMI21_SHM_EMP_DMA_MEM_SIZE * HDMI21_SHM_EMP_DMA_MEM_NUM_MAX)
#define MACRO_H21_GET_PORT_OFFSET(x)    ((x >= DEF_HDMI21_PORT_START_INDEX) ? (x - DEF_HDMI21_PORT_START_INDEX) : 0x00)

typedef enum
{
    E_HDMI21_EMP_ORGANIZATION_ID_VENDOR_SPECIFIC = 0,
    E_HDMI21_EMP_ORGANIZATION_ID_SPEC = 1,
    E_HDMI21_EMP_ORGANIZATION_ID_CTA_861_G = 2,
    E_HDMI21_EMP_ORGANIZATION_ID_VESA = 3,

    E_HDMI_XC_EMP_ORGANIZATION_ID_RESERVED = 4,
} E_HDMI21_EMP_ORAGNIZATION_ID;

typedef struct
{
    UINT8 u8PB27;//pb27,md(20)
    UINT8 u8PB26;//pb26
    UINT8 u8PB25;//pb25
    UINT8 u8PB24;//pb24
    UINT8 u8PB23;//pb23
    UINT8 u8PB22;//pb22
    UINT8 u8PB21;//pb21
    UINT8 u8PB20;//pb20
    UINT8 u8PB19;//pb19
    UINT8 u8PB18;//pb18
    UINT8 u8PB17;//pb17
    UINT8 u8PB16;//pb16
    UINT8 u8PB15;//pb15
    UINT8 u8PB14;//pb14
    UINT8 u8PB13;//pb13
    UINT8 u8PB12;//pb12
    UINT8 u8PB11;//pb11
    UINT8 u8PB10;//pb10
    UINT8 u8PB9;//pb09
    UINT8 u8PB8;//pb08
    UINT8 u8PB7;//pb07,md(0)
    UINT8 u8PB6;//pb06,data_set_length_lsb
    UINT8 u8PB5;//pb05,data_set_length_msb
    UINT8 u8PB4;//pb04,data_set_tag_lsb
    UINT8 u8PB3;//pb03,data_set_tag_msb
    UINT8 u8PB2;//pb02,Organization_ID
    UINT8 u8PB1;//pb01
    UINT8 u8PB0;//pb00
    UINT8 u8HB2;//hd02, sequence_index
    UINT8 u8HB1;//hd01
    UINT8 u8HB0;//hd00=0x7F
    UINT8 u8ID;//ID
} HDMI_DMA_EMP_T;

typedef struct
{
    UINT8   u8CurDolbyEmpIndex;     // Indicate the current index of EMP DRAM BUFFER where Dolby EMPs are stored
    UINT8   *pu8DolbyEmpBuffer;     // Store Dolby EMPs copy from EMP DRAM BUFFER
    UINT16  u16DolbyEmpSize;
    UINT16  u16DolbyEmpMaxSize;
    UINT8   *pu8DolbyVsemBuffer;    // Store Dolby VS-EMDS retrieved from Dolby EMPs
    UINT16  u16DolbyVsemSize;
    UINT16  u16DolbyVsemMaxSize;
} HDMI21_HDR_DOLBY_METADATA_INFO;

enum
{
    HDMI21_TXFFE_LVL_0 = 0,
    HDMI21_TXFFE_LVL_1,
    HDMI21_TXFFE_LVL_2,
    HDMI21_TXFFE_LVL_3
};

enum
{
    HDMI21_DATA_LANE_0 = 0,
    HDMI21_DATA_LANE_1,
    HDMI21_DATA_LANE_2,
    HDMI21_DATA_LANE_3,
    HDMI21_DATA_LANE_MAX
};

enum
{
    HDMI21_LTS1_IDLE_STATE = HDMI_STABLE_STATE + 1,
    HDMI21_LTS2_WAIT_FRL,
    HDMI21_LTS3_PROC_FRL,
    HDMI21_LTS3_PROC_FRL_TXFFE_TRAIN,
    HDMI21_LTS4_FRL_RATE_UPDATED,
    HDMI21_LTSP_FRL_DONE,
    HDMI21_LTSL_SWITCH_TO_LEGACY_MODE,
    HDMI21_LTS_NONE
};

enum
{
    HDMI21_TIMING_DET_STAT_HSYNC_POL_CHG    = BIT0,
    HDMI21_TIMING_DET_STAT_VSYNC_POL_CHG    = BIT1,
    HDMI21_TIMING_DET_STAT_HSYNC_WIDTH_CHG  = BIT2,
    HDMI21_TIMING_DET_STAT_HFRNT_CHG        = BIT3,
    HDMI21_TIMING_DET_STAT_HDE_CHG          = BIT4,
    HDMI21_TIMING_DET_STAT_HTT_CHG          = BIT5,
    HDMI21_TIMING_DET_STAT_VSYNC_WIDTH_CHG  = BIT6,
    HDMI21_TIMING_DET_STAT_VFRNT_CHG        = BIT7,
    HDMI21_TIMING_DET_STAT_VDE_CHG          = BIT8,
    HDMI21_TIMING_DET_STAT_VTT_CHG          = BIT9,
    //HDMI21_TIMING_DET_STAT_HSYNC_POL_CHG_SC = BIT10,
    //HDMI21_TIMING_DET_STAT_HWIDTH_CHG_SC    = BIT11,
    //HDMI21_TIMING_DET_STAT_HFRNT_CHG_SC     = BIT12,
    //HDMI21_TIMING_DET_STAT_HDE_CHG_SC       = BIT13,
    //HDMI21_TIMING_DET_STAT_HTT_CHG_SC       = BIT14
};

/*
The enum value is assigned according to the define from audio channel status
     27  26  25  24
    "0   1   0   0" - Fs = 22.05 kHz
    "0   0   0   0" - Fs = 44.1 kHz
    "1   0   0   0" - Fs = 88.2 kHz
    "1   1   0   0" - Fs = 176.4 kHz
    "0   1   1   0" - Fs = 24 kHz
    "0   0   1   0" - Fs = 48 kHz
    "1   0   1   0" - Fs = 96 kHz
    "1   1   1   0" - Fs = 192 kHz
    "0   0   1   1" - Fs = 32 kHz
    "1   0   0   1" - Fs = 768 kHz (192 x 4) for High Bit Rate Audio
    "?   ?   ?   ?" - Fs = 84 kHz (94 x 4) for High Bit Rate Audio
    "0   0   0   1" - Fs = Sampling frequency not indicated
*/
typedef enum
{
    HDMI21_AUD_SAMPLE_RATE_44_1KHZ  = 0,
    HDMI21_AUD_SAMPLE_RATE_UNKNOWN  = 1,
    HDMI21_AUD_SAMPLE_RATE_48KHZ    = 2,
    HDMI21_AUD_SAMPLE_RATE_32KHZ    = 3,
    HDMI21_AUD_SAMPLE_RATE_22_05KHZ = 4,
    HDMI21_AUD_SAMPLE_RATE_24KHZ    = 6,
    HDMI21_AUD_SAMPLE_RATE_88_2KHZ  = 8,
    HDMI21_AUD_SAMPLE_RATE_768KHZ   = 9,
    HDMI21_AUD_SAMPLE_RATE_96KHZ    = 10,
    HDMI21_AUD_SAMPLE_RATE_176_4KHZ = 12,
    HDMI21_AUD_SAMPLE_RATE_192KHZ   = 14
} ENUM_HDMI21_AUD_SAMPLE_RATE;

typedef enum
{
    HDMI21_TDET_SPOT_DC_OUT_2P = 0,
    HDMI21_TDET_SPOT_DC_OUT_8P_L,
    HDMI21_TDET_SPOT_DC_OUT_8P_FRL,
    HDMI21_TDET_SPOT_TGEN_OUT,
    HDMI21_TDET_SPOT_DC_INPUT_2P,
    HDMI21_TDET_SPOT_DC_INPUT_2P_L,
    HDMI21_TDET_SPOT_DC_INPUT_2P_FRL,
    HDMI21_TDET_SPOT_AVGFF_OUTPUT
} ENUM_HDMI21_TIMING_DET_SPOT;

typedef enum
{
    HDMI21_RX_CLRSPC_UNKNOW,
    HDMI21_RX_CLRSPC_444,
    HDMI21_RX_CLRSPC_422,
    HDMI21_RX_CLRSPC_420
} ENUM_HDMI21_VP_COLOR_FORMAT;

typedef enum
{
    HDMI21_VP_2PLR_OUT,
    HDMI21_VP_1P_OUT,
    HDMI21_VP_8P_OUT,
} ENUM_HDMI21_VP_OUT_PATH_NUM;

typedef enum
{
    HDMI21_VP_861G_OUT,
    HDMI21_VP_CCIR_OUT
}ENUM_HDMI21_VP_OUT_TIMING;

typedef struct _HDMI21_AUD_HANDLER_T
{
    UINT8 u1PreAudSamplingRate;
    UINT8 u1AudSamplingRate;
    UINT8 u1CodingType;
    BOOL  fgIsPCM;
    BOOL  fgAudModeChg;
    UINT8 u1chNum;
} HDMI21_AUD_HANDLER_T;

typedef struct
{
    UINT16  u2PreSymbolErrCnt16B18B[DEF_HDMI_MAX_DATA_LANE_NUM];
    UINT16  u2SymbolErrCnt16B18B[DEF_HDMI_MAX_DATA_LANE_NUM];
    UINT16  u2SRSSBPeriod[DEF_HDMI_MAX_DATA_LANE_NUM];
    UINT8   u1PreWBDetectFSM[DEF_HDMI_MAX_DATA_LANE_NUM];
    UINT8   u1WBDetectFSM[DEF_HDMI_MAX_DATA_LANE_NUM];
    UINT8   u1PreWBDetLoseStatus[DEF_HDMI_MAX_DATA_LANE_NUM];
    UINT8   u1WBDetLoseStatus[DEF_HDMI_MAX_DATA_LANE_NUM];
    UINT8   u1SymbolLockStatus[DEF_HDMI_MAX_DATA_LANE_NUM];
    UINT8   u1InterSkewLock;
    UINT8   u1PreInterSkewUnlock;
    UINT8   u1InterSkewUnlock;
    UINT16  u2FRLVTT;
    UINT16  u2FRLHTT;
    UINT16  u2FRLVDE;
    UINT16  u2FRLHDE;
    UINT16  u2TmdsVTT;
    UINT16  u2TmdsHTT;
    UINT16  u2TmdsVDE;
    UINT16  u2TmdsHDE;
    UINT16  u2PixelVTT;
    UINT16  u2PixelHTT;
    UINT16  u2PixelVDE;
    UINT16  u2PixelHDE;
} HDMI21_ERR_DET_STAT_T;//HdmiV21ErrDetStat_t;

typedef struct
{
   UINT8 u1TimingIdx;
   UINT16 u2HDE;
   UINT16 u2VDE;
   UINT8 u1FrameRate;
   UINT8 u1InterClk;
   UINT8 u12PLROutClk;
   UINT8 u11POutClk;
   ENUM_HDMI21_VP_COLOR_FORMAT _ColorFmt;
   ENUM_HDMI21_VP_OUT_PATH_NUM     _OutPath;
   BOOL bDitherEn;
   BOOL bTruncEn;
   BOOL b422TuningMode;
   ENUM_HDMI21_VP_OUT_TIMING   _OutTiming;
}HDMI21_VP_TIMING_T;

typedef struct
{
    BOOL bCEDTimerStartFlag;
    UINT8 u1RecRdPt[HDMI21_DATA_LANE_MAX];
    UINT8 u1RecWrPt[HDMI21_DATA_LANE_MAX];
    UINT16 u2RecCEDList[HDMI21_DATA_LANE_MAX][DEF_HDMI21_SCDC_CED_REC_CNT_MAX];
} HDMI21_CTS_CED_RECORD_T;

typedef struct
{
    BOOL u1SCDC_h59_AccessFlag;
    UINT8 u1SCDCh59ReadCnt;
    UINT16 u2StoredFECDecCnt;
    UINT16 u2FECDecReportCnt;
} HDMI21_CTS_RS_RECORD_T;

typedef struct
{
    UINT8 u1CEDChkSum;
    UINT16 u2StoredREDRMDCnt[HDMI21_DATA_LANE_MAX];
    UINT16 u2ReportREDRMDCnt[HDMI21_DATA_LANE_MAX];
    UINT8 u1SCDC_h50_AccessCnt;
    UINT8 u1CEDByteCnt;
    UINT8 u1CEDLaneCnt;
    UINT8 u1ISROffset;
    BOOL bFLTNoRetrainFlag;
    BOOL bClearRSCCFlag;
    BOOL bClrREDRMDErrorFlag;
    HDMI21_CTS_CED_RECORD_T _Hdmi21CEDRecST;
    HDMI21_CTS_RS_RECORD_T _Hdmi21RSRecST;
} HDMI21_CTS_CONTEXT_T;

typedef struct
{
    UINT8 u1LossCnt;
} H21_AVI_PKT_CONTEXT;


typedef struct
{
    BOOL                    _fgTxFFEStartFlag;
    UINT8                   _u1VSIFCnt;
    UINT8                   _u1HFVSIFCnt;
    HDMI21_CTS_CONTEXT_T    _Hdmi21CTSContext;
    HDMI21_ERR_DET_STAT_T   _Hdmi21ErrDetStatObj;
    HDMI21_AUD_HANDLER_T    _Hdmi21RxAudHandler;
    HDMI21_VP_TIMING_T      _Hdmi21VPTIMING;
    UINT8                   _u1VPTimingIdx;
    UINT8                   _u1FRLSigStableCnt;
    UINT8                   _u1FRLSigUnStableCnt;
    UINT8                   _u1FRLTimingChgCnt;
    UINT8                   _u1WaitFRLSigStableCnt;
    UINT8                   _u1FrameRateUnstableCnt;
    UINT8                   _u1HdmiIPModeStableCnt;
    UINT8                   _u1H21SigRetryCnt;
#if DEF_HDMI21_FRL_RATE_DOWN_EN
    UINT8                   _u1H21LinkErrCnt;
#endif
    BOOL                    _bWaitFRLSigStableDone;
    BOOL                    _bFRLPLLDoneFlag;
    BOOL                    _bInterlaceMode;
    H21_AVI_PKT_CONTEXT     _AVIPktContext;
    BOOL                    fg1stFFE2ndTrain;
    UINT8                   u1MaxOptFFE;
    UINT8                   u1KickFFECnt;
} HDMI21_CONTEXT_T;//HdmiV21Context_t;

typedef struct __attribute__((packed))
{
    BOOL    bInit;
    UINT64  u8PhyBaseAddr;
    UINT32  u4Size;
    UINT8   u1MiuSel;
    UINT8*  pu1VirBaseAddr;
    UINT8*  pu1VirBaseAddrCached;
} HDMI21_SHARE_MEMORY_INFO;

/**
 * @brief        HDMI 2.1 digital initial setting by port index
 * @param        ePort ---- port index
*/
extern void vHDMI21ComMacInitSinglePort(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 digital initial setting
*/
extern void vHDMI21MacInit(void);

/**
 * @brief        HDMI 2.1 software initial setting by port index
 * @param        ePort ---- port index
*/
extern void vHDMI21InitSinglePort(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 initial setting (software + hardware)
*/
extern void vHDMI21Init(void);

/**
 * @brief        HDMI 2.1 get FRL rate
 * @param        ePort ---- port index
 * @retval       FRL rate, ex: 3L3G, 3L6G..etc;
*/
extern UINT8 u1HDMI21GetFRLRate(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 get FRL rate
 * @param        ePort ---- port index
 * @retval       Audio sampling rate, ex: 32Khz, 48Khz,..etc.
*/
extern UINT8 u1HDMI21GetAudSamplingRate(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 get FRL mode flag
 * @param        ePort ---- port index
 * @retval       flag to indicate if HDMI is on FRL mode or not;
*/
extern BOOL fgHDMI21GetFRLMode(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 get AFIFO status
 * @param        ePort ---- port index
 * @retval       return TRUE if HDMI afifo is underflow or overflow
*/
extern BOOL fgHDMI21AudFifoFault(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 get FRL 3 lane mode flag
 * @param        ePort ---- port index
 * @retval       flag to indicate if FRL is under 3 lane mode;
*/
extern BOOL fgHDMI21IS3LaneMode(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        print video infomation of HDMI v2.1
 * @param        ePort ---- port index
*/
extern void vHDMI21PrintHdmiVideoStatus(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        print audio infomation of HDMI v2.1
 * @param        ePort ---- port index
*/
extern void vHDMI21PrintHdmiAudioStatus(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        print general infomation of HDMI v2.1
 * @param        ePort ---- port index
*/
extern void vHDMI21PrintHdmiGeneralStatus(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        print error detect status of HDMI v2.1
 * @param        ePort ---- port index
*/
extern void vHDMI21PrintErrorDetectStatus(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        print all infomation of HDMI v2.1
 * @param        ePort ---- port index
*/
extern void vHDMI21PrintHdmiStatus(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        Adjust link quality check timer
 * @param        ePort ---- port index
 * @param        u2StartTimerOffset ---- offset of timer start value
 * @param        u2EndTimerOffset ---- offset of timer end value
*/
extern void vHDMI21SetCheckLinkQaulityTimer(E_HDMI_SWITCH_NUM ePort, UINT16 u2StartTimerOffset, UINT16 u2EndTimerOffset);

/**
 * @brief        Adjust link quality check timer
 * @param        ePort ---- port index
 * @param        fgEnableBypass ---- flag to bypass or not bypass check
*/
extern void vHDMI21BypassFLTDecoderChk(E_HDMI_SWITCH_NUM ePort, BOOL fgEnableBypass);

/**
 * @brief        Dump HDMI v2.1 error status
 * @param        ePort ---- port index
*/
extern void vHDMI21DumpDebugInfo(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        Adjust link quality check timer
 * @param        ePort ---- port index
 * @param        fgEnableBypass ---- flag to bypass or not bypass check
*/
extern void vHDMI21BypassFLTSRSSBChk(E_HDMI_SWITCH_NUM ePort, BOOL fgEnableBypass);

/**
 * @brief        Set VP timing Index
 * @param        ePort ---- port index
 * @param        u1VPTimingIdx ---- VP timing index
*/
extern void vHDMI21SetVPTimingIndex(E_HDMI_SWITCH_NUM ePort, UINT8 u1VPTimingIdx);

/**
 * @brief        search VP timing
 * @param        pstHdmi21RxObj ---- HDMI2.1 timing info
*/
extern UINT8 u1HDMI21SearchVPTiming(HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        Configurate video processor
 * @param        ePort ---- port index
 * @param        pVpTiming ---- VP info
*/
extern void vHDMI21ConfigVideoProcessor(E_HDMI_SWITCH_NUM ePort, const HDMI21_VP_TIMING_T* pVpTiming);

/**
 * @brief        dump debug info of CED CTS testing items
*/
extern void vHDMI21CTSDBGDumpCEDInfo(void);

/**
 * @brief        dump debug info of RS CTS testing items
*/
extern void vHDMI21CTSDBGDumpRSInfo(void);

/**
 * @brief        Set SCDC offset address which is used to trigger ISR
 * @param        eHdmiPort---- HDMI port number
 * @param        u1SCDCISROffset---- SCDC offset
*/
extern void vHDMI21SetSCDCISROffset(E_HDMI_SWITCH_NUM ePort, UINT8 u1SCDCISROffset);

/**
 * @brief        Dump timing detect info of different timing detect spot
 * @param        eHdmiPort---- HDMI port number
 * @param        u1TDetSpot---- Timing detect spot
*/
extern void vHDMI21DbgDumpTimingDetectInfo(E_HDMI_SWITCH_NUM ePort, UINT8 u1TDetSpot);

/**
 * @brief        Dump timing detect info of different timing detect spot
 * @param        ePort ---- HDMI port number
 * @param        u1EnableFlag ---- enable flag
 * @param        u1PGType ---- pattern gen type
*/
extern void vHDMI21EnablePatternGen(E_HDMI_SWITCH_NUM ePort, UINT8 u1EnableFlag, UINT8 u1PGType);

/**
 * @brief        Read packet content for all packets
*/
extern void vHDMI21ReadInfoframes(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief        Get HDMI21 infoframe for hdmi_if interface
 * @param        eHdmiPort---- HDMI port number
 * @param        *ptInfo---- Pointer to HdmiRxInfo_t
 * @param        u1Type---- Infoframe type, see HdmiInfoFrameID_t
 * @retval
*/
extern UINT8 bHDMI21GetInfoFrameToIF(E_HDMI_SWITCH_NUM ePort, HdmiRxInfo_t *ptInfo, UINT8 u1Type);
/**
 * @brief        Get HDMI v2.1 state machine
 * @param        ePort ---- HDMI port number
 * @retal        HDMI v2.1 state
*/
extern UINT8 vHDMI21GetStateMachine(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        Set HDMI v2.1 state machine
 * @param        ePort ---- HDMI port number
 * @param        u1HdmiSta ---- HDMI v2.1 state
*/
extern void vHDMI21SetStateMachine(E_HDMI_SWITCH_NUM ePort, UINT8 u1HdmiState);

/**
 * @brief        Set HDMI v2.1 FLT_Ready field
 * @param        ePort ---- HDMI port number
 * @param        fgEnable ---- set or clear FLT_Ready field
*/
extern void vHDMI21SetFLTReadyFlag(E_HDMI_SWITCH_NUM ePort, BOOL fgEnable);

/**
 * @brief        Check HDMI DSC enable flag and do DSC settings
 * @param        ePort ---- HDMI port number
*/
extern void vHDMI21DscSetting(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI v2.1 main loop
*/
extern void vHDMI21MainLoop(E_HDMI_SWITCH_NUM   eHdmi21Port);

/**
 * @brief        HDMI v2.1 suspend
*/
extern void HDMI21_pm_suspend(void);
/**
 * @brief        HDMI v2.1 resume
*/
extern void HDMI21_pm_resume(void);
/**
 * @brief        Set HDMI2.0 MAC to VP path
 * @param        ePort ---- HDMI port number
 * @param        fgHDMI20VpEn ---- set or clear HDMI2.0 to VP path
*/
extern void vHDMI21VPHDMI20PathEn(E_HDMI_SWITCH_NUM ePort, BOOL fgHDMI20VpEn);
/**
 * @brief        Get HDMI2.1 420 mode
 * @param        ePort ---- HDMI port number
*/
extern BOOL fgHDMI21Get420Mode(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief        Get HDMI2.1 422 mode
 * @param        ePort ---- HDMI port number
*/
extern UINT8 bHDMI21422Input(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief        Get HDMI2.1 infoframe for hdmi_if interface
 * @param        eHdmiPort---- HDMI port number
 * @param        *ptInfo---- Pointer to HdmiRxInfo_t
 * @param        u1Type---- Infoframe type, see HdmiInfoFrameID_t
 * @retval
*/
extern UINT8 bHDMI21GetInfoFrameToIF(E_HDMI_SWITCH_NUM ePort, HdmiRxInfo_t *ptInfo, UINT8 u1Type);
/**
 * @brief        Get HDMI2.1 get scan info
 * @param        ePort ---- HDMI port number
*/
extern UINT8 bHDMI21ScanInfo(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief        Get HDMI2.1 get AFD info
 * @param        ePort ---- HDMI port number
*/
extern UINT8 bHDMI21AFD(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        Get HDMI2.1 ITC flag
 * @param        ePort ---- HDMI port number
*/
extern UINT8 bHDMI21ITCFlag(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        Get HDMI2.1 ITC content
 * @param        ePort ---- HDMI port number
*/
extern UINT8 bHDMI21ITCContent(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        Get HDMI2.1 get RGB Input
 * @param        ePort ---- HDMI port number
*/
extern UINT8 bHDMI21RgbInput(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief        Get HDMI2.1 get aspect ratio
 * @param        ePort ---- HDMI port number
*/
extern UINT8 bHDMI21AspectRatio(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief        Get HDMI2.1 get deep color status
 * @param        ePort ---- HDMI port number
*/
extern HdmiRxBitDepth_t bHDMI21DeepColorStatus(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief        Get HDMI2.1 get audio channel number
 * @param        ePort ---- HDMI port number
*/
extern UINT8 bHDMI21GetAudChannelNum(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief        Get HDMI2.1 get range
 * @param        ePort ---- HDMI port number
*/
extern UINT8 bHDMI21RgbRange(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        vHDMI21HDREMPHandler
 * @param     ePort ---- HDMI port number
*/
extern void vHDMI21HDREMPHandler(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief        vHDMI21EMPIsrHandler
 * @param     ePort ---- HDMI port number
*/
extern void vHDMI21EMPIsrHandler(E_HDMI_SWITCH_NUM u1Port);
/**
 * @brief        vHDMI21UnMapEmpDMAShm
 * @param     None
*/
extern void vHDMI21UnMapEmpDMAShm(void);
/**
 * @brief        vHDMI21SetEmpDMAShmInfor
 * @param     None
*/
extern void vHDMI21SetEmpDMAShmInfor(void);
/**
 * @brief     vHDMI21SignalStableMonitor
 * @param     ePort ---- HDMI port number
*/
//extern void vHDMI21SignalStableMonitor(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief     bIsHDMI21Stable
 * @param     ePort ---- HDMI port number
*/
extern UINT8 bIsHDMI21Stable(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief     bIsHDMI212PMode
 * @param     ePort ---- HDMI port number
*/
extern UINT8 bIsHDMI212PLRMode(E_HDMI_SWITCH_NUM ePort);
/**
 * @brief     bdolbyCRCSwCal32
 * @param
*/
extern BOOL bdolbyCRCSwCal32(const UINT8 *pu8Data, const UINT32 u32Size, UINT32 *pu32CRC);
/**
 * @brief     vHDMI21AudOutSel
 * @param
*/
extern void vHDMI21AudOutSel(BOOL bEn);
extern void vHDMI21InterruptsEnable(E_HDMI_SWITCH_NUM ePort, BOOL bEnable);

extern BOOL fgHDMI21AudDsdOn(void);
extern BOOL fgHDMI21AudHbrOn(void);
extern UINT8 bHDMI21AudStatus(void);
extern UINT8 u1HDMI21SearchVRRBaseTimig(E_HDMI_SWITCH_NUM eHdmiPort);
extern UINT8 u1HDMI21GetVPTimingIndex(E_HDMI_SWITCH_NUM ePort);
extern UINT32 u32HDMI21GetVTotal(E_HDMI_SWITCH_NUM eHdmiPort);
extern UINT32 u32HDMI21GetFrameRate(E_HDMI_SWITCH_NUM eHdmiPort);

extern void vHDMI21SetIGain(E_HDMI_SWITCH_NUM ePort, UINT8 u1Igain);
extern void vHDMI21SetPGain(E_HDMI_SWITCH_NUM ePort, UINT8 u1Pgain);
extern void vHDMI21ClkPathSel(E_HDMI_SWITCH_NUM eHdmiPort);
#endif //#ifndef _H_DRV_HDMI2P1_H_
