/*----------------------------------------------------------------------------*
 * No Warranty                                                                *
 * Except as may be otherwise agreed to in writing, no warranties of any      *
 * kind, whether express or implied, are given by MTK with respect to any MTK *
 * Deliverables or any use thereof, and MTK Deliverables are provided on an   *
 * "AS IS" basis.  MTK hereby expressly disclaims all such warranties,        *
 * including any implied warranties of merchantability, non-infringement and  *
 * fitness for a particular purpose and any warranties arising out of course  *
 * of performance, course of dealing or usage of trade.  Parties further      *
 * acknowledge that Company may, either presently and/or in the future,       *
 * instruct MTK to assist it in the development and the implementation, in    *
 * accordance with Company's designs, of certain softwares relating to        *
 * Company's product(s) (the "Services").  Except as may be otherwise agreed  *
 * to in writing, no warranties of any kind, whether express or implied, are  *
 * given by MTK with respect to the Services provided, and the Services are   *
 * provided on an "AS IS" basis.  Company further acknowledges that the       *
 * Services may contain errors, that testing is important and Company is      *
 * solely responsible for fully testing the Services and/or derivatives       *
 * thereof before they are used, sublicensed or distributed.  Should there be *
 * any third party action brought against MTK, arising out of or relating to  *
 * the Services, Company agree to fully indemnify and hold MTK harmless.      *
 * If the parties mutually agree to enter into or continue a business         *
 * relationship or other arrangement, the terms and conditions set forth      *
 * hereunder shall remain effective and, unless explicitly stated otherwise,  *
 * shall prevail in the event of a conflict in the terms in any agreements    *
 * entered into between the parties.                                          *
 *---------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
 * Copyright (c) 2005, MediaTek Inc.
 * All rights reserved.
 *
 * Unauthorized use, practice, perform, copy, distribution, reproduction,
 * or disclosure of this information in whole or in part is prohibited.
 *-----------------------------------------------------------------------------
 *
 * $Author: xiaojun.zhu $
 * $Date: 2015/08/08 $
 * $RCSfile: dmx_if.h,v $
 * $Revision: #2 $
 *
 *---------------------------------------------------------------------------*/

/** @file gcpu_if.h
 *  Interface of gcpu driver
 */


#ifndef GCPU_IF_H
#define GCPU_IF_H

//-----------------------------------------------------------------------------
// Include files
//-----------------------------------------------------------------------------
#include "x_typedef.h"

//-----------------------------------------------------------------------------
// Configurations
//-----------------------------------------------------------------------------
//#define CC_EMULATION

//-----------------------------------------------------------------------------
// Constant definitions
//-----------------------------------------------------------------------------
#define CSS_CMD_SID             (0x0 << 8)
#define CPPM_CMD_SID            (0x1 << 8)
#define AES_CMD_SID             (0x2 << 8)
#define VCPS_CMD_SID            (0x3 << 8)
#define AACS_CMD_SID            (0x4 << 8)
#define TDES_CMD_SID            (0x5 << 8)
#define BDRE_CMD_SID            (0x6 << 8)
#define EFUSE_CMD_SID           (0x7 << 8)
#define MISC_CMD_SID            (0x8 << 8)
#define SW_CMD_SID              (0x9 << 8)

#define GCPU_FIFO_ALIGNMENT     (32)
//-----------------------------------------------------------------------------
// Type definitions
//-----------------------------------------------------------------------------
enum
{
    S_GCPU_OK,
    E_GCPU_NO_RES,
    E_GCPU_PARAM_WRONG,
    E_GCPU_UNEXPECT,
    E_GCPU_OS_OPERA_FAIL,
    E_GCPU_OVER_LIMIT,
    E_GCPU_OPERATE_FORBID,
    E_GCPU_CMD_FAIL,
    E_GCPU_NO_MEM,
    E_GCPU_INV_ARG,
    E_GCPU_PAGE_FAULT,
    E_GCPU_FAIL,
};

enum
{
    GCPU_CSS_AUTH_DRV = CSS_CMD_SID,
    GCPU_CSS_AUTH_DEC,
    GCPU_CSS_AUTH_BK,
    GCPU_CSS_DEC_DK,
    GCPU_CSS_DEC_TK,
    GCPU_CSS_DSC_AV,
};

enum
{
    GCPU_AES_D = AES_CMD_SID,
    GCPU_AES_E,
    GCPU_AESPK_D,
    GCPU_AES_G,
    GCPU_AES_DPAK,
    GCPU_AES_CMAC,
    GCPU_AESPK_DPAK,
    GCPU_AES_EPAK,
    GCPU_AES_D_CMP,
    GCPU_AESPK_E,
    GCPU_AESEK_E,
    GCPU_AESPK_EPAK,
    GCPU_AESPK_DCBC,
    GCPU_AESPK_ECBC,
    GCPU_AESEK_D,
    GCPU_AES_DCBC,
    GCPU_AES_ECBC,
    GCPU_AESPK_EK_D,
    GCPU_AESPK_EK_E,
    GCPU_AESPK_EK_DCBC,
    GCPU_AES_H,
    GCPU_AES_CTR,
    GCPU_AES_OFB,
    GCPU_AES_WRAPD,
    GCPU_AES_WRAPE,
    GCPU_AES,
};

enum
{
    GCPU_C2_D = CPPM_CMD_SID,
    GCPU_C2_E,
    GCPU_C2_H,
    GCPU_C2_G,
    GCPU_CPPM_DPAK,
    GCPU_CPRM_DPAK,
    GCPU_CPRM_EPAK,
    GCPU_CPRM_DCI_VFY,
};

enum
{
    GCPU_VCPS_HASH = VCPS_CMD_SID,
    GCPU_VCPS_DPAK,
    GCPU_VCPS_EPAK,
    GCPU_VCPS_DKBH,
    GCPU_VCPS_DHDK,
    GCPU_VCPS_DCBC,
    GCPU_VCPS_ECBC,
};

enum
{
    GCPU_IF_READ = EFUSE_CMD_SID,
    GCPU_IF_WRITE,
};

enum
{
    GCPU_TDES_D = TDES_CMD_SID,
    GCPU_TDES_E,
    GCPU_TDES_DMA_D,
    GCPU_TDES_DMA_E,
    GCPU_TDES_CBC_D,
    GCPU_TDES_CBC_E,
    GCPU_TDES,
};

enum
{
    GCPU_AACS_DBD = AACS_CMD_SID,
    GCPU_AACS_EBD,
    GCPU_AACS_DTN,
    GCPU_AACS_ETN,
    GCPU_AACS_DHD,
    GCPU_AACS_EHD,
    GCPU_AACS_DV_CALC,
};

enum
{
    GCPU_BDRE_DBD = BDRE_CMD_SID,
    GCPU_BDRE_EBD,
    GCPU_BDRE_DTN,
    GCPU_BDRE_ETN,
    GCPU_BDRE_BE,
};

enum
{
    GCPU_MEMCPY = MISC_CMD_SID,
    GCPU_DMA,
    GCPU_SHA_1,
    GCPU_SHA_256,
    GCPU_MD5,
    GCPU_SHA_224,
    GCPU_HMAC_SHA_256,
    GCPU_MEM_XOR,
    GCPU_RNG,
    GCPU_RC4_KSA,
    GCPU_RC4,
    GCPU_ROM_BIST,
    GCPU_PTX,
    GCPU_TSDESC,
    GCPU_TSSCRM,
    GCPU_RSA,
    GCPU_SECU,
    GCPU_DMXDMA,
    GCPU_SLOTDM,
};

typedef enum
{
    HASH_FIRST_PACKET_MODE,
    HASH_SUCCESSIVE_PACKET_MODE,
} HASH_MODE;

typedef enum
{
    CPRM_HASH_FIRST_PACKET_MODE,
    CPRM_HASH_SUCCESSIVE_PACKET_MODE,
} CPRM_HASH_MODE;

typedef enum
{
    DESCRAMBLE_MODE_OFF,
    DESCRAMBLE_MODE_ON,
    DESCRAMBLE_MODE_AUTO,
    DESCRAMBLE_MODE_RESERVED,
} DESCRAMBLE_MODE;

typedef enum
{
    CPRM_CIPHER_MODE_OFF,
    CPRM_CIPHER_MODE_ON,
    CPRM_CIPHER_MODE_AUTO,
    CPRM_CIPHER_MODE_RESERVED,
} CPRM_CIPHER_MODE;

typedef enum
{
    BLOCK_CIPHER_MODE_ECB,
    BLOCK_CIPHER_MODE_CBC,
    BLOCK_CIPHER_MODE_OFB,
    BLOCK_CIPHER_MODE_CTR,
    BLOCK_CIPHER_MODE_CBC_FRAME,
    BLOCK_CIPHER_MODE_CTR_WRAP,
} BLOCK_CIPHER_MODE;

typedef enum
{
    KEY_BIT_LEN_40 = 40,
    KEY_BIT_LEN_64 = 64,
    KEY_BIT_LEN_128 = 128,
    KEY_BIT_LEN_192 = 192,
    KEY_BIT_LEN_256 = 256,
} KEY_BIT_LEN;

typedef enum
{
	PHASE_1st = 0,
	PHASE_2nd = 1,
	PHASE_3rd = 2,
}HMAC_MODE_PHASE;

typedef enum
{
    AES_CMAC_ONE_PASS_COMPLETE_MODE,
    AES_CMAC_ONE_PASS_REMAINDER_MODE,
    AES_CMAC_START_MODE,
    AES_CMAC_UPDATE_MODE,
    AES_CMAC_FINALIZE_COMPLETE_MODE,
    AES_CMAC_FINALIZE_REMAINDER_MODE,
} AES_CMAC_MODE;

typedef enum
{
    CSS_AV_MODE_OFF,
    CSS_AV_MODE_ON,
    CSS_AV_MODE_AUTO,
    CSS_AV_MODE_RESERVED,
} CSS_AV_MODE;

typedef enum
{
    BDRE_ALWAYS_OFF_MODE,
    BDRE_ALWAYS_ON_MODE,
    BDRE_DEPEND_ON_PACKET_MODE,
    BDRE_DEPEND_ON_CCI_MODE,
} BDRE_MODE;

typedef enum
{
    DMA_MODE_FROM_DRAM_TO_DMEM = 1 | 8,
    DMA_MODE_FROM_DRAM_TO_IMEM = 5 | 8,
    DMA_MODE_FROM_IMEM_TO_DRAM = 7 | 8,
} DMA_MODE;

typedef enum
{
    SECUDM_SECU_TO_DMEM = 0x1,
    SECUDM_DMEM_TO_SECU = 0x3,
    SECUDM_SECU_TO_DMEM_CIR = 0x9,
    SECUDM_DMEM_TO_SECU_CIR = 0xB,
} SECU_MODE;

typedef enum
{
	SLOT_TO_DMEM = 0x1,
	DMEM_TO_SLOT = 0x3,	
}SLOT_MODE;

typedef enum
{
    DMX_TO_DMEM = 0x1,
    DMEM_TO_DMX = 0x3,
    DMX_TO_DMEM_CIR = 0x9,
    DMEM_TO_DMX_CIR = 0xB,
}DMX_MODE;

typedef enum
{
    PTX_FIRST_BYTE_MODE,
    PTX_SUCCESSIVE_BYTES_MODE,
} PTX_MODE;

typedef enum
{
    BLOCK_CIPHER_EMU_MODE_ECB,
    BLOCK_CIPHER_EMU_MODE_GEN,
    BLOCK_CIPHER_EMU_MODE_CMAC,
} BLOCK_CIPHER_EMU_MODE;

typedef enum
{
    TSDESC_188_PACKET_FORM,
    TSDESC_192_PACKET_FORM,
} TSDESC_PACKET_FORM;

typedef enum
{
    TSDESC_FIRST_PACKET_MODE,
    TSDESC_SUCCESSIVE_PACKET_MODE,
} TSDESC_PACKET_MODE;

typedef enum
{
    TSDESC_DESC_SCHEME_CLEAR = 0x0,
    TSDESC_DESC_SCHEME_EVEN_KEY = 0x2,      ///< only in encryption
    TSDESC_DESC_SCHEME_ODD_KEY = 0x3,       ///< only in encryption
    TSDESC_DESC_SCHEME_EVEN_ODD_KEY = 0x4,  ///< only in decryption
    TSDESC_DESC_SCHEME_CBC_SCTE52 = 0xE,
    TSDESC_DESC_SCHEME_CTR = 0xF,
} TSDESC_DESC_SCHEME;

typedef enum
{
    TSDESC_CIPHER_CLEAR = 0x0,
    TSDESC_CIPHER_ECB,
    TSDESC_CIPHER_CBC,
    TSDESC_CIPHER_CBC_SCTE52,     ///< only in decryption
    TSDESC_CIPHER_CTR             ///< only in decryption
} TSDESC_CIPHER_MODE;

typedef enum
{   
    RSA_MODE_KEY_1024 = 0x0,
    RSA_MODE_KEY_2048,
}RSA_MODE;

typedef enum
{
    RSA_C_ARRAY_CALC_MODE_GENERATE = 0x0,
    RSA_C_ARRAY_CALC_MODE_SPECIFIED,   
}RSA_C_ARRAY_CALC_MODE;

typedef enum
{
    DATA_SRC_DRAM = 0x0,
    DATA_SRC_DMX,
    DATA_SRC_SECU,
    DATA_SRC_SRAM,
}DATA_SRC_TYPE;

typedef enum
{
    KEY_SRC_DMEM = 0x0,
    KEY_SRC_SECUSRAM,
    KEY_SRC_EFUSE,
}KEY_SRC_TYPE;
//
// CSS
//
typedef struct
{
    UINT8 au1RDK[5];
    UINT8 au1EDK[5];
    UINT8 au1Res[4];
} CSS_DK_PARAM_T;

typedef struct
{
    UINT8 au1ETK[5];
} CSS_TK_PARAM_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    CSS_AV_MODE eMode;
} CSS_AV_PARAM_T;

typedef struct
{
    UINT8 au1CD[10];
    UINT8 au1RD[5];
    UINT32 u4ACC;
} CSS_AUTH_PARAM_T;

//
// CPPM/CPRM
//
typedef struct
{
    UINT8 au1Key[8];
    UINT8 au1Dat[8];
    UINT8 au1Res[8];
} C2_PARAM_T;


typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UINT32 u4DatLen;
    BOOL fgFirstPacket;
    BOOL fgLastPacket;
    UINT8 au1Hash[8];
} C2_HASH_PARAM_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    CPRM_CIPHER_MODE eMode;
    UINT8 au1Key[8];
    UINT32 u4APSTB;
} CPRM_PARAM_T;

typedef struct
{
    UINT8 au1KT[8];
    UINT8 au1DCI[8];
    UINT8 au1DTKC[8];
    UINT8 au1Res[8];
} CPRM_DCICCI_PARAM_T;

typedef enum
{
    CALC_FIRST_COUNTER_VALUE = 0x0,
    CALC_ADD_HASH_DATA = 0x2,
    MESS_ENC_DECRYPTION = 0x4,
    MESS_AUTHENTICATION = 0x8,
}AES_GCM_CALC_MODE;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4DstStartAddr;
	UPTR u4IvAddr;
	UPTR u4AADAddr;
    UINT32 u4DatLen;
	UINT32 u4IvLen;
	UINT32 u4AADLen;
    UINT8 au1Key[32];
	UINT8 au1Ctr[16];	
	UINT8 au1Tag[16];
    KEY_BIT_LEN eKeyBitLen;
	//AES_GCM_CALC_MODE eCalcMode;
	UINT32 u4CalcMode;
	UINT32 u4PacketMode;
    BOOL fgEncrypt;
} AES_GCM_PARAM_T;

typedef struct
{
    BOOL fgEncrypt;
    UPTR u4SrcAddr;
    UPTR u4DstAddr;
    UINT32 u4DatLen;
    KEY_BIT_LEN eKeyBitLen;
    UINT32 au4Key1[8];
    UINT32 au4Key2[8];
    UINT32 au4Tweak[4];
} AES_XTS_PARAM_T;

//
// AES
//
typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    UINT8 au1Key[32];
    UINT8 au1Iv[16];
    KEY_BIT_LEN eKeyBitLen;
    BLOCK_CIPHER_MODE eMode;
    BOOL fgEncrypt;
    UINT32 u4FrameLen;
    DATA_SRC_TYPE eDataSrcType;
    UINT32 u4SrcMmuTblAddr;
    UINT32 u4DstMmuTblAddr;

    BOOL fgNewAesIP;
    BOOL fgSm4;
    BOOL fgBlkRng;
    UINT32 u4BlkRngRnd;
} AES_PARAM_T;

typedef struct
{
    UINT8 au1Dat[16];
    UINT8 au1Res[16];
    UINT8 au1Key[32];
    KEY_BIT_LEN eKeyBitLen;
    UINT32 u4SecureKeyPtr;
} SIM_AES_PARAM_T;

typedef struct
{
    UINT8 au1Dat[16];
    UINT8 au1Res[16];
    UINT8 au1Key[32];
    KEY_BIT_LEN eKeyBitLen;
    UINT32 u4CmpRes;
    UINT32 u4Value;
} AES_DCMP_PARAM_T;

//
// VCPS
//
typedef struct
{
    UINT8 au1Key[16];
    UINT8 au1Dat[16];
    UINT8 au1Res[16];
} VCPS_HASH_PARAM_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    DESCRAMBLE_MODE eMode;
    UINT8 au1Key[16];
} VCPS_PARAM_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UINT32 u4DatLen;
    HASH_MODE eMode;
    UINT8 au1HashValue[16];
} VCPS_DKB_HASH_PARAM_T;

typedef struct
{
    UINT8 au1Key[16];
    UINT8 au1Dat[32];
} VCPS_AES_CBC_PARAM_T;

typedef struct
{
    UPTR u4SecureDatPtr;
    UPTR u4SecureResPtr;
} VCPS_DHDK_PARAM_T;

//
// AACS
//
typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    UINT8 au1Uk[16];
    UINT8 au1Iv[16];
} AACS_AV_PARAM_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    UINT8 au1Kt[16];
    UINT8 au1Cpi[12];
    DESCRAMBLE_MODE eMode;
} AACS_HDDVD_PARAM_T;

typedef struct
{
    UINT8 au1Kmsi[16];
    UINT8 au1Xfcr[16];
    UINT8 au1Dkder[16];
    UINT8 au1Dv[12];
    UINT32 u4KmsiSecureSlotPtr;
    UINT32 u4DvSecureSlotPtr;
    UINT32 u4Mode;
    UINT32 u4DVLSB10;
    UINT32 u4Cmp;
} AACS_DVCALC_PARAM_T;


//
// BDRE
//
typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    UINT8 au1Krec[16];
    UINT32 u4Vbkg;
    BDRE_MODE eMode;
    UINT32 u4Cci;
} BDRE_PARAM_T;

typedef struct
{
    UINT8 au1Dat[8];
} BDRE_BE_PARAM_T;

//
// DES
//
typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    UINT8 au1Key[24];
    UINT8 au1Iv[8];
    KEY_BIT_LEN eKeyBitLen;
    BLOCK_CIPHER_MODE eMode;
    BOOL fgEncrypt;
} DES_PARAM_T;


typedef struct
{
    UINT8 au1Dat[16];
    UINT8 au1Res[16];
    UINT8 au1Key[24];
    KEY_BIT_LEN eKeyBitLen;
    UPTR u4SecureKeyPtr;
} SIM_DES_PARAM_T;

//
// MISC
//
typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UINT32 u4DatLen;
    UINT64 u8BitCnt;
    UINT8 au1Hash[32];
    BOOL fgFirstPacket;
    BOOL fgLastPacket;
    DATA_SRC_TYPE eDataSrc;
    UINT32 u4MmuTblAddr;
} MD_PARAM_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UINT32 u4DatLen;
    UINT8 au1Hash[32];
	UINT8 au1Key[64];
	HMAC_MODE_PHASE ePhase;
    DATA_SRC_TYPE eDataSrc;
} HMAC_PARAM_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
} MEMCPY_PARAM_T;

typedef struct
{
    UINT8 au1Key[12];
    UINT32 u4KeyLen;
    UPTR u4keyAddr;
} RC4_KEY_PARAM_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    UINT32 u4ResidualLen;
    UINT8 au1Key[12];
    UPTR u4keyAddr;
    UINT32 u4InitIJ;
    UINT32 au4ResidualBytes[2];
} RC4_PARAM_T;

typedef struct
{
    UPTR u4DramStartAddr;
    UPTR u4DramBufStart;
    UPTR u4DramBufEnd;
    UPTR u4SramStartAddr;
    UINT32 u4DatLen;
    DMA_MODE eMode;
} DMA_PARAM_T;

typedef struct
{
    UPTR u4SecuStartAddr;
    UPTR u4SecuBufStart;
    UPTR u4SecuBufEnd;
    UPTR u4SramStartAddr;
    UINT32 u4DatLen;
    SECU_MODE eMode;
} SECU_PARAM_T;

typedef struct
{
    UPTR u4SlotAddr;
    UPTR u4SramStartAddr;
    UINT32 u4DatLen;
    SLOT_MODE eMode;
} SLOT_PARAM_T;


typedef struct
{
    UPTR u4DmxStartAddr;
    UPTR u4DmxBufStart;
    UPTR u4DmxBufEnd;
    UPTR u4SramStartAddr;
    UINT32 u4DatLen;
    DMX_MODE eMode;
} DMX_PARAM_T;

typedef struct
{
    UINT8 au1Dat[4];
    UINT8 au1Xor[4];
} XOR_PARAM_T;

typedef struct
{
    UINT8 au1Seed[16];
    UINT8 au1Res[16];
} RNG_PARAM_T;

typedef struct
{
    UINT32 u4Res;
} ROBBIST_PARAM_T;

typedef struct
{
    UPTR u4CmdAddr;
    UINT32 u4CmdNum;
    UPTR u4IntStartAddr;
    UPTR u4IntBufStart;
    UPTR u4IntBufEnd;
    PTX_MODE eMode;
    UINT32 u4PicNum;
    UINT32 u4PicStruct[19];
} PTX_PARAM_T;

typedef struct
{
    UINT8 au1Dat[16];
    UINT8 au1Res[16];
    UINT8 au1Key[32];
    KEY_BIT_LEN eKeyBitLen;
    BLOCK_CIPHER_EMU_MODE eMode;
    BOOL fgEncrypt;
    AES_CMAC_MODE eCmacMode;
    UPTR u4SecureKeyPtr;
} AES_EMU_PARAM_T;

typedef struct
{
    UINT32 u4ADR;
    UINT8 *pu1Data;
    UINT8 u1DataLen;
} GCPU_IF_PARAM_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    TSDESC_PACKET_FORM eForm;
    TSDESC_PACKET_MODE eMode;
    TSDESC_CIPHER_MODE eCipher;
    KEY_BIT_LEN eKeyBitLen;
    BOOL fgEncryptByEvenKey;
    UINT32 u4TsState[4];
    UINT8 au1Key[2][16];
    UINT8 au1Iv[2][16];
} TSDESC_PARAM_T;

typedef struct
{
    UPTR u4AesKeyPtr;
    UPTR u4AesIvPtr;
    UPTR u4AesRetIvPtr;
} GCPU_STRUCT_T;

typedef struct
{
    UINT8 au1Hash[32];
    UINT32 u4CompleteSize;
    BOOL fgFirstPacket;
    BOOL fgIOMMU;
} GCPU_SHA_HDL_T;

typedef struct
{
    UINT32 au4KeyExpo[64];
    UINT32 au4KeyModu[64];
} RSA_PKA_KEY_T;

typedef struct
{
    UINT32 au4CArray[64];
} RSA_PKA_ID_T;

typedef struct
{
    UPTR u4SrcStartAddr;
    UPTR u4SrcBufStart;
    UPTR u4SrcBufEnd;
    UPTR u4DstStartAddr;
    UPTR u4DstBufStart;
    UPTR u4DstBufEnd;
    UINT32 u4DatLen;
    RSA_MODE eKeyMode;
    DATA_SRC_TYPE eDataSrc;
    KEY_SRC_TYPE eKeySrc;
    RSA_PKA_KEY_T *prPkaKey;
    RSA_C_ARRAY_CALC_MODE eCArrayMode;
    RSA_PKA_ID_T *prPkaId;
} RSA_PARAM_T;
//-----------------------------------------------------------------------------
// Macro definitions
//-----------------------------------------------------------------------------
#define KEY_WRAPPER(p)  ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))

#define GCPU_LINER_BUFFER_START(u4Addr) (((u4Addr) % GCPU_FIFO_ALIGNMENT) == 0)?(u4Addr): \
                                    (u4Addr) - ((u4Addr) % GCPU_FIFO_ALIGNMENT)

#define GCPU_LINER_BUFFER_END(u4Addr) (((u4Addr) % GCPU_FIFO_ALIGNMENT) == 0)?(u4Addr): \
                                    (u4Addr) + (GCPU_FIFO_ALIGNMENT - ((u4Addr) % GCPU_FIFO_ALIGNMENT))

//-----------------------------------------------------------------------------
// Prototype  of public functions
//-----------------------------------------------------------------------------
EXTERN BOOL GCPU_Init(UINT32 u4Mode);
EXTERN INT32 GCPU_Cmd(UPTR u4Handle, UINT32 u4Cmd, void* pvParam);
EXTERN INT32 GCPU_CmdEx(UPTR u4Handle, UINT32 u4Cmd, void* pvParam, BOOL fgIOMMU);
EXTERN INT32 GCPU_CmdSw(UPTR u4Handle, UINT32 u4Cmd, void* pvParam);
EXTERN UINT32 GCPU_AllocSecureSlot(UINT32 u4Size);
EXTERN INT32 GCPU_FreeSecureSlot(UINT32 u4SlotPtr);
EXTERN INT32 GCPU_SetSecureSlot(UINT32 u4SlotPtr, UINT8* pu1Data, UINT32 u4Size);
EXTERN UPTR GCPU_CreateHandle(void);
EXTERN INT32 GCPU_ClostHandle(UPTR u4Handle);
EXTERN BOOL GCPU_SHA256_Init(UPTR u4Handle, BOOL fgIOMMU);
EXTERN BOOL GCPU_SHA256_Update(UPTR u4Handle, UINT8 *pu1Buf, UINT32 u4Size, BOOL fgLastPacket);
EXTERN BOOL GCPU_SHA256_UpdateEx(UPTR u4Handle, UINT8 *pu1Buf, UINT32 u4Size, BOOL fgLastPacket, UINT32 u4MmuTblAddr);

EXTERN BOOL GCPU_SHA256_Final(UPTR u4Handle, UINT8 au1Digest[32]);
EXTERN BOOL GCPU_RSA_decrypt(UINT8 *pu1Signature, UINT8 *pu1PublicKey, UINT8 *pu1CheckSum, UINT32 e, UINT32 u4Len);
EXTERN INT32 GCPU_AESGCM(UINT32 u4Handle,  void* prParam, BOOL fgIOMMU);
EXTERN INT32 GCPU_AESXTS(UINT32 u4Handle, AES_XTS_PARAM_T *prParam, BOOL fgIOMMU);

#if defined(CC_SUPPORT_STR) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
EXTERN void GCPU_pm_str_suspend(void);
EXTERN void GCPU_pm_str_resume(void);
#endif

#if defined(CC_MTK_PRELOADER) || defined(CC_MTK_LOADER)
BOOL GCPU_LoaderInit(UINT32 u4Mode);
BOOL GCPU_SetAesKey(UINT8 *pu1Key, KEY_BIT_LEN eKeyBitLen, UINT8 *pu1Iv);
BOOL GCPU_AesDecrypt(UINT32 u4InBufStart, UINT32 u4OutBufStart, UINT32 u4BufSize);
BOOL GCPU_AesEncrypt(UINT32 u4InBufStart, UINT32 u4OutBufStart, UINT32 u4BufSize);
BOOL GCPU_SHA256(UINT8 *pu1Buf, UINT32 u4Size, UINT8 Message_Digest[32]);
#endif // defined(CC_MTK_PRELOADER) || defined(CC_MTK_LOADER)

#endif  // GCPU_IF_H

