/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author$
 * $Date$
 * $RCSfile: x_bim.h,v $
 * $Revision$
 *
 *---------------------------------------------------------------------------*/

/** @file x_bim.h
 *  x_bim.h The BIM (Bus Interface Module) interface header file
 */


#ifndef X_BIM_H
#define X_BIM_H

//-----------------------------------------------------------------------------
// Include files
//-----------------------------------------------------------------------------

#include "x_hal_5381.h"
#include "x_typedef.h"

//===========================================================================
// Configuration
//===========================================================================
#define CC_VECTOR_HAS_MISC3

//===========================================================================
// Constant definitions
#define DUALLOADER_A        (0xA55A55AA)
#define DUALLOADER_B        (DUALLOADER_A+1)
#ifdef CC_CP_CUST
#define SECOND_BANK_OFFSET  (4*1024*1024)
#else
#define SECOND_BANK_OFFSET  (2*1024*1024)
#endif

//===========================================================================
// Macros for register read/write

#if defined(YES_BIMSWAP)
#define BIMSWAP(X) ((((X) & 0xf00) > 0x200) ? (X) : (((X) & 0xffffffeb) | (((X) & 0x10) >> 2) | (((X) & 0x4) << 2)))
#else
#define BIMSWAP(X) (X)
#endif

#define BIM_READ8(offset)           IO_READ8(BIM_BASE, BIMSWAP(offset))
#define BIM_READ16(offset)          IO_READ16(BIM_BASE, BIMSWAP(offset))
#define BIM_READ32(offset)          IO_READ32(BIM_BASE, BIMSWAP(offset))

#define BIM_WRITE8(offset, value)   IO_WRITE8(BIM_BASE, BIMSWAP(offset), (value))
#define BIM_WRITE16(offset, value)  IO_WRITE16(BIM_BASE, BIMSWAP(offset), (value))
#define BIM_WRITE32(offset, value)  IO_WRITE32(BIM_BASE, BIMSWAP(offset), (value))

#define BIM_REG8(offset)            IO_REG8(BIM_BASE, BIMSWAP(offset))
#define BIM_REG16(offset)           IO_REG16(BIM_BASE, BIMSWAP(offset))
#define BIM_REG32(offset)           IO_REG32(BIM_BASE, BIMSWAP(offset))

#define GICD_READ8(offset)           IO_READ8(GIC_DIST_BASE, offset)
#define GICD_READ16(offset)          IO_READ16(GIC_DIST_BASE, offset)
#define GICD_READ32(offset)          IO_READ32(GIC_DIST_BASE, offset)

#define GICD_WRITE8(offset, value)   IO_WRITE8(GIC_DIST_BASE, offset, (value))
#define GICD_WRITE16(offset, value)  IO_WRITE16(GIC_DIST_BASE, offset, (value))
#define GICD_WRITE32(offset, value)  IO_WRITE32(GIC_DIST_BASE, offset, (value))

#define GICR_READ8(offset)           IO_READ8(GIC_RDIST_BASE, offset)
#define GICR_READ16(offset)          IO_READ16(GIC_RDIST_BASE, offset)
#define GICR_READ32(offset)          IO_READ32(GIC_RDIST_BASE, offset)

#define GICR_WRITE8(offset, value)   IO_WRITE8(GIC_RDIST_BASE, offset, (value))
#define GICR_WRITE16(offset, value)  IO_WRITE16(GIC_RDIST_BASE, offset, (value))
#define GICR_WRITE32(offset, value)  IO_WRITE32(GIC_RDIST_BASE, offset, (value))


#define GICC_READ8(offset)           IO_READ8(GIC_CPU_BASE, offset)
#define GICC_READ16(offset)          IO_READ16(GIC_CPU_BASE, offset)
#define GICC_READ32(offset)          IO_READ32(GIC_CPU_BASE, offset)

#define GICC_WRITE8(offset, value)   IO_WRITE8(GIC_CPU_BASE, offset, (value))
#define GICC_WRITE16(offset, value)  IO_WRITE16(GIC_CPU_BASE, offset, (value))
#define GICC_WRITE32(offset, value)  IO_WRITE32(GIC_CPU_BASE, offset, (value))

#define TRNG_READ32(offset)          IO_READ32(TRNG_BASE, BIMSWAP(offset))
#define TRNG_WRITE32(offset, value)  IO_WRITE32(TRNG_BASE, BIMSWAP(offset), (value))

#define MCU_READ32(offset)          IO_READ32(MCUSYS_BASE, BIMSWAP(offset))
#define MCU_WRITE32(offset, value)  IO_WRITE32(MCUSYS_BASE, BIMSWAP(offset), (value))

//===========================================================================
// L2C register
#define L2C_READ32(offset)                  IO_READ32(L2C_BASE, offset)
#define L2C_WRITE32(offset, value)          IO_WRITE32(L2C_BASE, offset, value)
#define L2C_WRITE32MSK(offset, value, msk)  IO_WRITE32MSK(L2C_BASE, offset, value, msk)

#define L2C_REG_CONTROL                    0x100
    #define L2C_REG_CONTROL_EN             (1 << 0)
#define L2C_REG_AUX_CONTROL                0x104
    #define L2C_REG_CONTROL_PREFETCH       (0x3 << 28)
    #define L2C_REG_CONTROL_FORCE_ALLOCATE (0x2 << 23)
#define L2C_REG_SYNC                       0x730
#define L2C_REG_INVALIDATE_LINE            0x770
#define L2C_REG_INVALIDATE_WAY             0x77c
#define L2C_REG_CLEAN_LINE                 0x7b0
#define L2C_REG_CLEAN_WAY                  0x7bc
#define L2C_REG_CLEAN_AND_INVALIDATE_LINE  0x7f0
#define L2C_REG_CLEAN_AND_INVALIDATE_WAY   0x7fc
#define L2C_REG_CLEAN_AND_INVALIDATE_WAY   0x7fc
#define L2C_REG_DEBUG                      0xf40
#define L2C_REG_EV_COUNTER_CTRL            0x200
    #define L2C_REG_EV_COUNTER1_RST        (0x1 << 2)
    #define L2C_REG_EV_COUNTER0_RST        (0x1 << 1)
    #define L2C_REG_EV_COUNTING_EN         (0x1 << 0)
#define L2C_REG_EV_COUNTER1_CFG            0x204
#define L2C_REG_EV_COUNTER0_CFG            0x208
    #define L2C_REG_EV_TYPE_BIT_SHIFT      2
    #define L2C_REG_EV_TYPE_CO             (1 << L2C_REG_EV_TYPE_BIT_SHIFT) //Eviction, CastOut, of a line from the L2 cache
    #define L2C_REG_EV_TYPE_DRHIT          (2 << L2C_REG_EV_TYPE_BIT_SHIFT) //Data read hit
    #define L2C_REG_EV_TYPE_DRREQ          (3 << L2C_REG_EV_TYPE_BIT_SHIFT) //Data read request
    #define L2C_REG_EV_TYPE_DWHIT          (4 << L2C_REG_EV_TYPE_BIT_SHIFT) //Data write hit
    #define L2C_REG_EV_TYPE_DWREQ          (5 << L2C_REG_EV_TYPE_BIT_SHIFT) //Data write request
    #define L2C_REG_EV_TYPE_DWTREQ         (6 << L2C_REG_EV_TYPE_BIT_SHIFT) //Data write request with write-through attribute
    #define L2C_REG_EV_TYPE_IRHIT          (7 << L2C_REG_EV_TYPE_BIT_SHIFT) //Instruction read hit
    #define L2C_REG_EV_TYPE_IRREQ          (8 << L2C_REG_EV_TYPE_BIT_SHIFT) //Instruction read request
    #define L2C_REG_EV_TYPE_WA             (9 << L2C_REG_EV_TYPE_BIT_SHIFT) //Write allocate
#define L2C_REG_EV_COUNTER1                0x20c
#define L2C_REG_EV_COUNTER0                0x210

//===========================================================================
// BIM register and bitmap defintions

//----------------------------------------------------------------------------
// PBI bus related registers
#define REG_RO_ICE          0x0000      // RISC ICE Register
    #define ICE_MODE_STATUS (1U << 0)   // ICE mode status, 0: disable, 1: enable
#define REG_RW_REMAP        0x001c      // Remap Register
    #define REMAP_ENABLE    (1)
#define REG_RW_TIMEOUT_CTRL 0x0020      // Timeout Control Register
    #define TO_FLASH_CNT    (0xffU << 24)   // Flash timeout count
    #define TO_DRAM_CNT     (0xffU << 16)   // Dram timeout count
    #define TO_IOBUS_CNT    (0xffU << 8)    // IOBus timeout count
    #define TO_FLASH_EN     (1U << 2)       // Flash timeout enable
    #define TO_DRAM_EN      (1U << 1)       // Dram timeout enable
    #define TO_IOBUS_EN     (1U << 0)       // IOBus timeout enable
#define REG_RW_BTIME            0x0024          // Timeout Control Register
    #define TO_IORW             (0xf << 4)       // IO read wait state count
    #define TO_IOWW             (0xf << 0)       // IO write wait state count

#define REG_MISC2         0x002c         // misc2 register
    #define SMI1_COMMON_CLKEN       (1U << 1)
    #define SMI0_COMMON_CLKEN       (1U << 0)
//----------------------------------------------------------------------------
// IRQ/FIQ registers
#define REG_IRQST           0x0030      // RISC IRQ Status Register
#define REG_RO_IRQST        0x0030      // RISC IRQ Status Register
#define REG_IRQEN           0x0034      // RISC IRQ Enable Register
#define REG_RW_IRQEN        0x0034      // RISC IRQ Enable Register
#define REG_IRQCL           0x0038      // RISC IRQ Clear Register
#define REG_RW_IRQCL        0x0038      // RISC IRQ Clear Register
#define REG_FIQST           0x003c      // RISC IRQ Status Register
#define REG_RO_FIQST        0x003c      // RISC IRQ Status Register
#define REG_FIQEN           0x0040      // RISC IRQ Enable Register
#define REG_RW_FIQEN        0x0040      // RISC IRQ Enable Register
#define REG_FIQCL           0x0044      // RISC IRQ Clear Register
#define REG_RW_FIQCL        0x0044      // RISC IRQ Clear Register

#define SPI_OFFSET          104

// Interrupt vectors
    //#define VECTOR_SPTE     (29)                     //Secure Physical Timer Event
    //#define VECTOR_NSPTE    (30)                     //Not-Secure Physical Timer Event
    #define VECTOR_PDWNC    (0)           // Power Down module Interrupt
    #define VECTOR_SERIAL   (1)           // Serial Interface Interrupt
    #define VECTOR_NAND     (2)           // NAND-Flash interface interrupt
    #define VECTOR_T0       (3)           // Timer 0
    #define VECTOR_T1       (4)           // Timer 1
    #define VECTOR_T2       (5)           // Timer 2
    #define VECTOR_SMCARD0  (6)           // Smart Card Interrupt
    #define VECTOR_WDT      (7)           // watchdog
    #define VECTOR_ENET     (8)           // Ethernet interrupt
    #define VECTOR_MISC3    (9)           // MISC3
    #define VECTOR_MSPI0    (9)           // MSPI0
    #define VECTOR_PSCAN    (10)          // PSCAN interrupt
    #define VECTOR_USB1     (11)          // USB1 Interrupt
    #define VECTOR_IMGRZ5   (12)          // osd IMGRZ interrupt
    #define VECTOR_MSPI1     (11)          // MSPI1 Interrupt

    #define VECTOR_VENC     (13)          // VENC interrupt
    #define VECTOR_SPDIF    (14)          // Audio PSR/SPDIF interrupt
    #define VECTOR_PSR      (14)          // Audio PSR/SPDIF interrupt
    #define VECTOR_USB      (15)          // USB0 Interrupt
    #define VECTOR_USB0     (15)          // USB0 Interrupt
    #define VECTOR_AUDIO    (16)          // Audio DSP interrupt
    #define VECTOR_DSP      (16)          // Audio DSP Interrupt
    #define VECTOR_RS232    (17)          // RS232 Interrupt 1
    #define VECTOR_LED      (18)          // LED interrupt
    #define VECTOR_OSD      (19)          // OSD interrupt
    #define VECTOR_VDOIN    (20)          // Video In interrupt (8202 side)
    #define VECTOR_BLK2RS   (21)          // Block to Raster Interrupt
    #define VECTOR_DISPLAY  (21)          // Block to Raster Interrupt
    #define VECTOR_FLASH    (22)          // Serial Flash interrupt
    #define VECTOR_POST_PROC (23)         // POST process interrupt
    #define VECTOR_TCON     (23)          //TCON interrupt
    #define VECTOR_VDEC     (24)          // VDEC interrupt
    #define VECTOR_GFX      (25)          // Graphic Interrupt
    #define VECTOR_DEMUX    (26)          // Transport demuxer interrupt
    #define VECTOR_DEMOD    (27)          // Demod interrupt enable bit
    #define VECTOR_FCI      (28)          // FCI interrupt
    #define VECTOR_APWM     (29)          // Audio PWM Interrupt
    #define VECTOR_MISC2    (30)          // MISC2 interrupt
    #define VECTOR_MISC     (31)          // MISC interrupt
    #define VECTOR_MSPI2    (30)          // MSPI interrupt
    #define VECTOR_MSPI3     (31)          // MSPI interrupt
    #define VECTOR_MISC_BASE  (32)
    #define VECTOR_MISC2_BASE (64)
    #define VECTOR_MISC3_BASE (96)
    #define VECTOR_MISC4_BASE (128)
    #define VECTOR_MISC5_BASE (160)
    #define VECTOR_MISC6_BASE (192)
    #define VECTOR_DRAMC        (VECTOR_MISC_BASE+0)          // 0. DRAM Controller interrupt
    #define VECTOR_EXT1         (VECTOR_MISC_BASE+1)          // 1. Dedicated GPIO edge interrupt
	#define VECTOR_POD          (VECTOR_MISC_BASE+2)
    #define VECTOR_PMU1         (VECTOR_MISC_BASE+3)
    #define VECTOR_PMU0         (VECTOR_MISC_BASE+4)
    #define VECTOR_PMU          VECTOR_PMU0                   // ARM performance monitor interrupt
    #define VECTOR_DRAMC_CHB    (VECTOR_MISC_BASE+5)          // 5. DRAM Controller 1 interrupt
	#define VECTOR_LD_CH1     (VECTOR_MISC_BASE+2)
    #define VECTOR_LDM_DONE0         (VECTOR_MISC_BASE+3)
    #define VECTOR_LDM_DONE1         (VECTOR_MISC_BASE+4)
    //#define VECTOR_PMU          VECTOR_PMU0                   // ARM performance monitor interrupt
    #define VECTOR_RGB_3D_LUT_BLANK    (VECTOR_MISC_BASE+5)          // 5. DRAM Controller 1 interrupt
    #define VECTOR_TVE          (VECTOR_MISC_BASE+6)          // 6. TVE interrupt
    #define VECTOR_PCIE         (VECTOR_MISC_BASE+7)
	#define VECTOR_SCALER       (VECTOR_MISC_BASE+7)          //7. Scaler interrupt
    #define VECTOR_APWM2        (VECTOR_MISC_BASE+8)          // 8. APWM2 interrupt
    #define VECTOR_SPI          (VECTOR_MISC_BASE+9)          // 9. SPI interrupt
    #define VECTOR_JPGDEC       (VECTOR_MISC_BASE+10)         // 10. Jpeg Decoder interrupt
    #define VECTOR_P            (VECTOR_MISC_BASE+11)         // 11. P interrupt   //MT5395 Parser DMA is 43
    #define VECTOR_AES          (VECTOR_MISC_BASE+12)         // 12. AES interrupt
    #define VECTOR_UP0          (VECTOR_MISC_BASE+12)         // 12. AES 8032 interrupt 0
    #define VECTOR_GCPU			(VECTOR_MISC_BASE+12)		  // 12. GCPU interrupt
    #define VECTOR_TCON_EH      (VECTOR_MISC_BASE+13)         // 13. TCON error
    #define VECTOR_TCON_TCH     (VECTOR_MISC_BASE+14)         // 14. TCON Timing control
    #define VECTOR_OD           (VECTOR_MISC_BASE+15)         // 15. OD
    #define VECTOR_LDM_DMA_DONE3 (VECTOR_MISC_BASE+15)
    #define VECTOR_USB2         (VECTOR_MISC_BASE+16)         // 16. USB2 Interrupt
    #define VECTOR_LED_ADD      (VECTOR_MISC_BASE+16)         // 16. LED_ADD Interrupt
    #define VECTOR_USB3         (VECTOR_MISC_BASE+17)         // 17. USB3 Interrupt
    #define VECTOR_LED_B      (VECTOR_MISC_BASE+16)         // 16. LED_B Interrupt
    #define VECTOR_TCON1_TC         (VECTOR_MISC_BASE+17)         // 17. USB3 Interrupt
    #define VECTOR_PCMCIA       (VECTOR_MISC_BASE+17)        // 17. PCMCIA Interrupt
    #define VECTOR_GDMA         (VECTOR_MISC_BASE+18)         // 18. GDMA
    #define VECTOR_EPHY         (VECTOR_MISC_BASE+19)         // 19. ethernet PHY
    #define VECTOR_TCPIP        (VECTOR_MISC_BASE+20)         // 20. TCPIP checksum
    #define VECTOR_AMBI        (VECTOR_MISC_BASE+20)         // 20. TCPIP checksum
    #define VECTOR_USB3_DEV     (VECTOR_MISC_BASE+21)
    #define VECTOR_GFX3D_GP     (VECTOR_MISC_BASE+21)         // useless
    #define VECTOR_USB3_XHCI    (VECTOR_MISC_BASE+22)
    #define VECTOR_GFX3D_PP     (VECTOR_MISC_BASE+22)         // useless
    #define VECTOR_GFX3D_PMU    (VECTOR_MISC_BASE+23)         // useless
    #define VECTOR_JPGDEC_BITS  (VECTOR_MISC_BASE+23)         //23. JPEGDEC BitsInterrupt
    #define VECTOR_I2C          (VECTOR_MISC_BASE+24)
    #define VECTOR_GFX3D_GPMMU  (VECTOR_MISC_BASE+24)         // useless
    #define VECTOR_USB3_D       (VECTOR_MISC_BASE+24)         // useless
    #define VECTOR_DOLBY        (VECTOR_MISC_BASE+25)
    //#define VECTOR_R2R          (VECTOR_MISC_BASE+25)         // useless
    #define VECTOR_MMU_GFX      (VECTOR_MISC_BASE+26)
    #define VECTOR_GFX_IOMMU      (VECTOR_MISC_BASE+26)
    #define VECTOR_MMU_GCPU     (VECTOR_MISC_BASE+27)
    #define VECTOR_AP_DMA       (VECTOR_MISC_BASE+28)
    #define VECTOR_LDM_DMA_DONE2 (VECTOR_MISC_BASE+29)
    #define VECTOR_MMU_JPG      (VECTOR_MISC_BASE+29)
    #define VECTOR_MMU_GDMA     (VECTOR_MISC_BASE+30)
    #define VECTOR_DDI          (VECTOR_MISC_BASE+31)
    #define VECTOR_LZHS         (VECTOR_MISC2_BASE+0)
    #define VECTOR_SRS          (VECTOR_MISC2_BASE+1)
	#define VECTOR_SFLASH       (VECTOR_MISC2_BASE+1)         // useless
    #define VECTOR_L2C          (VECTOR_MISC2_BASE+1)
    #define VECTOR_IMGRZ        (VECTOR_MISC2_BASE+2)
    #define VECTOR_IMGRZ2       (VECTOR_MISC2_BASE+3)
    #define VECTOR_PNG1         (VECTOR_MISC2_BASE+5)
    #define VECTOR_PNG2         (VECTOR_MISC2_BASE+6)
    #define VECTOR_PNG3         (VECTOR_MISC2_BASE+7)
    #define VECTOR_LD_CH2      (VECTOR_MISC2_BASE+8)
    #define VECTOR_MMU_PNG      (VECTOR_MISC2_BASE+8)
	#define VECTOR_SMCARD1      (VECTOR_MISC2_BASE+9)
	#define VECTOR_PREMJC     (VECTOR_MISC2_BASE+10)
	#define VECTOR_TDDC         (VECTOR_MISC2_BASE+10)
	#define VECTOR_APWM3        (VECTOR_MISC2_BASE+11)
	#define VECTOR_MMU_VDEC     (VECTOR_MISC2_BASE+12)
	#define VECTOR_IRT_DMA      (VECTOR_MISC2_BASE+12)
       #define VECTOR_MMU_DDI      (VECTOR_MISC2_BASE+13)
       #define VECTOR_MMU_DMX      (VECTOR_MISC2_BASE+14)
	#define VECTOR_DDI_IOMMU      (VECTOR_MISC2_BASE+13)
	#define VECTOR_DMX_IOMMU      (VECTOR_MISC2_BASE+14)
    #define VECTOR_PDWNC_TIMER  (VECTOR_MISC2_BASE+15)
	#define VECTOR_USB3_1       (VECTOR_MISC2_BASE+15)      // useless
	#define VECTOR_SSUSB        (VECTOR_MISC2_BASE+15)      // useless
	#define VECTOR_UART_DMA		(VECTOR_MISC2_BASE+16)
	#define VECTOR_RS232_1		(VECTOR_MISC2_BASE+16)
	#define VECTOR_CERT           (VECTOR_MISC2_BASE+17)
	#define VECTOR_ZZ           (VECTOR_MISC2_BASE+19)
	#define VECTOR_RS232_BT      (VECTOR_MISC2_BASE+19)
	#define VECTOR_RS232_0      (VECTOR_MISC2_BASE+19)
	#define VECTOR_LT           (VECTOR_MISC2_BASE+20)      // useless
	#define VECTOR_OSD_INT2     (VECTOR_MISC2_BASE+20)      // useless
	#define VECTOR_OSD_INT3     (VECTOR_MISC2_BASE+21)      // useless
       #define VECTOR_VDEC_LAE0    (VECTOR_MISC2_BASE+21)
	#define VECTOR_VDEC_LAT0    (VECTOR_MISC2_BASE+21)
	#define VECTOR_TRNG         (VECTOR_MISC2_BASE+23)
	#define VECTOR_TRNG_NAGRA         (VECTOR_MISC2_BASE+24)
	#define VECTOR_P_B          (VECTOR_MISC2_BASE+24)
	#define VECTOR_VDEC_IOMMU   (VECTOR_MISC2_BASE+25)      // useless
       #define VECTOR_ABIM_0        (VECTOR_MISC2_BASE+26)
       #define VECTOR_ABIM_1        (VECTOR_MISC2_BASE+27)
       #define VECTOR_ABIM_2        (VECTOR_MISC2_BASE+28)
       #define VECTOR_ABIM_3        (VECTOR_MISC2_BASE+29)
	#define VECTOR_ACPU_AP0        (VECTOR_MISC2_BASE+26)
	#define VECTOR_ACPU_AP1        (VECTOR_MISC2_BASE+27)
	#define VECTOR_ACPU_AP2        (VECTOR_MISC2_BASE+28)
	#define VECTOR_ACPU_AP3        (VECTOR_MISC2_BASE+29)
	#define VECTOR_CI_FMR       (VECTOR_MISC2_BASE+30)
	#define VECTOR_CI_FMR2      (VECTOR_MISC2_BASE+31)

    #define VECTOR_PTP_THERM    (0+VECTOR_MISC3_BASE)
    #define VECTOR_PTP_FSM      (1+VECTOR_MISC3_BASE)
    #define VECTOR_THERMAL0     (0+VECTOR_MISC3_BASE)
    #define VECTOR_THERMAL1     (1+VECTOR_MISC3_BASE)
    #define VECTOR_SC_TIMER     (2+VECTOR_MISC3_BASE)
    #define VECTOR_TOPAXI_SI6_DFSLV_SET_R  (3+VECTOR_MISC3_BASE)
    #define VECTOR_HDMIRX_20    (3+VECTOR_MISC3_BASE)
    #define VECTOR_DRAMC_C       (3+VECTOR_MISC3_BASE)
    #define VECTOR_EXT_EDGE_FIQ   (4+VECTOR_MISC3_BASE)
    #define VECTOR_EXT_INT0     (4+VECTOR_MISC3_BASE)
    #define VECTOR_VDEC_LAT1     (4+VECTOR_MISC3_BASE)
    #define VECTOR_EXT_INT1     (5+VECTOR_MISC3_BASE)
    //#define VECTOR_VDEC_CORE1     (5+VECTOR_MISC3_BASE)
    #define VECTOR_EXT_INT2     (6+VECTOR_MISC3_BASE)
    #define VECTOR_OSD_VSYNC    (7+VECTOR_MISC3_BASE)
    #define VECTOR_OSD2         (8+VECTOR_MISC3_BASE)
    #define VECTOR_OSD3         (9+VECTOR_MISC3_BASE)
    #define VECTOR_TOPAXI_SI6_DFSLV_SET_W    (10+VECTOR_MISC3_BASE)
    #define VECTOR_UFOZIP       (10+VECTOR_MISC3_BASE)
    #define VECTOR_ECBUS        (11+VECTOR_MISC3_BASE)
    #define VECTOR_EARC          (12+VECTOR_MISC3_BASE)
    #define VECTOR_IMGRZ3       (13+VECTOR_MISC3_BASE)
    #define VECTOR_IMGRZ4       (14+VECTOR_MISC3_BASE)
    #define VECTOR_UFOZIP_MMU   (14+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO0   (15+VECTOR_MISC3_BASE)
    #define VECTOR_HDMIRX_A_20  (16+VECTOR_MISC3_BASE)
    #define VECTOR_HDMIRX_B_20  (17+VECTOR_MISC3_BASE)
    #define VECTOR_HDMIRX_C_20  (18+VECTOR_MISC3_BASE)
    #define VECTOR_HDMIRX_D_20  (19+VECTOR_MISC3_BASE)
    #define VECTOR_USB3_0D      (20+VECTOR_MISC3_BASE)
    #define VECTOR_DOLBY_META   (20+VECTOR_MISC3_BASE)
    #define VECTOR_TNR          (21+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO1   (22+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO2   (23+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO3   (24+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO4   (25+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO5   (26+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO6   (27+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO7   (28+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO8   (29+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO9   (30+VECTOR_MISC3_BASE)
    #define VECTOR_ARM_AUDIO10  (31+VECTOR_MISC3_BASE)

    #define VECTOR_R2R          (0+VECTOR_MISC4_BASE)
    #define VECTOR_IEC2         (1+VECTOR_MISC4_BASE)
    #define VECTOR_USB3_DEV_P0  (2+VECTOR_MISC4_BASE)
    #define VECTOR_USB3_XHCI_P0 (3+VECTOR_MISC4_BASE)
    #define VECTOR_USB3_OTG_P0 (4+VECTOR_MISC4_BASE)
    #define VECTOR_OSD_IOMMU    (4+VECTOR_MISC4_BASE)
    #define VECTOR_CI_LINK_ERR   (5+VECTOR_MISC4_BASE)
    #define VECTOR_OSD_R        (5+VECTOR_MISC4_BASE)
    #define VECTOR_CI_LINK2_ERR   (6+VECTOR_MISC4_BASE)
    #define VECTOR_OSD2_R       (6+VECTOR_MISC4_BASE)
    #define VECTOR_FD_IRQ       (7+VECTOR_MISC4_BASE)
    #define VECTOR_OSD3_R       (7+VECTOR_MISC4_BASE)
    #define VECTOR_YUV_HISTG  (8+VECTOR_MISC4_BASE)

    #define VECTOR_MJC          (9+VECTOR_MISC4_BASE)
    #define VECTOR_MJC1          (9+VECTOR_MISC4_BASE)
    #define VECTOR_MJC2          (10+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI0    (10+VECTOR_MISC4_BASE)
    #define VECTOR_MJC3          (11+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI1    (11+VECTOR_MISC4_BASE)
    #define VECTOR_MJC_SYNC      (12+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI2    (12+VECTOR_MISC4_BASE)
    #define VECTOR_PCIE_INT_OUT_P0    (13+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI3    (13+VECTOR_MISC4_BASE)
    #define VECTOR_MJC_CMQ      (13+VECTOR_MISC4_BASE)
    #define VECTOR_APUSYS3    (14+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI4    (14+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI5    (15+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI6    (16+VECTOR_MISC4_BASE)
    #define VECTOR_OSD1    (17+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI7    (17+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI8    (18+VECTOR_MISC4_BASE)
    #define VECTOR_OSD_R_VSYNC    (18+VECTOR_MISC4_BASE)
    #define VECTOR_YUV_HISTG2    (19+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI9    (19+VECTOR_MISC4_BASE)
    #define VECTOR_RS232_INT3   (20+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI10   (20+VECTOR_MISC4_BASE)
    #define VECTOR_DMX_HADDS_27M   (21+VECTOR_MISC4_BASE)
    #define VECTOR_MEMC_AXI11   (21+VECTOR_MISC4_BASE)
    #define VECTOR_MFG_IRQ_B3    (22+VECTOR_MISC4_BASE)
    #define VECTOR_G3D_EVENT    (22+VECTOR_MISC4_BASE)
    #define VECTOR_MFG_IRQ_B2      (23+VECTOR_MISC4_BASE)
    #define VECTOR_G3D_JOB      (23+VECTOR_MISC4_BASE)
    #define VECTOR_MFG_IRQ_B1      (24+VECTOR_MISC4_BASE)
    #define VECTOR_G3D_MMU      (24+VECTOR_MISC4_BASE)
    #define VECTOR_MFG_IRQ_B0      (25+VECTOR_MISC4_BASE)
    #define VECTOR_G3D_GPU      (25+VECTOR_MISC4_BASE)
    #define VECTOR_MMU1         (26+VECTOR_MISC4_BASE)
    #define VECTOR_MMU1_SEC     (27+VECTOR_MISC4_BASE)
    #define VECTOR_MMU2         (28+VECTOR_MISC4_BASE)
    #define VECTOR_MMU2_SEC     (29+VECTOR_MISC4_BASE)
    #define VECTOR_MM1_IOMMU         (26+VECTOR_MISC4_BASE)
    #define VECTOR_MM1_IOMMU_SEC     (27+VECTOR_MISC4_BASE)
    #define VECTOR_MM2_IOMMU         (28+VECTOR_MISC4_BASE)
    #define VECTOR_MM2_IOMMU_SEC     (29+VECTOR_MISC4_BASE)


    #define VECTOR_AOUT_2RISC   (0+VECTOR_MISC5_BASE)
    #define VECTOR_AOUT2_2RISC  (1+VECTOR_MISC5_BASE)
    #define VECTOR_AOUT3_2RISC  (2+VECTOR_MISC5_BASE)
    #define VECTOR_IEC_2RISC    (3+VECTOR_MISC5_BASE)
    #define VECTOR_ASRC_2RISC   (4+VECTOR_MISC5_BASE)
    #define VECTOR_ASRC2_2RISC  (5+VECTOR_MISC5_BASE)
    #define VECTOR_ASRC3_2RISC  (6+VECTOR_MISC5_BASE)
    #define VECTOR_ASRC4_2RISC  (7+VECTOR_MISC5_BASE)
    #define VECTOR_G3D_DVFS     (8+VECTOR_MISC5_BASE)
    #define VECTOR_MFG_DVFS     (8+VECTOR_MISC5_BASE)
    #define VECTOR_DISP_OVL0    (9+VECTOR_MISC5_BASE)
    #define VECTOR_DISP_WDMA0   (10+VECTOR_MISC5_BASE)
    #define VECTOR_DISP_OVL1    (11+VECTOR_MISC5_BASE)
    #define VECTOR_DISP_WDMA1   (12+VECTOR_MISC5_BASE)
    #define VECTOR_VM_TOP_SOM   (13+VECTOR_MISC5_BASE)
    #define VECTOR_VM_TOP_EOM   (14+VECTOR_MISC5_BASE)
    #define VECTOR_VM_TOP_VSYNC (15+VECTOR_MISC5_BASE)
    #define VECTOR_CERT_KTKS    (15+VECTOR_MISC5_BASE)
    #define VECTOR_CERT_KTKS_NONSEC    (16+VECTOR_MISC5_BASE)
    #define VECTOR_VDEC_LAE1    (16+VECTOR_MISC5_BASE)
  //  #define VECTOR_VDEC_CORE1   (17+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB0    (18+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB1    (19+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB2    (20+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB3    (21+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB4    (22+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB5    (23+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB6    (24+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB7    (25+VECTOR_MISC5_BASE)
    #define VECTOR_LARB0    (18+VECTOR_MISC5_BASE)
    #define VECTOR_LARB1    (19+VECTOR_MISC5_BASE)
    #define VECTOR_LARB2    (20+VECTOR_MISC5_BASE)
    #define VECTOR_LARB3    (21+VECTOR_MISC5_BASE)
    #define VECTOR_LARB4    (22+VECTOR_MISC5_BASE)
    #define VECTOR_LARB5    (23+VECTOR_MISC5_BASE)
    #define VECTOR_MEMC_LARB6    (24+VECTOR_MISC5_BASE)
    #define VECTOR_MEMC_LARB7    (25+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB8    (26+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB9    (27+VECTOR_MISC5_BASE)
    #define VECTOR_LARB9    (27+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB10   (28+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB11   (29+VECTOR_MISC5_BASE)
    #define VECTOR_SMI_LARB12   (30+VECTOR_MISC5_BASE)
    #define VECTOR_LARB11   (29+VECTOR_MISC5_BASE)
    #define VECTOR_LARB12   (30+VECTOR_MISC5_BASE)
    #define VECTOR_DISP_AAL     (31+VECTOR_MISC5_BASE)

    #define VECTOR_TRACKER      (0+VECTOR_MISC6_BASE)
    #define VECTOR_DEC_ERR      (1+VECTOR_MISC6_BASE)
    #define VECTOR_SECURE_VIO   (2+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI0_B (3+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI0_R (4+VECTOR_MISC6_BASE)
    #define VECTOR_LARB27 (5+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI1_B (5+VECTOR_MISC6_BASE)
    #define VECTOR_LARB28 (6+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI1_R (6+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI0_R (7+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI0_W (8+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI1_R (9+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI1_W (10+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI2_R (11+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI2_W (12+VECTOR_MISC6_BASE)


    #define VECTOR_SYS_TIMER0   (12+VECTOR_MISC6_BASE)
    #define VECTOR_SYS_TIMER1   (13+VECTOR_MISC6_BASE)
    #define VECTOR_MM3_IOMMU   (13+VECTOR_MISC6_BASE)
    #define VECTOR_MM3_IOMMU_SEC   (14+VECTOR_MISC6_BASE)
    #define VECTOR_SYS_TIMER2   (14+VECTOR_MISC6_BASE)
    #define VECTOR_SYS_TIMER3   (15+VECTOR_MISC6_BASE)
    #define VECTOR_EMI2_DOMAIN_ABT   (15+VECTOR_MISC6_BASE)
    #define VECTOR_SUPER_RES    (16+VECTOR_MISC6_BASE)
    #define VECTOR_DOMAIN_ABT   (17+VECTOR_MISC6_BASE)
    #define VECTOR_EMI_HRT_URGENT   (18+VECTOR_MISC6_BASE)
    #define VECTOR_LARB13_X1  (19+VECTOR_MISC6_BASE)
    #define VECTOR_LARB14_X1  (20+VECTOR_MISC6_BASE)
    #define VECTOR_LARB15  (21+VECTOR_MISC6_BASE)
    #define VECTOR_PERI_GSPI  (22+VECTOR_MISC6_BASE)

    #define VECTOR_GCE0  (24+VECTOR_MISC6_BASE)
    #define VECTOR_GCE0_SEC  (25+VECTOR_MISC6_BASE)
    #define VECTOR_GCE1  (26+VECTOR_MISC6_BASE)
    #define VECTOR_GCE1_SEC  (27+VECTOR_MISC6_BASE)
    #define VECTOR_GCE2  (28+VECTOR_MISC6_BASE)
    #define VECTOR_GCE2_SEC  (29+VECTOR_MISC6_BASE)
    #define VECTOR_GCE3  (30+VECTOR_MISC6_BASE)
    #define VECTOR_GCE3_SEC  (31+VECTOR_MISC6_BASE)
    #define VECTOR_HIFI0  (32+VECTOR_MISC6_BASE)
    #define VECTOR_HIFI1  (33+VECTOR_MISC6_BASE)
    #define VECTOR_LARB16  (34+VECTOR_MISC6_BASE)
    #define VECTOR_LARB17  (35+VECTOR_MISC6_BASE)
    #define VECTOR_LARB18  (36+VECTOR_MISC6_BASE)
    #define VECTOR_LARB19  (37+VECTOR_MISC6_BASE)
    #define VECTOR_LARB20  (38+VECTOR_MISC6_BASE)
    #define VECTOR_LARB21  (39+VECTOR_MISC6_BASE)
    #define VECTOR_LARB22  (40+VECTOR_MISC6_BASE)
    #define VECTOR_LARB23  (41+VECTOR_MISC6_BASE)

    #define VECTOR_IMGRZ_DMA_MULTICH  (43+VECTOR_MISC6_BASE)
    #define VECTOR_HDMI0  (44+VECTOR_MISC6_BASE)
    #define VECTOR_HDMI1  (45+VECTOR_MISC6_BASE)
    #define VECTOR_HDMI2  (46+VECTOR_MISC6_BASE)
    #define VECTOR_HDMI3  (47+VECTOR_MISC6_BASE)
    #define VECTOR_HDMI2P1_C  (48+VECTOR_MISC6_BASE)
    #define VECTOR_HDMI2P1_D  (49+VECTOR_MISC6_BASE)
    #define VECTOR_HDMI2P1_DSC  (50+VECTOR_MISC6_BASE)
    #define VECTOR_APUSYS0  (51+VECTOR_MISC6_BASE)
    #define VECTOR_APUSYS1  (52+VECTOR_MISC6_BASE)
    #define VECTOR_APUSYS2  (53+VECTOR_MISC6_BASE)
    #define VECTOR_IMGRZ0_DMA  (54+VECTOR_MISC6_BASE)
    #define VECTOR_IMGRZ1_DMA  (55+VECTOR_MISC6_BASE)
    #define VECTOR_IMGRZ2_DMA  (56+VECTOR_MISC6_BASE)
    #define VECTOR_IMGRZ3_DMA  (57+VECTOR_MISC6_BASE)
    #define VECTOR_IMGRZ4_DMA  (58+VECTOR_MISC6_BASE)
    #define VECTOR_IMGRZ5_DMA  (59+VECTOR_MISC6_BASE)
    #define VECTOR_IMGRZ6_DMA  (60+VECTOR_MISC6_BASE)
    #define VECTOR_IMGRZ7_DMA  (61+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_SC  (62+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_EXT  (63+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_DIP  (64+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_MSPI0  (65+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_MSPI1  (66+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_MSPI2  (67+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_MSPI3  (68+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_LDDMA0_DONE  (69+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_LDDMA1_DONE  (70+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_LDDMA2_DONE  (71+VECTOR_MISC6_BASE)
    #define VECTOR_SC8K_LDDMA3_DONE  (72+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI4_DFSLV_SET_R  (73+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI4_DFSLV_SET_W  (74+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI5_DFSLV_SET_R  (75+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI5_DFSLV_SET_W  (76+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI7_DFSLV_SET_R  (77+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI7_DFSLV_SET_W  (78+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI9_DFSLV_SET_R  (79+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI9_DFSLV_SET_W  (80+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI10_DFSLV_SET_R  (81+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI10_DFSLV_SET_W  (82+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI11_DFSLV_SET_R  (83+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI11_DFSLV_SET_W  (84+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI12_DFSLV_SET_R  (85+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_SI12_DFSLV_SET_W  (86+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI1_ERRMID_SET_B  (87+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI1_ERRMID_SET_R  (88+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI2_ERRMID_SET_B  (89+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI2_ERRMID_SET_R  (90+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI3_ERRMID_SET_B  (91+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI3_ERRMID_SET_R  (92+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI4_ERRMID_SET_B  (93+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI4_ERRMID_SET_R  (94+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI6_ERRMID_SET_B  (95+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI6_ERRMID_SET_R  (96+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI7_ERRMID_SET_B   (97+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI7_ERRMID_SET_R  (98+VECTOR_MISC6_BASE) 
    #define VECTOR_TOPAXI_MI8_ERRMID_SET_B   (99+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI8_ERRMID_SET_R   (100+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI9_ERRMID_SET_B   (101+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI9_ERRMID_SET_R   (102+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI10_ERRMID_SET_B   (103+VECTOR_MISC6_BASE)
    #define VECTOR_TOPAXI_MI10_ERRMID_SET_R   (104+VECTOR_MISC6_BASE)
    #define VECTOR_LARB24  (105+VECTOR_MISC6_BASE)
    #define VECTOR_LARB25  (106+VECTOR_MISC6_BASE)
    #define VECTOR_LARB26  (107+VECTOR_MISC6_BASE)

    #define MAX_IRQ_VECTOR      VECTOR_LARB26

    #define MAX_VECTOR_ID       MAX_IRQ_VECTOR
    #define ISR_VECTOR_SIZE     (MAX_VECTOR_ID + 1) // Max number of registered vector

// Interrupt bits
    #define _IRQ(v)         (1U << (v)) // IRQ bit by vector
    #define _MISCIRQ(v)     (1U << (v - VECTOR_MISC_BASE))    // MISC IRQ bit by vector
    #define _MISC2IRQ(v)    (1U << (v - VECTOR_MISC2_BASE))    // MISC2 IRQ bit by vector
    #define _MISC3IRQ(v)    (1U << (v - VECTOR_MISC3_BASE))    // MISC3 IRQ bit by vector
    #define _MISC5IRQ(v)    (1U << (v - VECTOR_MISC5_BASE))    // MISC5 IRQ bit by vector

#define REG_MISC_IRQST      0x0048      // MISC Interrupt Status Register
#define REG_MISC_IRQEN      0x004c      // MISC Interrupt Enable Register
#define REG_MISC_IRQCLR     0x005c      // MISC Interrupt Clear Register
    #define MAX_MISC_VECTOR 32

#define REG_MISC2_IRQST      0x0080      // MISC2 Interrupt Status Register
#define REG_MISC2_IRQEN      0x0084      // MISC2 Interrupt Enable Register
#define REG_MISC2_IRQCLR     0x0088      // MISC2 Interrupt Clear Register
    #define MAX_MISC2_VECTOR 32

#define REG_MISC3_IRQST      0x008c      // MISC3 Interrupt Status Register
#define REG_MISC3_IRQEN      0x0090      // MISC3 Interrupt Enable Register
#define REG_MISC3_IRQCLR     0x007c      // MISC3 Interrupt Clear Register
    #define MAX_MISC3_VECTOR 32

#define REG_MISC5_IRQST      0x0198      // MISC5 Interrupt Status Register
#define REG_MISC5_IRQEN      0x019c      // MISC5 Interrupt Enable Register
#define REG_MISC5_IRQCLR     0x01ac      // MISC5 Interrupt Clear Register
    #define MAX_MISC5_VECTOR 8

//----------------------------------------------------------------------------
// Timer registers
#define REG_RW_TIMER0_LLMT  0x0060      // RISC Timer 0 Low Limit Register
#define REG_RW_TIMER0_LOW   0x0064      // RISC Timer 0 Low Register
#define REG_RW_TIMER0_HLMT  0x0180      // RISC Timer 0 High Limit Register
#define REG_RW_TIMER0_HIGH  0x0184      // RISC Timer 0 High Register

#define REG_RW_TIMER1_LLMT  0x0068      // RISC Timer 1 Low Limit Register
#define REG_RW_TIMER1_LOW   0x006c      // RISC Timer 1 Low Register
#define REG_RW_TIMER1_HLMT  0x0188      // RISC Timer 1 High Limit Register
#define REG_RW_TIMER1_HIGH  0x018c      // RISC Timer 1 High Register

#define REG_RW_TIMER2_LLMT  0x0070      // RISC Timer 2 Low Limit Register
#define REG_RW_TIMER2_LOW   0x0074      // RISC Timer 2 Low Register
#define REG_RW_TIMER2_HLMT  0x0190      // RISC Timer 2 High Limit Register
#define REG_RW_TIMER2_HIGH  0x0194      // RISC Timer 2 High Register

#define REG_RW_TIMER_CTRL   0x0078      // RISC Timer Control Register
    #define TMR0_CNTDWN_EN  (1U << 0)   // Timer 0 enable to count down
    #define TMR0_AUTOLD_EN  (1U << 1)   // Timer 0 auto-load enable
    #define TMR1_CNTDWN_EN  (1U << 8)   // Timer 1 enable to count down
    #define TMR1_AUTOLD_EN  (1U << 9)   // Timer 1 auto-load enable
    #define TMR2_CNTDWN_EN  (1U << 16)  // Timer 2 enable to count down
    #define TMR2_AUTOLD_EN  (1U << 17)  // Timer 2 auto-load enable
    #define TMR_CNTDWN_EN(x) (1U << (x*8))
    #define TMR_AUTOLD_EN(x) (1U << (1+(x*8)))

#define REG_RW_DBG_MONSEL   0x0094      // Monitor Select Register

#ifdef CC_NO_BIM_INTR
#define REG_BIM_INTR_CLEAR          0x1B8
	#define TMR0_INTR_CLEAR  (1U << 0)
	#define TMR1_INTR_CLEAR  (1U << 1)
	#define TMR2_INTR_CLEAR  (1U << 2)
	#define LZHS_INTR_CLEAR  (1U << 3)
#endif
//----------------------------------------------------------------------------
// MISC register
#define REG_RW_MISC         0x0098      // MISC. Register
    #define MISC_MI_BP      (1U << 0)    // Multi-ICE JTAG signal by pass mode
    #define MISC_IRQ_BP     (1U << 3)    // RISC IRQ 0:registered connected/1:by pass
    #define MISC_FIQ_BP     (1U << 4)    // RISC FIQ 0:registered connected/1:by pass
    #define MISC_INT_ST     (1U << 5)    // Interrupt status bit 0: events & IRQEN/FIQEN, 1:events
    #define MISC_RSREG      (1U << 6)    // RS232 read/write RISC IO register enable
    #define MISC_PMU_LEV    (1U << 8)    // ARM1176 nPMUIRQ level/edge trigger interrupt
    #define MISC_SFLASH_SWRST (1U << 15) // Serial Flash soft reset
    #define MISC_HOTPLUG_EN (1U << 23)   // CPU hotplug 0:disable 1:enable

#define REG_RW_HOTPLUG_ADDR 0x01dc      // CPU hotplug address register

//----------------------------------------------------------------------------
// RISC General Purpose Registers
#define REG_RW_GPRB0        0x00e0      // RISC Byte General Purpose Register 0
#define REG_RW_GPRB1        0x00e4      // RISC Byte General Purpose Register 1
#define REG_RW_GPRB2        0x00e8      // RISC Byte General Purpose Register 2
#define REG_RW_GPRB3        0x00ec      // RISC Byte General Purpose Register 3
#define REG_RW_GPRB4        0x00f0      // RISC Byte General Purpose Register 4
#define REG_RW_GPRB5        0x00f4      // RISC Byte General Purpose Register 5
#define REG_RW_GPRB6        0x00f8      // RISC Byte General Purpose Register 6
#define REG_RW_GPRB7        0x00fc      // RISC Byte General Purpose Register 7
#define REG_RW_GPRDW0       0x0100      // RISC Double Word General Purpose Register 0
#define REG_RW_GPRDW1       0x0104      // RISC Double Word General Purpose Register 1
#define REG_RW_GPRDW2       0x0108      // RISC Double Word General Purpose Register 2
#define REG_RW_GPRDW3       0x010c      // RISC Double Word General Purpose Register 3
#define REG_RW_GPRDW4       0x0150      // RISC Double Word General Purpose Register 4
#define REG_RW_GPRDW5       0x0154      // RISC Double Word General Purpose Register 5
#define REG_RW_GPRDW6       0x0160      // RISC Double Word General Purpose Register 6


//----------------------------------------------------------------------------
// Ring Oscillator
#define REG_RW_ROSCCTL      0x012c      // Ring Oscillator Control Register
    #define ROSC_TRIGGER    (1U << 0)    // Ring-oscillator trigger bit
    #define ROSC_CLR        (1U << 1)    // Clear ring-oscillator counter & ref.cnt.reg
    #define ROSC_SEL        (1U << 2)    // 1 before set TRIG, 0 before set CLR
#define REG_RO_ROSCCNT      0x0130      // Ring Oscillator Reference Counter Register

//----------------------------------------------------------------------------
// ROM BIST
#define REG_RW_ROM_BIST         0x134       // ROM bist control register
    #define ROM_MULTI_CNT       (7U << 1)   // ROM multi-bist number = 2^(MULTI_CNT) - 1
    #define ROM_MULTI_BIST_EN   (1U << 0)   // ROM multi-bist enable bit
#define REG_RW_ROM_CKSUM0       0x138       // ROM even checksum 0
#define REG_RW_ROM_CKSUM1       0x13c       // ROM even checksum 1
    #define ROM_CKSUM_MASK      (0xff)


//----------------------------------------------------------------------------
// CPI
#define REG_RW_CPI0         0x01a0      // CPI meter 0 Register
#define REG_RW_CPI1         0x01a4      // CPI meter 1 Register
#define REG_RW_CPI2         0x01a8      // CPI meter 2 Register
#define REG_RW_CPI3         0x01ac      // CPI meter 3 Register
#define REG_RW_CPICFG       0x01b0      // CPI meter configuration register
    #define CPICFG_CLR      (1U << 1)   // Clear CPI meter
    #define CPICFG_EN       (1U << 0)   // Enable CPI meter

//----------------------------------------------------------------------------
// LZHS
#define REG_LZHS_CTRL       0x00b0
    #define LZHS_FILTER_END     (1U << 16)
    #define LZHS_FILTER_BYPASS  (1U << 15)
	#define ALE_EN              (1U << 14)
    #define LZHSMON_SEL         (1U << 13)
    #define SRC_SEL             (1U << 12)
    #define DEC_START           (1U << 11)
    #define MCKEN               (1U << 10)
    #define SWRST               (1U << 9)
    #define LZHS_INT            (1U << 8)
    #define CHECKSUM            (0xffU << 0)
#define REG_LZHS_R_ADDR     0x00b4
#define REG_LZHS_W_ADDR     0x00b8
#define REG_LZHS_W_END_ADDR 0x00bc
#define REG_LZHS_RAMCK      0x01d0
    #define LZHS_BUSCK_SEL  (1U << 6)   // LZHS SRAM clock selection indicator
    #define LZHS_CHGOK      (1U << 5)   // LZHS SRAM change index
    #define SRAM_CLK_SEL    (1U << 4)   // LZHS clock selection
    #define LZHS_SRAM_EN    (1U << 3)   // LZHS SRAM enable bit
    #define GPR_EN          (1U << 1)   // TCM SRAM used as GPR, map to 0x10000

//----------------------------------------------------------------------------
// BIM
#define REG_RO_SW_ID        0x0064      // Software ID register
#define REG_WO_BIM_RSTCTL   0x01f4      // BIM Reset Control Register
#define REG_RO_FPGA_ID      0x01f8      // FPGA ID Register
#define REG_RO_CHIP_ID      0x0060      // Chip ID Register
#define REG_CA9_CTL         0x0490
#define REG_PL310_SRAM_CTL  0x04C8
#define BANK_SECURE_ENABLE1 (0x20c)

// FIFO
#define REG_DRAMIF          0x0110      // DRAMIF CONTROL REGISTER
    #define WFIFO_EN        (1U << 0)   // CPU/DRAM interface write FIFO enable bit
    #define DOUBLE_READ     (1U << 1)   // Read DRAM data twice and compare the data content, will response error if different
    #define FORCE_FAIL      (1U << 2)   // Force the read data error when DOUBLE_READ enable
#define REG_WFIFO           0x0114      // WFIFO CONTROL REGISTER
    #define MERGE_EN        (1U << 0)   // CPU-DRAM write data merge of same address enable register, 0: disable, 1: enable
    #define AUTO_FLUSH      (1U << 1)   // CPU-DRAM WFIFO auto flush by IO regiser access, 0: disable, 1: enable
    #define FLUSH_CMD       (1U << 4)   // CPU-DRAM WFIFO flush command when AUTO_FLUSH disable
    #define MERGE_TOUT_CNT  (fU << 8)   // Write merge time out counter value, when merge time out counter = WMERGE_TOUT_CNT, the merged data will flush to DRAM

//----------------------------------------------------------------------------
//PWM...
#define REG_RW_PWMPHASE     0x0130
#define REG_RW_PWM0         0x0100     // PWM0 Register
#define REG_RW_PWM0VSYNC    0x0104
#define REG_RW_PWM1         0x0110      // PWM1 Register
#define REG_RW_PWM1VSYNC    0x0114
#define REG_RW_PWM2         0x0120      // PWM2 Register
#define REG_RW_PWM2VSYNC    0x0124
		//
    #define PWME            (1)             // enable

//----------------------------------------------------------------------------
// SIF ...

//----------------------------------------------------------------------------
// IRTX read/write configuration registers
#define IRTX_CONFIG_REG             0x0298
    #define IRTX_CONF_BITNUM_MASK   (0x7f00U)
    #define IRTX_CONF_IRNIV         (1U << 7)
    #define IRTX_CONF_IROS          (1U << 6)
    #define IRTX_CONF_RORD          (1U << 5)
    #define IRTX_CONF_BORD          (1U << 4)
    #define IRTX_CONF_MODE_MASK     (0x000eU)
    #define IRTX_INIT_CONF_MASK     (0x00feU)
    #define IRTX_CONF_MODE_SWO_EN   (1U << 3)
    #define IRTX_CONF_MODE_PWC      (0U << 1)
    #define IRTX_CONF_MODE_RC5      (1U << 1)
    #define IRTX_CONF_MODE_RC6      (2U << 1)
    #define IRTX_CONF_MODE_SWO      (3U << 1)
    #define IRTX_CONF_START_SEND    (1U << 0)
#define IRTX_DATA_BYTE_3_0          0x029c      // byte 0 is least significant.
#define IRTX_DATA_BYTE_7_4          0x02a0
#define IRTX_DATA_BYTE_11_8         0x02a4
#define IRTX_SYNC_HIGH_REG          0x02a8
#define IRTX_SYNC_LOW_REG           0x02ac
#define IRTX_DATA0_HIGH_REG         0x02b0
#define IRTX_DATA0_LOW_REG          0x02b4
#define IRTX_DATA1_HIGH_REG         0x02b8
#define IRTX_DATA1_LOW_REG          0x02bc
#define IRTX_MODULATION_REG         0x02c0

//----------------------------------------------------------------------------
// Internal HDCP
#define REG_RW_HDCP_DEV     0x02E0      // Internal HDCP Device Address Register
#define REG_RW_HDCP_ADDR    0x02E4      // Internal HDCP SRAM Address Register
#define REG_RW_HDCP_DATA    0x02E8      // Internal HDCP SRAM Data Register

//----------------------------------------------------------------------------
// CPU Power Control
#define REG_MCUSYS_ACLKEN_DIV       (0xE0640)
#define REG_MP2_PLL_DIVIDER_CFG     (0xE07A8)
#define REG_MCUSYS_BUS_PLL_DIV_CFG  (0xE07C0)

#define REG_CA15CLK_CTL		(0x0400)	// CA15L CLK CONTROL
    #define ARMPLL_CK_OFF	(1U << 0)
    #define PLL1_CK_OFF		(1U << 1)
    #define ARM_K1			(0xffU << 2)
    #define MUX1_SEL		(3U << 10)
    #define DCM_ENABLE		(1U << 12)
    #define ARMWFI_DCM_EN	(1U << 13)
    #define ARMWFE_DCM_EN	(1U << 14)
    #define FCA9_CLK_OFF	(1U << 15)
    #define SC_ARMCK_OFF_EN	(1U << 16)
    #define OCC_CTL			(0x3fU << 17)
#ifndef CC_MT5893
#define REG_CA15ISOLATECPU	(0x0404)	// CA15L ISOLATE CONTROL
#define REG_CPU0_PWR_CTL	(0x0404)	// CPU0 POWER CONTROL
#define REG_CPU1_PWR_CTL	(0x0408)	// CPU1 POWER CONTROL
#define REG_CPU2_PWR_CTL	(0x040c)	// CPU2 POWER CONTROL
#define REG_CPU3_PWR_CTL	(0x0410)	// CPU3 POWER CONTROL
    #define MEM_PD  	    (1U << 0)
	#define MEM_ISOINTB  	(1U << 1)
	#define MEM_CKISO       (1U << 2)
	#define MEM_PD_ACK      (1U << 3)
	#define PWR_CLK_DIS  	(1U << 4)
    #define PWR_RST_EN  	(1U << 5)
    #define PWR_ON			(1U << 6)
    #define PWR_ON_2ND		(1U << 7)
    #define PWR_ON_ACK		(1U << 8)
    #define PWR_ON_2ND_ACK	(1U << 9)
	#define CLAMP       	(1U << 10)
	#define SLPD_CLAMP    	(1U << 11)
#else
#define REG_SMPC_PWR_CTL    (0x0438)    // SMPC power control
    #define PWR_ON          (1U << 0)
    #define PWR_ACK         (1U << 1)
    #define PWR_RST         (1U << 2)
#endif
#define REG_CKDIV			(0x0420)	// CKDIV
#define REG_GIC_CTL			(0x0424)	// GIC CONTROL
#define REG_DCM_CNT			(0x0428)	// DCM CNT

//ABIM register for cpu bootup/hotplug
// Main to Audio shared regsiters (0 ~ 6)
#define APROC_M2ASR30                            (0x8f8)
#define APROC_M2ASR31                            (0x8fc)

#define REG_CORE1_UP_MAGIC   APROC_M2ASR30
#define REG_CORE1_UP_ADDR    APROC_M2ASR31

#define REG_ATF_R0           (0x8d0)
#define REG_ATF_R1           (0x8d4)
#define REG_ATF_R2           (0x8d8)
#define REG_ATF_R3           (0x180)

#define REG_PICACHU_PEN_OFF  (0x180)
#define REG_CORE1_PEN_OFF    (0x184)
#define REG_CORE2_PEN_OFF    (0x188)
#define REG_CORE3_PEN_OFF    (0x18c)
#define REG_MISCCFG_RO_RSVD  (0x49c)
//----------------------------------------------------------------------------
// NAND ...

//----------------------------------------------------------------------------
// BIST
#define REG_RW_BISTCTRL     0x0500      // SRAM BIST Control Register
    #define BISTCTRL_SLOW           (1U << 8)   // Set 1 to enable BIST slow mode
    #define BISTCTRL_RSTBIST        (1U << 7)   // Reset all BIST Status to 0
    #define BISTCTRL_TESTPAT_UD     (0x3U << 5) // BIST test pattern options for up/down count
    #define BISTCTRL_TESTPAT_SEQ    (0x3U << 3) // BIST test pattern options sequence
    #define BISTCTRL_DIAGEN         (1U << 2)   // Diagnosis enable
    #define BISTCTRL_FORCEFAIL      (1U << 1)   // Force all register into fail status, just for test
    #define BISTCTRL_BISTTRIG       (1U << 0)   // BIST trigger
#define REG_RO_BISTSTAT     0x0504      // SRAM BIST Controller Status Register
    #define BISTSTAT_STATE  (0xfU << 28)
    #define BISTSTAT_RCNT   (3U << 26)
    #define BISTSTAT_WCNT   (3U << 24)
    #define BISTSTAT_VERIFY (1U << 23)
    #define BISTSTAT_PHIW   (1U << 22)
    #define BISTSTAT_PHIR   (1U << 21)
    #define BISTSTAT_PHIV   (1U << 20)
    #define BISTSTAT_EXPD   (3U << 18)
    #define BISTSTAT_UP     (1U << 17)
    #define BISTSTAT_LAST   (1U << 16)
    #define BISTSTAT_FR     (1U << 15)
    #define BISTSTAT_WALKADDR   (0x3ffU)
#define REG_RW_BISTEN0      0x0508      // BIST Enable 0 Register
#define REG_RW_BISTST0      0x050c      // BIST Status 0 Register
    #define BIST0_AUD_WR    (1U << 31)
    #define BIST0_AUD_RD    (1U << 30)
    #define BIST0_VD0IN     (0x1fffff << 9)
    #define BIST0_HDCP      (1U << 8)
    #define BIST0_SDIO      (1U << 7)
    #define BIST0_FCI       (1U << 6)
    #define BIST0_POD_TX    (1U << 5)
    #define BIST0_POD_RX    (1U << 4)
    #define BIST0_DFST      (3U << 2)
    #define BIST0_DTCM      (1U << 1)
    #define BIST0_ITCM      (1U << 0)
#define REG_RW_BISTEN1      0x0510      // BIST Enable 1 Register
#define REG_RW_BISTST1      0x0514      // BIST Status 1 Register
    #define BIST1_MCS_MB    (1U << 31)
    #define BIST1_IDCT_TM   (1U << 30)
    #define BIST1_MC_MB     (1U << 29)
    #define BIST1_MC_OBC    (1U << 28)
    #define BIST1_VLD_JS2   (1U << 27)
    #define BIST1_VLD_JS1   (1U << 26)
    #define BIST1_VLD_MV    (1U << 25)
    #define BIST1_VLD_EC    (1U << 24)
    #define BIST1_VLD_IQ    (1U << 23)
    #define BIST1_VLD_IS    (1U << 22)
    #define BIST1_VLD_VB    (1U << 21)
    #define BIST1_ITXBUF    (1U << 20)
    #define BIST1_ATXBUFHI  (1U << 19)
    #define BIST1_ATXBUFLO  (1U << 18)
    #define BIST1_IRXBUF    (1U << 17)
    #define BIST1_ARXBUF    (1U << 16)
    #define BIST1_AVTXBUF1  (1U << 15)
    #define BIST1_AVTXBUF0  (1U << 14)
    #define BIST1_AVRXBUF1HI    (1U << 13)
    #define BIST1_AVRXBUF0HI    (1U << 12)
    #define BIST1_AVRXBUF1LO    (1U << 11)
    #define BIST1_AVRXBUF0LO    (1U << 10)
    #define BIST1_PID       (3U << 8)
    #define BIST1_AIN       (0x3f << 2)
    #define BIST1_AUD_IC    (1U << 1)
    #define BIST1_AUD_RTCMPT    (1U << 0)
#define REG_RW_BISTEN2      0x0518      // BIST Enable 2 Register
#define REG_RW_BISTST2      0x051c      // BIST Status 2 Register
    #define BIST2_TPPSWF_YL (1U << 31)
    #define BIST2_TPPSWF_CE (1U << 30)
    #define BIST2_TPPSWF_YE (1U << 29)
    #define BIST2_TPPSXF_CL (1U << 28)
    #define BIST2_TPPSXF_YL (1U << 27)
    #define BIST2_YPPSCL2   (1U << 26)
    #define BIST2_TPPSYL2   (1U << 25)
    #define BIST2_TPPSCL    (1U << 24)
    #define BIST2_TPPSYL    (1U << 23)
    #define BIST2_TPPSCS    (1U << 22)
    #define BIST2_TPPSYS    (1U << 21)
    #define BIST2_TMPSSAWCOMB   (1U << 20)
    #define BIST2_TMPSEDGE  (1U << 19)
    #define BIST2_TMPSZF_CS (1U << 18)
    #define BIST2_TMPSZF_YS (1U << 17)
    #define BIST2_TMPSWF_CL (1U << 16)
    #define BIST2_TMPSWF_YL (1U << 15)
    #define BIST2_TMPSWF_CE (1U << 14)
    #define BIST2_TMPSWF_YE (1U << 13)
    #define BIST2_TMPSXF_CL (1U << 12)
    #define BIST2_TMPSXF_YL (1U << 11)
    #define BIST2_TMPSC_L2  (1U << 10)
    #define BIST2_TMPSY_L2  (1U << 9)
    #define BIST2_TMPSC_L   (1U << 8)
    #define BIST2_TMPSY_L   (1U << 7)
    #define BIST2_TMPSCS    (1U << 6)
    #define BIST2_TMPSYS    (1U << 5)
    #define BIST2_B2R0      (1U << 4)
    #define BIST2_B2R1      (1U << 3)
    #define BIST2_B2R2      (1U << 2)
    #define BIST2_B2R3      (1U << 1)
    #define BIST2_MCS_AB    (1U << 0)
#define REG_RW_BISTEN3      0x0520      // BIST Enable 3 Register
#define REG_RW_BISTST3      0x0524      // BIST Status 3 Register
    #define BIST3_SCPOS_4   (1U << 31)
    #define BIST3_SCPOS_5   (1U << 30)
    #define BIST3_SCPOS_6   (1U << 29)
    #define BIST3_SCPOS_7   (1U << 28)
    #define BIST3_SCPOS_8   (1U << 27)
    #define BIST3_SCPOS_9   (1U << 26)
    #define BIST3_SCPOS_10  (1U << 25)
    #define BIST3_SCPOS_11  (1U << 24)
    #define BIST3_SCPOS_12  (1U << 23)
    #define BIST3_OSDCSR    (1U << 22)
    #define BIST3_OSDSCD    (1U << 21)
    #define BIST3_OSDSCC    (1U << 20)
    #define BIST3_OSDSCB    (1U << 19)
    #define BIST3_OSDSCA    (1U << 18)
    #define BIST3_OSD3_P    (1U << 17)
    #define BIST3_OSD3_F    (1U << 16)
    #define BIST3_OSD2_P    (1U << 15)
    #define BIST3_OSD2_F    (1U << 14)
    #define BIST3_OSD1_P    (1U << 13)
    #define BIST3_OSD1_F    (1U << 12)
    #define BIST3_GRASC_SCB (1U << 11)  // GRASC_SCFIF_O_B
    #define BIST3_GRASC_SCA (1U << 10)  // GRASC_SCFIF_O_A
    #define BIST3_GRASC     (1U << 9)
    #define BIST3_GRASC_CMD (1U << 8)
    #define BIST3_GRA       (1U << 7)
    #define BIST3_GRA_CMD   (1U << 6)
    #define BIST3_SHARP     (1U << 5)
    #define BIST3_TPPSSAWCOMB   (1U << 4)
    #define BIST3_TPPSEDGE  (1U << 3)
    #define BIST3_TPPSSZ_CS (1U << 2)
    #define BIST3_TPPSZF_YS (1U << 1)
    #define BIST3_TPPSWF_CL (1U << 0)
#define REG_RW_BISTEN4      0x0528      // BIST Enable 4 Register
#define REG_RW_BISTST4      0x052c      // BIST Status 4 Register
    #define BIST4_ADAC      (1U << 4)
    #define BIST4_SCPOS_0   (1U << 3)
    #define BIST4_SCPOS_1   (1U << 2)
    #define BIST4_SCPOS_2   (1U << 1)
    #define BIST4_SCPOS_3   (1U << 0)
#define REG_RW_BISTEN5      0x0530      // BIST Enable 5 Register
#define REG_RW_BISTST5      0x0534      // BIST Status 5 Register
    #define BIST5_DSP       (7U << 16)
    #define BIST5_CPU       (0x3fffU)
#define REG_RW_BISTEN6      0x0538      // BIST Enable 6 Register
#define REG_RW_BISTST6      0x053c      // BIST Status 6 Register
    #define BIST6_DEMUX     (0x3fffffU)

//----------------------------------------------------------------------------
// CC TTX
#define REG_RW_TTX_CFG      0x0600      // CCTTX Configuration Register
    #define TTX_CFG_ODD_CORRECT 0x08    //Put 0x20 in decoded packet if incorrect odd parity
    #define TTX_CFG_DEC_PKT 0x04    // Decode packet data trigger
    #define TTX_CFG_DEC_HEAD    0x02    // Decode packet data trigger

#define REG_RW_TTX_DEC0_CTL 0x0604      // CCTTX Decode Control 0 Register
#define REG_RW_TTX_DEC1_CTL 0x0608      // CCTTX Decode Control 1 Register
#define REG_RW_TTX_PKTDT0   0x060c      // CCTTX Packet Data 0 Register
#define REG_RW_TTX_PKTDT1   0x0610      // CCTTX Packet Data 1 Register
#define REG_RW_TTX_PKTDT2   0x0614      // CCTTX Packet Data 2 Register
#define REG_RW_TTX_PKTDT3   0x0618      // CCTTX Packet Data 3 Register
#define REG_RW_TTX_PKTDT4   0x061c      // CCTTX Packet Data 4 Register
#define REG_RW_TTX_PKTDT5   0x0620      // CCTTX Packet Data 5 Register
#define REG_RW_TTX_PKTDT6   0x0624      // CCTTX Packet Data 6 Register
#define REG_RW_TTX_PKTDT7   0x0628      // CCTTX Packet Data 7 Register
#define REG_RW_TTX_PKTDT8   0x062c      // CCTTX Packet Data 8 Register
#define REG_RW_TTX_PKTDT9   0x0630      // CCTTX Packet Data 9 Register
#define REG_RW_TTX_PKTDTa   0x0634      // CCTTX Packet Data a Register
#define REG_RW_TTX_ERR0     0x0638      // CCTTX Error Flag 0 Register
#define REG_RW_TTX_ERR1     0x063C      // CCTTX Error Flag 1 Register
    #define TTX_ERR1_INDICATION 0x400   // Is there any error in packet decoding
// To be continued...

//----------------------------------------------------------------------------
//GIC...
#define GIC_CPU_CTRL            0x00
#define GIC_CPU_PRIMASK         0x04
#define GIC_CPU_BINPOINT        0x08
#define GIC_CPU_INTACK          0x0c
#define GIC_CPU_EOI             0x10
#define GIC_CPU_RUNNINGPRI      0x14
#define GIC_CPU_HIGHPRI         0x18

#define GIC_DIST_CTRL           0x000
#define GIC_DIST_CTR            0x004
#define GIC_DIST_IIDR		0x008
#define GIC_DIST_IGROUPR        0x080
#define GIC_DIST_ENABLE_SET     0x100
#define GIC_DIST_ENABLE_CLEAR   0x180
#define GIC_DIST_PENDING_SET    0x200
#define GIC_DIST_PENDING_CLEAR  0x280
#define GIC_DIST_ACTIVE_SET     0x300
#define GIC_DIST_ACTIVE_CLEAR     0x380
#define GIC_DIST_PRI            0x400
#define GIC_DIST_TARGET         0x800
#define GIC_DIST_CONFIG         0xc00
#define GIC_DIST_NSACR         0xe00
#define GIC_DIST_SOFTINT        0xf00

/*******************************************************************************
 * GICv3 private macro definitions
 ******************************************************************************/

/* Constants to indicate the status of the RWP bit */
#define RWP_TRUE		1
#define RWP_FALSE		0

/*
 * Macro to wait for updates to :
 * GICD_CTLR[2:0] - the Group Enables
 * GICD_CTLR[5:4] - the ARE bits
 * GICD_ICENABLERn - the clearing of enable state for SPIs
 */
#define gicd_wait_for_pending_write()			\
	do {							\
		;						\
	} while (GICD_READ32(GICD_CTLR) & GICD_CTLR_RWP_BIT)

/*
 * Macro to convert an mpidr to a value suitable for programming into a
 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
 * to GICv3.
 */
#define gicd_irouter_val_from_mpidr(mpidr, irm)		\
	((mpidr & ~(0xff << 24)) |			\
	 (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT)

/*
 * Macro to wait for updates to :
 * GICR_ICENABLER0
 * GICR_CTLR.DPG1S
 * GICR_CTLR.DPG1NS
 * GICR_CTLR.DPG0
 */
#define gicr_wait_for_pending_write()			\
	do {							\
		;						\
	} while (GICR_READ32(GICR_CTLR) & GICR_CTLR_RWP_BIT)

/*
 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
 * are zeroes.
 */
#ifdef AARCH32
#define mpidr_from_gicr_typer(typer_val)	(((typer_val) >> 32) & 0xffffff)
#else
#define mpidr_from_gicr_typer(typer_val)				 \
	(((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
	 (((typer_val) >> 32) & 0xffffff))
#endif

/*******************************************************************************
 * GIC Distributor interface general definitions
 ******************************************************************************/
/* Constants to categorise interrupts */
#define MIN_SGI_ID		0
#define MIN_PPI_ID		16
#define MIN_SPI_ID		32

/* Mask for the priority field common to all GIC interfaces */
#define GIC_PRI_MASK			0xff

/* Constant to indicate a spurious interrupt in all GIC versions */
#define GIC_SPURIOUS_INTERRUPT		1023

/* Constants to categorise priorities */
#define GIC_HIGHEST_SEC_PRIORITY	0
#define GIC_LOWEST_SEC_PRIORITY		127
#define GIC_HIGHEST_NS_PRIORITY		128
#define GIC_LOWEST_NS_PRIORITY		254 /* 255 would disable an interrupt */

/*******************************************************************************
 * GIC Distributor interface register offsets that are common to GICv3 & GICv2
 ******************************************************************************/
#define GICD_CTLR		0x0
#define GICD_TYPER		0x4
#define GICD_IIDR		0x8
#define GICD_IGROUPR		0x80
#define GICD_ISENABLER		0x100
#define GICD_ICENABLER		0x180
#define GICD_ISPENDR		0x200
#define GICD_ICPENDR		0x280
#define GICD_ISACTIVER		0x300
#define GICD_ICACTIVER		0x380
#define GICD_IPRIORITYR		0x400
#define GICD_ICFGR		0xc00
#define GICD_NSACR		0xe00

/* GICD_CTLR bit definitions */
#define CTLR_ENABLE_G0_SHIFT		0
#define CTLR_ENABLE_G0_MASK		0x1
#define CTLR_ENABLE_G0_BIT		(1 << CTLR_ENABLE_G0_SHIFT)

/*******************************************************************************
 * GIC Distributor interface register constants that are common to GICv3 & GICv2
 ******************************************************************************/
#define PIDR2_ARCH_REV_SHIFT	4
#define PIDR2_ARCH_REV_MASK	0xf

/* GICv3 revision as reported by the PIDR2 register */
#define ARCH_REV_GICV3		0x3
/* GICv2 revision as reported by the PIDR2 register */
#define ARCH_REV_GICV2		0x2

#define IGROUPR_SHIFT		5
#define ISENABLER_SHIFT		5
#define ICENABLER_SHIFT		ISENABLER_SHIFT
#define ISPENDR_SHIFT		5
#define ICPENDR_SHIFT		ISPENDR_SHIFT
#define ISACTIVER_SHIFT		5
#define ICACTIVER_SHIFT		ISACTIVER_SHIFT
#define IPRIORITYR_SHIFT	2
#define ICFGR_SHIFT		4
#define NSACR_SHIFT		4

/* GICD_TYPER shifts and masks */
#define TYPER_IT_LINES_NO_SHIFT	0
#define TYPER_IT_LINES_NO_MASK	0x1f

/* Value used to initialize Normal world interrupt priorities four at a time */
#define GICD_IPRIORITYR_DEF_VAL			\
	(GIC_HIGHEST_NS_PRIORITY	|	\
	(GIC_HIGHEST_NS_PRIORITY << 8)	|	\
	(GIC_HIGHEST_NS_PRIORITY << 16)	|	\
	(GIC_HIGHEST_NS_PRIORITY << 24))

/*******************************************************************************
 * GICv3 miscellaneous definitions
 ******************************************************************************/
/* Interrupt group definitions */
#define INTR_GROUP1S		0
#define INTR_GROUP0		1
#define INTR_GROUP1NS		2

/* Interrupt IDs reported by the HPPIR and IAR registers */
#define PENDING_G1S_INTID	1020
#define PENDING_G1NS_INTID	1021

/* Constant to categorize LPI interrupt */
#define MIN_LPI_ID		8192

/*******************************************************************************
 * GICv3 specific Distributor interface register offsets and constants.
 ******************************************************************************/
#define GICD_STATUSR		0x10
#define GICD_SETSPI_NSR		0x40
#define GICD_CLRSPI_NSR		0x48
#define GICD_SETSPI_SR		0x50
#define GICD_CLRSPI_SR		0x50
#define GICD_IGRPMODR		0xd00
/*
 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and
 * n >= 32, making the effective offset as 0x6100.
 */
#define GICD_IROUTER		0x6000
#define GICD_PIDR2_GICV3	0xffe8

#define IGRPMODR_SHIFT		5

/* GICD_CTLR bit definitions */
#define CTLR_ENABLE_G1NS_SHIFT		1
#define CTLR_ENABLE_G1S_SHIFT		2
#define CTLR_ARE_S_SHIFT		4
#define CTLR_ARE_NS_SHIFT		5
#define CTLR_DS_SHIFT			6
#define CTLR_E1NWF_SHIFT		7
#define GICD_CTLR_RWP_SHIFT		31

#define CTLR_ENABLE_G1NS_MASK		0x1
#define CTLR_ENABLE_G1S_MASK		0x1
#define CTLR_ARE_S_MASK			0x1
#define CTLR_ARE_NS_MASK		0x1
#define CTLR_DS_MASK			0x1
#define CTLR_E1NWF_MASK			0x1
#define GICD_CTLR_RWP_MASK		0x1

#define CTLR_ENABLE_G1NS_BIT		(1 << CTLR_ENABLE_G1NS_SHIFT)
#define CTLR_ENABLE_G1S_BIT		(1 << CTLR_ENABLE_G1S_SHIFT)
#define CTLR_ARE_S_BIT			(1 << CTLR_ARE_S_SHIFT)
#define CTLR_ARE_NS_BIT			(1 << CTLR_ARE_NS_SHIFT)
#define CTLR_DS_BIT			(1 << CTLR_DS_SHIFT)
#define CTLR_E1NWF_BIT			(1 << CTLR_E1NWF_SHIFT)
#define GICD_CTLR_RWP_BIT		(1 << GICD_CTLR_RWP_SHIFT)

/* GICD_IROUTER shifts and masks */
#define IROUTER_IRM_SHIFT	31
#define IROUTER_IRM_MASK	0x1

/*******************************************************************************
 * GICv3 Re-distributor interface registers & constants
 ******************************************************************************/
#define GICR_PCPUBASE_SHIFT	0x11
#define GICR_SGIBASE_OFFSET	(1 << 0x10)	/* 64 KB */
#define GICR_CTLR		0x0
#define GICR_TYPER		0x08
#define GICR_WAKER		0x14
#define GICR_IGROUPR0		(GICR_SGIBASE_OFFSET + 0x80)
#define GICR_ISENABLER0		(GICR_SGIBASE_OFFSET + 0x100)
#define GICR_ICENABLER0		(GICR_SGIBASE_OFFSET + 0x180)
#define GICR_IPRIORITYR		(GICR_SGIBASE_OFFSET + 0x400)
#define GICR_ICFGR0		(GICR_SGIBASE_OFFSET + 0xc00)
#define GICR_ICFGR1		(GICR_SGIBASE_OFFSET + 0xc04)
#define GICR_IGRPMODR0		(GICR_SGIBASE_OFFSET + 0xd00)

/* GICR_CTLR bit definitions */
#define GICR_CTLR_RWP_SHIFT	3
#define GICR_CTLR_RWP_MASK	0x1
#define GICR_CTLR_RWP_BIT	(1 << GICR_CTLR_RWP_SHIFT)

/* GICR_WAKER bit definitions */
#define WAKER_CA_SHIFT		2
#define WAKER_PS_SHIFT		1

#define WAKER_CA_MASK		0x1
#define WAKER_PS_MASK		0x1

#define WAKER_CA_BIT		(1 << WAKER_CA_SHIFT)
#define WAKER_PS_BIT		(1 << WAKER_PS_SHIFT)

/* GICR_TYPER bit definitions */
#define TYPER_AFF_VAL_SHIFT	32
#define TYPER_PROC_NUM_SHIFT	8
#define TYPER_LAST_SHIFT	4

#define TYPER_AFF_VAL_MASK	0xffffffff
#define TYPER_PROC_NUM_MASK	0xffff
#define TYPER_LAST_MASK		0x1

#define TYPER_LAST_BIT		(1 << TYPER_LAST_SHIFT)

/*******************************************************************************
 * GICv3 CPU interface registers & constants
 ******************************************************************************/
/* ICC_SRE bit definitions*/
#define ICC_SRE_EN_BIT		(1 << 3)
#define ICC_SRE_DIB_BIT		(1 << 2)
#define ICC_SRE_DFB_BIT		(1 << 1)
#define ICC_SRE_SRE_BIT		(1 << 0)

/* ICC_IGRPEN1_EL3 bit definitions */
#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT	0
#define IGRPEN1_EL3_ENABLE_G1S_SHIFT	1

#define IGRPEN1_EL3_ENABLE_G1NS_BIT	(1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
#define IGRPEN1_EL3_ENABLE_G1S_BIT	(1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT)

/* ICC_IGRPEN0_EL1 bit definitions */
#define IGRPEN1_EL1_ENABLE_G0_SHIFT	0
#define IGRPEN1_EL1_ENABLE_G0_BIT	(1 << IGRPEN1_EL1_ENABLE_G0_SHIFT)

/* ICC_HPPIR0_EL1 bit definitions */
#define HPPIR0_EL1_INTID_SHIFT		0
#define HPPIR0_EL1_INTID_MASK		0xffffff

/* ICC_HPPIR1_EL1 bit definitions */
#define HPPIR1_EL1_INTID_SHIFT		0
#define HPPIR1_EL1_INTID_MASK		0xffffff

/* ICC_IAR0_EL1 bit definitions */
#define IAR0_EL1_INTID_SHIFT		0
#define IAR0_EL1_INTID_MASK		0xffffff

/* ICC_IAR1_EL1 bit definitions */
#define IAR1_EL1_INTID_SHIFT		0
#define IAR1_EL1_INTID_MASK		0xffffff

#define GIC_IRQS				(288)

#define BIM_IS_SECURE_BOOT      (BIM_READ32(0x664) & (1U << 20))
#define BIM_WITH_SECURE_ID      (BIM_READ32(0x664) & (1U << 31))

//----------------------------------------------------------------------------
//MCUSYS
#define RVADDR0_L               (MCUSYS_CONFIG_BASE + 0x290)
#define RVADDR1_L               (MCUSYS_CONFIG_BASE + 0x298)
#define RVADDR2_L               (MCUSYS_CONFIG_BASE + 0x2c0)
#define RVADDR3_L               (MCUSYS_CONFIG_BASE + 0x2c8)

#define CPU1_SPMC0              (0x438)
#define CPU2_SPMC0              (0x440)
#define CPU3_SPMC0              (0x448)

#define REG_MCU_INT_POL_CTL0 (0xa80)

//----------------------------------------------------------------------------
// TRNG
#define TRNG_CTRL            (0x00)
    #define TRNG_CTRL_START         (0x1)
    #define TRNG_CTRL_RDY           (0x80000000)
#define TRNG_TIME            (0x04)
#define TRNG_DATA            (0x08)
#define TRNG_CONF            (0x0c)
#define TRNG_INT_SET         (0x10)
#define TRNG_INT_CLR         (0x14)

//-----------------------------------------------------------------------------
// Constant for TIME Log
//-----------------------------------------------------------------------------

#define BIM_SetTimeLog(x)       BIM_WRITE32((REG_RW_GPRB0 + (x << 2)), BIM_READ32(REG_RW_TIMER2_LOW))
#define BIM_ClrTimeLog(x)       BIM_WRITE32((REG_RW_GPRB0 + (x << 2)), 0)
#define BIM_GetTimeLog(x)       BIM_READ32((REG_RW_GPRB0 + (x << 2)))

#define MAX_SW_TIMESTAMP_SIZE   (1024)

//-----------------------------------------------------------------------------
// Type definitions
//-----------------------------------------------------------------------------
typedef struct _TIME_STAMP
{
    UINT32 u4TimeStamp;
    CHAR *szString;
	CHAR *szComm;
} TIME_STAMP_T;

// RTC related interfaces moved to rtc_if.h
/*
typedef struct
{
    UINT8   u1Year;
    UINT8   u1Month;
    UINT8   u1Day;
    UINT8   u1Hour;
    UINT8   u1Minute;
    UINT8   u1Second;
} RTC_T;

typedef void (*PFN_RTC_ALERT_HANDLER_T)(void);
*/

//-----------------------------------------------------------------------------
// Public functions
//-----------------------------------------------------------------------------

EXTERN BOOL BIM_EnableIrq(UINT32 u4Vector);

EXTERN BOOL BIM_DisableIrq(UINT32 u4Vector);

EXTERN BOOL BIM_IsIrqEnabled(UINT32 u4Vector);

EXTERN BOOL BIM_IsIrqPending(UINT32 u4Vector);

EXTERN BOOL BIM_ClearIrq(UINT32 u4Vector);

EXTERN VOID BIM_Set7Seg(UINT32 u4Value);

EXTERN UINT32 BIM_GetOscillator(VOID);

EXTERN VOID BIM_LockModifyReg32(UINT32 reg, UINT32 mask, UINT32 setVal);

EXTERN VOID BIM_Reboot(VOID);

EXTERN INT32 BIM_IsSecureBoot(VOID); // check if this is a secure boot IC

EXTERN VOID ARM_SendEvent(VOID);

EXTERN VOID HaltSystem(VOID);

EXTERN BOOL LZHS_SetIsrEnable(BOOL fgSet);

EXTERN INT32 LZHS_Dec(UINT32 u4SrcAddr, UINT32 u4DestAddr, UINT32 u4Len, UINT8 *pu1CheckSum);

EXTERN VOID x_os_drv_set_timestamp(CHAR *szString);

EXTERN TIME_STAMP_T * x_os_drv_get_timestamp(UINT32 *pu4Size);

VOID x_os_drv_reset_timestamp(VOID);

EXTERN INT32 BIM_GetDeviceData(BYTE *pu1DeviceID, BYTE u1Size);

EXTERN INT32 BIM_GetDmKey(BYTE *pu1Buf, BYTE u1Size);

EXTERN INT32 BIM_GetULPK(BYTE *pu1Buf, BYTE u1Size);

EXTERN INT32 BIM_GetRomKey(BYTE *pu1Buf, UINT32 u4Offset, BYTE u1Size);

// RTC related interfaces moved to rtc_if.h
/*
EXTERN BOOL RTC_IsAllRegsBcd(void);

EXTERN BOOL RTC_RtcToUtc(UINT64* pu8Utc, const RTC_T* prRtc);

EXTERN BOOL RTC_UtcToRtc(RTC_T* prRtc, UINT64 u8Utc);

EXTERN BOOL RTC_Init(void);

EXTERN BOOL RTC_GetTimeDate(UINT64* prTime);

EXTERN INT32 RTC_SetTimeDate(const UINT64* prTime);

EXTERN void RTC_SetAlertTime(UINT64 u8Utc);

EXTERN void RTC_HookAlertHandler(PFN_RTC_ALERT_HANDLER_T pfnHandler);
*/

EXTERN void GIC_Init(void);
EXTERN void BIM_CpuDie(UINT32 cpu);
EXTERN void BIM_ClusterUp(UINT32 u4Cluster);
EXTERN void BIM_ClusterUpCA17Only(UINT32 u4Cluster);
EXTERN void BIM_CA7_CpuUp(UINT32 cpu);

EXTERN void BIM_ClearDisableIrq(void);
EXTERN UINT32 BIM_Random(VOID);
#endif  // X_BIM_H

