/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
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 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
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 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
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 *    notice, this list of conditions and the following disclaimer in
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 *****************************************************************************/

#ifndef ARM_CPU_H
#define ARM_CPU_H

#define BIM_BASE            0x10008000
#define REG_RW_REMAP        (BIM_BASE + 0x1C)
#define BIT_REMAP           0x39

/*
#define SRAM_OSD_BASE	(0xfb000000)
#define SRAM_LZHS_BASE	(SRAM_OSD_BASE + 0x4000)
#define SRAM_DMX_BASE	(SRAM_LZHS_BASE + 0x1000)
#define SRAM_DMX_END    (SRAM_DMX_BASE + 0x7000)
#define SRAM_START      (SRAM_OSD_BASE)
#define SRAM_END        (SRAM_DMX_END)
#define SRAM_ITCM_BASE  (SRAM_LZHS_BASE)
*/
#define SRAM_CORE1_BASE (0x04114000)

/*
@ CPU mode
*/
#define MODE_USR                     0x10
#define MODE_FIQ                     0x11
#define MODE_IRQ                     0x12
#define MODE_SVC                     0x13
#define MODE_ABT                     0x17
#define MODE_UDF                     0x1B
#define MODE_MASK                    0x1F

#define BIT_I                        0x80
#define BIT_F                        0x40
#define IF_MASK                      0xc0
/*
@ CP15 control register (r1) definitions
*/
#define CR_UNALIGNMENT_SUPPORT       (1 << 22)       @ unalignment support
#define CR_ICACHE                    (1 << 12)       @ I-cache enable
#define CR_BPRDCT                    (1 << 11)       @ branch prediction enable
#define CR_DCACHE                    (1 << 2)        @ D-cache enable
#define CR_ALIGNMENT                 (1 << 1)        @ Alignment fault checking
#define CR_MMU                       (1 << 0)        @ MMU enable
#define CR_V                         (1 << 13)       @vector table in high or low
#define CR_CP1011_PRI_ONLY           (0xf << 20)     @ cp10/11 control

#endif
