/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author$
 * $Date$
 * $RCSfile: sif_hw_reg.h,v $
 * $Revision$
 *
 *---------------------------------------------------------------------------*/

/** @file sif_hw_reg.h
 *  Define SIF hardware register information.
 */
#include"x_hal_5381.h"

#ifndef SIF_HW_REG_H
#define SIF_HW_REG_H


#if defined(CC_MT5891) || defined(CC_MT5886) || defined(CC_MT5893)
#ifndef VECTOR_I2C
	#define VECTOR_I2C			(VECTOR_MISC_BASE+24)		   // useless
#endif
#endif

#define IO_SIF_BASE (IO_VIRT + 0x20000 + 0x9000)
#define IO_SIF_SM3_BASE (IO_VIRT + 0x30000 + 0xc000)
#if defined(CC_MT5883) 	|| defined(CC_MT5863)
#define IO_SIF_SEC_BASE (IO_SIF_BASE + 0x5000 + 0x200)
#define IO_SIF_I2C_BASE (IO_SIF_BASE + 0x5000)
#else
#define IO_SIF_SEC_BASE (IO_SIF_BASE + 0x13000)
#define IO_SIF_I2C_BASE (IO_SIF_SEC_BASE + 0x000)
#endif

//MT5895 SM0
#if defined(CC_MT5895)

#define SIF_SM3CTL0 (IO_SIF_BASE + 0x000)
    #define FLD_SM3_ODRAIN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SM3_VSYNC_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_SM3_CLK_DIV Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SM3_DEG_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM3_WAIT_LEVEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SM3_DEG_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SM3_CS_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SM3_SCL_STATE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SM3_SDA_STATE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SM3_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM3_SCL_STRECH Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM3CTL1 (IO_SIF_BASE + 0x004)
    #define FLD_SM3_ACK0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_SM3_PGLEN Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_SM3_MODE Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SM3_TRI Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM3CTL2 (IO_SIF_BASE + 0x008)
    #define FLD_SM3_SCL_RISE_VALUE Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SM3_SCL_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM3CTL3 (IO_SIF_BASE + 0x00C)
    #define FLD_SM3_ACK1 Fld(21,11,AC_MSKDW)//[31:11]
    #define FLD_SM3_WD_STOP_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SM3_STR_WD_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SM3_STR_WD_STOP_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SM3_RDNACK_STOP_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SM3_STR_RDACK_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SM3_STR_RDNACK_STOP_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM3_SDEV_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM3SDEV (IO_SIF_BASE + 0x010)
    #define FLD_SM3_DEV_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM3D0 (IO_SIF_BASE + 0x014)
    #define FLD_SM3_DATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define SIF_SM3D1 (IO_SIF_BASE + 0x018)
    #define FLD_SM3_DATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define SIF_SM3D2 (IO_SIF_BASE + 0x01C)
    #define FLD_SM3_DATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define SIF_SM3D3 (IO_SIF_BASE + 0x020)
    #define FLD_SM3_DATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define SIF_SM3D4 (IO_SIF_BASE + 0x024)
    #define FLD_SM3_DATA4 Fld(32,0,AC_FULLDW)//[31:0]
#define SIF_SM3D5 (IO_SIF_BASE + 0x028)
    #define FLD_SM3_DATA5 Fld(32,0,AC_FULLDW)//[31:0]
#define SIF_SM3D6 (IO_SIF_BASE + 0x02C)
    #define FLD_SM3_DATA6 Fld(32,0,AC_FULLDW)//[31:0]
#define SIF_SM3D7 (IO_SIF_BASE + 0x030)
    #define FLD_SM3_DATA7 Fld(32,0,AC_FULLDW)//[31:0]
#define SIF_SM3D8 (IO_SIF_BASE + 0x034)
    #define FLD_SM3_DATA8 Fld(32,0,AC_FULLDW)//[31:0]
#define SIF_I2CINTEN (IO_SIF_BASE + 0x100)
    #define FLD_SM3_INT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_I2CINTST (IO_SIF_BASE + 0x104)
    #define FLD_SM3_INT_ST Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_I2CINTCL (IO_SIF_BASE + 0x108)
    #define FLD_SM3_INT_CL Fld(1,0,AC_MSKB0)//[0:0]
#endif //(CC_MT5895)

//Page MISC
#define SIF_PERMISC (IO_SIF_BASE + 0x000)
#if defined(CC_MT5883)
    //#define FLD_LED_SW_RST Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SM1_SW_RST Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SM0_SW_RST Fld(1,28,AC_MSKB3)//[28:28]
    //#define FLD_HDCP_SW_RST Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SECSM0_SW_RST Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_SCL_RISE_MODE Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_SCL_RISE_VALUE Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM_PAD_SWAP_CONFIGURE_REGISTER Fld(1,3,AC_MSKB0)//[3:3]
#elif defined(CC_MT5891) || defined(CC_MT5886) || defined(CC_MT5863) || defined(CC_MT5893)
    #define FLD_SM0_SW_RST Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SM1_SW_RST Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SM2_SW_RST Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_SECSM0_SW_RST Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_SIFM_PAD_CFG Fld(3,3,AC_MSKB0)//[5:3]
#endif

//Page SIFM0_1_2
#define SIF_SM0CTL0 (IO_SIF_BASE + 0x240)
    #define FLD_SM0_ODRAIN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SM0_VSYNC_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_SM0_CLK_DIV Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SM0_DEG_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_WAIT_LEVEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SM0_DEG_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SM0_CS_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SM0_SCL_STATE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SM0_SDA_STATE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SM0_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM0_SCL_STRECH Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM0CTL1 (IO_SIF_BASE + 0x244)
    #define FLD_SM0_ACK0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_SM0_PGLEN Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_SM0_MODE Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SM0_TRI Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM0CTL2 (IO_SIF_BASE + 0x248)
    #define FLD_SM0_SCL_RISE_VALUE Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SM0_SCL_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM0SDEV (IO_SIF_BASE + 0x24C)
    #define FLD_SM0_DEV_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM0CTL3 (IO_SIF_BASE + 0x2FC)
	#define FLD_SM0_ACK1_DEVADDR_ACK Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SM0_ACK1 Fld(20,11,AC_MSKDW)//[31:11]
    #define FLD_SM0_WD_STOP_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SM0_STR_WD_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SM0_STR_WD_STOP_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SM0_RDNACK_STOP_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SM0_STR_RDACK_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SM0_STR_RDNACK_STOP_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM0_SDEV_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM0D0 (IO_SIF_BASE + 0x250)
    #define FLD_SM0_DATA3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM0_DATA2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM0_DATA1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_DATA0 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM0D1 (IO_SIF_BASE + 0x254)
    #define FLD_SM0_DATA7 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM0_DATA6 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM0_DATA5 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_DATA4 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM0D2 (IO_SIF_BASE + 0x2E0)
    #define FLD_SM0_DATA11 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM0_DATA10 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM0_DATA9 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_DATA8 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM0D3 (IO_SIF_BASE + 0x2E4)
    #define FLD_SM0_DATA15 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM0_DATA14 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM0_DATA13 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_DATA12 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM0D4 (IO_SIF_BASE + 0x2E8)
    #define FLD_SM0_DATA19 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM0_DATA18 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM0_DATA17 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_DATA16 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM0D5 (IO_SIF_BASE + 0x2EC)
    #define FLD_SM0_DATA23 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM0_DATA22 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM0_DATA21 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_DATA20 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM0D6 (IO_SIF_BASE + 0x2F0)
    #define FLD_SM0_DATA27 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM0_DATA26 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM0_DATA25 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_DATA24 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM0D7 (IO_SIF_BASE + 0x2F4)
    #define FLD_SM0_DATA31 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM0_DATA30 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM0_DATA29 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_DATA28 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM0D8 (IO_SIF_BASE + 0x2F8)
    #define FLD_SM0_DATA35 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM0_DATA34 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM0_DATA33 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM0_DATA32 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_PINTEN (IO_SIF_BASE + 0x25C)
#if defined(CC_MT5895) || defined(CC_MT5886) || defined(CC_MT5893)
    #define FLD_SM2_INT_EN Fld(1,2,AC_MSKB0)//[2:2]
#endif
    #define FLD_SM1_INT_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM0_INT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_PINTST (IO_SIF_BASE + 0x260)
#if defined(CC_MT5895) || defined(CC_MT5886) || defined(CC_MT5893)
    #define FLD_SM2_INT_ST Fld(1,2,AC_MSKB0)//[4:4]
#endif
    #define FLD_SM1_INT_ST Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM0_INT_ST Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_PINTCL (IO_SIF_BASE + 0x264)
#if defined(CC_MT5891)
    #define FLD_SM2_INT_CL Fld(1,4,AC_MSKB0)//[4:4]
#elif defined(CC_MT5895) || defined(CC_MT5893)
	#define FLD_SM2_INT_CL Fld(1,2,AC_MSKB0)//[2:2]
#endif
    #define FLD_SM1_INT_CL Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM0_INT_CL Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM1CTL0 (IO_SIF_BASE + 0x270)
    #define FLD_SM1_ODRAIN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SM1_VSYNC_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_SM1_CLK_DIV Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SM1_DEG_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_WAIT_LEVEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SM1_DEG_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SM1_CS_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SM1_SCL_STATE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SM1_SDA_STATE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SM1_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM1_SCL_STRECH Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM1CTL1 (IO_SIF_BASE + 0x274)
    #define FLD_SM1_ACK0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_SM1_PGLEN Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_SM1_MODE Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SM1_TRI Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM1CTL2 (IO_SIF_BASE + 0x278)
    #define FLD_SM1_SCL_RISE_VALUE Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SM1_SCL_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM1SDEV (IO_SIF_BASE + 0x27C)
    #define FLD_SM1_DEV_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM1CTL3 (IO_SIF_BASE + 0x2A8)
	#define FLD_SM1_ACK1_DEVADDR_ACK Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SM1_ACK1 Fld(21,11,AC_MSKDW)//[31:11]
    #define FLD_SM1_WD_STOP_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SM1_STR_WD_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SM1_STR_WD_STOP_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SM1_RDNACK_STOP_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SM1_STR_RDACK_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SM1_STR_RDNACK_STOP_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM1_SDEV_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM1D0 (IO_SIF_BASE + 0x280)
    #define FLD_SM1_DATA3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM1_DATA2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM1_DATA1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_DATA0 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM1D1 (IO_SIF_BASE + 0x284)
    #define FLD_SM1_DATA7 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM1_DATA6 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM1_DATA5 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_DATA4 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM1D2 (IO_SIF_BASE + 0x288)
    #define FLD_SM1_DATA11 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM1_DATA10 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM1_DATA9 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_DATA8 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM1D3 (IO_SIF_BASE + 0x28C)
    #define FLD_SM1_DATA15 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM1_DATA14 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM1_DATA13 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_DATA12 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM1D4 (IO_SIF_BASE + 0x290)
    #define FLD_SM1_DATA19 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM1_DATA18 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM1_DATA17 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_DATA16 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM1D5 (IO_SIF_BASE + 0x294)
    #define FLD_SM1_DATA23 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM1_DATA22 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM1_DATA21 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_DATA20 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM1D6 (IO_SIF_BASE + 0x298)
    #define FLD_SM1_DATA27 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM1_DATA26 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM1_DATA25 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_DATA24 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM1D7 (IO_SIF_BASE + 0x29C)
    #define FLD_SM1_DATA31 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM1_DATA30 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM1_DATA29 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_DATA28 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM1D8 (IO_SIF_BASE + 0x2A4)
    #define FLD_SM1_DATA35 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM1_DATA34 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM1_DATA33 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM1_DATA32 Fld(8,0,AC_FULLB0)//[7:0]

#if defined(CC_MT5893) || defined(CC_MT5895)
#define SIF_SM2CTL0 (IO_SIF_BASE + 0x200)
    #define FLD_SM2_ODRAIN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SM2_VSYNC_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_SM2_CLK_DIV Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SM2_DEG_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_WAIT_LEVEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SM2_DEG_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SM2_CS_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SM2_SCL_STATE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SM2_SDA_STATE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SM2_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM2_SCL_STRECH Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM2CTL1 (IO_SIF_BASE + 0x204)
    #define FLD_SM2_ACK0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_SM2_PGLEN Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_SM2_MODE Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SM2_TRI Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM2CTL2 (IO_SIF_BASE + 0x208)
    #define FLD_SM2_SCL_RISE_VALUE Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SM2_SCL_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM2SDEV (IO_SIF_BASE + 0x20C)
    #define FLD_SM2_DEV_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM2CTL3 (IO_SIF_BASE + 0x238)
	#define FLD_SM2_ACK1_DEVADDR_ACK Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SM2_ACK1 Fld(21,11,AC_MSKDW)//[31:11]
    #define FLD_SM2_WD_STOP_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SM2_STR_WD_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SM2_STR_WD_STOP_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SM2_RDNACK_STOP_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SM2_STR_RDACK_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SM2_STR_RDNACK_STOP_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SM2_SDEV_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SM2D0 (IO_SIF_BASE + 0x210)
    #define FLD_SM2_DATA3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM2_DATA2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM2_DATA1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_DATA0 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM2D1 (IO_SIF_BASE + 0x214)
    #define FLD_SM2_DATA7 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM2_DATA6 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM2_DATA5 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_DATA4 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM2D2 (IO_SIF_BASE + 0x218)
    #define FLD_SM2_DATA11 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM2_DATA10 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM2_DATA9 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_DATA8 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM2D3 (IO_SIF_BASE + 0x21C)
    #define FLD_SM2_DATA15 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM2_DATA14 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM2_DATA13 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_DATA12 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM2D4 (IO_SIF_BASE + 0x220)
    #define FLD_SM2_DATA19 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM2_DATA18 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM2_DATA17 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_DATA16 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM2D5 (IO_SIF_BASE + 0x224)
    #define FLD_SM2_DATA23 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM2_DATA22 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM2_DATA21 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_DATA20 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM2D6 (IO_SIF_BASE + 0x228)
    #define FLD_SM2_DATA27 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM2_DATA26 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM2_DATA25 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_DATA24 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM2D7 (IO_SIF_BASE + 0x22C)
    #define FLD_SM2_DATA31 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM2_DATA30 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM2_DATA29 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_DATA28 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SM2D8 (IO_SIF_BASE + 0x234)
    #define FLD_SM2_DATA35 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SM2_DATA34 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SM2_DATA33 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SM2_DATA32 Fld(8,0,AC_FULLB0)//[7:0]
#endif

//Page SIFSECSM0
#define SIF_SECSM0CTL0 (IO_SIF_SEC_BASE + 0x000)
    #define FLD_SECSM0_ODRAIN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SECSM0_VSYNC_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_SECSM0_CLK_DIV Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SECSM0_DEG_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_WAIT_LEVEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SECSM0_DEG_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SECSM0_CS_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SECSM0_SCL_STATE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SECSM0_SDA_STATE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SECSM0_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SECSM0_SCL_STRECH Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SECSM0CTL1 (IO_SIF_SEC_BASE + 0x004)
    #define FLD_SECSM0_ACK0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_SECSM0_PGLEN Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_SECSM0_MODE Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SECSM0_TRI Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SECSM0CTL2 (IO_SIF_SEC_BASE + 0x008)
    #define FLD_SECSM0_SCL_RISE_VALUE Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SECSM0_SCL_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SECSM0CTL3 (IO_SIF_SEC_BASE + 0x00C)
	#define FLD_SECSM0_ACK1_DEVADDR_ACK Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SECSM0_ACK1 Fld(21,11,AC_MSKDW)//[31:11]
    #define FLD_SECSM0_WD_STOP_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SECSM0_STR_WD_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SECSM0_STR_WD_STOP_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SECSM0_RDNACK_STOP_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SECSM0_STR_RDACK_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SECSM0_STR_RDNACK_STOP_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SECSM0_SDEV_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define SIF_SECSM0SDEV (IO_SIF_SEC_BASE + 0x010)
    #define FLD_SECSM0_DEV_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SECSM0D0 (IO_SIF_SEC_BASE + 0x014)
    #define FLD_SECSM0_DATA3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SECSM0_DATA2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SECSM0_DATA1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_DATA0 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SECSM0D1 (IO_SIF_SEC_BASE + 0x018)
    #define FLD_SECSM0_DATA7 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SECSM0_DATA6 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SECSM0_DATA5 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_DATA4 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SECSM0D2 (IO_SIF_SEC_BASE + 0x01C)
    #define FLD_SECSM0_DATA11 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SECSM0_DATA10 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SECSM0_DATA9 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_DATA8 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SECSM0D3 (IO_SIF_SEC_BASE + 0x020)
    #define FLD_SECSM0_DATA15 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SECSM0_DATA14 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SECSM0_DATA13 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_DATA12 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SECSM0D4 (IO_SIF_SEC_BASE + 0x024)
    #define FLD_SECSM0_DATA19 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SECSM0_DATA18 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SECSM0_DATA17 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_DATA16 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SECSM0D5 (IO_SIF_SEC_BASE + 0x028)
    #define FLD_SECSM0_DATA23 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SECSM0_DATA22 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SECSM0_DATA21 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_DATA20 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SECSM0D6 (IO_SIF_SEC_BASE + 0x02C)
    #define FLD_SECSM0_DATA27 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SECSM0_DATA26 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SECSM0_DATA25 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_DATA24 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SECSM0D7 (IO_SIF_SEC_BASE + 0x030)
    #define FLD_SECSM0_DATA31 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SECSM0_DATA30 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SECSM0_DATA29 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_DATA28 Fld(8,0,AC_FULLB0)//[7:0]
#define SIF_SECSM0D8 (IO_SIF_SEC_BASE + 0x034)
    #define FLD_SECSM0_DATA35 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SECSM0_DATA34 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SECSM0_DATA33 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SECSM0_DATA32 Fld(8,0,AC_FULLB0)//[7:0]

//---------------------------------------------------------------------------
// Macro definitions
//---------------------------------------------------------------------------

// SIF_MODE: start ==>data==>stop, start==>data, data==>stop, only data
typedef enum
{
	MODE_START		  = 0x1,
	MODE_WR_DATA	  = 0x2,
	MODE_STOP		  = 0x3,
	MODE_RD_DATA_LAST = 0x4,
	MODE_RD_DATA	  = 0x5,
} SIF_MODE_T;

//      need  deleate this enum 

typedef struct _I2CREG_T
{
	UINT32 ctl0;
	UINT32 ctl1;
	UINT32 ctl2;
	UINT32 ctl3;
	UINT32 sdev;
	UINT32 data0;
	UINT32 data1;
	UINT32 data2;
	UINT32 data3;
	UINT32 data4;
	UINT32 data5;
	UINT32 data6;
	UINT32 data7;
	UINT32 data8;
	UINT32 intren;
	UINT32 intren_fld;
	UINT32 intrst;
	UINT32 intrst_fld;
	UINT32 intrcl;
	UINT32 intrcl_fld;
	UINT32 hwrst;
	UINT32 hwrst_fld;
}I2CREG_T;

typedef struct _I2CMAST_T
{
	UINT8 strentch;
	UINT8 devmod;	
	UINT32 base;
	I2CREG_T I2cReg;	
}I2CMAST_T;

#define SIF_W   (0)
#define SIF_R   (1)

#define SIF_MAX_ALL_ICS_MASTER 6

//---------------------------------------------------------------------------
// Inter-file functions
//---------------------------------------------------------------------------
extern INT32 SIF_HwInit(UINT8 u1Channel);

#ifdef CC_CLI
extern INT32 SIF_Master_Stop(UINT8 u1Channel);
#endif

extern UINT16 SIF_RW(UINT16 clkdiv, UINT8 u1Channel, UINT8 addr, UINT32 sub_addr,
		UINT8 sub_addr_num, UINT8 isread, UINT8 *buf, UINT32 len);


#endif // SIF_HW_REG_H

