/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 * $Author:
 * $Date:
 * $RCSfile:
 * $Revision:
 *---------------------------------------------------------------------------*/

 /*
 **Check hard clip,volume formula,vol ramp,and loudness polling time
 */

#ifndef _AUD_AMP_RT9119_H_
#define _AUD_AMP_RT9119_H_

//---------------------------------------------------------------------------
// Include files
//---------------------------------------------------------------------------
#include "x_typedef.h"
//---------------------------------------------------------------------------
// Constant definitions
//---------------------------------------------------------------------------
typedef enum {
    RT9119_E_OK = 0,
    RT9119_E_ACCESS = -1,   // Access error
    RT9119_E_STATUS = -2,   // Status error
    RT9119_E_PARAM = -3,    // Parameter error
} RT9119_Error;

typedef enum {
    RT9119_AMP_ID_MAIN_SPEAKER,
    RT9119_AMP_ID_ASSIST_SPEAKER,
    RT9119_AMP_ID_MAX,
    RT9119_AMP_ID_INVALID
} RT9119_AmpId ;

typedef enum {
    RT9119_VERSION_RT9119 = 0x11,
    RT9119_VERSION_INVALID = 0xFF
} RT9119_Version ;

typedef enum {
    RT9119_OUTPUT_MODE_MONO,
    RT9119_OUTPUT_MODE_STEREO
} RT9119_OutputMode ;

typedef enum {
    RT9119_MONO_MIX_MUTE,
    RT9119_MONO_MIX_L_ONLY,
    RT9119_MONO_MIX_R_ONLY,
    RT9119_MONO_MIX_LR
} RT9119_MonoMix ;

typedef enum {
    RT9119_PHASE_NORMAL,
    RT9119_PHASE_REVERSE
} RT9119_Phase ;

typedef struct {
    int b0;
    int b1;
    int b2;
    int a1;
    int a2;
} RT9119IirCoeffSet;

typedef struct {
    RT9119IirCoeffSet sbqBass;
    RT9119IirCoeffSet sbqTreble;
} RT9119SbqCoeffSet;

/*
 * Channel Mixer
 */
typedef struct RT9119_ChMix {
    unsigned char mix_1[4];
    unsigned char mix_0[4];
} RT9119_ChMix;

typedef int RT9119_Fix32Q29;
#define RT9119_NULL 0
#define SIF_CLK_DIV 0x4D

#define RT9119_BQID_1       0
#define RT9119_BQID_2       1
#define RT9119_BQID_3       2
#define RT9119_BQID_4       3
#define RT9119_BQID_5       4
#define RT9119_BQID_6       5
#define RT9119_BQID_7       6
#define RT9119_BQID_8       7
#define RT9119_BQID_9       8
#define RT9119_BQID_10      9
#define RT9119_BQID_11      10
#define RT9119_BQID_12      11
#define RT9119_BQID_13      12
#define RT9119_BQID_14      13
#define RT9119_BQID_15      14
#define RT9119_BQID_16      15
#define RT9119_BQID_17      16
#define RT9119_BQID_18      17
//#define   RT9119_BASS_BQ      18
//#define   RT9119_TREBLE_BQ    19
#define RT9119_BQID_DRC1_1  18
#define RT9119_BQID_DRC1_2  19
#define RT9119_BQID_DRC2_1  20
#define RT9119_BQID_DRC2_2  21
#define RT9119_BQID_DRC3_1  22

#define RT9119_BQID_NUM     23

/*
**|DEFINE|ADDRESS|SIZE|VALUE|
*/
#define RT9119_REG_I2S_FMT_RPT          0x00    // Report Register
#define RT9119_REG_I2S_FMT_RPT_SIZE         1

#define RT9119_REG_DEV_ID               0x01    // Device ID
#define RT9119_REG_DEV_ID_SIZE              1

#define RT9119_REG_I2S_FMT              0x02    // I2S format Register
#define RT9119_REG_I2S_FMT_SIZE             1
#define RT9119_REG_MASK_SR_MODE_SEL             0x80    // Sampling Rate Selection(0:Auto Detection only)
#define RT9119_SR_MODE_SEL_AUTO                 0x00
#define RT9119_AUD_MODE_32BIT_I2S               0x07

#define RT9119_REG_ERR_RPT              0x03    // Error Report Register
#define RT9119_REG_ERR_RPT_SIZE             1
#define RT9119_ERR_RPT_CLEAR                    0x00

#define RT9119_REG_ERROR_MASK           0x04
#define RT9119_REG_ERROR_MASK_SIZE          1
#define RT9119_ERR_MASK_ENABLE                  1
#define RT9119_ERR_MASK_DISABLE                 0
#define RT9119_ERROR_MASK(no, enable)           (enable << (no-1))

#define RT9119_REG_SYS_CTL              0x05
#define RT9119_REG_SYS_CTL_SIZE             1
#define RT9119_REG_MASK_SHUDOWN                 0x40    // shutdown
#define RT9119_SHUDOWN_ON                       0x40
#define RT9119_SHUDOWN_OFF                      0x00
#define RT9119_D_SPK_VT_FREQ_800K               0x10
#define RT9119_D_SPK_VT_FREQ_400K               0x00
#define RT9119_DIS_A_SEL_PU_ENABLE              0x00
#define RT9119_DIS_A_SEL_PU_DISABLE             0x08
#define RT9119_DSR_DIV_SEL_AUTO                 0x00
#define RT9119_DSR_DIV_SEL_DEPEND               0x04
#define RT9119_MS_EN_MASTER_MODE                0x02
#define RT9119_MS_EN_SLAVE_MODE                 0x00
#define RT9119_REG_MASK_DREF_SEL                0x01
#define RT9119_DREF_SEL_MCLK                    0x00
#define RT9119_DREF_SEL_SCLK                    0x01

#define RT9119_REG_ERROR_TYPE           0x06
#define RT9119_REG_ERROR_TYPE_SIZE          1
#define RT9119_FAULT_TYPE_RECV                  0
#define RT9119_FAULT_TYPE_LATCH                 1
#define RT9119_FAULT_TYPE(no, enable)           (enable << (no-1))

#define RT9119_REG_MS_VOL               0x07    // Master Volume register
#define RT9119_REG_MS_VOL_SIZE              2
#define RT9119_REG_CH1_VOL              0x08    // Channel Volume(CH1) register
#define RT9119_REG_CH1_VOL_SIZE             2
#define RT9119_REG_CH2_VOL              0x09    // Channel Volume(CH2) register
#define RT9119_REG_CH2_VOL_SIZE             2
#define RT9119_REG_VOL_RAMP             0x0A    // Volumne Slew step control
#define RT9119_REG_VOL_RAMP_SIZE            1
#define RT9119_VOL_RAMP_STEP_512                0x00    // 43ms @48KHz
#define RT9119_VOL_RAMP_STEP_1024               0x01    // 85ms @48KHz
#define RT9119_VOL_RAMP_STEP_2048               0x02    // 171ms@48KHz
#define RT9119_VOL_RAMP_STEP_256                0x03    // 21ms @48KHz

#define RT9119_REG_AUTO_RCVRY           0x0B    // Power Stage auto recovery time
#define RT9119_REG_AUTO_RCVRY_SIZE          1
#define RT9119_BKD_TIME_300MS                   0x02
#define RT9119_BKD_TIME_450MS                   0x03
#define RT9119_BKD_TIME_600MS                   0x04
#define RT9119_BKD_TIME_750MS                   0x05
#define RT9119_BKD_TIME_900MS                   0x06
#define RT9119_BKD_TIME_1050MS                  0x07
#define RT9119_BKD_TIME_1200MS                  0x08
#define RT9119_BKD_TIME_1350MS                  0x09
#define RT9119_BKD_TIME_1500MS                  0x0A

#define RT9119_REG_FLTR_MISC            0x0C
#define RT9119_REG_FLTR_MISC_SIZE           1
#define RT9119_HPF_ENABLE                       0x80
#define RT9119_HPF_POS_ENABLE                   0x40
#define RT9119_REG_COMP_DISABLE                 0x00
#define RT9119_REG_MASK_FIR                     0x04
#define RT9119_FIR_ENABLE                       0x04
#define RT9119_FIR_DISABLE                      0x00
#define RT9119_SRC_RES_SEL_32                   0x02
#define RT9119_REG_MASK_PAGE_SEL                0x01
#define RT9119_PAGE_SEL_FIR                     0x01
#define RT9119_PAGE_SEL_DEFAULT                 0x00

#define RT9119_REG_SDIO_SEL             0x0D    // SDIN Selection
#define RT9119_REG_SDIO_SEL_SIZE            1
#define RT9119_CH1_SI_LEFT                      0x00
#define RT9119_CH1_SI_RIGHT                     0x04
#define RT9119_CH2_SI_LEFT                      0x00
#define RT9119_CH2_SI_RIGHT                     0x01
#define RT9119_CH_NORMAL                        (RT9119_CH1_SI_LEFT|RT9119_CH2_SI_RIGHT)
#define RT9119_CH_INVERSE                       (RT9119_CH1_SI_RIGHT|RT9119_CH2_SI_LEFT)

#define RT9119_REG_SPK_GAIN             0x0E    // Speaker Gain
#define RT9119_REG_SPK_GAIN_SIZE            1
#define RT9119_SPK_GAIN_8p00                    0x07
#define RT9119_SPK_GAIN_6p15                    0x06    // 6.15x
#define RT9119_SPK_GAIN_5p50                    0x05    // 5.50x
#define RT9119_SPK_GAIN_5p00                    0x04    // 5.00x
#define RT9119_SPK_GAIN_4p50                    0x03    // 4.50x
#define RT9119_SPK_GAIN_4p00                    0x02    // 4.50x
#define RT9119_SPK_GAIN_3p50                    0x01    // 3.50x
#define RT9119_SPK_GAIN_3p00                    0x00    // 3.50x

#define RT9119_REG_INTER_PWR_CTRL       0x0F    // Output Mode configuration
#define RT9119_REG_INTER_PWR_CTRL_SIZE      1
#define RT9119_REG_MASK_DAC_LPF_R               0x80    // DAC RCH LPF
#define RT9119_DAC_LPF_R_ENABLE                 0x80
#define RT9119_DAC_LPF_R_DISABLE                0x00
#define RT9119_REG_MASK_DAC_LPF_L               0x40    // DAC LCH LPF
#define RT9119_DAC_LPF_L_ENABLE                 0x40
#define RT9119_DAC_LPF_L_DISABLE                0x00
#define RT9119_REG_MASK_DAC_PWR_R               0x20    // DAC RCH PWR stage
#define RT9119_DAC_PWR_R_ENABLE                 0x20
#define RT9119_DAC_PWR_R_DISABLE                0x00
#define RT9119_REG_MASK_DAC_PWR_L               0x10    // DAC LCH LPF
#define RT9119_DAC_PWR_L_ENABLE                 0x10
#define RT9119_DAC_PWR_L_DISABLE                0x00
#define RT9119_REG_MASK_DAC_RCH                 0x08    // DAC RCH
#define RT9119_DAC_RCH_ENABLE                   0x08
#define RT9119_DAC_RCH_DISABLE                  0x00
#define RT9119_REG_MASK_DAC_LCH                 0x04    // DAC LCH
#define RT9119_DAC_LCH_ENABLE                   0x04
#define RT9119_DAC_LCH_DISABLE                  0x00
#define RT9119_REG_MASK_SPK_RCH                 0x02    // SPK RCH
#define RT9119_SPK_RCH_ENABLE                   0x02
#define RT9119_SPK_RCH_DISABLE                  0x00
#define RT9119_REG_MASK_SPK_LCH                 0x01    // SPK LCH
#define RT9119_SPK_LCH_ENABLE                   0x01
#define RT9119_SPK_LCH_DISABLE                  0x00

#define RT9119_REG_DC_PROTECT           0x10
#define RT9119_REG_DC_PROTECT_SIZE          1
#define RT9119_DC_TH_DISABLE                    0x00
#define RT9119_DC_TH_12p5                       0x10
#define RT9119_DC_TH_18p75                      0x20
#define RT9119_DC_TH_25                         0x30
#define RT9119_DC_FREQ_768K                     0x00
#define RT9119_DC_FREQ_384K                     0x04
#define RT9119_DC_TIME_342                      0x00
#define RT9119_DC_TIME_684                      0x02
#define RT9119_DC_PROTECT_ENABLE                0x01

#define RT9119_REG_PWM_SS_OPT1          0x11    // PWM SS OPT
#define RT9119_REG_PWM_SS_OPT_SIZE          1
#define RT9119_REG_PWM_SS_OPT_DEFAULT           0x01

#define RT9119_REG_CHx_MIX_SIZE             sizeof(RT9119_ChMix)
#define RT9119_REG_CH1_IN_MIX           0x12
#define RT9119_REG_CH2_IN_MIX           0x13
#define RT9119_REG_CH1_OUT_MIX          0xA4
#define RT9119_REG_CH2_OUT_MIX          0xA5
#define RT9119_OUT_MIXDEFAULT_POS               24

#define RT9119_REG_L_BQ_BOOST           0x14
#define RT9119_REG_R_BQ_BOOST           0x15
#define RT9119_REG_EQ_BYPASS_L          0x16
#define RT9119_REG_EQ_BYPASS_R          0x17
#define RT9119_REG_EQ_CTRL              0x18
#define RT9119_REG_PEQ_L_GAIN_SIZE          4
#define RT9119_REG_PEQ_R_GAIN_SIZE          4
#define RT9119_REG_EQ_CTRL_SIZE             1
#define RT9119_PEQ_GAIN_DEFAULT                 0x00000000
#define RT9119_EQ_LINK                          0x10
#define RT9119_DRC_EQ_LINK                      0x08

#define RT9119_REG_SBQ_ALPHA            0x19
#define RT9119_REG_SBQ_CTRL             0x1A
#define RT9119_REG_SBQ_ALPHA_SIZE           4
#define RT9119_REG_SBQ_CTRL_SIZE            4
#define RT9119_SBQ_UPDATE_DELAY_1024            0x0000FF00
#define RT9119_SBQ_CTRL_LINEAR_GAIN             0x00000008
#define RT9119_SBQ_DONE_BIT                     0x00000004
#define RT9119_REG_MASK_SBQ_UPDATE              0x00000003
#define RT9119_SBQ_UPDATE                       0x00000003
#define RT9119_SBQ_NO_UPDATE                    0x00000000

//#define RT9119_BQ_COEFF_SIZE              4
typedef struct RT9119_BqCoeff {
    unsigned char b0[4];
    unsigned char b1[4];
    unsigned char b2[4];
    unsigned char a1[4];
    unsigned char a2[4];
} RT9119_BqCoeff;
#define RT9119_REG_BQx_SIZE                 sizeof(RT9119_BqCoeff)      // BQ filter register size
#define RT9119_REG_CH1_BQ_01            0x20    // BQ filter 1
#define RT9119_REG_CH1_BQ_02            0x21    // BQ filter 2
#define RT9119_REG_CH1_BQ_03            0x22    // BQ filter 3
#define RT9119_REG_CH1_BQ_04            0x23    // BQ filter 4
#define RT9119_REG_CH1_BQ_05            0x24    // BQ filter 5
#define RT9119_REG_CH1_BQ_06            0x25    // BQ filter 6
#define RT9119_REG_CH1_BQ_07            0x26    // BQ filter 7
#define RT9119_REG_CH1_BQ_08            0x27    // BQ filter 8
#define RT9119_REG_CH1_BQ_09            0x28    // BQ filter 9
#define RT9119_REG_CH1_BQ_10            0x29    // BQ filter 10
#define RT9119_REG_CH1_BQ_11            0x2A    // BQ filter 11
#define RT9119_REG_CH1_BQ_12            0x2B    // BQ filter 12
#define RT9119_REG_CH1_SBQ_13           0x2C    // BQ filter 13
#define RT9119_REG_CH1_SBQ_14           0x2D    // BQ filter 14
#define RT9119_REG_CH1_SBQ_15           0x2E    // BQ filter 15
#define RT9119_REG_CH1_SBQ_16           0x2F    // BQ filter 16
#define RT9119_REG_CH1_SBQ_17           0x30    // BQ filter 17
#define RT9119_REG_CH1_SBQ_18           0x31    // BQ filter 18
#define RT9119_REG_CH1_SBQ_BK_1         0x32    // BQ filter 19
#define RT9119_REG_CH1_SBQ_BK_2         0x33    // BQ filter 20
#define RT9119_REG_DRC1_CH1_BQ_1        0x70    // DRC LB BQ 1
#define RT9119_REG_DRC1_CH1_BQ_2        0x71    // DRC LB BQ 2
#define RT9119_REG_DRC1_CH2_BQ_1        0x72    // DRC LB BQ 1
#define RT9119_REG_DRC1_CH2_BQ_2        0x73    // DRC LB BQ 2
#define RT9119_REG_DRC2_CH1_BQ_1        0x74    // DRC MB BQ 1
#define RT9119_REG_DRC2_CH1_BQ_2        0x75    // DRC MB BQ 2
#define RT9119_REG_DRC2_CH2_BQ_1        0x76    // DRC MB BQ 1
#define RT9119_REG_DRC2_CH2_BQ_2        0x77    // DRC MB BQ 2
#define RT9119_REG_DRC3_CH1_BQ_1        0x78    // DRC HB BQ 1
#define RT9119_REG_DRC3_CH2_BQ_1        0x79    // DRC HB BQ 1

typedef enum  {
    RT9119_DRC_RMS_MODE = 0,
    RT9119_DRC_PEAK_MODE = 1
}   RT9119_DrcPeakMode;
#define RT9119_REG_DRC_CTRL1            0x60
#define RT9119_REG_DRC_CTRL2            0x61
#define RT9119_REG_DRC_CTRL1_SIZE           1
#define RT9119_REG_DRC_CTRL2_SIZE           1
#define RT9119_REG_MASK_DRC4_PEAK               0x80
#define RT9119_REG_MASK_DRC3_PEAK               0x40
#define RT9119_REG_MASK_DRC2_PEAK               0x20
#define RT9119_REG_MASK_DRC1_PEAK               0x10
#define RT9119_DRCxPeak(no, mode)               (mode << (4+no-1))
#define RT9119_DRCPeak                          0xF0
#define RT9119_REG_MASK_DRC4_ENABLE             0x08    // DRC4 Enable
#define RT9119_DRC4_ENABLE                      0x08
#define RT9119_DRC4_DISABLE                     0x00
#define RT9119_REG_MASK_DRC3_ENABLE             0x04    // DRC3 Enable
#define RT9119_DRC3_ENABLE                      0x04
#define RT9119_DRC3_DISABLE                     0x00
#define RT9119_REG_MASK_DRC2_ENABLE             0x02    // DRC2 Enable
#define RT9119_DRC2_ENABLE                      0x02
#define RT9119_DRC2_DISABLE                     0x00
#define RT9119_REG_MASK_DRC1_ENABLE             0x01    // DRC1 Enable
#define RT9119_DRC1_ENABLE                      0x01
#define RT9119_DRC1_DISABLE                     0x00
#define RT9119_REG_MASK_DRC4_N_EN               0x80
#define RT9119_REG_MASK_DRC3_N_EN               0x40
#define RT9119_REG_MASK_DRC2_N_EN               0x20
#define RT9119_REG_MASK_DRC1_N_EN               0x10
#define RT9119_DRC_NOISE_GATE_ENABLE            1
#define RT9119_DRC_NOISE_GATE_DISABLE           0
#define RT9119_DRCxNoiseGate(no, enable)        (enable << (4+no-1))
#define RT9119_REG_MASK_DRC3_BYPASS             0x08
#define RT9119_REG_DRC2_BYPASS_ENABLE           0x08
#define RT9119_REG_DRC2_BYPASS_DISABLE          0x00
#define RT9119_REG_MASK_DRC1_BYPASS             0x04
#define RT9119_REG_DRC1_BYPASS_ENABLE           0x04
#define RT9119_REG_DRC1_BYPASS_DISABLE          0x00
#define RT9119_REG_MASK_DRC2_BYPASS             0x02
#define RT9119_REG_DRC3_BYPASS_ENABLE           0x02
#define RT9119_REG_DRC3_BYPASS_DISABLE          0x00
#define RT9119_REG_MASK_FREQ_DRC_MODE           0x01
#define RT9119_FREQ_DRC_MODE_ON                 0x01
#define RT9119_FREQ_DRC_MODE_OFF                0x00
#define RT9119_REG_DRC4_DELAY           0xA8    // DRC4 delay
#define RT9119_REG_DRC4_DELAY_SIZE          1

/*
 * DRC
 */
typedef struct RT9119_RmsAe {
    unsigned char ae[4];
    unsigned char o_ae[4];
} RT9119_RmsAe;
#define RT9119_REG_DRCx_RMS_AE_SIZE         sizeof(RT9119_RmsAe)

typedef struct RT9119_GainAa {
    unsigned char aa[4];
    unsigned char o_aa[4];
} RT9119_GainAa;
#define RT9119_REG_DRCx_GAIN_AA_SIZE        sizeof(RT9119_GainAa)

typedef struct RT9119_GainAd {
    unsigned char ad[4];
    unsigned char o_ad[4];
} RT9119_GainAd;
#define RT9119_REG_DRCx_GAIN_AD_SIZE        sizeof(RT9119_GainAd)

#define RT9119_REG_DRCx_T_SIZE              4
#define RT9119_REG_DRCx_K_SIZE              4
#define RT9119_REG_DRCx_O_SIZE              4

#define RT9119_REG_DRC1_RMS_AE                  0x90
#define RT9119_REG_DRC1_GAIN_AA                 0x91
#define RT9119_REG_DRC1_GAIN_AD                 0x92
#define RT9119_REG_DRC1_T                       0x93
#define RT9119_REG_DRC1_K                       0x94
#define RT9119_REG_DRC1_O                       0x95

#define RT9119_REG_DRC2_RMS_AE                  0x96
#define RT9119_REG_DRC2_GAIN_AA                 0x97
#define RT9119_REG_DRC2_GAIN_AD                 0x98
#define RT9119_REG_DRC2_T                       0x99
#define RT9119_REG_DRC2_K                       0x9A
#define RT9119_REG_DRC2_O                       0x9B

#define RT9119_REG_DRC3_RMS_AE                  0x9C
#define RT9119_REG_DRC3_GAIN_AA                 0x9D
#define RT9119_REG_DRC3_GAIN_AD                 0x9E
#define RT9119_REG_DRC3_T                       0x9F
#define RT9119_REG_DRC3_K                       0xA0
#define RT9119_REG_DRC3_O                       0xA1

#define RT9119_REG_DRC4_RMS_AE                  0xAD
#define RT9119_REG_DRC4_GAIN_AA                 0xAE
#define RT9119_REG_DRC4_GAIN_AD                 0xAF
#define RT9119_REG_DRC4_T                       0xAA
#define RT9119_REG_DRC4_K                       0xAB
#define RT9119_REG_DRC4_O                       0xAC

#define RT9119_DRC_MAX_THRESHOLD                240
#define RT9119_DRC_MIN_THRESHOLD                -1200
#define RT9119_DRC_MAX_RATIO                    100
#define RT9119_DRC_MIN_RATIO                    0
#define RT9119_DRC_MAX_OFFSET                   255
#define RT9119_DRC_MIN_OFFSET                   -120

typedef struct RT9119_DrcMix {
    unsigned char low[4];
    unsigned char mid[4];
    unsigned char hi[4];
} RT9119_DrcMix;
#define RT9119_REG_DRC_MIX_SIZE             sizeof(RT9119_DrcMix)
#define RT9119_REG_DRC_MIX_LEFT         0xA2
#define RT9119_REG_DRC_MIX_RIGHT        0xA3
#define RT9119_REG_DRC_NG_TH            0xA9
#define RT9119_REG_DRC_NG_TH_SIZE           4

/*
 * Scaler
 */
#define RT9119_REG_POST_SCALE               0xA7    // Post Scaler
#define RT9119_REG_POST_SCALE_SIZE          4
#define RT9119_REG_PRE_SCALE                0xA6    // Pre Scaler(9.17 format. 0dB : 0x00020000)
#define RT9119_REG_PRE_SCALE_SIZE           4


/*
 * Hard Clipper
 */
#define RT9119_REG_HARD_CLIP            0xB0
#define RT9119_REG_HARD_CLIP_SIZE           4
#define RT9119_REG_MASK_HARD_CLIP_EN            0x80000000
#define RT9119_HARD_CLIP_ENABLE                 0x80000000
#define RT9119_HARD_CLIP_DISABLE                0x00000000
#define RT9119_REG_MASK_DF_CLIP_EN              0x40000000
#define RT9119_DF_CLIP_ENABLE                   0x40000000
#define RT9119_REG_MASK_HARD_CLIP_TH            0x0007FF00
#define RT9119_HARD_CLIP_TH_24DB                0x000
#define RT9119_HARD_CLIP_TH_0DB                 0x180
#define RT9119_REG_SHIFT_HARD_CLIP_TH           8
#define RT9119_POST_IDF_0DB                     0x00000080

/*
 * FINAL GAIN Output
 */
#define RT9119_REG_FINAL_GAIN_OPT           0xBB
#define RT9119_REG_FINAL_GAIN_OUT_SIZE      1
#define RT9119_FINAL_GAIN_0DB               0x00
#define RT9119_FINAL_GAIN_6DB               0x08
#define RT9119_GAIN_PAIR_CTRL_0DB           0x00
#define RT9119_GAIN_PAIR_CTRL_6DB           0x01
#define RT9119_GAIN_PAIR_CTRL_12DB          0x02
#define RT9119_GAIN_PAIR_CTRL_18DB          0x03

//Prohibited
#define RT9119_REG_PWR_SEL                  0xD5
#define RT9119_REG_PWR_SEL_SIZE                 1
#define RT9119_VR_ANA_5_7V                          0x01
#define RT9119_REG_ANA_MODULTR2             0xCE
#define RT9119_REG_ANA_MODULTR2_SIZE            1
#define RT9119_VCM_0_5                              0x0C
#define RT9119_REG_DEPOP_GLITCH             0xD8
#define RT9119_REG_DEPOP_GLITCH_SIZE            1
#define RT9119_DEPOP_GLITCH_DISABLE                 0x01
#define RT9119_REG_SERVO_TIME_OPT           0xE0
#define RT9119_REG_SERVO_TIME_OPT_SIZE          1
#define RT9119_SST_40MS                             0x31

typedef enum {
    RT9119_FALSE,
    RT9119_TRUE
} RT9119_Bool;

#define RT9119_FIR_COEFF_SIZE                   4
#define RT9119_FIR_TAP_NO                       128
#define RT9119_FIR_CLEAR                        0x00000000

typedef enum {
    RT9119_MULTI_DRC_MODE_DISABLE,      // Disable
    RT9119_MULTI_DRC_MODE_1BAND,
    RT9119_MULTI_DRC_MODE_2BAND,
    RT9119_MULTI_DRC_MODE_3BAND
} RT9119_MultiDrcMode;

typedef struct {
//  unsigned char report[RT9119_REG_I2S_FMT_RPT_SIZE];              // 0x00 : RT9119_REG_I2S_FMT_RPT(RO)
//  unsigned char deviceId[RT9119_REG_DEV_ID_SIZE];                 // 0x01 : RT9119_REG_DEV_ID(RO)
    unsigned char i2sFmt[RT9119_REG_I2S_FMT_SIZE];                  // 0x02 : RT9119_REG_I2S_FMT
    unsigned char errReport[RT9119_REG_ERR_RPT_SIZE];               // 0x03 : RT9119_REG_ERR_RPT
    unsigned char errMask[RT9119_REG_ERROR_MASK_SIZE];              // 0x04 : RT9119_REG_ERROR_MASK
    unsigned char sys_ctl[RT9119_REG_SYS_CTL_SIZE];                     // 0x05 : RT9119_SYS_CTL
    unsigned char errType[RT9119_REG_ERROR_TYPE_SIZE];              // 0x06 : RT9119_REG_ERROR_TYPE
    unsigned char masterVolume[RT9119_REG_MS_VOL_SIZE];             // 0x07 : RT9119_REG_MS_VOL
    unsigned char ch1Volume[RT9119_REG_CH1_VOL_SIZE];               // 0x08 : RT9119_REG_CH1_VOL
    unsigned char ch2Volume[RT9119_REG_CH2_VOL_SIZE];               // 0x09 : RT9119_REG_CH2_VOL
    unsigned char volRamp[RT9119_REG_VOL_RAMP_SIZE];                // 0x0A : RT9119_REG_VOL_RAMP
    unsigned char autoRcvry[RT9119_REG_AUTO_RCVRY_SIZE];            // 0x0B : RT9119_REG_AUTO_RCVRY
    unsigned char fltrMisc[RT9119_REG_FLTR_MISC_SIZE];                  // 0x0C : RT9119_REG_FLTR_MISC
    unsigned char sdIoSel[RT9119_REG_SDIO_SEL_SIZE];                // 0x0D : RT9119_REG_SDIO_SEL
    unsigned char spkGain[RT9119_REG_SPK_GAIN_SIZE];                // 0x0E : RT9119_REG_SPK_GAIN
    unsigned char interPwrCtrl[RT9119_REG_INTER_PWR_CTRL_SIZE];     // 0x0F : RT9119_REG_INTER_PWR_CTRL
    unsigned char dcProtect[RT9119_REG_DC_PROTECT_SIZE];            // 0x10 : RT9119_REG_DC_PROT
    unsigned char pwmSsOpt[RT9119_REG_PWM_SS_OPT_SIZE];             // 0x11 : RT9119_REG_PWM_SS_OPT1
    unsigned char ch1InMix[RT9119_REG_CHx_MIX_SIZE];                // 0x12 : RT9119_REG_CH1_IN_MIX
    unsigned char ch2InMix[RT9119_REG_CHx_MIX_SIZE];                // 0x13 : RT9119_REG_CH2_IN_MIX
    unsigned char eqBoostL[RT9119_REG_PEQ_L_GAIN_SIZE];             // 0x14 : EQ_BOOST_L
    unsigned char eqBoostR[RT9119_REG_PEQ_R_GAIN_SIZE];             // 0x15 : EQ_BOOST_R
//  unsigned char eqBypassL[RT9119_REG_PEQ_L_GAIN_SIZE];            // 0x16 : RT9119_REG_EQ_BYPASS_L
//  unsigned char eqBypassR[RT9119_REG_PEQ_R_GAIN_SIZE];            // 0x17 : RT9119_REG_EQ_BYPASS_R
    unsigned char eqCtrl[RT9119_REG_EQ_CTRL_SIZE];                  // 0x18 : RT9119_REG_EQ_CTRL
    unsigned char sbqAlphaCoeff[RT9119_REG_SBQ_ALPHA_SIZE];         // 0x19 : RT9119_RT9119_REG_SBQ_ALPHA
    unsigned char sbqBqctrl[RT9119_REG_SBQ_CTRL_SIZE];              // 0x1A : RT9119_REG_SBQ_CTRL
    unsigned char ch1Bq01[RT9119_REG_BQx_SIZE];                     // 0x20 : RT9119_REG_CH1_BQ_01
    unsigned char ch1Bq02[RT9119_REG_BQx_SIZE];                     // 0x21 : RT9119_REG_CH1_BQ_02
    unsigned char ch1Bq03[RT9119_REG_BQx_SIZE];                     // 0x22 : RT9119_REG_CH1_BQ_03
    unsigned char ch1Bq04[RT9119_REG_BQx_SIZE];                     // 0x23 : RT9119_REG_CH1_BQ_04
    unsigned char ch1Bq05[RT9119_REG_BQx_SIZE];                     // 0x24 : RT9119_REG_CH1_BQ_05
    unsigned char ch1Bq06[RT9119_REG_BQx_SIZE];                     // 0x25 : RT9119_REG_CH1_BQ_06
    unsigned char ch1Bq07[RT9119_REG_BQx_SIZE];                     // 0x26 : RT9119_REG_CH1_BQ_07
    unsigned char ch1Bq08[RT9119_REG_BQx_SIZE];                     // 0x27 : RT9119_REG_CH1_BQ_08
    unsigned char ch1Bq09[RT9119_REG_BQx_SIZE];                     // 0x28 : RT9119_REG_CH1_BQ_09
    unsigned char ch1Bq10[RT9119_REG_BQx_SIZE];                     // 0x29 : RT9119_REG_CH1_BQ_10
    unsigned char ch1Bq11[RT9119_REG_BQx_SIZE];                     // 0x2A : RT9119_REG_CH1_BQ_11
    unsigned char ch1Bq12[RT9119_REG_BQx_SIZE];                     // 0x2B : RT9119_REG_CH1_BQ_12
    unsigned char ch1SBq13[RT9119_REG_BQx_SIZE];                    // 0x2C : RT9119_REG_CH1_SBQ_13
    unsigned char ch1SBq14[RT9119_REG_BQx_SIZE];                    // 0x2D : RT9119_REG_CH1_SBQ_14
    unsigned char ch1SBq15[RT9119_REG_BQx_SIZE];                    // 0x2E : RT9119_REG_CH1_SBQ_15
    unsigned char ch1SBq16[RT9119_REG_BQx_SIZE];                    // 0x2F : RT9119_REG_CH1_SBQ_16
    unsigned char ch1SBq17[RT9119_REG_BQx_SIZE];                    // 0x30 : RT9119_REG_CH1_SBQ_17
    unsigned char ch1SBq18[RT9119_REG_BQx_SIZE];                    // 0x31 : RT9119_REG_CH1_SBQ_18
    unsigned char ch1SBqBk1[RT9119_REG_BQx_SIZE];                   // 0x32 : RT9119_REG_CH1_SBQ_BK_1
    unsigned char ch1SBqBk2[RT9119_REG_BQx_SIZE];                   // 0x33 : RT9119_REG_CH1_SBQ_BK_2
//  unsigned char ch2Bq01[RT9119_REG_BQx_SIZE];                     // 0x40 : RT9119_REG_CH2_BQ_01
//  unsigned char ch2Bq02[RT9119_REG_BQx_SIZE];                     // 0x41 : RT9119_REG_CH2_BQ_02
//  unsigned char ch2Bq03[RT9119_REG_BQx_SIZE];                     // 0x42 : RT9119_REG_CH2_BQ_03
//  unsigned char ch2Bq04[RT9119_REG_BQx_SIZE];                     // 0x43 : RT9119_REG_CH2_BQ_04
//  unsigned char ch2Bq05[RT9119_REG_BQx_SIZE];                     // 0x44 : RT9119_REG_CH2_BQ_05
//  unsigned char ch2Bq06[RT9119_REG_BQx_SIZE];                     // 0x45 : RT9119_REG_CH2_BQ_06
//  unsigned char ch2Bq07[RT9119_REG_BQx_SIZE];                     // 0x46 : RT9119_REG_CH2_BQ_07
//  unsigned char ch2Bq08[RT9119_REG_BQx_SIZE];                     // 0x47 : RT9119_REG_CH2_BQ_08
//  unsigned char ch2Bq09[RT9119_REG_BQx_SIZE];                     // 0x48 : RT9119_REG_CH2_BQ_09
//  unsigned char ch2Bq10[RT9119_REG_BQx_SIZE];                     // 0x49 : RT9119_REG_CH2_BQ_10
//  unsigned char ch2Bq11[RT9119_REG_BQx_SIZE];                     // 0x4A : RT9119_REG_CH2_BQ_11
//  unsigned char ch2Bq12[RT9119_REG_BQx_SIZE];                     // 0x4B : RT9119_REG_CH2_BQ_12
//  unsigned char ch2SBq13[RT9119_REG_BQx_SIZE];                    // 0x4C : RT9119_REG_CH2_SBQ_13
//  unsigned char ch2SBq14[RT9119_REG_BQx_SIZE];                    // 0x4D : RT9119_REG_CH2_SBQ_14
//  unsigned char ch2SBq15[RT9119_REG_BQx_SIZE];                    // 0x4E : RT9119_REG_CH2_SBQ_15
//  unsigned char ch2SBq16[RT9119_REG_BQx_SIZE];                    // 0x4F : RT9119_REG_CH2_SBQ_16
//  unsigned char ch2SBq17[RT9119_REG_BQx_SIZE];                    // 0x50 : RT9119_REG_CH2_SBQ_17
//  unsigned char ch2SBq18[RT9119_REG_BQx_SIZE];                    // 0x51 : RT9119_REG_CH2_SBQ_18
//  unsigned char ch2SBqBk1[RT9119_REG_BQx_SIZE];                   // 0x52 : RT9119_REG_CH2_SBQ_BK_1
//  unsigned char ch2SBqBk1[RT9119_REG_BQx_SIZE];                   // 0x53 : RT9119_REG_CH1_SBQ_BK_2
    unsigned char drcCtrl1[RT9119_REG_DRC_CTRL1_SIZE];              // 0x60 : RT9119_REG_DRC_CTRL1
    unsigned char drcCtrl2[RT9119_REG_DRC_CTRL2_SIZE];              // 0x61 : RT9119_REG_DRC_CTRL2
//  unsigned char skipMBDrcBQ1[RT9119_REG_MB_BQ1_SKIP_SIZE];        // 0x62 : RT9119_REG_MB_BQ1_SKIP
//  unsigned char skipMBDrcBQ2[RT9119_REG_MB_BQ2_SKIP_SIZE];        // 0x63 : RT9119_REG_MB_BQ2_SKIP
/*
Drc1 - LB
*/
    unsigned char drc1Ch1Bq1[RT9119_REG_BQx_SIZE];                  // 0x70 : RT9119_REG_DRC1_CH1_BQ_1
    unsigned char drc1Ch1Bq2[RT9119_REG_BQx_SIZE];                  // 0x71 : RT9119_REG_DRC1_CH1_BQ_2
//  unsigned char drc1Ch2Bq1[RT9119_REG_BQx_SIZE];                  // 0x72 : RT9119_REG_DRC1_CH2_BQ_1
//  unsigned char drc1Ch2Bq2[RT9119_REG_BQx_SIZE];                  // 0x73 : RT9119_REG_DRC1_CH2_BQ_2
/*
DRC2 - MB
*/
    unsigned char drc2Ch1Bq1[RT9119_REG_BQx_SIZE];                  // 0x74 : RT9119_REG_DRC2_CH1_BQ_1
    unsigned char drc2Ch1Bq2[RT9119_REG_BQx_SIZE];                  // 0x75 : RT9119_REG_DRC2_CH1_BQ_2
//  unsigned char drc2Ch2Bq1[RT9119_REG_BQx_SIZE];                  // 0x76 : RT9119_REG_DRC2_CH2_BQ_1
//  unsigned char drc2Ch2Bq2[RT9119_REG_BQx_SIZE];                  // 0x77 : RT9119_REG_DRC2_CH2_BQ_2
/*
DRC3 - HB
*/
    unsigned char drc3Ch1Bq1[RT9119_REG_BQx_SIZE];                  // 0x78 : RT9119_REG_DRC3_CH1_BQ_1
//  unsigned char drc3Ch1Bq2[RT9119_REG_BQx_SIZE];                  // 0x79 : RT9119_REG_DRC3_CH1_BQ_2

//  unsigned char sfReset[RT9119_REG_SF_RESET_SIZE];                // 0x80 : RT9119_REG_SF_RESET

/*
DRC CTRL
*/
    unsigned char drc1RmsAe[RT9119_REG_DRCx_RMS_AE_SIZE];           // 0x90 : RT9119_REG_DRC1_RMS_AE
    unsigned char drc1GainAa[RT9119_REG_DRCx_GAIN_AA_SIZE];         // 0x91 : RT9119_REG_DRC1_GAIN_AA
    unsigned char drc1GainAd[RT9119_REG_DRCx_GAIN_AD_SIZE];         // 0x92 : RT9119_REG_DRC1_GAIN_AD
    unsigned char drc1T[RT9119_REG_DRCx_T_SIZE];                    // 0x93 : RT9119_REG_DRC1_T
    unsigned char drc1K[RT9119_REG_DRCx_K_SIZE];                    // 0x94 : RT9119_REG_DRC1_K
    unsigned char drc1O[RT9119_REG_DRCx_O_SIZE];                    // 0x95 : RT9119_REG_DRC1_O
    unsigned char drc2RmsAe[RT9119_REG_DRCx_RMS_AE_SIZE];           // 0x96 : RT9119_REG_DRC2_RMS_AE
    unsigned char drc2GainAa[RT9119_REG_DRCx_GAIN_AA_SIZE];         // 0x97 : RT9119_REG_DRC2_GAIN_AA
    unsigned char drc2GainAd[RT9119_REG_DRCx_GAIN_AD_SIZE];         // 0x98 : RT9119_REG_DRC2_GAIN_AD
    unsigned char drc2T[RT9119_REG_DRCx_T_SIZE];                    // 0x99 : RT9119_REG_DRC2_T
    unsigned char drc2K[RT9119_REG_DRCx_K_SIZE];                    // 0x9A : RT9119_REG_DRC2_K
    unsigned char drc2O[RT9119_REG_DRCx_O_SIZE];                    // 0x9B : RT9119_REG_DRC2_O
    unsigned char drc3RmsAe[RT9119_REG_DRCx_RMS_AE_SIZE];           // 0x9C : RT9119_REG_DRC3_RMS_AE
    unsigned char drc3GainAa[RT9119_REG_DRCx_GAIN_AA_SIZE];         // 0x9D : RT9119_REG_DRC3_GAIN_AA
    unsigned char drc3GainAd[RT9119_REG_DRCx_GAIN_AD_SIZE];         // 0x9E : RT9119_REG_DRC3_GAIN_AD
    unsigned char drc3T[RT9119_REG_DRCx_T_SIZE];                    // 0x9F : RT9119_REG_DRC3_T
    unsigned char drc3K[RT9119_REG_DRCx_K_SIZE];                    // 0xA0 : RT9119_REG_DRC3_K
    unsigned char drc3O[RT9119_REG_DRCx_O_SIZE];                    // 0xA1 : RT9119_REG_DRC3_O
    unsigned char drcMixLeft[RT9119_REG_DRC_MIX_SIZE];              // 0xA2 : RT9119_REG_DRC_MIX_LEFT
    unsigned char drcMixRight[RT9119_REG_DRC_MIX_SIZE];             // 0xA3 : RT9119_REG_DRC_MIX_RIGHT

    unsigned char ch1OutMix[RT9119_REG_CHx_MIX_SIZE];               // 0xA4 : RT9119_REG_CH1_OUT_MIX
    unsigned char ch2OutMix[RT9119_REG_CHx_MIX_SIZE];               // 0xA5 : RT9119_REG_CH2_OUT_MIX

    unsigned char preScale[RT9119_REG_PRE_SCALE_SIZE];              // 0xA6 : RT9119_REG_PRE_SCALE
    unsigned char postScale[RT9119_REG_POST_SCALE_SIZE];            // 0xA7 : RT9119_REG_POST_SCALE

/*
DRC4
*/
    unsigned char drc4Delay[RT9119_REG_DRC4_DELAY_SIZE];            // 0x0A : RT9119_REG_DRC4_DELAY
    unsigned char drcNT[RT9119_REG_DRC_NG_TH_SIZE];                 // 0xA9 : RT9119_REG_DRC_NG_TH
    unsigned char drc4T[RT9119_REG_DRCx_T_SIZE];                    // 0xAA : RT9119_REG_DRC4_T
    unsigned char drc4K[RT9119_REG_DRCx_K_SIZE];                    // 0xAB : RT9119_REG_DRC4_K
    unsigned char drc4O[RT9119_REG_DRCx_O_SIZE];                    // 0xAC : RT9119_REG_DRC4_O
    unsigned char drc4RmsAe[RT9119_REG_DRCx_RMS_AE_SIZE];           // 0xAD : RT9119_REG_DRC4_RMS_AE
    unsigned char drc4GainAa[RT9119_REG_DRCx_GAIN_AA_SIZE];         // 0xAE : RT9119_REG_DRC4_GAIN_AA
    unsigned char drc4GainAd[RT9119_REG_DRCx_GAIN_AD_SIZE];         // 0xAF : RT9119_REG_DRC3_GAIN_AD

    unsigned char hardClip[RT9119_REG_HARD_CLIP_SIZE];              // 0xB0 : RT9119_REG_HARD_CLIP
//  unsigned char compFLTR1[RT9119_REG_COMP_FLTR1_SIZE]             // 0xB1 : RT9119_REG_COMP_FLTR1
//  unsigned char compFLTR2[RT9119_REG_COMP_FLTR2_SIZE]             // 0xB2 : RT9119_REG_COMP_FLTR2
//  unsigned char outLevelA[]                                       // 0xB8 : RT9119_REG_OUT_LEVEL_A
//  unsigned char ch1RmsReport[RT9119_REG_CH1_RMS_REPORT_SIZE];     // 0xB9 : RT9119_REG_CH1_RMS_REPORT(RO)
//  unsigned char ch2RmsReport[RT9119_REG_CH1_RMS_REPORT_SIZE];     // 0xBA : RT9119_REG_CH2_RMS_REPORT(RO)
    unsigned char gainOpt[RT9119_REG_FINAL_GAIN_OUT_SIZE];          // 0xBB : RT9119_REG_FINAL_GAIN_OPT
    unsigned char fir[RT9119_FIR_TAP_NO][RT9119_FIR_COEFF_SIZE];    //
    unsigned char depopGlitch[RT9119_REG_DEPOP_GLITCH_SIZE];        // 0xD8 : RT9119_REG_DEPOP_GLITCH
    unsigned char servotimeOpt[RT9119_REG_SERVO_TIME_OPT_SIZE];     // 0xE0 : RT9119_REG_SERVO_TIME_OPT
/*
PROHIBITED
//  unsigned char pll1[RT9119_REG_PLL1_SIZE];                       // 0xC0 : RT9119_REG_PLL1
//  unsigned char pll2[RT9119_REG_PLL2_SIZE];                       // 0xC1 : RT9119_REG_PLL2
//  unsigned char pll3[RT9119_REG_PLL3_SIZE];                       // 0xC2 : RT9119_REG_PLL3
//  unsigned char pll4[RT9119_REG_PLL4_SIZE];                       // 0xC3 : RT9119_REG_PLL4
//  unsigned char pll5[RT9119_REG_PLL5_SIZE];                       // 0xC4 : RT9119_REG_PLL5(RO)
//                      .                                                                       .
//                      .                                                                       .
//                      .                                                                       .
//  unsigned char scanMode[];                                       // 0xFA : RT9119_REG_SCAN_MODE
*/
} RT9119Reg;

typedef struct {
    RT9119_Bool IsUsed;
    RT9119_AmpId    Id;
    unsigned short  u2ClkDiv;
    unsigned char   u1DevAddr;
    RT9119Reg       *Reg;
} RT9119_HANDLE;

typedef struct {
    int rmsEnergy;
    int gainAttack;
    int gainDecay;
    int t;
    int k;
    int o;
    RT9119_Bool noiseGate;
} RT9119_Drc;

typedef struct {
    RT9119_MultiDrcMode multiDrcMode;       // DRC mode
    RT9119_Bool         freqDrcMode;
    int                     drc1EnergyAttackTime;       // 0.1ms/step
    int                     drc1EnergyReleaseTime;// 10ms/step
    int                     drc1AttackTime;     // 0.1ms/step
    int                     subs_drc1AttackTime;// 10ms/step
    int                     drc1DecayTime;      // 100ms/step
    int                     subs_drc1DecayTime; // 10ms/step
    int                     drc1T;              // 0.1dB/step
    int                     drc1K;              // 0.01/step
    int                     drc1O;              // 0.1dB/step
    RT9119_Bool         drc1NoiseGate;      // TRUE for ON, FALSE for OFF
    RT9119_DrcPeakMode      drc1PeakMode;
    RT9119IirCoeffSet           drc1Bq1;
    RT9119IirCoeffSet           drc1Bq2;
    //int                   drc2EnergyTime;     // 0.1ms/step
    //int                   subs_drc2EnergyTime;// 10ms/step
    int                     drc2EnergyAttackTime;       // 0.1ms/step
    int                     drc2EnergyReleaseTime;// 10ms/step
    int                     drc2AttackTime;     // 0.1ms/step
    int                     subs_drc2AttackTime;// 10ms/step
    int                     drc2DecayTime;      // 100ms/step
    int                     subs_drc2DecayTime; // 10ms/step
    int                     drc2T;              // 0.1dB/step
    int                     drc2K;              // 0.01/step
    int                     drc2O;              // 0.1dB/step
    RT9119_Bool         drc2NoiseGate;      // TRUE for ON, FALSE for OFF
    RT9119_DrcPeakMode      drc2PeakMode;
    RT9119IirCoeffSet           drc2Bq1;
    RT9119IirCoeffSet           drc2Bq2;
    //int                   drc3EnergyTime;     // 0.1ms/step
    //int                   subs_drc3EnergyTime;// 10ms/step
    int                     drc3EnergyAttackTime;       // 0.1ms/step
    int                     drc3EnergyReleaseTime;// 10ms/step
    int                     drc3AttackTime;     // 0.1ms/step
    int                     subs_drc3AttackTime;// 10ms/step
    int                     drc3DecayTime;      // 100ms/step
    int                     subs_drc3DecayTime; // 10ms/step
    int                     drc3T;              // 0.1dB/step
    int                     drc3K;              // 0.01/step
    int                     drc3O;              // 0.1dB/step
    RT9119_Bool         drc3NoiseGate;      // TRUE for ON, FALSE for OFF
    RT9119_DrcPeakMode      drc3PeakMode;
    RT9119IirCoeffSet           drc3Bq1;
    RT9119_Bool         drc4Enable;         // TRUE for ON, FALSE for OFF
    //int                   drc4EnergyTime;     // 0.1ms/step
    //int                   subs_drc4EnergyTime;// 10ms/step
    int                     drc4EnergyAttackTime;       // 0.1ms/step
    int                     drc4EnergyReleaseTime;// 10ms/step
    int                     drc4AttackTime;     // 0.1ms/step
    int                     subs_drc4AttackTime;// 10ms/step
    int                     drc4DecayTime;      // 100ms/step
    int                     subs_drc4DecayTime; // 10ms/step
    int                     drc4T;              // 0.1dB/step
    int                     drc4K;              // 0.01/step
    int                     drc4O;              // 0.1dB/step
    RT9119_Bool         drc4NoiseGate;      // TRUE for ON, FALSE for OFF
    RT9119_DrcPeakMode      drc4PeakMode;
    unsigned char           drc4Delay;          // 1sample/step, 0 = 0sample, 8F = 143sample = 3ms@48KHz
    int                     noiseGateThreshold; // 0.1dB/step
    RT9119_Bool         inverseMidBand;     // Added for drcMixer
    RT9119_Bool         drc_GainEnable;
} RT9119_DrcInfo;


//---------------------------------------------------------------------------
// Global variables
//---------------------------------------------------------------------------

//---------------------------------------------------------------------------
// Public functions
//---------------------------------------------------------------------------
extern RT9119_HANDLE*   RT9119_CreateHandle(RT9119_AmpId ampId, RT9119Reg* handle);
extern void             RT9119_DeleteHandle(RT9119_HANDLE* handle);
extern RT9119_Error     RT9119_Init_General(RT9119_HANDLE* handle);
extern RT9119_Error     RT9119_SetOutputMode(RT9119_HANDLE* handle, RT9119_OutputMode mode);
extern RT9119_Error     RT9119_Init_DSP_Functions(RT9119_HANDLE* handle);
extern RT9119_Error     RT9119_Init_IO_Mixer(RT9119_HANDLE* handle);
extern RT9119_Error     RT9119_SetVolume(RT9119_HANDLE* handle, int i4Volume);
extern RT9119_Error     RT9119_SetClipper(RT9119_HANDLE* handle, unsigned int u4ClipLevel);
extern RT9119_Error     RT9119_SetPreScaler(RT9119_HANDLE* handle, int i4Level);
extern RT9119_Error     RT9119_SetBQ(RT9119_HANDLE* handle, unsigned int bqId, RT9119_Fix32Q29 b0, RT9119_Fix32Q29 b1, RT9119_Fix32Q29 b2, RT9119_Fix32Q29 a1, RT9119_Fix32Q29 a2);
extern RT9119_Error     RT9119_SetDRC(RT9119_HANDLE* handle, RT9119_DrcInfo * drcInfo);
extern RT9119_Error     RT9119_SetFIR(RT9119_HANDLE*, UINT32 *, UINT32);
extern RT9119_Error     RT9119_SetChannelVolume(RT9119_HANDLE*, int, int);
extern RT9119_Error     RT9119_SetSmoothBQ(RT9119_HANDLE*, RT9119IirCoeffSet*, RT9119IirCoeffSet*, int, int);
#endif  // _AUD_AMP_RT9119_H_
