/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author$
 * $Date$
 * $RCSfile: aproc_common_if.h,v $
 * $Revision$
 *
 *---------------------------------------------------------------------------*/

/** @file Aproc_common_if.h
 * Declare audio related structure and function table.
 */

#ifndef APROC_COMMON_IF_H
#define APROC_COMMON_IF_H

// all resgiters in word (4 bytes)
#define APROC_REGMAP_REGSIZE 4 // bytes

#define APROC_REGMAP_IO_GRP_SIZE 32
#define APROC_REGMAP_IO_GRP_IDX_MASK (APROC_REGMAP_IO_GRP_SIZE-1)

// for Aproc Render usage
#define APROC_ASM_ADDR(grp,idx) ((grp) * APROC_REGMAP_IO_GRP_SIZE + (idx))
/* APROC Shared Register (ASM)
    */
typedef enum
{
    APROC_ASM_ID_COMM_0 = 0x0, // APROC_ASM_COMM0_T
    APROC_ASM_ID_COMM_1, // APROC_ASM_COMM1_T
    APROC_ASM_ID_COMM_2, // APROC_ASM_COMM2_T
    APROC_ASM_ID_COMM_3, // APROC_ASM_COMM3_T
    APROC_ASM_ID_AENV_0 = 0x4, // APROC_ASM_AENV0_T
    APROC_ASM_ID_AENV_1, // APROC_ASM_AENV1_T
    APROC_ASM_ID_AENV_2, // APROC_ASM_AENV2_T
#ifdef CC_AUD_RISCIEC_SUPPORT
    ARPOC_ASM_ID_RISCIEC_0, // APROC_ASM_RISCIEC_T
#endif // CC_AUD_RISCIEC_SUPPORT
    APROC_ASM_ID_AVSYNC_0= 0x8, // APROC_ASM_AVSYNC0_T
    APROC_ASM_ID_IOBUF_0, // APROC_ASM_IOBUF0_T
    APROC_ASM_ID_MIXSND_0, // APROC_ASM_MIXSND0_T
    APROC_ASM_ID_CPU_0,    // APROC_ASM_CPU_T
    APROC_ASM_ID_CPU_1,    // APROC_ASM_CPU_T_1
#ifdef CC_AUD_DOLBY_SUPPORT_MS12
    APROC_ASM_ID_MS12_IOBUF, // APROC_ASM_MS12_IOBUF_T
#endif // CC_AUD_DOLBY_SUPPORT_MS12
#ifdef CC_AUD_CPU_DEC
    APROC_ASM_ID_CPU_DEC_1,
#endif
    APROC_ASM_ID_UPLOAD3,
    APROC_ASM_ID_POSTPROC_0 = 0x10, // APROC_ASM_POSTPROC0_T
    APROC_ASM_ID_POSTPROC_1, // APROC_ASM_POSTPROC1_T
    APROC_ASM_ID_POSTPROC_2, // APROC_ASM_POSTPROC2_T
    APROC_ASM_ID_POSTPROC_3, // APROC_ASM_POSTPROC3_T
    APROC_ASM_ID_POSTPROC_4, // APROC_ASM_POSTPROC4_T
    APROC_ASM_ID_POSTPROC_5, // APROC_ASM_POSTPROC5_T
    APROC_ASM_ID_POSTPROC_6, // APROC_ASM_POSTPROC6_T
    APROC_ASM_ID_POSTPROC_7, // APROC_ASM_POSTPROC7_T for SP EQ
    APROC_ASM_ID_POSTPROC_8, // APROC_ASM_POSTPROC8_T
    APROC_ASM_ID_POSTPROC_9, // APROC_ASM_POSTPROC9_T
    APROC_ASM_ID_POSTPROC_A, // APROC_ASM_POSTPROCA_T
    APROC_ASM_ID_POSTPROC_B, // APROC_ASM_POSTPROCB_T
    APROC_ASM_ID_POSTPROC_C, // APROC_ASM_POSTPROCC_T
    APROC_ASM_ID_POSTPROC_D, // APROC_ASM_POSTPROCD_T
    APROC_ASM_ID_POSTPROC_E, // APROC_ASM_POSTPROCE_T
    APROC_ASM_ID_POSTPROC_F, // APROC_ASM_POSTPROCF_T
    APROC_ASM_ID_POSTPROC_10, // APROC_ASM_POSTPROC10_T    0X20
    APROC_ASM_ID_SEL_0, //APROC_ASM_ID_SEL0_T
    APROC_ASM_ID_POSTPROC_12, // APROC_ASM_POSTPROC12_T
    APROC_ASM_ID_3RD_POST_23,
    APROC_ASM_ID_3RD_POST_24,
    APROC_ASM_ID_3RD_POST_25,
    APROC_ASM_ID_3RD_POST_26,
    APROC_ASM_ID_3RD_POST_27,
    APROC_ASM_ID_3RD_POST_28,
    APROC_ASM_ID_3RD_POST_29,
    APROC_ASM_ID_3RD_POST_2A,
    APROC_ASM_ID_3RD_POST_2B,
    APROC_ASM_ID_3RD_POST_2C,
    APROC_ASM_ID_3RD_POST_2D,
    APROC_ASM_ID_3RD_POST_2E,
    APROC_ASM_ID_3RD_POST_2F,
    APROC_ASM_ID_POSTPROC_20 = 0x30, // APROC_ASM_POSTPROC10_T
    APROC_ASM_ID_POSTPROC_21, // APROC_ASM_POSTPROC10_T
    APROC_ASM_ID_HW_MIXSND_0, //APROC_ASM_HW_MIXSND0_T
    APROC_ASM_ID_3RD_POST_33,
    APROC_ASM_ID_3RD_POST_34,
    APROC_ASM_ID_MIXSND_1, // APROC_ASM_MIXSND1_T
    APROC_ASM_ID_EQSPECTRUM, // 0x36
    APROC_ASM_ID_ENC_MP3 = 0x37, // APROC_ASM_ENC_MP3_T
    APROC_ASM_ID_POSTPROC_38 = 0x38, // APROC_ASM_POSTPROC38_T
    APROC_ASM_ID_POSTPROC_39,       // APROC_ASM_POSTPROC39_T
    APROC_ASM_ID_POSTPROC_3A,       // APROC_ASM_POSTPROC3A_T
    APROC_ASM_ID_POSTPROC_3B,       // APROC_ASM_POSTPROC3B_T for HP_EQ
    APROC_ASM_ID_POSTPROC_3C,       // APROC_ASM_POSTPROC3C_T
#ifdef CC_AUD_DOLBY_SUPPORT_MS12
    APROC_ASM_ID_MS12 = 0x3D,       // APROC_ASM_MS12_T
    APROC_ASM_ID_UPLOAD = 0x3E,     // APROC_ASM_UPLOAD_T
#endif // CC_AUD_DOLBY_SUPPORT_MS12
    APROC_ASM_ID_A2M_ISR = 0x3f,
#ifdef CC_AUD_CPU_DEC
    APROC_ASM_ID_CPU_DEC = 0x40,
    APROC_ASM_ID_CPU_IEC = 0x41,
#endif // CC_AUD_CPU_DEC
#ifdef CC_AUD_DOLBY_SUPPORT_DAPv2
    APROC_ASM_ID_UPLOAD2 = 0x42,     // APROC_ASM_UPLOAD2_T
#endif //CC_AUD_DOLBY_SUPPORT_DAPv2
#ifdef CC_AUD_DOLBY_SUPPORT_MS12B
#ifdef CC_AUD_DOLBY_SUPPORT_MS12v2_FADER
    APROC_ASM_ID_FADER = 0x43,  // APROC_ASM_FADER_T
#else
    APROC_ASM_ID_DUAL_MAIN_FADER = 0x43,  // APROC_ASM_DUAL_MAIN_FADER_T
#endif
#endif // CC_AUD_DOLBY_SUPPORT_MS12B
    APORC_ASM_ID_SILENCECTRL = 0x44,
    APORC_ASM_ID_DECINFO = 0x45,  // APROC_ASM_DECINFO_T
    APROC_ASM_DAP_PARAMETER = 0x46,// APROC_ASM_DAP_PARAMETER_T
#ifdef CC_AUD_DOLBY_SUPPORT_MS12v2
    APROC_ASM_ID_MIXED_MD,  // APROC_ASM_MIXED_MD_T
    APROC_ASM_ID_MIXER_CTRL, //APROC_ASM_MIXER_CTRL_T
#endif
    APROC_ASM_ID_POSTPROC_49 = 0x49, // APROC_ASM_POSTPROC49_T, for 32 band geq
    APROC_ASM_ID_POSTPROC_4A = 0x4A, // APROC_ASM_POSTPROC4A_T, for 32 band geq
    APROC_ASM_ID_POSTPROC_4B = 0x4B, // APROC_ASM_POSTPROC4B_T, for 32 band geq
    APROC_ASM_ID_POSTPROC_4C = 0x4C, // APROC_ASM_POSTPROC4C_T, for 32 band geq
    APROC_ASM_ID_POSTPROC_4D = 0x4D, // APROC_ASM_POSTPROC4D_T, for 32 band geq
    APROC_ASM_ID_POSTPROC_4E = 0x4E,

    APROC_ASM_ID_A2M_ISR_FLAG = 0x50,
#ifdef CC_EARC_SW_BYPASS
    APROC_ASM_ID_M2A_ISR2_FLAG = 0x5C,
    APROC_ASM_ID_A2M_ISR2_FLAG = 0x5D,
#endif // CC_EARC_SW_BYPASS
#ifdef CC_TEST_PERFORMANCE
    APROC_ASM_ID_TEST_PERFORMANCE = 0x5E, // APROC_ASM_TEST_PERFORMANCE_T, added for performance estimation 0,1,2
#endif // CC_TEST_PERFORMANCE
#ifdef CC_AUD_CPU_DEC
    APROC_ASM_ID_DEBUG = 0x5F, // added for debug only
#endif // CC_AUD_CPU_DEC
    APROC_ASM_ID_NUM = 0x60 /*_extend_to 0x60 */
} APROC_ASM_ID_T;

#define APROC_REGMAP_SIZE    (APROC_ASM_ID_NUM * APROC_REGMAP_IO_GRP_SIZE) // maximun regmap size = 1024 (regmap.s)



typedef enum {
    APROC_REG_VERSION = 0x0,

    APROC_REG_CPUSIDE_BASE, // APROC base address at CPU side
    APROC_REG_IOBUF_BASE,
    APROC_REG_DELAYBUF_BASE,
    APROC_REG_ADSPCMMBUF_BASE,
    APROC_REG_ADSPCMMCMPT_BASE,
    APROC_REG_DELAYBUF_SIZE,
    APROC_REG_AMX2_MODE,
    APROC_REG_POST_BYPASS_FLAG,
    APROC_REG_POST_OUTBUF_SIZE,
    APROC_REG_IMAGE_ROM_BASE,
    APROC_REG_IMAGE_ROM_LIMIT,
    APROC_REG_IMAGE_RAM_BASE,
    APROC_REG_IMAGE_RAM_LIMIT,
    APROC_REG_IMAGE_HEAP_BASE,
    APROC_REG_IMAGE_HEAP_LIMIT,
    APROC_REG_SPK_MIPS_TEST_LOG_ONFF = 0x11,
    APROC_REG_CPUDEC_DBG,
    APROC_REG_AMX_DBG,
    APROC_REG_SRC_DBG,
    APROC_REG_UPLOAD_DBG,
    APROC_REG_POST_DBG,
    APROC_REG_MCPU_SUSPEND_INDICATOR,

    APROC_REG_DSP_MVS_VERSION = 0x18,
    APROC_REG_DSP_MVB_VERSION,
    APROC_REG_DTS_OR_MTKPOST,  //1: DSP, 0: MTK_POST
    APROC_REG_BYPASS_PROC,
#ifdef CC_AUD_SUPPORT_AUTO_MUTE
    // Aout Auto Mute Test
    APROC_REG_AOUT_AUTO_MUTE_CTRL, // 0x1c, [0] 0:disable 1:enable, [1] 1:force aout1 underrun
    // Aout Auto Mute Threshold
    APROC_REG_AOUT_AUTO_MUTE_THRESHOLD, // 0x1d
#endif // CC_AUD_SUPPORT_AUTO_MUTE
    APROC_REG_ENABLE_SWSRC, // [0]:192k to 96k
    APROC_REG_HDMI_BUFFER_DATA
} APROC_ASM_COMM0_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_COMM0_T
 * Group: 0x01 ==> APROC_ASM_ID_COMM_1
 * Range: 0x020 ~ 0x03F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // Profiling
    APROC_REG_PROFILE_MOS_THREADTBL_BASE = 0x0,
    APROC_REG_PROFILE_MOS_THREADLIST_BASE,
    APROC_REG_PROFILE_MOS_DEVINFO_BASE,
    APROC_REG_PROFILE_IOBUF_BASE,

    // Debug
    APROC_REG_DBG_ROUTINE_BASE = 0x8,
    APROC_REG_DBG_DBGINFO_BASE,//[Debug SOP]
    APROC_REG_DBG_MULTI_CH,
    APROC_REG_DBG_AVSYNC_INFO,
    APROC_REG_DBG_GLOBLEDEF_INFO,

    // Assert system
    APROC_REG_ASSERTSYS_ADDR = 0x10,
    APROC_REG_ASSERTSYS_DATA0,
    APROC_REG_ASSERTSYS_DATA1,
    APROC_REG_ASSERTSYS_DATA2,

    APROC_REG_AMX_SKIP0 = 0x14,
    APROC_REG_AMX_SKIP1,
    APROC_REG_AMX_SKIP2,

    // analysis
    APROC_REG_LEVEL_DET_FLAG = 0x18,
    APROC_REG_LEVEL_DET_POSMAX_0,
    APROC_REG_LEVEL_DET_RESULT_0,
    APROC_REG_LEVEL_DET_POSMAX_1,
    APROC_REG_LEVEL_DET_RESULT_1,
#ifdef CC_AUD_SAKURA_RENDER
    // for emergency reset.
    APROC_REG_HEART_BEAT
#endif // CC_AUD_SAKURA_RENDER
} APROC_ASM_COMM1_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_COMM2_T
 * Group: 0x02 ==> APROC_ASM_ID_COMM_2
 * Range: 0x040 ~ 0x05F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_BYPASS_DSP = 0x0,
    APROC_REG_AMIXER0_DOWNMIX_ENABLE,
    APROC_REG_AMIXER2_ADMIX_FLAG, // bit[0]: AD enable flag, bit[1]: Dolby xmx enable flag
    APROC_REG_DSP_TESTTONE_FLAG,
    APROC_REG_AMIXER2_ADMIX_FADE,
    APROC_REG_AMIXER2_ADMIX_PAN,
#ifdef CC_AUD_UNICORN_CUST
    APROC_REG_ENABLE_SPOST, //b'01 is enable SAPost, b'10 is enable AQ trim
#endif
    APROC_REG_IECRAW_SET = 0x7, //bit[0] =1 is for MT5885/MT5891 IEC raw setting, bit[0] = 0 is for other IC.
#ifndef CC_AUD_DOLBY_SUPPORT_MS12
    // cache meter
    APROC_REG_CACHEMETER_FLAG = 0x8,
    APROC_REG_CACHEMETER_IMISS,
    APROC_REG_CACHEMETER_IPENALTY,
    APROC_REG_CACHEMETER_DMISS,
    APROC_REG_CACHEMETER_DPENALTY,
#endif // CC_AUD_DOLBY_SUPPORT_MS12
    APROC_REG_DBG_MUTE_ALL_SWOUT,
    APROC_REG_DBG_RECOVER_A2DSIG_TH,
    APROC_REG_DBG_RECOVER_A2DSIG_COUNT,

    APROC_REG_AMIXER0_HDMI_PCM_MODE = 0x10,
    APROC_REG_AMIXER1_HDMI_PCM_MODE,
#ifdef CC_AUD_DOLBY_SUPPORT_MS12
    APROC_REG_AMIXER2_ADMIX_GAIN_BYTE_CENTER = 0x18,
    APROC_REG_AMIXER2_ADMIX_GAIN_BYTE_FRONT,
    APROC_REG_AMIXER2_ADMIX_GAIN_BYTE_SURROUND,
#endif // CC_AUD_DOLBY_SUPPORT_MS12
#ifdef CC_AUD_DOLBY_SUPPORT_MS12B
    //for dual main enable/disable
    APROC_REG_DUAL_MAIN_ENABLE,
#endif
} APROC_ASM_COMM2_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_COMM2_T
 * Group: 0x03 ==> APROC_ASM_ID_COMM_3
 * Range: 0x060 ~ 0x07F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_DBG_CMD = 0x0,
    APROC_REG_DBG_ADDR,
    APROC_REG_DBG_DATA,
    APROC_REG_DBG_TIMER0,
    APROC_REG_DBG_AMX0_READ_TIME,
    APROC_REG_DBG_AMX0_READ_TIME_MAX,
    APROC_REG_DBG_AMX1_READ_TIME,
    APROC_REG_DBG_AMX1_READ_TIME_MAX,
    APROC_REG_DBG_AMX2_READ_TIME,
    APROC_REG_DBG_AMX2_READ_TIME_MAX,

    APROC_REG_DBG_RENDER_IN0 = 0x10,
    APROC_REG_DBG_RENDER_IN1,
    APROC_REG_DBG_RENDER_IN2,
    APROC_REG_DBG_RENDER_OUT,
    APROC_REG_DBG_POST_MHZ,
    APROC_REG_DBG_POST_MHZ_PERIOD,
    APROC_REG_DBG_INPUT_DATA = 0x18,
#if (defined(CC_AUD_SAKURA_RENDER)||defined(CC_AUD_UNICORN_CUST))
    APROC_REG_DBG_CAP,
    APROC_REG_DBG_INP,
    APROC_REG_SPD_AVG,
    APROC_REG_SPD_MIN,
    APROC_REG_SPD_MAX,
    APROC_REG_SPD_ID,
    APROC_REG_DBG_DMX_BYPASS,
    APROC_REG_SPD_COUNT,
#endif /* CC_AUD_SAKURA_RENDER */
} APROC_ASM_COMM3_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_AENV0_T
 * Group: 0x04 ==> APROC_ASM_ID_AENV_0
 * Range: 0x080 ~ 0x09F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_AENV_SRC0_FREQMODE = 0x0,
    APROC_REG_AENV_SRC2_FREQMODE,
    APROC_REG_AENV_SRC0_MUTECOUNT,
    APROC_REG_AENV_SRC1_MUTECOUNT,
    APROC_REG_AENV_SRC2_MUTECOUNT,
    APROC_REG_AENV_SRC0_ADJ_SWITCH,
    APROC_REG_AENV_SRC0_ADJ_OFFSET,
    APROC_REG_AENV_SRC1_ADJ_SWITCH,
    APROC_REG_AENV_SRC1_ADJ_OFFSET,
    APROC_REG_AENV_SRC2_ADJ_SWITCH,
    APROC_REG_AENV_SRC2_ADJ_OFFSET, //10
    APROC_REG_AENV_SRC1_FREQMODE,
    APROC_REG_AENV_SRC_HALF_PLL_MODE,
    APROC_REG_AENV_SRC_RECOVER_DBG = 0xf,

    APROC_REG_SPEED_BANKSAMP_AMIXER0 = 0x10,
    APROC_REG_SPEED_BANKSAMP_AMIXER1,
    APROC_REG_SPEED_BANKSAMP_AMIXER2,
    APROC_REG_SPEED_SHIFT_LEN_AMIXER0,
    APROC_REG_SPEED_SHIFT_LEN_AMIXER1,
    APROC_REG_SPEED_SHIFT_LEN_AMIXER2,
    APROC_REG_SPEED_AMIXER0,
    APROC_REG_SPEED_AMIXER1,
    APROC_REG_SPEED_AMIXER2,
    APROC_REG_SPEED_OVERLAP_DBG0,
    APROC_REG_SPEED_OVERLAP_DBG1,
    APROC_REG_SPEED_OVERLAP_DBG2,
    APROC_REG_AENV_SRC0_TWIST_BANK,
    APROC_REG_AENV_SRC1_TWIST_BANK,
    APROC_REG_AENV_SRC2_TWIST_BANK,
} APROC_ASM_AENV0_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_AENV1_T
 * Group: 0x05 ==> APROC_ASM_ID_AENV_1
 * Range: 0x0A0 ~ 0x0BF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_AENV_IEC_FLAG = 0x0,
    APROC_REG_AENV_IEC_CHCFG0,
    APROC_REG_AENV_IEC_CHCFG1,
    APROC_REG_AENV_IEC_CHCFG2,
    APROC_REG_AENV_IEC_BURSTINFO,
    APROC_REG_AENV_IEC_NSNUM,
    APROC_REG_AENV_IEC_RAWMUTE,
    APROC_REG_AENV_IEC_RAWDELAY,
    APROC_REG_AENV_IEC_RAWUNDERRUN,
    APROC_REG_AENV_IEC_AMX0_VALID,
    APROC_REG_AENV_IEC_AMX1_VALID,
    APROC_REG_AENV_IEC_MODE,
    APROC_REG_AENV_IEC_FRAME,
    APROC_REG_AENV_IEC_OUT,
    APROC_REG_AENV_IEC_OVF,
    APROC_REG_DBG_IEC_TIME,
    APROC_REG_DBG_IEC_TIME_MAX,
} APROC_ASM_AENV1_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_AENV2_T
 * Group: 0x06 ==> APROC_ASM_ID_AENV_2
 * Range: 0x0C0 ~ 0x0DF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_AENV_AOUT_APUT = 0x0,
    APROC_REG_AENV_AOUT_AOUT,
    APROC_REG_AENV_AOUT_UNDERRUN,
    APROC_REG_AMX0_SKIP_DONE,
    APROC_REG_AMX1_SKIP_DONE,
    APROC_REG_AMX2_SKIP_DONE,
    APROC_REG_DBG_AOUT_TIME = 0x7,
    APROC_REG_AUD_MEASURE_LATENCY,
    APROC_REG_DBG_AOUT_TIME_MAX,
    APROC_REG_NRD50_MIXSND0_SUM,
    APROC_REG_NRD50_MIXSND1_SUM,
    APROC_REG_AOUT3_PNT_DBG,
    APROC_REG_AOUT3_PNT_DBG2,
    APROC_REG_AOUT3_PNT_DBG3,

    APROC_REG_AENV_AOUT2_APUT = 0x10,
    APROC_REG_AENV_AOUT2_AOUT,
    APROC_REG_AENV_AOUT2_UNDERRUN,

#if defined(CC_MT5895)
    APROC_REG_AENV_AOUT3_APUT = 0x13,
    APROC_REG_AENV_AOUT3_AOUT,
    APROC_REG_AENV_AOUT3_UNDERRUN,
#endif
    APROC_REG_AENV_AOUT_AMX0_BANK = 0x16,
    APROC_REG_AENV_AOUT_AMX1_BANK,
    APROC_REG_AENV_AOUT_AMX2_BANK,
    APROC_REG_AENV_AOUT_AMX3_BANK,

    APROC_REG_APTS64L_SRC0 = 0x1A,
    APROC_REG_APTS64L_SRC1,
    APROC_REG_APTS64L_SRC2,
    APROC_REG_APTS64H_SRC0,
    APROC_REG_APTS64H_SRC1,
    APROC_REG_APTS64H_SRC2
} APROC_ASM_AENV2_T;

#ifdef CC_AUD_RISCIEC_SUPPORT
/*-----------------------------------------------------------
 * Type: APROC_ASM_RISCIEC_T
 * Group: 0x07 ==> APROC_ASM_ID_RISCIEC_0
 * Range: 0x0E0 ~ 0x0FF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_AENV_IEC_BUF_START,
    APROC_REG_AENV_IEC_BUF_END,
    APROC_REG_AENV_IEC_BUF_SIZE,
    APROC_REG_AENV_IEC_BUF_ADDR,
    APROC_REG_AENV_IEC_WP,
    APROC_REG_AENV_IEC_RP,
} APROC_ASM_RISCIEC_T;
#endif

#ifdef CC_AUD_CPU_DEC
/*-----------------------------------------------------------
 * Type: APROC_ASM_CPU_DEC_1_T
 * Group: 0x0E ==> APROC_ASM_ID_CPU_DEC_1
 * Range: 0x1C0 ~ 0x1DF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_CPUDEC0_UPDATE_WP,
    APROC_REG_CPUDEC1_UPDATE_WP,
    APROC_REG_CPUDEC2_UPDATE_WP,
} APROC_ASM_CPU_DEC_1_T;
#endif
/*-----------------------------------------------------------
 * Type: APROC_ASM_AVSYNC0_T
 * Group: 0x08 ==> APROC_ASM_ID_AVSYNC_0
 * Range: 0x100 ~ 0x11F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_AVSYNC_CMD_SRC0 = 0x0,
    APROC_REG_AVSYNC_CMD_SRC1,
    APROC_REG_AVSYNC_CMD_SRC2,
    APROC_REG_STC_SPEC_SRC0,   // 3   //STC Spec -- 0: 90K  1: 45K
    APROC_REG_STC_SPEC_SRC1,
    APROC_REG_STC_SPEC_SRC2,
    APROC_REG_APTS_SRC0,       // 6   //PTS
    APROC_REG_APTS_SRC1,
    APROC_REG_APTS_SRC2,
    APROC_REG_APTS_APUT_BANK0,  // 9   //aput_bank with the APTS from DSP
    APROC_REG_APTS_APUT_BANK1,
    APROC_REG_APTS_APUT_BANK2,
    APROC_REG_APTS_FRM_SZ_SRC0, //12  //APTS_FRM_SIZE,  Frame Size in samples
    APROC_REG_APTS_FRM_SZ_SRC1,
    APROC_REG_APTS_FRM_SZ_SRC2,
    APROC_REG_SKIP_FRMNUM_SRC0, //15  //Skip Frame Number
    APROC_REG_SKIP_FRMNUM_SRC1,
    APROC_REG_SKIP_FRMNUM_SRC2,
        //Reserved for debug
        //bit0 : 0-SRC0 is systerm master  1-audio master
        //bit1 : 0-SRC1 is systerm master  1-audio master
        //bit2 : 0-SRC2 is systerm master  1-audio master
    APROC_REG_AVSYNC_RESERVED,      // 18, 0x12
    APROC_REG_PTS_QRY_RESULT_ADDR,  // 19, 0x13
    APROC_REG_PTS_TABLE_ADDR,       // 20, 0x14
    APROC_REG_PTS_TABLE_SIZE,       // 21, 0x15
    APROC_REG_AFIFO0_ADDR,          // 22, 0x14
    APROC_REG_AFIFO1_ADDR,          // 23, 0x14

    APROC_REG_AVSYNC_NOTIFY_APTS_SRC0 = 0x18, // 24, 0x18
    APROC_REG_AVSYNC_NOTIFY_APTS_SRC1,
    APROC_REG_AVSYNC_NOTIFY_APTS_SRC2,
    APROC_REG_AVSYNC_NOTIFY_HOLD_OK_SRC0,
    APROC_REG_AVSYNC_NOTIFY_HOLD_OK_SRC1,
    APROC_REG_AVSYNC_NOTIFY_HOLD_OK_SRC2,      // 29, 0x1D
    APROC_REG_AFIFO2_ADDR,               // 30, 0x1E
    APROC_REG_DO_SKIP_ONLY_IN_AMX    // 31, 0x1F
} APROC_ASM_AVSYNC0_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_IOBUF0_T
 * Group: 0x09 ==> APROC_ASM_ID_IOBUF_0
 * Range: 0x120 ~ 0x13F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_IOBUF_DEC0_START = 0x0,
    APROC_REG_IOBUF_DEC0_END,
    APROC_REG_IOBUF_DEC0_SIZE, // bytes
    APROC_REG_IOBUF_DEC0_CH,
    APROC_REG_IOBUF_DEC0_SI_BASE,

    APROC_REG_IOBUF_DEC1_START = 0x8,
    APROC_REG_IOBUF_DEC1_END,
    APROC_REG_IOBUF_DEC1_SIZE, // bytes
    APROC_REG_IOBUF_DEC1_CH,
    APROC_REG_IOBUF_DEC1_SI_BASE,

    APROC_REG_IOBUF_DEC2_START = 0x10,
    APROC_REG_IOBUF_DEC2_END,
    APROC_REG_IOBUF_DEC2_SIZE, // bytes
    APROC_REG_IOBUF_DEC2_CH,
    APROC_REG_IOBUF_DEC2_SI_BASE,

    APROC_REG_IOBUF_SWDEC0_START,
    APROC_REG_IOBUF_SWDEC0_END,
    APROC_REG_IOBUF_SWDEC0_SIZE,
    APROC_REG_IOBUF_SWDEC0_CH,
    APROC_REG_IOBUF_SWDEC0_SI_BASE

} APROC_ASM_IOBUF0_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_MIXSND0_T
 * Group: 0x0A ==> APROC_ASM_ID_MIXSND_0
 * Range: 0x140 ~ 0x15F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_IOBUF_MIXSND_INPUT0_START = 0x0,   //parson mixsnd
    APROC_REG_IOBUF_MIXSND_INPUT0_END,
    APROC_REG_IOBUF_MIXSND_INPUT0_SIZE,            // in bytes
    APROC_REG_IOBUF_MIXSND_INPUT0_CH,
    APROC_REG_IOBUF_MIXSND_INPUT0_ENABLE,
    APROC_REG_IOBUF_MIXSND_INPUT0_STATUS,
    APROC_REG_IOBUF_MIXSND_INPUT0_IN_UNDERRUN,
    APROC_REG_IOBUF_MIXSND_INPUT0_IN_WRITECNT,
    APROC_REG_IOBUF_MIXSND_INPUT1_START = 0x8,   //parson mixsnd
    APROC_REG_IOBUF_MIXSND_INPUT1_END,
    APROC_REG_IOBUF_MIXSND_INPUT1_SIZE,            // in bytes
    APROC_REG_IOBUF_MIXSND_INPUT1_CH,
    APROC_REG_IOBUF_MIXSND_INPUT1_ENABLE,
    APROC_REG_IOBUF_MIXSND_INPUT1_STATUS,
    APROC_REG_IOBUF_MIXSND_INPUT1_IN_UNDERRUN,
    APROC_REG_IOBUF_MIXSND_INPUT1_IN_WRITECNT,
    #ifdef CC_AUD_UNICORN_MS11_SUPPORT
    APROC_REG_MIXSND01_IN_TRIM_DEFAULT = 0x10,
    APROC_REG_MIXSND0_IN_TRIM0,
    #else
    APROC_REG_MIXSND0_IN_TRIM0 = 0x10,
    #endif
    APROC_REG_MIXSND0_IN_TRIM1,
    APROC_REG_MIXSND1_IN_TRIM0,
    APROC_REG_MIXSND1_IN_TRIM1,
    APROC_REG_INPUT_MIX0_TRIM,
    APROC_REG_INPUT_MIX1_TRIM,
    APROC_REG_INPUT_MIX0_TYPE,
    APROC_REG_INPUT_MIX1_TYPE,
#ifdef CC_AUD_UNICORN_CUST
    // Trim Scale
    APROC_REG_MIXSND1_IN_TRIM0_SCL,
#endif /* CC_AUD_UNICORN_CUST */
    APROC_REG_MIXSND0_NOT_MIX,
    APROC_REG_INPUT0_MIX_FLAG = 0x1A,
    APROC_REG_INPUT1_MIX_FLAG,
    APROC_REG_INPUT2_MIX_FLAG,
#ifdef CC_AUD_DOLBY_SUPPORT_MS12v2
    APROC_REG_MIXSND_INPUT0_ACMOD_LFE,
    APROC_REG_MIXSND_INPUT1_ACMOD_LFE
#endif
} APROC_ASM_MIXSND0_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_HW_MIXSND0_T
 * Group: 0x30 ==> APROC_ASM_ID_HW_MIXSND_0
 * Range: 0x640 ~ 0x65F
 * Description:
 *-----------------------------------------------------------*/

typedef enum {
    APROC_REG_IOBUF_MIXSND_INPUT2_START = 0x0,   //
    APROC_REG_IOBUF_MIXSND_INPUT2_END,
    APROC_REG_IOBUF_MIXSND_INPUT2_SIZE,            //
    APROC_REG_IOBUF_MIXSND_INPUT2_CH,
    APROC_REG_IOBUF_MIXSND_INPUT2_ENABLE,
    APROC_REG_IOBUF_MIXSND_INPUT2_STATUS,
    APROC_REG_IOBUF_MIXSND_INPUT2_IN_UNDERRUN,
    APROC_REG_IOBUF_MIXSND_INPUT2_IN_WRITECNT,
    APROC_REG_IOBUF_MIXSND_INPUT3_START = 0x8,   //
    APROC_REG_IOBUF_MIXSND_INPUT3_END,
    APROC_REG_IOBUF_MIXSND_INPUT3_SIZE,            //
    APROC_REG_IOBUF_MIXSND_INPUT3_CH,
    APROC_REG_IOBUF_MIXSND_INPUT3_ENABLE,
    APROC_REG_IOBUF_MIXSND_INPUT3_STATUS,
    APROC_REG_IOBUF_MIXSND_INPUT3_IN_UNDERRUN,
    APROC_REG_IOBUF_MIXSND_INPUT3_IN_WRITECNT,
    APROC_REG_MIXSND2_IN_TRIM0 = 0x10,
    APROC_REG_MIXSND2_IN_TRIM1,
    APROC_REG_MIXSND3_IN_TRIM0,
    APROC_REG_MIXSND3_IN_TRIM1,
    APROC_REG_INPUT_MIX2_TRIM,
    APROC_REG_INPUT_MIX3_TRIM,
    APROC_REG_INPUT_MIX2_TYPE,
    APROC_REG_INPUT_MIX3_TYPE,
#ifdef CC_AUD_DOLBY_SUPPORT_MS12v2
    APROC_REG_MIXSND_INPUT2_ACMOD_LFE
#endif
} APROC_ASM_MIXSND1_T;

typedef enum {
    APROC_REG_IOBUF_HW_MIXSND_INPUT0_START = 0x0,   //HW mixsnd
    APROC_REG_IOBUF_HW_MIXSND_INPUT0_END,
    APROC_REG_IOBUF_HW_MIXSND_INPUT0_SIZE,            // in bytes
    APROC_REG_IOBUF_HW_MIXSND_INPUT0_CH,
    APROC_REG_IOBUF_HW_MIXSND_INPUT0_ENABLE,
    APROC_REG_IOBUF_HW_MIXSND_INPUT0_STATUS,
    APROC_REG_IOBUF_HW_MIXSND_INPUT0_IN_UNDERRUN,
  APROC_REG_IOBUF_HW_MIXSND_INPUT0_IN_WRITECNT,
    APROC_REG_IOBUF_HW_MIXSND_INPUT1_START = 0x8,   //HW mixsnd
    APROC_REG_IOBUF_HW_MIXSND_INPUT1_END,
    APROC_REG_IOBUF_HW_MIXSND_INPUT1_SIZE,            // in bytes
    APROC_REG_IOBUF_HW_MIXSND_INPUT1_CH,
    APROC_REG_IOBUF_HW_MIXSND_INPUT1_ENABLE,
    APROC_REG_IOBUF_HW_MIXSND_INPUT1_STATUS,
    APROC_REG_IOBUF_HW_MIXSND_INPUT1_IN_UNDERRUN,
  APROC_REG_IOBUF_HW_MIXSND_INPUT1_IN_WRITECNT,
    APROC_REG_HW_MIXSND0_IN_TRIM = 0x10,
    APROC_REG_HW_MIXSND1_IN_TRIM,
    APROC_REG_HW_MIXSND0_CH_CFG,
    APROC_REG_HW_MIXSND1_CH_CFG,
    APROC_REG_RISC_MIXSND0_WP = 0x14,
    APROC_REG_RISC_MIXSND1_WP,
    APROC_REG_RISC_MIXSND2_WP,
    APROC_REG_RISC_MIXSND3_WP,
} APROC_ASM_HW_MIXSND0_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_CPU_T
 * Group: 0x0B ==> APROC_ASM_ID_CPU_0
 * Range: 0x160 ~ 0x17F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_IOBUF_UPLOAD0_START = 0x0,   //parson upload
    APROC_REG_IOBUF_UPLOAD0_END,
    APROC_REG_IOBUF_UPLOAD0_SIZE,            // in bytes
    APROC_REG_IOBUF_UPLOAD0_CH,
    APROC_REG_IOBUF_UPLOAD0_ENABLE,
    APROC_REG_IOBUF_UPLOAD0_INPUT,

    APROC_REG_IOBUF_UPLOAD1_START,   //parson upload
    APROC_REG_IOBUF_UPLOAD1_END,
    APROC_REG_IOBUF_UPLOAD1_SIZE,            // in bytes
    APROC_REG_IOBUF_UPLOAD1_CH,
    APROC_REG_IOBUF_UPLOAD1_ENABLE,
    APROC_REG_IOBUF_UPLOAD1_INPUT,

    APROC_REG_IOBUF_UPLOAD2_START,
    APROC_REG_IOBUF_UPLOAD2_END,
    APROC_REG_IOBUF_UPLOAD2_SIZE,            // in bytes
    APROC_REG_IOBUF_UPLOAD2_CH,
    APROC_REG_IOBUF_UPLOAD2_ENABLE,
    APROC_REG_IOBUF_UPLOAD2_INPUT,

    APROC_REG_IOBUF_UPLOAD3_START,
    APROC_REG_IOBUF_UPLOAD3_END,
    APROC_REG_IOBUF_UPLOAD3_SIZE,            // in bytes
    APROC_REG_IOBUF_UPLOAD3_CH,
    APROC_REG_IOBUF_UPLOAD3_ENABLE,
    APROC_REG_IOBUF_UPLOAD3_INPUT,

    APROC_REG_IOBUF_RISCPOST_START,        //parson riscpost
    APROC_REG_IOBUF_RISCPOST_END,
    APROC_REG_IOBUF_RISCPOST_SIZE,            // in bytes
    APROC_REG_IOBUF_RISCPOST_CH,
    APROC_REG_IOBUF_RISCPOST_ENABLE,
    APROC_REG_IOBUF_RISCPOST_INPUT,
    APROC_REG_IOBUF_RISCPOST_SUSPEND, //0x17e
} APROC_ASM_CPU_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_CPU_T
 * Group: 0x0C ==> APROC_ASM_ID_CPU_1
 * Range: 0x180 ~ 0x19F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_IOBUF_UPLOAD0_UPDATE_COUNT = 0x0,
    APROC_REG_IOBUF_UPLOAD1_UPDATE_COUNT,
    APROC_REG_IOBUF_UPLOAD2_UPDATE_COUNT,
    APROC_REG_IOBUF_UPLOAD3_UPDATE_COUNT,

    APROC_REG_IOBUF_UPLOAD0_UPDATE_COUNT_CUR,
    APROC_REG_IOBUF_UPLOAD1_UPDATE_COUNT_CUR,
    APROC_REG_IOBUF_UPLOAD2_UPDATE_COUNT_CUR,
    APROC_REG_IOBUF_UPLOAD3_UPDATE_COUNT_CUR,

    APROC_REG_IOBUF_UPLOAD0_AOUT_START = 0x8,
    APROC_REG_IOBUF_UPLOAD0_AOUT_END,
    APROC_REG_IOBUF_UPLOAD0_AOUT_SIZE,
    APROC_REG_IOBUF_UPLOAD0_AOUT_CH,

    APROC_REG_IOBUF_UPLOAD1_AOUT_START = 0xc,
    APROC_REG_IOBUF_UPLOAD1_AOUT_END,
    APROC_REG_IOBUF_UPLOAD1_AOUT_SIZE,
    APROC_REG_IOBUF_UPLOAD1_AOUT_CH,

    APROC_REG_IOBUF_UPLOAD2_AOUT_START = 0x10,
    APROC_REG_IOBUF_UPLOAD2_AOUT_END,
    APROC_REG_IOBUF_UPLOAD2_AOUT_SIZE,
    APROC_REG_IOBUF_UPLOAD2_AOUT_CH,

    APROC_REG_IOBUF_UPLOAD0_AOUT_RP = 0x14,
    APROC_REG_IOBUF_UPLOAD1_AOUT_RP,
    APROC_REG_IOBUF_UPLOAD2_AOUT_RP,
    APROC_REG_IOBUF_UPLOAD3_AOUT_RP,

    APROC_REG_IOBUF_AOUT_START,
    APROC_REG_IOBUF_AOUT_END,
    APROC_REG_IOBUF_AOUT_SIZE,
    APROC_REG_IOBUF_AOUT_CH,
    APROC_REG_UPLOAD_BUF_FLAG,
} APROC_ASM_CPU_T_1;

#ifdef CC_AUD_CPU_DEC
/*-----------------------------------------------------------
 * Type: APROC_ASM_ID_CPU_DEC_T
 * Group: 0x3D ==> APROC_ASM_ID_CPU_DEC
 * Range: 0x7A0 ~ 0x7BF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_CPU_DEC0_BUF_START = 0x0,
    APROC_REG_CPU_DEC0_BUF_END,
    APROC_REG_CPU_DEC0_BUF_SIZE, // bytes
    APROC_REG_CPU_DEC0_BUF_CH,

    APROC_REG_CPU_IEC0_BUF_START, // 4
    APROC_REG_CPU_IEC0_BUF_END,
    APROC_REG_CPU_IEC0_BUF_SIZE, // bytes

    APROC_REG_CPU_DEC0_SI_START, // 7
    APROC_REG_CPU_DEC0_SI_END,
    APROC_REG_CPU_DEC0_SI_SIZE, // bytes

    APROC_REG_CPU_DEC1_BUF_START,// a
    APROC_REG_CPU_DEC1_BUF_END,
    APROC_REG_CPU_DEC1_BUF_SIZE, // bytes
    APROC_REG_CPU_DEC1_BUF_CH,

    APROC_REG_CPU_IEC1_BUF_START, // e
    APROC_REG_CPU_IEC1_BUF_END,
    APROC_REG_CPU_IEC1_BUF_SIZE, // bytes

    APROC_REG_CPU_DEC1_SI_START, // 11
    APROC_REG_CPU_DEC1_SI_END,
    APROC_REG_CPU_DEC1_SI_SIZE, // bytes

    APROC_REG_CPU_DEC2_BUF_START,// 14
    APROC_REG_CPU_DEC2_BUF_END,
    APROC_REG_CPU_DEC2_BUF_SIZE, // bytes
    APROC_REG_CPU_DEC2_BUF_CH,

    APROC_REG_CPU_IEC2_BUF_START, // 18
    APROC_REG_CPU_IEC2_BUF_END,
    APROC_REG_CPU_IEC2_BUF_SIZE, // bytes

    APROC_REG_CPU_DEC2_SI_START, // 1b
    APROC_REG_CPU_DEC2_SI_END,
    APROC_REG_CPU_DEC2_SI_SIZE, // bytes

	APROC_REG_CPU_DEC_FLAG, // 1e, 0 : DSP  1: CPU
	APROC_REG_CPU_DEC_DBG_FLAG, //1: open

} APROC_ASM_ID_CPU_DEC_T;
#endif // CC_AUD_CPU_DEC
/*-----------------------------------------------------------
 * Type: APROC_ASM_A2M_ISR_T
 * Group: 0x3F ==> APROC_ASM_ID_A2M_ISR
 * Range: 0x7E0 ~ 0x7FF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_A2M_ISR_MIXSND0_FLAG = 0x0,
    APROC_REG_A2M_ISR_MIXSND1_FLAG,
    APROC_REG_A2M_ISR_MIXSND2_FLAG,
    APROC_REG_A2M_ISR_MIXSND3_FLAG,
    APROC_REG_A2M_ISR_UPLOAD0_FLAG,
    APROC_REG_A2M_ISR_UPLOAD1_FLAG,
    APROC_REG_A2M_ISR_UPLOAD2_FLAG,
#ifdef CC_AUD_DOLBY_SUPPORT_MS12_RISCENC
    APROC_REG_A2M_ISR_RISCENC_UP_FLAG, // Upload data to Risc
    APROC_REG_A2M_ISR_RISCENC_DOWN_FLAG, // Download data to Risc
#endif // CC_AUD_DOLBY_SUPPORT_MS12_RISCENC
#ifdef CC_AUD_CPU_DEC
	APROC_REG_A2M_ISR_CPUDEC0_FLAG,
	APROC_REG_A2M_ISR_CPUIEC0_FLAG,
	APROC_REG_A2M_ISR_CPUDEC1_FLAG,
	APROC_REG_A2M_ISR_CPUIEC1_FLAG,
	APROC_REG_A2M_ISR_CPUDEC2_FLAG,
	APROC_REG_A2M_ISR_CPUIEC2_FLAG,
#endif // CC_AUD_CPU_DEC
    APROC_REG_A2M_ISR_MIXSND0_RP = 0x10,
    APROC_REG_A2M_ISR_MIXSND1_RP,
    APROC_REG_A2M_ISR_MIXSND2_RP,
    APROC_REG_A2M_ISR_MIXSND3_RP,

    APROC_REG_A2M_ISR_UPLOAD0_WP,
    APROC_REG_A2M_ISR_UPLOAD1_WP,
    APROC_REG_A2M_ISR_UPLOAD2_WP,
    APROC_REG_A2M_ISR_UPLOAD3_NULL, //not used now

#ifdef CC_AUD_DOLBY_SUPPORT_MS12_RISCENC
    APROC_REG_A2M_ISR_RISCENC_WP, // Update wp to Risc
    APROC_REG_A2M_ISR_RISCENC_RP, // Update rp to Risc
#endif // CC_AUD_DOLBY_SUPPORT_MS12_RISCENC
} APROC_ASM_A2M_ISR_T;


/*-----------------------------------------------------------
 * Type: APROC_ASM_A2M_ISR_T
 * Group: 0x50 ==> APROC_ASM_ID_A2M_ISR_FLAG
 * Range: 0xA00 ~ 0xA1F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
     APROC_REG_A2M_ISR_UPLOAD3_FLAG = 0x0,
    APROC_REG_A2M_ISR_UPLOAD3_WP = 0x10,
}APROC_ASM_A2M_ISR_FLAG_T;

typedef enum {
    APROC_REG_A2M_ISR_CPUDEC0_RP,
    APROC_REG_A2M_ISR_CPUIEC0_RP,
    APROC_REG_A2M_ISR_CPUDEC1_RP,
    APROC_REG_A2M_ISR_CPUIEC1_RP,
    APROC_REG_A2M_ISR_CPUDEC2_RP,
    APROC_REG_A2M_ISR_CPUIEC2_RP,
} APROC_ASM_POSTPROC4E_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC0_T
 * Group: 0x10 ==> APROC_ASM_ID_POSTPROC_0
 * Range: 0x200 ~ 0x21F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // Trims
    APROC_REG_INPUT0_TRIM = 0x0,
    APROC_REG_INPUT1_TRIM,
    APROC_REG_INPUT2_TRIM,
    APROC_REG_SP_TRIM,
    APROC_REG_SP_LSRS_TRIM,
    APROC_REG_SPSW_TRIM,
    APROC_REG_HP_TRIM,    // 6
    APROC_REG_MON_TRIM,
    APROC_REG_IEC_TRIM,
    APROC_REG_SCART_TRIM, // 9
    APROC_REG_BT_TRIM,
    APROC_REG_AMIXER0_TRIM,
    APROC_REG_AMIXER1_TRIM,
    APROC_REG_AMIXER2_TRIM,
    APROC_REG_DELAY0_TRIM,
    APROC_REG_DELAY1_TRIM,
    APROC_REG_DELAY2_TRIM, // 0x10

    // Volume
    APROC_REG_SP_VOL,
    APROC_REG_SP_LSRS_VOL,
    APROC_REG_SPSW_VOL,
    APROC_REG_HP_VOL,
    APROC_REG_MON_VOL,
    APROC_REG_IEC_VOL,
    APROC_REG_SCART_VOL,
    APROC_REG_BT_VOL,
    APROC_REG_AMIXER0_VOL, // 0x19
    APROC_REG_AMIXER1_VOL,
    APROC_REG_AMIXER2_VOL,

    APROC_REG_DSP_TRIMVOL_PERIOD,
    APROC_REG_AMIXER_TRIMVOL_PERIOD,
    APROC_REG_SP_VOL_L,
    APROC_REG_SP_VOL_R,
} APROC_ASM_POSTPROC0_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC0_T
 * Group: 0x11 ==> APROC_ASM_ID_POSTPROC_1
 * Range: 0x220 ~ 0x23F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // Balancer
    APROC_REG_SP_BALANCE_0 = 0x0,
    APROC_REG_SP_BALANCE_1,
    APROC_REG_HP_BALANCE_0,
    APROC_REG_HP_BALANCE_1,

    APROC_REG_BALANCE_PERIOD,

    // Inverter
    APROC_REG_SP_INV = 0x8,
    APROC_REG_SP_LSRS_INV,
    APROC_REG_SPSW_INV,
    // SPSW mono mix
    APROC_REG_SPSW_MONOMIX_FLAG,


    APROC_REG_DELAY3_TRIM = 0x10,
    APROC_REG_DELAY4_TRIM,
    APROC_REG_DELAY5_TRIM,
    APROC_REG_DELAY6_TRIM,
    APROC_REG_SNPT_TRIM,
    APROC_REG_AMIXER2_AD_TRIM,
    APROC_REG_AMIXER2_AD_VOL,
    APROC_REG_INPUT2_AD_TRIM,


    APROC_REG_LSRS_BALANCE_0 = 0x18,
    APROC_REG_LSRS_BALANCE_1,
    APROC_REG_IEC_BALANCE_0,
    APROC_REG_IEC_BALANCE_1,
#ifdef CC_AUD_UNICORN_CUST
    // Trim Scale
    APROC_REG_SNPT_TRIM_SCL,  // 0x1a
    APROC_REG_SP_TRIM_SCL,
    APROC_REG_SP_LSRS_TRIM_SCL,
    APROC_REG_HP_TRIM_SCL,
#endif /* CC_AUD_UNICORN_CUST */

} APROC_ASM_POSTPROC1_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC2_T
 * Group: 0x12 ==> APROC_ASM_ID_POSTPROC_2
 * Range: 0x240 ~ 0x25F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // AVC SP band 0
    APROC_REG_AVC_SP_TARGET_0 = 0x0,
    APROC_REG_AVC_SP_ATTACK_0,
    APROC_REG_AVC_SP_RELEASE_0,
    APROC_REG_AVC_SP_RATIO_0,
    APROC_REG_AVC_SP_SILENCE_0,
    APROC_REG_AVC_SP_MAX_EXPAND_0,
    APROC_REG_AVC_SP_POST_GAIN_0,
    APROC_REG_AVC_SP_HOLD_0,

    // AVC SP band 1
    APROC_REG_AVC_SP_TARGET_1 = 0x8,
    APROC_REG_AVC_SP_ATTACK_1,
    APROC_REG_AVC_SP_RELEASE_1,
    APROC_REG_AVC_SP_RATIO_1,
    APROC_REG_AVC_SP_SILENCE_1,
    APROC_REG_AVC_SP_MAX_EXPAND_1,
    APROC_REG_AVC_SP_POST_GAIN_1,
    APROC_REG_AVC_SP_HOLD_1,

    // AVC SP band 2
    APROC_REG_AVC_SP_TARGET_2 = 0x10,
    APROC_REG_AVC_SP_ATTACK_2,
    APROC_REG_AVC_SP_RELEASE_2,
    APROC_REG_AVC_SP_RATIO_2,
    APROC_REG_AVC_SP_SILENCE_2,
    APROC_REG_AVC_SP_MAX_EXPAND_2,
    APROC_REG_AVC_SP_POST_GAIN_2,
    APROC_REG_AVC_SP_HOLD_2,

    // AVC HP band 0
    APROC_REG_AVC_HP_TARGET_0 = 0x18,
    APROC_REG_AVC_HP_ATTACK_0,
    APROC_REG_AVC_HP_RELEASE_0,
    APROC_REG_AVC_HP_RATIO_0,
    APROC_REG_AVC_HP_SILENCE_0,
    APROC_REG_AVC_HP_MAX_EXPAND_0,
    APROC_REG_AVC_HP_POST_GAIN_0,
    APROC_REG_AVC_HP_HOLD_0
} APROC_ASM_POSTPROC2_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC3_T
 * Group: 0x13 ==> APROC_ASM_ID_POSTPROC_3
 * Range: 0x260 ~ 0x27F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // AVC SP band 0
    APROC_REG_BIQ_SP_AVC_0_TYPE_0 = 0x0,
    APROC_REG_BIQ_SP_AVC_0_FC_0,
    APROC_REG_BIQ_SP_AVC_0_Q_0,
    APROC_REG_BIQ_SP_AVC_0_GAIN_0,
    APROC_REG_BIQ_SP_AVC_0_TYPE_1,
    APROC_REG_BIQ_SP_AVC_0_FC_1,
    APROC_REG_BIQ_SP_AVC_0_Q_1,
    APROC_REG_BIQ_SP_AVC_0_GAIN_1,

    // AVC SP band 1
    APROC_REG_BIQ_SP_AVC_1_TYPE_0 = 0x8,
    APROC_REG_BIQ_SP_AVC_1_FC_0,
    APROC_REG_BIQ_SP_AVC_1_Q_0,
    APROC_REG_BIQ_SP_AVC_1_GAIN_0,
    APROC_REG_BIQ_SP_AVC_1_TYPE_1,
    APROC_REG_BIQ_SP_AVC_1_FC_1,
    APROC_REG_BIQ_SP_AVC_1_Q_1,
    APROC_REG_BIQ_SP_AVC_1_GAIN_1,

    // AVC SP band 2
    APROC_REG_BIQ_SP_AVC_2_TYPE_0 = 0x10,
    APROC_REG_BIQ_SP_AVC_2_FC_0,
    APROC_REG_BIQ_SP_AVC_2_Q_0,
    APROC_REG_BIQ_SP_AVC_2_GAIN_0,
    APROC_REG_BIQ_SP_AVC_2_TYPE_1,
    APROC_REG_BIQ_SP_AVC_2_FC_1,
    APROC_REG_BIQ_SP_AVC_2_Q_1,
    APROC_REG_BIQ_SP_AVC_2_GAIN_1,

    // AVC HP band 0
    APROC_REG_BIQ_HP_AVC_0_TYPE_0 = 0x18,
    APROC_REG_BIQ_HP_AVC_0_FC_0,
    APROC_REG_BIQ_HP_AVC_0_Q_0,
    APROC_REG_BIQ_HP_AVC_0_GAIN_0,
    APROC_REG_BIQ_HP_AVC_0_TYPE_1,
    APROC_REG_BIQ_HP_AVC_0_FC_1,
    APROC_REG_BIQ_HP_AVC_0_Q_1,
    APROC_REG_BIQ_HP_AVC_0_GAIN_1,

} APROC_ASM_POSTPROC3_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC4_T
 * Group: 0x14 ==> APROC_ASM_ID_POSTPROC_4
 * Range: 0x280 ~ 0x29F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // Delay
    APROC_REG_DELAY_SP = 0x0,
    APROC_REG_DELAY_HP,
    APROC_REG_DELAY_SPDIF_PCM,
    APROC_REG_DELAY_SP_DBG,
    APROC_REG_DELAY_HP_DBG,
    APROC_REG_DELAY_SPDIF_PCM_DBG,
    APROC_REG_DELAY_SP_LSRS,
    APROC_REG_MDELAY_SNPT,
    APROC_REG_DELAY_AUDIO_OUT,
    APROC_REG_MDELAY_SPDIF_PCM,
    // Downmix
    APROC_REG_DMIX_AMIXER0_FLAG = 0xA, // 0xA
    APROC_REG_DMIX_AMIXER1_FLAG,
    APROC_REG_DMIX_AMIXER2_FLAG,
    APROC_REG_DMIX_AMIXER0_WAIT,
    APROC_REG_DMIX_AMIXER1_WAIT,
    APROC_REG_DMIX_AMIXER2_WAIT,
    APROC_REG_DMIX_AMIXER0_INFO, //0x10
    APROC_REG_DMIX_AMIXER1_INFO,
    APROC_REG_DMIX_AMIXER2_INFO,
#ifdef CC_AUD_UNICORN_CUST
    APROC_REG_DELAY_SAMPLE_SP,
    APROC_REG_DELAY_SAMPLE_SP_LSRS,
    APROC_REG_MDELAY_SAMPLE_SNPT,
    APROC_REG_DELAY_SAMPLE_AUDIO_OUT,
    APROC_REG_MDELAY_SAMPLE_SPDIF_PCM,
    APROC_REG_DELAY_SAMPLE_HP,
    APROC_REG_DELAY_SAMPLE_SPDIF_PCM,
    APROC_REG_MDELAY_SCART,
    APROC_REG_MDELAY_SAMPLE_SCART,
#endif // CC_AUD_UNICORN_CUST
#ifdef CC_MT5895
    APROC_REG_DELAY_EARC_AOUT_PCM,
    APROC_REG_DELAY_EARC_AOUT_RAW,
#endif
} APROC_ASM_POSTPROC4_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC5_T
 * Group: 0x15 ==> APROC_ASM_ID_POSTPROC_5
 * Range: 0x2A0 ~ 0x2BF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // SP Bass
    APROC_REG_BIQ_SP_BASS_TYPE = 0x0,
    APROC_REG_BIQ_SP_BASS_FC,
    APROC_REG_BIQ_SP_BASS_Q,
    APROC_REG_BIQ_SP_BASS_GAIN,

    // SP Treble
    APROC_REG_BIQ_SP_TREBLE_TYPE,
    APROC_REG_BIQ_SP_TREBLE_FC,
    APROC_REG_BIQ_SP_TREBLE_Q,
    APROC_REG_BIQ_SP_TREBLE_GAIN,

    // HP Bass
    APROC_REG_BIQ_HP_BASS_TYPE,
    APROC_REG_BIQ_HP_BASS_FC,
    APROC_REG_BIQ_HP_BASS_Q,
    APROC_REG_BIQ_HP_BASS_GAIN,

    // HP Treble
    APROC_REG_BIQ_HP_TREBLE_TYPE,
    APROC_REG_BIQ_HP_TREBLE_FC,
    APROC_REG_BIQ_HP_TREBLE_Q,
    APROC_REG_BIQ_HP_TREBLE_GAIN,

    // SP_LSRS Bass
    APROC_REG_BIQ_SP_LSRS_BASS_TYPE,
    APROC_REG_BIQ_SP_LSRS_BASS_FC,
    APROC_REG_BIQ_SP_LSRS_BASS_Q,
    APROC_REG_BIQ_SP_LSRS_BASS_GAIN,

    // SP_LSRS Treble
    APROC_REG_BIQ_SP_LSRS_TREBLE_TYPE,
    APROC_REG_BIQ_SP_LSRS_TREBLE_FC,
    APROC_REG_BIQ_SP_LSRS_TREBLE_Q,
    APROC_REG_BIQ_SP_LSRS_TREBLE_GAIN,

    APROC_REG_BIQ_SP_BASSTREBLE_FLAG = 0x18,
    APROC_REG_BIQ_HP_BASSTREBLE_FLAG,
    APROC_REG_BIQ_SP_BASSTREBLE_STEP,
    APROC_REG_BIQ_HP_BASSTREBLE_STEP,
    APROC_REG_BIQ_SP_LSRS_BASSTREBLE_FLAG,
    APROC_REG_BIQ_SP_LSRS_BASSTREBLE_STEP
} APROC_ASM_POSTPROC5_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC6_T
 * Group: 0x16 ==> APROC_ASM_ID_POSTPROC_6
 * Range: 0x2C0 ~ 0x2DF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // SP HPF
    APROC_REG_BIQ_SP_HPF_0_TYPE = 0x0,
    APROC_REG_BIQ_SP_HPF_0_FC,
    APROC_REG_BIQ_SP_HPF_0_Q,
    APROC_REG_BIQ_SP_HPF_0_GAIN,
    APROC_REG_BIQ_SP_HPF_1_TYPE,
    APROC_REG_BIQ_SP_HPF_1_FC,
    APROC_REG_BIQ_SP_HPF_1_Q,
    APROC_REG_BIQ_SP_HPF_1_GAIN,

    // SP LSRS HPF
    APROC_REG_BIQ_SP_LSRS_HPF_0_TYPE,
    APROC_REG_BIQ_SP_LSRS_HPF_0_FC,
    APROC_REG_BIQ_SP_LSRS_HPF_0_Q,
    APROC_REG_BIQ_SP_LSRS_HPF_0_GAIN,
    APROC_REG_BIQ_SP_LSRS_HPF_1_TYPE,
    APROC_REG_BIQ_SP_LSRS_HPF_1_FC,
    APROC_REG_BIQ_SP_LSRS_HPF_1_Q,
    APROC_REG_BIQ_SP_LSRS_HPF_1_GAIN,

    // SPSW LPF
    APROC_REG_BIQ_SPSW_LPF_0_TYPE,
    APROC_REG_BIQ_SPSW_LPF_0_FC,
    APROC_REG_BIQ_SPSW_LPF_0_Q,
    APROC_REG_BIQ_SPSW_LPF_0_GAIN,
    APROC_REG_BIQ_SPSW_LPF_1_TYPE,
    APROC_REG_BIQ_SPSW_LPF_1_FC,
    APROC_REG_BIQ_SPSW_LPF_1_Q,
    APROC_REG_BIQ_SPSW_LPF_1_GAIN,

    APROC_REG_BIQ_SP_HPF_FLAG = 0x18,
    APROC_REG_BIQ_SP_LSRS_HPF_FLAG,
    APROC_REG_BIQ_SPSW_LPF_FLAG
} APROC_ASM_POSTPROC6_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC7_T
 * Group: 0x17 ==> APROC_ASM_ID_POSTPROC_7
 * Range: 0x2E0 ~ 0x2FF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // band 0
    APROC_REG_BIQ_SP_EQ_0_TYPE = 0x0,
    APROC_REG_BIQ_SP_EQ_0_FC,
    APROC_REG_BIQ_SP_EQ_0_Q,
    APROC_REG_BIQ_SP_EQ_0_GAIN,

    // band 1
    APROC_REG_BIQ_SP_EQ_1_TYPE,
    APROC_REG_BIQ_SP_EQ_1_FC,
    APROC_REG_BIQ_SP_EQ_1_Q,
    APROC_REG_BIQ_SP_EQ_1_GAIN,

    // band 2
    APROC_REG_BIQ_SP_EQ_2_TYPE,
    APROC_REG_BIQ_SP_EQ_2_FC,
    APROC_REG_BIQ_SP_EQ_2_Q,
    APROC_REG_BIQ_SP_EQ_2_GAIN,

    // band 3
    APROC_REG_BIQ_SP_EQ_3_TYPE,
    APROC_REG_BIQ_SP_EQ_3_FC,
    APROC_REG_BIQ_SP_EQ_3_Q,
    APROC_REG_BIQ_SP_EQ_3_GAIN,

    // band 4
    APROC_REG_BIQ_SP_EQ_4_TYPE,
    APROC_REG_BIQ_SP_EQ_4_FC,
    APROC_REG_BIQ_SP_EQ_4_Q,
    APROC_REG_BIQ_SP_EQ_4_GAIN,

    // band 5
    APROC_REG_BIQ_SP_EQ_5_TYPE,
    APROC_REG_BIQ_SP_EQ_5_FC,
    APROC_REG_BIQ_SP_EQ_5_Q,
    APROC_REG_BIQ_SP_EQ_5_GAIN,

    // band 6
    APROC_REG_BIQ_SP_EQ_6_TYPE,
    APROC_REG_BIQ_SP_EQ_6_FC,
    APROC_REG_BIQ_SP_EQ_6_Q,
    APROC_REG_BIQ_SP_EQ_6_GAIN,

    // band 7
    APROC_REG_BIQ_SP_EQ_7_TYPE,
    APROC_REG_BIQ_SP_EQ_7_FC,
    APROC_REG_BIQ_SP_EQ_7_Q,
    APROC_REG_BIQ_SP_EQ_7_GAIN
} APROC_ASM_POSTPROC7_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC8_T
 * Group: 0x18 ==> APROC_ASM_ID_POSTPROC_8
 * Range: 0x300 ~ 0x31F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // DC cut SRC0
    APROC_REG_BIQ_DCCUT_SRC0_0_TYPE = 0x0,
    APROC_REG_BIQ_DCCUT_SRC0_0_FC,
    APROC_REG_BIQ_DCCUT_SRC0_0_Q,
    APROC_REG_BIQ_DCCUT_SRC0_0_GAIN,
    APROC_REG_BIQ_DCCUT_SRC0_1_TYPE,
    APROC_REG_BIQ_DCCUT_SRC0_1_FC,
    APROC_REG_BIQ_DCCUT_SRC0_1_Q,
    APROC_REG_BIQ_DCCUT_SRC0_1_GAIN,

    // DC cut SRC1
    APROC_REG_BIQ_DCCUT_SRC1_0_TYPE,
    APROC_REG_BIQ_DCCUT_SRC1_0_FC,
    APROC_REG_BIQ_DCCUT_SRC1_0_Q,
    APROC_REG_BIQ_DCCUT_SRC1_0_GAIN,
    APROC_REG_BIQ_DCCUT_SRC1_1_TYPE,
    APROC_REG_BIQ_DCCUT_SRC1_1_FC,
    APROC_REG_BIQ_DCCUT_SRC1_1_Q,
    APROC_REG_BIQ_DCCUT_SRC1_1_GAIN,

    // DC cut SRC2
    APROC_REG_BIQ_DCCUT_SRC2_0_TYPE,
    APROC_REG_BIQ_DCCUT_SRC2_0_FC,
    APROC_REG_BIQ_DCCUT_SRC2_0_Q,
    APROC_REG_BIQ_DCCUT_SRC2_0_GAIN,
    APROC_REG_BIQ_DCCUT_SRC2_1_TYPE,
    APROC_REG_BIQ_DCCUT_SRC2_1_FC,
    APROC_REG_BIQ_DCCUT_SRC2_1_Q,
    APROC_REG_BIQ_DCCUT_SRC2_1_GAIN,

    APROC_REG_BIQ_DCCUT_SRC0_FLAG = 0x18,
    APROC_REG_BIQ_DCCUT_SRC1_FLAG,
    APROC_REG_BIQ_DCCUT_SRC2_FLAG
} APROC_ASM_POSTPROC8_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC9_T
 * Group: 0x19 ==> APROC_ASM_ID_POSTPROC_9
 * Range: 0x320 ~ 0x33F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // DC cut Mix0
    APROC_REG_BIQ_DCCUT_MIX0_0_TYPE = 0x0,
    APROC_REG_BIQ_DCCUT_MIX0_0_FC,
    APROC_REG_BIQ_DCCUT_MIX0_0_Q,
    APROC_REG_BIQ_DCCUT_MIX0_0_GAIN,
    APROC_REG_BIQ_DCCUT_MIX0_1_TYPE,
    APROC_REG_BIQ_DCCUT_MIX0_1_FC,
    APROC_REG_BIQ_DCCUT_MIX0_1_Q,
    APROC_REG_BIQ_DCCUT_MIX0_1_GAIN,

    // DC cut Mix1
    APROC_REG_BIQ_DCCUT_MIX1_0_TYPE,
    APROC_REG_BIQ_DCCUT_MIX1_0_FC,
    APROC_REG_BIQ_DCCUT_MIX1_0_Q,
    APROC_REG_BIQ_DCCUT_MIX1_0_GAIN,
    APROC_REG_BIQ_DCCUT_MIX1_1_TYPE,
    APROC_REG_BIQ_DCCUT_MIX1_1_FC,
    APROC_REG_BIQ_DCCUT_MIX1_1_Q,
    APROC_REG_BIQ_DCCUT_MIX1_1_GAIN,

    // DC cut Mix2
    APROC_REG_BIQ_DCCUT_MIX2_0_TYPE = 0x10,
    APROC_REG_BIQ_DCCUT_MIX2_0_FC,
    APROC_REG_BIQ_DCCUT_MIX2_0_Q,
    APROC_REG_BIQ_DCCUT_MIX2_0_GAIN,
    APROC_REG_BIQ_DCCUT_MIX2_1_TYPE,
    APROC_REG_BIQ_DCCUT_MIX2_1_FC,
    APROC_REG_BIQ_DCCUT_MIX2_1_Q,
    APROC_REG_BIQ_DCCUT_MIX2_1_GAIN,

    APROC_REG_BIQ_DCCUT_MIX0_FLAG = 0x18,
    APROC_REG_BIQ_DCCUT_MIX1_FLAG,
    APROC_REG_BIQ_DCCUT_MIX2_FLAG,
    APROC_REG_BIQ_DCCUT_MIX3_FLAG,
} APROC_ASM_POSTPROC9_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROCA_T
 * Group: 0x1A ==> APROC_ASM_ID_POSTPROC_A
 * Range: 0x340 ~ 0x35F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    //MUTE SRC
    APROC_REG_MUTE_SRC0_FLAG = 0x0,
    APROC_REG_MUTE_SRC0_PERIOD,
    APROC_REG_MUTE_SRC1_FLAG,
    APROC_REG_MUTE_SRC1_PERIOD,
    APROC_REG_MUTE_SRC2_FLAG,
    APROC_REG_MUTE_SRC2_PERIOD,

    // AVC
    APROC_REG_SP_AVC_FLAG,
    APROC_REG_SP_AVC_DET_PERIOD,
    APROC_REG_SP_LSRS_AVC_FLAG,
    APROC_REG_SP_LSRS_AVC_DET_PERIOD,
    APROC_REG_HP_AVC_FLAG,
    APROC_REG_HP_AVC_DET_PERIOD,
    APROC_REG_AVC_MODE,
    APROC_REG_AVC_SGAIN_PERIOD,
    APROC_REG_SP_AVC_TYPE,
    APROC_REG_HP_AVC_TYPE,
    APROC_REG_SP_LSRS_AVC_TYPE = 0x10,


    // PCMR MUTE
    APROC_REG_MUTE_PCMR_FLAG = 0x11,
    APROC_REG_MUTE_PCMR_PERIOD,

    // DC cut Mix3
    APROC_REG_BIQ_DCCUT_MIX3_0_TYPE = 0x18,
    APROC_REG_BIQ_DCCUT_MIX3_0_FC,
    APROC_REG_BIQ_DCCUT_MIX3_0_Q,
    APROC_REG_BIQ_DCCUT_MIX3_0_GAIN,
    APROC_REG_BIQ_DCCUT_MIX3_1_TYPE,
    APROC_REG_BIQ_DCCUT_MIX3_1_FC,
    APROC_REG_BIQ_DCCUT_MIX3_1_Q,
    APROC_REG_BIQ_DCCUT_MIX3_1_GAIN,
} APROC_ASM_POSTPROCA_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROCB_T
 * Group: 0x1B ==> APROC_ASM_ID_POSTPROC_B
 * Range: 0x360 ~ 0x37F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // MVS
    APROC_REG_MVS_SP_CLARITY = 0x0,
    APROC_REG_MVS_SP_WIDTH,
    APROC_REG_MVS_SP_LR_GAIN,
    APROC_REG_MVS_SP_CROSSTALK,
    APROC_REG_MVS_SP_OUTPUT_GAIN,
    APROC_REG_MVS_SP_BASS_GAIN,
    APROC_REG_MVS_SP_FO,

    // VB
    APROC_REG_MVB_SPSW_OUTPUT_GAIN = 0x8,
    APROC_REG_MVB_SPSW_BASS_GAIN,
    APROC_REG_MVB_SPSW_FO,
    APROC_REG_MVB_SPSW_ATTAK,
    APROC_REG_MVB_SPSW_RELEASE,
    APROC_REG_MVB_SPSW_TH,
    APROC_REG_MVB_SPSW_DET_GAIN,

    APROC_REG_MVS_SP_FLAG = 0x18,
    APROC_REG_MVB_SPSW_FLAG

} APROC_ASM_POSTPROCB_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROCC_T
 * Group: 0x1C ==> APROC_ASM_ID_POSTPROC_C
 * Range: 0x380 ~ 0x39F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // Limiter SP
    APROC_REG_LIMITER_SP_TARGET = 0x0,
    APROC_REG_LIMITER_SP_ATTACK,
    APROC_REG_LIMITER_SP_RELEASE,
    APROC_REG_LIMITER_SP_RATIO,
    APROC_REG_LIMITER_SP_SILENCE,
    APROC_REG_LIMITER_SP_MAX_EXPAND,
    APROC_REG_LIMITER_SP_POST_GAIN,
    APROC_REG_LIMITER_SP_HOLD,

    // Limiter SPSW
    APROC_REG_LIMITER_SPSW_TARGET = 0x8,
    APROC_REG_LIMITER_SPSW_ATTACK,
    APROC_REG_LIMITER_SPSW_RELEASE,
    APROC_REG_LIMITER_SPSW_RATIO,
    APROC_REG_LIMITER_SPSW_SILENCE,
    APROC_REG_LIMITER_SPSW_MAX_EXPAND,
    APROC_REG_LIMITER_SPSW_POST_GAIN,
    APROC_REG_LIMITER_SPSW_HOLD,

     //Limiter IEC
    APROC_REG_LIMITER_IEC_TARGET = 0x10,
    APROC_REG_LIMITER_IEC_ATTACK,
    APROC_REG_LIMITER_IEC_RELEASE,
    APROC_REG_LIMITER_IEC_RATIO,
    APROC_REG_LIMITER_IEC_SILENCE,
    APROC_REG_LIMITER_IEC_MAX_EXPAND,
    APROC_REG_LIMITER_IEC_POST_GAIN,
    APROC_REG_LIMITER_IEC_HOLD,

    APROC_REG_LIMITER_SP_FLAG = 0x18,
    APROC_REG_LIMITER_SP_DET_PERIOD,
    APROC_REG_LIMITER_SPSW_FLAG,
    APROC_REG_LIMITER_SPSW_DET_PERIOD,
    APROC_REG_LIMITER_MODE,
    APROC_REG_LIMITER_SGAIN_PERIOD,
    APROC_REG_LIMITER_IEC_FLAG,
    APROC_REG_LIMITER_IEC_DET_PERIOD,
} APROC_ASM_POSTPROCC_T;

typedef enum {
    APROC_SPK_OUTPUT_4_0 = 0x0, // L+R+LS+RS
    APROC_SPK_OUTPUT_4_1,       //L+R+LS+RS+SW
    APROC_SPK_OUTPUT_2_2,       //L+R+SW_L+SW_R
    APROC_SPK_OUTPUT_2_1,       //L+R+SW
    APROC_SPK_OUTPUT_2_0,       //L+R
    APROC_SPK_OUTPUT_BT,
    APROC_SPK_OUTPUT_5_1,       //L+R+C+LS+RS+SW
    APROC_SPK_OUTPUT_7_1,       //L+R+C+LS+RS+SW+CH7+CH8
    APROC_SPK_OUTPUT_TEST = 0x100,
} APROC_SPK_OUTPUT_T;

typedef enum {
    APROC_HP_OUTPUT_HP = 0x0,
    APROC_HP_OUTPUT_MON,
    APROC_HP_OUTPUT_WOOFER,
} APROC_HP_OUTPUT_T;

typedef enum {
    APROC_IEC_OUTPUT_PCM = 0x0,
    APROC_IEC_OUTPUT_AUTO1,
    APROC_IEC_OUTPUT_AUTO2,
    APROC_IEC_OUTPUT_SOUND_BAR,
} APROC_IEC_OUTPUT_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROCD_T
 * Group: 0x1D ==> APROC_ASM_ID_POSTPROC_D
 * Range: 0x3A0 ~ 0x3BF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // TSM
    APROC_REG_TSM_0_FLAG = 0x0,
    APROC_REG_TSM_0_SPEED,
    APROC_REG_TSM_1_FLAG,
    APROC_REG_TSM_1_SPEED,
#ifdef CC_AUD_UNICORN_CUST
    // POST selection
    APROC_REG_SP_OUT_SEL, //APROC_SPK_OUTPUT_T
    APROC_REG_AUDIO_OUT_SEL, //APROC_HP_OUTPUT_T
    APROC_REG_IEC_OUT_SEL, //APROC_IEC_OUTPUT_T
    APROC_REG_EXTDEV_OUT_SEL, //APROC_EXTDEV_OUTPUT_T
#else
    // POST selection
    APROC_REG_SP_OUT_SEL, //APROC_SPK_OUTPUT_T
    APROC_REG_LSRS_FROM_LR_SEL,
    APROC_REG_HP_POST_FLAG,
    APROC_REG_IEC_OUT_SEL,
#endif
    // Dual mono
    APROC_REG_DUALMONO_0_FLAG = 0x8,
    APROC_REG_DUALMONO_0_MODE,
    APROC_REG_DUALMONO_1_FLAG,
    APROC_REG_DUALMONO_1_MODE,
    APROC_REG_DUALMONO_2_FLAG,
    APROC_REG_DUALMONO_2_MODE,
#ifdef CC_AUD_UNICORN_CUST
    APROC_REG_DUALMONO_SNPT_FLAG = 0x10,
    APROC_REG_DUALMONO_SNPT_MODE,
    APROC_REG_DUALMONO_SPSW_FLAG,
    APROC_REG_DUALMONO_SPSW_MODE,
    APROC_REG_DUALMONO_MON_FLAG,
    APROC_REG_DUALMONO_MON_MODE,
    APROC_REG_DUALMONO_HP_FLAG,
    APROC_REG_DUALMONO_HP_MODE,
    APROC_REG_DUALMONO_IEC_FLAG,
    APROC_REG_DUALMONO_IEC_MODE,
    APROC_REG_DUALMONO_SP_FLAG,
    APROC_REG_DUALMONO_SP_MODE,
    APROC_REG_DUALMONO_DMIX_MODE,
    // SW phase
    APROC_REG_SW_PHASE = 0x1d,
    // SW mix coeff
    APROC_REG_SW_MIX_COEFF,
#endif /* CC_AUD_UNICORN_CUST */

} APROC_ASM_POSTPROCD_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROCE_T
 * Group: 0x1E ==> APROC_ASM_ID_POSTPROC_E
 * Range: 0x3C0 ~ 0x3DF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // band 0
    APROC_REG_BIQ_SP_LSRS_EQ_0_TYPE = 0x0,
    APROC_REG_BIQ_SP_LSRS_EQ_0_FC,
    APROC_REG_BIQ_SP_LSRS_EQ_0_Q,
    APROC_REG_BIQ_SP_LSRS_EQ_0_GAIN,

    // band 1
    APROC_REG_BIQ_SP_LSRS_EQ_1_TYPE,
    APROC_REG_BIQ_SP_LSRS_EQ_1_FC,
    APROC_REG_BIQ_SP_LSRS_EQ_1_Q,
    APROC_REG_BIQ_SP_LSRS_EQ_1_GAIN,

    // band 2
    APROC_REG_BIQ_SP_LSRS_EQ_2_TYPE,
    APROC_REG_BIQ_SP_LSRS_EQ_2_FC,
    APROC_REG_BIQ_SP_LSRS_EQ_2_Q,
    APROC_REG_BIQ_SP_LSRS_EQ_2_GAIN,

    // band 3
    APROC_REG_BIQ_SP_LSRS_EQ_3_TYPE,
    APROC_REG_BIQ_SP_LSRS_EQ_3_FC,
    APROC_REG_BIQ_SP_LSRS_EQ_3_Q,
    APROC_REG_BIQ_SP_LSRS_EQ_3_GAIN,

    // band 4
    APROC_REG_BIQ_SP_LSRS_EQ_4_TYPE,
    APROC_REG_BIQ_SP_LSRS_EQ_4_FC,
    APROC_REG_BIQ_SP_LSRS_EQ_4_Q,
    APROC_REG_BIQ_SP_LSRS_EQ_4_GAIN,

    // band 5
    APROC_REG_BIQ_SP_LSRS_EQ_5_TYPE,
    APROC_REG_BIQ_SP_LSRS_EQ_5_FC,
    APROC_REG_BIQ_SP_LSRS_EQ_5_Q,
    APROC_REG_BIQ_SP_LSRS_EQ_5_GAIN,

    // band 6
    APROC_REG_BIQ_SP_LSRS_EQ_6_TYPE,
    APROC_REG_BIQ_SP_LSRS_EQ_6_FC,
    APROC_REG_BIQ_SP_LSRS_EQ_6_Q,
    APROC_REG_BIQ_SP_LSRS_EQ_6_GAIN,

    // band 7
    APROC_REG_BIQ_SP_LSRS_EQ_7_TYPE,
    APROC_REG_BIQ_SP_LSRS_EQ_7_FC,
    APROC_REG_BIQ_SP_LSRS_EQ_7_Q,
    APROC_REG_BIQ_SP_LSRS_EQ_7_GAIN
    } APROC_ASM_POSTPROCE_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC12_T
 * Group: 0x22 ==> APROC_ASM_ID_POSTPROC_12
 * Range: 0x440 ~ 0x45F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {

    // EQ
    APROC_REG_BIQ_SP_EQ_FLAG,
    APROC_REG_EQ_FIR_SP_FLAG,
    APROC_REG_BIQ_SP_EQ_STEP,
    APROC_REG_BIQ_SP_LSRS_EQ_FLAG,
    APROC_REG_EQ_FIR_SP_LSRS_FLAG,
    APROC_REG_BIQ_SP_LSRS_EQ_STEP,
    APROC_REG_BIQ_HP_EQ_FLAG,
    APROC_REG_EQ_FIR_HP_FLAG,
    APROC_REG_BIQ_HP_EQ_STEP,
    APROC_REG_EQ_SP_32EQ_FLAG,
    APROC_REG_EQ_SP_32EQ_STEP,

    // SW,woofer channel
    APROC_REG_SW_FLAG = 0x10,

} APROC_ASM_POSTPROC12_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROCF_T
 * Group: 0x1F ==> APROC_ASM_ID_POSTPROC_F
 * Range: 0x3E0 ~ 0x3FF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // AVC SP LSRS band 0
    APROC_REG_AVC_SP_LSRS_TARGET_0 = 0x0,
    APROC_REG_AVC_SP_LSRS_ATTACK_0,
    APROC_REG_AVC_SP_LSRS_RELEASE_0,
    APROC_REG_AVC_SP_LSRS_RATIO_0,
    APROC_REG_AVC_SP_LSRS_SILENCE_0,
    APROC_REG_AVC_SP_LSRS_MAX_EXPAND_0,
    APROC_REG_AVC_SP_LSRS_POST_GAIN_0,
    APROC_REG_AVC_SP_LSRS_HOLD_0,

    // AVC SP LSRS band 0
    APROC_REG_BIQ_SP_LSRS_AVC_0_TYPE_0 = 0x8,
    APROC_REG_BIQ_SP_LSRS_AVC_0_FC_0,
    APROC_REG_BIQ_SP_LSRS_AVC_0_Q_0,
    APROC_REG_BIQ_SP_LSRS_AVC_0_GAIN_0,
    APROC_REG_BIQ_SP_LSRS_AVC_0_TYPE_1,
    APROC_REG_BIQ_SP_LSRS_AVC_0_FC_1,
    APROC_REG_BIQ_SP_LSRS_AVC_0_Q_1,
    APROC_REG_BIQ_SP_LSRS_AVC_0_GAIN_1,

    APROC_REG_DBXTV_EN =0x10, //DBX TV Enable
    APROC_REG_DBX_TYPE,
    APROC_REG_DBX_OFFSET,
    APROC_REG_DBX_READPC,
    APROC_REG_DBX_READRPC,
    APROC_REG_DBX_VOLUME_MAP,
    ARPOC_REG_DTS_TS3D_EN,

} APROC_ASM_POSTPROCF_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC10_T
 * Group: 0x20 ==> APROC_ASM_ID_POSTPROC_10
 * Range: 0x400 ~ 0x41F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // Limiter SP LSRS
    APROC_REG_LIMITER_SP_LSRS_TARGET = 0x0,
    APROC_REG_LIMITER_SP_LSRS_ATTACK,
    APROC_REG_LIMITER_SP_LSRS_RELEASE,
    APROC_REG_LIMITER_SP_LSRS_RATIO,
    APROC_REG_LIMITER_SP_LSRS_SILENCE,
    APROC_REG_LIMITER_SP_LSRS_MAX_EXPAND,
    APROC_REG_LIMITER_SP_LSRS_POST_GAIN,
    APROC_REG_LIMITER_SP_LSRS_HOLD,

    // Limiter HP
    APROC_REG_LIMITER_HP_TARGET = 0x8,
    APROC_REG_LIMITER_HP_ATTACK,
    APROC_REG_LIMITER_HP_RELEASE,
    APROC_REG_LIMITER_HP_RATIO,
    APROC_REG_LIMITER_HP_SILENCE,
    APROC_REG_LIMITER_HP_MAX_EXPAND,
    APROC_REG_LIMITER_HP_POST_GAIN,
    APROC_REG_LIMITER_HP_HOLD,

    APROC_REG_LIMITER_SP_LSRS_FLAG = 0x18,
    APROC_REG_LIMITER_SP_LSRS_DET_PERIOD,
    APROC_REG_LIMITER_HP_FLAG,
    APROC_REG_LIMITER_HP_DET_PERIOD,
#ifdef CC_AUD_UNICORN_CUST
    // Limiter BT
    APROC_REG_LIMITER_BT_TARGET,
#endif /* CC_AUD_UNICORN_CUST */
} APROC_ASM_POSTPROC10_T;
/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC20_T
 * Group: 0x30 ==> APROC_ASM_ID_POSTPROC_20
 * Range: 0x600 ~ 0x61F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    //Bass Management
    APROC_REG_BMANG_CTRL_FLAG = 0x0,
    APROC_REG_BMANG_CHID_CFG,
    APROC_REG_BMANG_LEF_TRIM,
    APROC_REG_BMANG_VOLUME,
    APROC_REG_BMANG_L_SIZE,
    APROC_REG_BMANG_R_SIZE,
    APROC_REG_BMANG_C_SIZE,
    APROC_REG_BMANG_LS_SIZE,
    APROC_REG_BMANG_RS_SIZE,
    APROC_REG_BMANG_SW_SIZE,
    APROC_REG_BMANG_LFE2CH,

    // SP
    APROC_REG_BIQ_BMANG_SP_HPF_TYPE,
    APROC_REG_BIQ_BMANG_SP_HPF_FC, // cutoff FC
    APROC_REG_BIQ_BMANG_SP_HPF_Q,
    APROC_REG_BIQ_BMANG_SP_HPF_GAIN,
    //SW
    APROC_REG_BIQ_BMANG_SW_LPF_TYPE,
    APROC_REG_BIQ_BMANG_SW_LPF_FC, // cutoff FC
    APROC_REG_BIQ_BMANG_SW_LPF_Q,
    APROC_REG_BIQ_BMANG_SW_LPF_GAIN,
}APROC_ASM_POSTPROC20_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC21_T
 * Group: 0x20 ==> APROC_ASM_ID_POSTPROC_21
 * Range: 0x620 ~ 0x63F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_PEQ_0_FC,
    APROC_REG_PEQ_1_FC,
    APROC_REG_PEQ_2_FC,
    APROC_REG_PEQ_3_FC,
    APROC_REG_PEQ_4_FC,
    APROC_REG_PEQ_5_FC,
    APROC_REG_PEQ_6_FC,
    APROC_REG_PEQ_7_FC,
    APROC_REG_PEQ_8_FC,

    APROC_REG_PEQ_0_Q,
    APROC_REG_PEQ_1_Q,
    APROC_REG_PEQ_2_Q,
    APROC_REG_PEQ_3_Q,
    APROC_REG_PEQ_4_Q,
    APROC_REG_PEQ_5_Q,
    APROC_REG_PEQ_6_Q,
    APROC_REG_PEQ_7_Q,
    APROC_REG_PEQ_8_Q,

    APROC_REG_PEQ_0_GAIN,
    APROC_REG_PEQ_1_GAIN,
    APROC_REG_PEQ_2_GAIN,
    APROC_REG_PEQ_3_GAIN,
    APROC_REG_PEQ_4_GAIN,
    APROC_REG_PEQ_5_GAIN,
    APROC_REG_PEQ_6_GAIN,
    APROC_REG_PEQ_7_GAIN,
    APROC_REG_PEQ_8_GAIN,

    APROC_REG_PEQ_SP_FLAG = 0x1B,

    APROC_REG_CDNOTCH_SP_FLAG,
    APROC_REG_CDNOTCH_FC,
    APROC_REG_CDNOTCH_Q,
    APROC_REG_CDNOTCH_GAIN,
    }APROC_ASM_POSTPROC21_T;

typedef enum {
    APROC_REG_PEQ_R_0_FC,
    APROC_REG_PEQ_R_1_FC,
    APROC_REG_PEQ_R_2_FC,
    APROC_REG_PEQ_R_3_FC,
    APROC_REG_PEQ_R_4_FC,
    APROC_REG_PEQ_R_5_FC,
    APROC_REG_PEQ_R_6_FC,
    APROC_REG_PEQ_R_7_FC,
    APROC_REG_PEQ_R_8_FC,

    APROC_REG_PEQ_R_0_Q,
    APROC_REG_PEQ_R_1_Q,
    APROC_REG_PEQ_R_2_Q,
    APROC_REG_PEQ_R_3_Q,
    APROC_REG_PEQ_R_4_Q,
    APROC_REG_PEQ_R_5_Q,
    APROC_REG_PEQ_R_6_Q,
    APROC_REG_PEQ_R_7_Q,
    APROC_REG_PEQ_R_8_Q,

    APROC_REG_PEQ_R_0_GAIN,
    APROC_REG_PEQ_R_1_GAIN,
    APROC_REG_PEQ_R_2_GAIN,
    APROC_REG_PEQ_R_3_GAIN,
    APROC_REG_PEQ_R_4_GAIN,
    APROC_REG_PEQ_R_5_GAIN,
    APROC_REG_PEQ_R_6_GAIN,
    APROC_REG_PEQ_R_7_GAIN,
    APROC_REG_PEQ_R_8_GAIN,

    //APROC_REG_PEQ_R_SP_FLAG = 0x1B,

    APROC_REG_BIQUAD_SP_FLAG = 0x1E,

}APROC_ASM_POSTPROC38_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_ID_SEL0_T
 * Group: 0x21 ==> APROC_ASM_ID_SEL_0
 * Range: 0x420 ~ 0x43F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {

    APROC_REG_SEL_DSP_SP_IN = 0x0,
    APROC_REG_SEL_DSP_HP_IN,
    APROC_REG_SEL_DSP_SPDIF_IN,
    APROC_REG_SEL_DSP_BT_IN,
    APROC_REG_SEL_DSP_MON_IN,
    APROC_REG_SEL_SCART_IN,
    APROC_REG_SEL_MIXSND0_IN,
    APROC_REG_SEL_MIXSND1_IN,
    APROC_REG_SEL_MIXSND0_MIX_IN,
    APROC_REG_SEL_MIXSND1_MIX_IN,
    APROC_REG_SEL_UPLOAD1_IN,
    APROC_REG_SEL_ENC_IN,
    APROC_REG_SEL_UPLOAD0_IN,
    APROC_REG_SEL_UPLOAD2_IN,
    APROC_REG_SEL_TV_IN,
    APROC_REG_SEL_NUM
} APROC_ASM_ID_SEL0_T;

typedef enum {
    // SRS SS3D
    APROC_REG_SS3D_SPSW_ENABLE = 0x0,
    APROC_REG_SS3D_SPSW_HEADGAIN,
    APROC_REG_SS3D_SPSW_BPGAIN,
    APROC_REG_SS3D_SPSW_MAINTECH,
    APROC_REG_SS3D_SPSW_MT_NONE,
    APROC_REG_SS3D_SPSW_MT_WOWHD,
    APROC_REG_SS3D_SPSW_MT_TSHD,
    APROC_REG_SS3D_SPSW_MT_CC3D,
    APROC_REG_SS3D_SPSW_MT_CSHP,
    APROC_REG_SS3D_SPSW_MT_TBHD,
    APROC_REG_SS3D_SPSW_MV_ENABLE,
    APROC_REG_SS3D_SPSW_TBHDRefOffset,
    APROC_REG_SS3D_SPSW_HdLmtBoostOffset,


} APROC_ASM_ID_SRS_SS3D_T;

typedef enum {
    // SRS TVOL
    APROC_REG_TVOL_SPSW_ENABLE = 0x0,
    APROC_REG_TVOL_SPSW_INPUTGAIN,
    APROC_REG_TVOL_SPSW_OUTGAIN,
    APROC_REG_TVOL_SPSW_BPGAIN,
    APROC_REG_TVOL_SPSW_LVINTER,
    APROC_REG_TVOL_SPSW_MODE,
    APROC_REG_TVOL_SPSW_NREN,
    APROC_REG_TVOL_SPSW_NRTH,
    APROC_REG_TVOL_SPSW_LKFS,
    APROC_REG_TVOL_SPSW_SMOOTHEN,

    // SRS AEQ
    APROC_REG_LAEQ_SPSW_ENABLE = 0xA,
    APROC_REG_LAEQ_SPSW_INPUTGAIN,
    APROC_REG_LAEQ_SPSW_OUTGAIN,
    APROC_REG_LAEQ_SPSW_BPGAIN,
    APROC_REG_RAEQ_SPSW_ENABLE,
    APROC_REG_RAEQ_SPSW_INPUTGAIN,
    APROC_REG_RAEQ_SPSW_OUTGAIN,
    APROC_REG_RAEQ_SPSW_BPGAIN,


    // SRS TruDialog
    APROC_REG_TRUD_SPSW_ENABLE = 0x12,
    APROC_REG_TRUD_SPSW_INPUTGAIN,
    APROC_REG_TRUD_SPSW_OUTGAIN,
    APROC_REG_TRUD_SPSW_BPGAIN,
    APROC_REG_TRUD_SPSW_PRGAIN,
    APROC_REG_TRUD_SPSW_CLAGAIN,

} APROC_ASM_ID_SRS_TVOL_AEQ_TRUD_T;

typedef enum {
    // SRS CC3D
    APROC_REG_CC3D_SPSW_ENABLE = 0x0,
    APROC_REG_CC3D_SPSW_INPUTGAIN,
    APROC_REG_CC3D_SPSW_OUTGAIN,
    APROC_REG_CC3D_SPSW_BPGAIN,
    APROC_REG_CC3D_SPSW_DPEN,
    APROC_REG_CC3D_SPSW_SUREN,
    APROC_REG_CC3D_SPSW_MODE,
    APROC_REG_CC3D_SPSW_DEPMODE,
    APROC_REG_CC3D_SPSW_DEPFADE_ENABLE,
    APROC_REG_CC3D_SPSW_LR_ENABLE,
    APROC_REG_CC3D_SPSW_LR_GAIN,
    APROC_REG_CC3D_SPSW_MIXFADE_CTRL,

} APROC_ASM_ID_SRS_CC3D_T;

typedef enum {
    // SRS STTSHD
    APROC_REG_TSHD_SPSW_ENABLE = 0x0,
    APROC_REG_TSHD_SPSW_INPUTGAIN,
    APROC_REG_TSHD_SPSW_OUTGAIN,
    APROC_REG_TSHD_SPSW_BPGAIN,
    APROC_REG_TSHD_SPSW_SURENABLE,
    APROC_REG_TSHD_SPSW_INMODE,
    APROC_REG_TSHD_SPSW_FS_CTRL,
    APROC_REG_TSHD_SPSW_FC_CTRL,
    APROC_REG_TSHD_SPSW_RS_CTRL,
    APROC_REG_TSHD_SPSW_RC_CTRL,
    APROC_REG_TSHD_SPSW_FR_GAIN1,
    APROC_REG_TSHD_SPSW_FR_GAIN2,
    APROC_REG_TSHD_SPSW_TS_LEV,
    APROC_REG_TSHD_SPSW_SPTUNE,
    APROC_REG_TSHD_SPSW_MF_CTRL,
    APROC_REG_TSHD_SPSW_MR_CTRLEXT,
    APROC_REG_TSHD_SPSW_MIX_EN,//0X10
    APROC_REG_TSHD_SPSW_LDEF_EN,
    APROC_REG_TSHD_SPSW_LDEF_Lev,
    APROC_REG_TSHD_SPSW_RDEF_EN,
    APROC_REG_TSHD_SPSW_RDEF_Lev,//0X14
    APROC_REG_TSHD_SPSW_LFOCUS_EN,
    APROC_REG_TSHD_SPSW_LFOCUS_Lev,
    APROC_REG_TSHD_SPSW_RFOCUS_EN,
    APROC_REG_TSHD_SPSW_RFOCUS_Lev,//0X18
    APROC_REG_TSHD_SPSW_CFOCUS_EN,
    APROC_REG_TSHD_SPSW_CFOCUS_Lev,//0X1A

    // SRS SPHPF
    APROC_REG_SPHPF_SPSW_ENABLE = 0x1B,
    APROC_REG_SPHPF_SPSW_INPUTGAIN,
    APROC_REG_SPHPF_SPSW_OUTGAIN,
    APROC_REG_SPHPF_SPSW_BPGAIN,
    APROC_REG_SPHPF_SPSW_CUTOFF_FRQ,

} APROC_ASM_ID_SRS_TSHD_SPHPF_T;

typedef enum {
    // SRS TBHD
    APROC_REG_TBHD_SPSW_ENABLE = 0x0,
    APROC_REG_TBHD_SPSW_INDEP,
    APROC_REG_TBHD_SPSW_ANA_EN,
    APROC_REG_TBHD_SPSW_INPUTGAIN,
    APROC_REG_TBHD_SPSW_OUTGAIN,
    APROC_REG_TBHD_SPSW_BPGAIN,
    APROC_REG_TBHD_SPSW_TB_CTRL,
    APROC_REG_TBHD_SPSW_CMP_CTRL,
    APROC_REG_TBHD_SPSW_RF_LEV,
    APROC_REG_TBHD_SPSW_INTGRA_LIMIT,
    APROC_REG_TBHD_SPSW_SPK_SIZE,
    APROC_REG_TBHD_SPSW_ANA_SIZE,
    APROC_REG_TBHD_SPSW_MODE,
    APROC_REG_TBHD_SPSW_OUT_OPT,
    APROC_REG_TBHD_SPSW_TBQ,
    APROC_REG_TBHD_SPSW_DCU_LEV,//0xF

    // SRS SRS3D
    APROC_REG_SRS3D_SPSW_ENABLE = 0x10,
    APROC_REG_SRS3D_SPSW_INPUTGAIN,
    APROC_REG_SRS3D_SPSW_OUTGAIN,
    APROC_REG_SRS3D_SPSW_BPGAIN,
    APROC_REG_SRS3D_SPSW_HBITRATE,
    APROC_REG_SRS3D_SPSW_SPACE_CTRL,
    APROC_REG_SRS3D_SPSW_CEN_CTRL,
    APROC_REG_SRS3D_SPSW_HP,
    APROC_REG_SRS3D_SPSW_MODE,
    APROC_REG_SRS3D_SPSW_NORM_GAIN,

} APROC_ASM_ID_SRS_TBHD_SRS3D_T;

typedef enum {
    // SRS CSHP
    APROC_REG_CSHP_SPSW_ENABLE = 0x0,
    APROC_REG_CSHP_SPSW_INPUTGAIN,
    APROC_REG_CSHP_SPSW_OUTGAIN,
    APROC_REG_CSHP_SPSW_BPGAIN,
    APROC_REG_CSHP_SPSW_RENDMODE,

} APROC_ASM_ID_SRS_CSHP_T;

typedef enum {
    // SRS GEQ5B
    APROC_REG_LGEQ5B_SPSW_ENABLE = 0x0,
    APROC_REG_LGEQ5B_SPSW_INTER_BNAD,
    APROC_REG_LGEQ5B_SPSW_EXBAND_BEH,
    APROC_REG_LGEQ5B_SPSW_BGAIN0,
    APROC_REG_LGEQ5B_SPSW_BGAIN1,
    APROC_REG_LGEQ5B_SPSW_BGAIN2,
    APROC_REG_LGEQ5B_SPSW_BGAIN3,
    APROC_REG_LGEQ5B_SPSW_BGAIN4,
    APROC_REG_LGEQ5B_SPSW_GAIN_UPDATE,
    APROC_REG_LGEQ5B_SPSW_INPUTGAIN,
    APROC_REG_RGEQ5B_SPSW_ENABLE,
    APROC_REG_RGEQ5B_SPSW_INTER_BNAD,
    APROC_REG_RGEQ5B_SPSW_EXBAND_BEH,
    APROC_REG_RGEQ5B_SPSW_BGAIN0,
    APROC_REG_RGEQ5B_SPSW_BGAIN1,
    APROC_REG_RGEQ5B_SPSW_BGAIN2,
    APROC_REG_RGEQ5B_SPSW_BGAIN3,
    APROC_REG_RGEQ5B_SPSW_BGAIN4,
    APROC_REG_RGEQ5B_SPSW_GAIN_UPDATE,
    APROC_REG_RGEQ5B_SPSW_INPUTGAIN,//0x13

     // SRS HPF
    APROC_REG_LHPF_SPSW_ENABLE = 0x14,
    APROC_REG_LHPF_SPSW_SECTION,
    APROC_REG_RHPF_SPSW_ENABLE,
    APROC_REG_RHPF_SPSW_SECTION,

} APROC_ASM_ID_SRS_GEQ_HPF_T;

typedef enum {
    // SRS BASSTREBLE
    APROC_REG_BASTRB_SPSW_EANBLE = 0x0,
    APROC_REG_BASTRB_SPSW_INPUTGAIN,
    APROC_REG_BASTRB_SPSW_OUTGAIN,
    APROC_REG_BASTRB_SPSW_BPGAIN,
    APROC_REG_BASTRB_SPSW_BASSGAIN,
    APROC_REG_BASTRB_SPSW_TRBGAIN,

    // SRS Master Volume
    APROC_REG_MVOL_SPSW_ENABLE = 0x8,
    APROC_REG_MVOL_SPSW_VOLSTEP,
    APROC_REG_MVOL_SPSW_PAN,
    APROC_REG_MVOL_SPSW_MUTE,
    APROC_REG_MVOL_SPSW_BPGAIN,
    APROC_REG_MVOL_SPSW_PROCMODE,
    APROC_REG_MVOL_SPSW_HL_BOOST,

     // SRS HardLimiter
    APROC_REG_HL_SPSW_ENABLE = 0x10,
    APROC_REG_HL_SPSW_INPUTGAIN,
    APROC_REG_HL_SPSW_OUTGAIN,
    APROC_REG_HL_SPSW_BPGAIN,
    APROC_REG_HL_SPSW_DEL_LEN,
    APROC_REG_HL_SPSW_BOOST,
    APROC_REG_HL_SPSW_AC_ENA,
    APROC_REG_HL_SPSW_AC_LEV,

} APROC_ASM_ID_SRS_BT_MV_HL_T;

typedef enum {
    // SRS  TS3D
    APROC_REG_TS3D_SP_DTSOFF = 0x0,
    APROC_REG_TS3D_SP_INCHCFG,
    APROC_REG_TS3D_SP_ENABLE,
    APROC_REG_TS3D_SP_HEADROOMGAIN,
    APROC_REG_TS3D_SP_BPGAIN,
    APROC_REG_TS3D_SP_PROCPATH,
    APROC_REG_TS3D_SP_DWNUPFLAG,
    APROC_REG_TS3D_SP_INCHG_LINGAIN,
    APROC_REG_TS3D_SP_INCHG_RINGAIN,
    APROC_REG_TS3D_SP_INCHG_CINGAIN,
    APROC_REG_TS3D_SP_INCHG_LSINGAIN,
    APROC_REG_TS3D_SP_INCHG_RSINGAIN,
    APROC_REG_TS3D_SP_INCHG_SUBINGAIN,
    APROC_REG_TS3D_SP_CSDMASTEREN,
    APROC_REG_TS3D_SP_CSDLRGAIN,
    APROC_REG_TS3D_SP_CSDLSRSGAIN,
    APROC_REG_TS3D_SP_CSDCENTERGAIN,
} APROC_ASM_ID_SRS2_TS3D_T;

typedef enum {
    // SRS   TruSHD
    APROC_REG_TRUSHD_SP_ENABLE = 0x0,
    APROC_REG_TRUSHD_SP_INPUTGAIN,
    APROC_REG_TRUSHD_SP_OUTPUTGAIN,
    APROC_REG_TRUSHD_SP_BPGAIN,
    APROC_REG_TRUSHD_SP_INMODE,
    APROC_REG_TRUSHD_SP_OUTMODE,
    APROC_REG_TRUSHD_SP_SURLEVEL,
    APROC_REG_TRUSHD_SP_SURENABLE,
    APROC_REG_TRUSHD_SP_MIXENABLE,
    APROC_REG_TRUSHD_SP_SPACECTUNE,
    APROC_REG_TRUSHD_SP_MIXFADECTRL,

    // SRS   level
    APROC_REG_LEVEL_SP_MODE = 0x10,
    APROC_REG_LEVEL_SP_ENCORRECTION,
    APROC_REG_LEVEL_SP_TRACKSP,
    APROC_REG_LEVEL_SP_BLKSIZE,

} APROC_ASM_ID_SRS2_TRUSHD_LEVEL_T;

typedef enum {

    // SRS   TvolHD
    APROC_REG_TVOL_SP_ENABLE = 0x0,
    APROC_REG_TVOL_SP_MODE,
    APROC_REG_TVOL_SP_MAXGAIN,
    APROC_REG_TVOL_SP_NORMALIZEREN,
    APROC_REG_TVOL_SP_NORMTHRESH,
    APROC_REG_TVOL_SP_RefLevel,
    APROC_REG_TVOL_SP_SMOOTHEN,

        // SRS   Trudiag
    APROC_REG_TRUD_SP_ENABLE = 0x10,
    APROC_REG_TRUD_SP_INPUTGAIN,
    APROC_REG_TRUD_SP_CLARIGAIN,
    APROC_REG_TRUD_SP_PROCESSGAIN,

} APROC_ASM_ID_SRS2_THD_TRUD_T;


typedef enum {

    // SRS CC3D
    APROC_REG_CC3D_SP_ENABLE = 0x0,
    APROC_REG_CC3D_SP_INPUTGAIN,
    APROC_REG_CC3D_SP_DEPTHPROCESS_ENABLE,
    APROC_REG_CC3D_SP_LR_ENABLE,
    APROC_REG_CC3D_SP_LR_GAIN,
    APROC_REG_CC3D_SP_MIXFADE_CTRL,

    // SRS STTSHD
    APROC_REG_TSHD_SP_ENABLE = 0x10,
    APROC_REG_TSHD_SP_INPUTGAIN,

    APROC_REG_TSHD_SP_TRUSLEVEL,
    APROC_REG_TSHD_SP_MIX_ENABLE,

}APROC_ASM_ID_SRS2_CC3D_TSHD_T;

typedef enum {
    // SRS CSD
    APROC_REG_CSD_SP_ENABLE= 0x0,
    APROC_REG_CSD_SP_INPUTGAIN ,
    APROC_REG_CSD_SP_MODE,

    // SRS CSHP
    APROC_REG_CSHP_SP_ENABLE = 0x5,


    // SRS SRS3D
    APROC_REG_SRS3D_SP_ENABLE = 0x10,
    APROC_REG_SRS3D_SP_INPUTGAIN,
    APROC_REG_SRS3D_SP_OUTGAIN,
    APROC_REG_SRS3D_SP_BPGAIN,
    APROC_REG_SRS3D_SP_HBITRATE,
    APROC_REG_SRS3D_SP_SPACE_CTRL,
    APROC_REG_SRS3D_SP_CEN_CTRL,
    APROC_REG_SRS3D_SP_HP,
    APROC_REG_SRS3D_SP_MODE,
    APROC_REG_SRS3D_SP_NORM_GAIN,

} APROC_ASM_ID_SRS2_CSD_CSHP_SRS3D_T;

typedef enum {
// SRS SPHPF
    APROC_REG_SPHPF_SP_ENABLE = 0x0,

// SRS TBHDX
    APROC_REG_TBHDX_SP_ENABLE = 0x1,
    APROC_REG_TBHDX_SP_MODE,
    APROC_REG_TBHDX_SP_INPUTGAIN,
    APROC_REG_TBHDX_SP_BPGAIN,
    APROC_REG_TBHDX_SP_SPEAKERSIZE,
    APROC_REG_TBHDX_SP_BASSLEVEL,
    APROC_REG_TBHDX_SP_DYNAMICS,
    APROC_REG_TBHDX_SP_HPORDER,

 // SRS HPF
    APROC_REG_HPF_SP_ENABLE = 0x9,
    APROC_REG_HPF_SP_SECTION,
    APROC_REG_HPF_SP_COF_PARAMTYPE,
    APROC_REG_HPF_SP_COF_PARAMVALUE,
 //srs def
    APROC_REG_DEF_SP_ENABLE=0xD,
    APROC_REG_DEF_SP_LEVEL,

    APROC_REG_DEF_SP_DecinChg0,
 //focust
    APROC_REG_FOCUS_SP_ENABLE=0x10,
    APROC_REG_FOCUS_SP_LEVEL,

    APROC_REG_TSHDSUR_SP_LEVEL,

    APROC_REG_DEF_SP_DecinChg1,
// SRS AEQ
    APROC_REG_AEQ_SP_ENABLE = 0x15,
    APROC_REG_AEQ_SP_INPUTGAIN,
    APROC_REG_AEQ_SP_OUTGAIN,
    APROC_REG_AEQ_SP_BPGAIN,
    APROC_REG_AEQ_SP_COF_PARAMTYPE,
    APROC_REG_AEQ_SP_COF_PARAMVALUE
}APROC_ASM_ID_SRS2_COMMON_AEQ_T;

typedef enum {
     // SRS GEQ5B
    APROC_REG_GEQ5B_SP_ENABLE = 0x0,
    APROC_REG_GEQ5B_SP_INPUTGAIN,
    APROC_REG_GEQ5B_SP_BGAIN0,
    APROC_REG_GEQ5B_SP_BGAIN1,
    APROC_REG_GEQ5B_SP_BGAIN2,
    APROC_REG_GEQ5B_SP_BGAIN3,
    APROC_REG_GEQ5B_SP_BGAIN4,

//hardlimiter
    APROC_REG_HDLMT_SP_ENABLE = 0xA,
    APROC_REG_HDLMT_SP_INPUTGAIN,


//WOWHD
    APROC_REG_WOWHD_SP_ENABLE = 0x10,
    APROC_REG_WOWHD_SP_INPUTGAIN,
    APROC_REG_WOWHD_SP_OUTGAIN,
    APROC_REG_WOWHD_SP_BPGAIN,
}APROC_ASM_ID_SRS2_GEQ_HL_WOW_T;

typedef enum {
 #if 1
//MCDynamics
    APROC_REG_MCDYNAMIC_SP_HLENABLE = 0x0,
    APROC_REG_MCDYNAMIC_SP_OUTPUTGAIN,
    APROC_REG_MCDYNAMIC_SP_ACLEVEL,
    APROC_REG_MCDYNAMIC_SP_COMATTACKS,
    APROC_REG_MCDYNAMIC_SP_LOWDECAY,
    APROC_REG_MCDYNAMIC_SP_MIDDECAY,
    APROC_REG_MCDYNAMIC_SP_HIGHDECAY,
    APROC_REG_MCDYNAMIC_SP_COMRATIO,
    APROC_REG_MCDYNAMIC_SP_FRTHLMODE,
    APROC_REG_MCDYNAMIC_SP_FRTBOOST,
    APROC_REG_MCDYNAMIC_SP_FRTLOWCROSS,
    APROC_REG_MCDYNAMIC_SP_FRTMIDCROSS,
    APROC_REG_MCDYNAMIC_SP_FRTLOWTHRESH,
    APROC_REG_MCDYNAMIC_SP_FRTMIDTHRESH,
    APROC_REG_MCDYNAMIC_SP_FRTHIGHTHRESH,
    APROC_REG_MCDYNAMIC_SP_FRTCOMMAKEUPGAIN,
#else
//hardlimiter
    APROC_REG_MBHL_SP_ENABLE = 0x0,
    APROC_REG_MBHL_SP_BOOSTGAIN,
    APROC_REG_MBHL_SP_OUTPUTGAIN,
#endif

//downup
    APROC_REG_DWNUP_SP_ENABLE = 0x1A,
    APROC_REG_DWNUP_SP_MIXCOEF,
    APROC_REG_DWNUP_SP_MODE,
    APROC_REG_DWNUP_SP_DELAYLEN,
}APROC_ASM_ID_SRS2_DYN_DOWNUP_T;

typedef enum {
    // Spost misc
    APROC_REG_SPOST_GETVAR_FLAG = 0x0,
    APROC_REG_SPOST_GETVAR_ISIZE,
    APROC_REG_SPOST_GETVAR_OSIZE,
    APROC_REG_SPOST_LOGOUT_FLAG,
    APROC_REG_SPOST_GEN_CONFIG, // 0x4,
    APROC_REG_SPOST_POST_CONFIG,
    APROC_REG_SPOST_STR_INFO,
    APROC_REG_SPOST_SP_MODE,
    APROC_REG_SPOST_BT_INFO,
    APROC_REG_SPOST_AUD_ITEM_CMD,
} APROC_ASM_SPOST_MISC23_T;

typedef enum {
    // EqSpectrum
    APROC_REG_SPECTRUM_ENABLE = 0x0,
    APROC_REG_SPECTRUM_0,
    APROC_REG_SPECTRUM_1,
    APROC_REG_SPECTRUM_2,
    APROC_REG_SPECTRUM_3,
    APROC_REG_SPECTRUM_4,
    APROC_REG_SPECTRUM_5,
    APROC_REG_SPECTRUM_6,
    APROC_REG_SPECTRUM_7,
    APROC_REG_SPECTRUM_8,
    APROC_REG_SPECTRUM_9,
    APROC_REG_SPECTRUM_10,
    APROC_REG_SPECTRUM_11,
    APROC_REG_SPECTRUM_12,
    APROC_REG_SPECTRUM_13,
    APROC_REG_SPECTRUM_14,
    //APROC_REG_SPECTRUM_15,

} APROC_ASM_ID_EQSPECTRUM_T;

typedef enum {
    // MP3 encoder
    APROC_REG_IOBUF_INTBUF4_ENA = 0x0,
    APROC_REG_IOBUF_INTBUF4_START,
    APROC_REG_IOBUF_INTBUF4_END,
    APROC_REG_IOBUF_INTBUF4_CH,
    APROC_REG_IOBUF_INTBUF4_SIZE,
    APROC_REG_IOBUF_INTBUF4_WP,
    APROC_REG_IOBUF_INTBUF4_RP,
    APROC_REG_IOBUF_UPLOAD0_RP,   //0x7
    APROC_REG_IOBUF_UPLOAD1_RP,
    APROC_REG_IOBUF_UPLOAD2_RP,
    APROC_REG_IOBUF_UPLOAD3_RP,

}APROC_ASM_ENC_MP3_T;

typedef enum {
    // band 0
    APROC_REG_BIQUAD_0_TYPE = 0x0,
    APROC_REG_BIQUAD_0_FC,
    APROC_REG_BIQUAD_0_Q,
    APROC_REG_BIQUAD_0_GAIN,

    // band 1
    APROC_REG_BIQUAD_1_TYPE,
    APROC_REG_BIQUAD_1_FC,
    APROC_REG_BIQUAD_1_Q,
    APROC_REG_BIQUAD_1_GAIN,

    // band 2
    APROC_REG_BIQUAD_2_TYPE,
    APROC_REG_BIQUAD_2_FC,
    APROC_REG_BIQUAD_2_Q,
    APROC_REG_BIQUAD_2_GAIN,

    // band 3
    APROC_REG_BIQUAD_3_TYPE,
    APROC_REG_BIQUAD_3_FC,
    APROC_REG_BIQUAD_3_Q,
    APROC_REG_BIQUAD_3_GAIN,

    // band 4
    APROC_REG_BIQUAD_4_TYPE,
    APROC_REG_BIQUAD_4_FC,
    APROC_REG_BIQUAD_4_Q,
    APROC_REG_BIQUAD_4_GAIN,

    // band 5
    APROC_REG_BIQUAD_5_TYPE,
    APROC_REG_BIQUAD_5_FC,
    APROC_REG_BIQUAD_5_Q,
    APROC_REG_BIQUAD_5_GAIN,

    // band 6
    APROC_REG_BIQUAD_6_TYPE,
    APROC_REG_BIQUAD_6_FC,
    APROC_REG_BIQUAD_6_Q,
    APROC_REG_BIQUAD_6_GAIN,

    // band 7
    APROC_REG_BIQUAD_7_TYPE,
    APROC_REG_BIQUAD_7_FC,
    APROC_REG_BIQUAD_7_Q,
    APROC_REG_BIQUAD_7_GAIN
} APROC_ASM_POSTPROC39_T;

typedef enum {
    // band 0
    APROC_REG_BIQUAD_R_0_TYPE = 0x0,
    APROC_REG_BIQUAD_R_0_FC,
    APROC_REG_BIQUAD_R_0_Q,
    APROC_REG_BIQUAD_R_0_GAIN,

    // band 1
    APROC_REG_BIQUAD_R_1_TYPE,
    APROC_REG_BIQUAD_R_1_FC,
    APROC_REG_BIQUAD_R_1_Q,
    APROC_REG_BIQUAD_R_1_GAIN,

    // band 2
    APROC_REG_BIQUAD_R_2_TYPE,
    APROC_REG_BIQUAD_R_2_FC,
    APROC_REG_BIQUAD_R_2_Q,
    APROC_REG_BIQUAD_R_2_GAIN,

    // band 3
    APROC_REG_BIQUAD_R_3_TYPE,
    APROC_REG_BIQUAD_R_3_FC,
    APROC_REG_BIQUAD_R_3_Q,
    APROC_REG_BIQUAD_R_3_GAIN,

    // band 4
    APROC_REG_BIQUAD_R_4_TYPE,
    APROC_REG_BIQUAD_R_4_FC,
    APROC_REG_BIQUAD_R_4_Q,
    APROC_REG_BIQUAD_R_4_GAIN,

    // band 5
    APROC_REG_BIQUAD_R_5_TYPE,
    APROC_REG_BIQUAD_R_5_FC,
    APROC_REG_BIQUAD_R_5_Q,
    APROC_REG_BIQUAD_R_5_GAIN,

    // band 6
    APROC_REG_BIQUAD_R_6_TYPE,
    APROC_REG_BIQUAD_R_6_FC,
    APROC_REG_BIQUAD_R_6_Q,
    APROC_REG_BIQUAD_R_6_GAIN,

    // band 7
    APROC_REG_BIQUAD_R_7_TYPE,
    APROC_REG_BIQUAD_R_7_FC,
    APROC_REG_BIQUAD_R_7_Q,
    APROC_REG_BIQUAD_R_7_GAIN
} APROC_ASM_POSTPROC3A_T;

typedef enum {

    // band 0
    APROC_REG_BIQ_HP_EQ_0_TYPE = 0x0,
    APROC_REG_BIQ_HP_EQ_0_FC,
    APROC_REG_BIQ_HP_EQ_0_Q,
    APROC_REG_BIQ_HP_EQ_0_GAIN,

    // band 1
    APROC_REG_BIQ_HP_EQ_1_TYPE,
    APROC_REG_BIQ_HP_EQ_1_FC,
    APROC_REG_BIQ_HP_EQ_1_Q,
    APROC_REG_BIQ_HP_EQ_1_GAIN,

    // band 2
    APROC_REG_BIQ_HP_EQ_2_TYPE,
    APROC_REG_BIQ_HP_EQ_2_FC,
    APROC_REG_BIQ_HP_EQ_2_Q,
    APROC_REG_BIQ_HP_EQ_2_GAIN,

    // band 3
    APROC_REG_BIQ_HP_EQ_3_TYPE,
    APROC_REG_BIQ_HP_EQ_3_FC,
    APROC_REG_BIQ_HP_EQ_3_Q,
    APROC_REG_BIQ_HP_EQ_3_GAIN,

    // band 4
    APROC_REG_BIQ_HP_EQ_4_TYPE,
    APROC_REG_BIQ_HP_EQ_4_FC,
    APROC_REG_BIQ_HP_EQ_4_Q,
    APROC_REG_BIQ_HP_EQ_4_GAIN,

    // band 5
    APROC_REG_BIQ_HP_EQ_5_TYPE,
    APROC_REG_BIQ_HP_EQ_5_FC,
    APROC_REG_BIQ_HP_EQ_5_Q,
    APROC_REG_BIQ_HP_EQ_5_GAIN,

    // band 6
    APROC_REG_BIQ_HP_EQ_6_TYPE,
    APROC_REG_BIQ_HP_EQ_6_FC,
    APROC_REG_BIQ_HP_EQ_6_Q,
    APROC_REG_BIQ_HP_EQ_6_GAIN,

    // band 7
    APROC_REG_BIQ_HP_EQ_7_TYPE,
    APROC_REG_BIQ_HP_EQ_7_FC,
    APROC_REG_BIQ_HP_EQ_7_Q,
    APROC_REG_BIQ_HP_EQ_7_GAIN
}APROC_ASM_POSTPROC3B_T;

typedef enum {
    // Trims
    APROC_REG_SP_CH7CH8_TRIM = 0x0,
    APROC_REG_DELAY7_TRIM,
    APROC_REG_DELAY8_TRIM,
    APROC_REG_PCMR_DMX_TRIM = 0x3,

    // Inverter
    APROC_REG_SP_CH7CH8_INV = 0x4,

    // Volume
    APROC_REG_SP_CH7CH8_VOL = 0x8,

    // Delay
    APROC_REG_DELAY_SP_CH7CH8 = 0x10,
    APROC_REG_DELAY_BT,
    APROC_REG_DELAY_RAW_ENC_TRIM,


    // Fade In/Fade Out
    APROC_REG_IOBUF_FADE_ENA = 0x14,
    APROC_REG_IOBUF_FADE_RESET,
    APROC_REG_IOBUF_FADE_TARGET,
    APROC_REG_IOBUF_FADE_PERIOD,
    APROC_REG_IOBUF_FADE_MODE,
    APROC_REG_IOBUF_FADE_PAUSE,
    APROC_REG_IOBUF_FADE_CUR_VOL
} APROC_ASM_POSTPROC3C_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC49_T
 * Group: 0x49 ==> APROC_ASM_ID_POSTPROC_49
 * Range: 0x920 ~ 0x93F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // band 0
    APROC_REG_32BIQ_SP_EQ_0_TYPE = 0x0,
    APROC_REG_32BIQ_SP_EQ_0_FC,
    APROC_REG_32BIQ_SP_EQ_0_Q,
    APROC_REG_32BIQ_SP_EQ_0_GAIN,

    // band 1
    APROC_REG_32BIQ_SP_EQ_1_TYPE,
    APROC_REG_32BIQ_SP_EQ_1_FC,
    APROC_REG_32BIQ_SP_EQ_1_Q,
    APROC_REG_32BIQ_SP_EQ_1_GAIN,

    // band 2
    APROC_REG_32BIQ_SP_EQ_2_TYPE,
    APROC_REG_32BIQ_SP_EQ_2_FC,
    APROC_REG_32BIQ_SP_EQ_2_Q,
    APROC_REG_32BIQ_SP_EQ_2_GAIN,

    // band 3
    APROC_REG_32BIQ_SP_EQ_3_TYPE,
    APROC_REG_32BIQ_SP_EQ_3_FC,
    APROC_REG_32BIQ_SP_EQ_3_Q,
    APROC_REG_32BIQ_SP_EQ_3_GAIN,

    // band 4
    APROC_REG_32BIQ_SP_EQ_4_TYPE,
    APROC_REG_32BIQ_SP_EQ_4_FC,
    APROC_REG_32BIQ_SP_EQ_4_Q,
    APROC_REG_32BIQ_SP_EQ_4_GAIN,

    // band 5
    APROC_REG_32BIQ_SP_EQ_5_TYPE,
    APROC_REG_32BIQ_SP_EQ_5_FC,
    APROC_REG_32BIQ_SP_EQ_5_Q,
    APROC_REG_32BIQ_SP_EQ_5_GAIN,

    // band 6
    APROC_REG_32BIQ_SP_EQ_6_TYPE,
    APROC_REG_32BIQ_SP_EQ_6_FC,
    APROC_REG_32BIQ_SP_EQ_6_Q,
    APROC_REG_32BIQ_SP_EQ_6_GAIN,

    // band 7
    APROC_REG_32BIQ_SP_EQ_7_TYPE,
    APROC_REG_32BIQ_SP_EQ_7_FC,
    APROC_REG_32BIQ_SP_EQ_7_Q,
    APROC_REG_32BIQ_SP_EQ_7_GAIN
} APROC_ASM_POSTPROC49_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC4A_T
 * Group: 0x4A ==> APROC_ASM_ID_POSTPROC_4A
 * Range: 0x940 ~ 0x95F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // band 8
    APROC_REG_32BIQ_SP_EQ_8_TYPE = 0x0,
    APROC_REG_32BIQ_SP_EQ_8_FC,
    APROC_REG_32BIQ_SP_EQ_8_Q,
    APROC_REG_32BIQ_SP_EQ_8_GAIN,

    // band 9
    APROC_REG_32BIQ_SP_EQ_9_TYPE,
    APROC_REG_32BIQ_SP_EQ_9_FC,
    APROC_REG_32BIQ_SP_EQ_9_Q,
    APROC_REG_32BIQ_SP_EQ_9_GAIN,

    // band 10
    APROC_REG_32BIQ_SP_EQ_10_TYPE,
    APROC_REG_32BIQ_SP_EQ_10_FC,
    APROC_REG_32BIQ_SP_EQ_10_Q,
    APROC_REG_32BIQ_SP_EQ_10_GAIN,

    // band 11
    APROC_REG_32BIQ_SP_EQ_11_TYPE,
    APROC_REG_32BIQ_SP_EQ_11_FC,
    APROC_REG_32BIQ_SP_EQ_11_Q,
    APROC_REG_32BIQ_SP_EQ_11_GAIN,

    // band 12
    APROC_REG_32BIQ_SP_EQ_12_TYPE,
    APROC_REG_32BIQ_SP_EQ_12_FC,
    APROC_REG_32BIQ_SP_EQ_12_Q,
    APROC_REG_32BIQ_SP_EQ_12_GAIN,

    // band 13
    APROC_REG_32BIQ_SP_EQ_13_TYPE,
    APROC_REG_32BIQ_SP_EQ_13_FC,
    APROC_REG_32BIQ_SP_EQ_13_Q,
    APROC_REG_32BIQ_SP_EQ_13_GAIN,

    // band 14
    APROC_REG_32BIQ_SP_EQ_14_TYPE,
    APROC_REG_32BIQ_SP_EQ_14_FC,
    APROC_REG_32BIQ_SP_EQ_14_Q,
    APROC_REG_32BIQ_SP_EQ_14_GAIN,

    // band 15
    APROC_REG_32BIQ_SP_EQ_15_TYPE,
    APROC_REG_32BIQ_SP_EQ_15_FC,
    APROC_REG_32BIQ_SP_EQ_15_Q,
    APROC_REG_32BIQ_SP_EQ_15_GAIN
} APROC_ASM_POSTPROC4A_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC4B_T
 * Group: 0x4B ==> APROC_ASM_ID_POSTPROC_4B
 * Range: 0x960 ~ 0x97F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // band 16
    APROC_REG_32BIQ_SP_EQ_16_TYPE = 0x0,
    APROC_REG_32BIQ_SP_EQ_16_FC,
    APROC_REG_32BIQ_SP_EQ_16_Q,
    APROC_REG_32BIQ_SP_EQ_16_GAIN,

    // band 17
    APROC_REG_32BIQ_SP_EQ_17_TYPE,
    APROC_REG_32BIQ_SP_EQ_17_FC,
    APROC_REG_32BIQ_SP_EQ_17_Q,
    APROC_REG_32BIQ_SP_EQ_17_GAIN,

    // band 18
    APROC_REG_32BIQ_SP_EQ_18_TYPE,
    APROC_REG_32BIQ_SP_EQ_18_FC,
    APROC_REG_32BIQ_SP_EQ_18_Q,
    APROC_REG_32BIQ_SP_EQ_18_GAIN,

    // band 19
    APROC_REG_32BIQ_SP_EQ_19_TYPE,
    APROC_REG_32BIQ_SP_EQ_19_FC,
    APROC_REG_32BIQ_SP_EQ_19_Q,
    APROC_REG_32BIQ_SP_EQ_19_GAIN,

    // band 20
    APROC_REG_32BIQ_SP_EQ_20_TYPE,
    APROC_REG_32BIQ_SP_EQ_20_FC,
    APROC_REG_32BIQ_SP_EQ_20_Q,
    APROC_REG_32BIQ_SP_EQ_20_GAIN,

    // band 21
    APROC_REG_32BIQ_SP_EQ_21_TYPE,
    APROC_REG_32BIQ_SP_EQ_21_FC,
    APROC_REG_32BIQ_SP_EQ_21_Q,
    APROC_REG_32BIQ_SP_EQ_21_GAIN,

    // band 22
    APROC_REG_32BIQ_SP_EQ_22_TYPE,
    APROC_REG_32BIQ_SP_EQ_22_FC,
    APROC_REG_32BIQ_SP_EQ_22_Q,
    APROC_REG_32BIQ_SP_EQ_22_GAIN,

    // band 23
    APROC_REG_32BIQ_SP_EQ_23_TYPE,
    APROC_REG_32BIQ_SP_EQ_23_FC,
    APROC_REG_32BIQ_SP_EQ_23_Q,
    APROC_REG_32BIQ_SP_EQ_23_GAIN
} APROC_ASM_POSTPROC4B_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC4C_T
 * Group: 0x4C ==> APROC_ASM_ID_POSTPROC_4C
 * Range: 0x980 ~ 0x99F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    // band 24
    APROC_REG_32BIQ_SP_EQ_24_TYPE = 0x0,
    APROC_REG_32BIQ_SP_EQ_24_FC,
    APROC_REG_32BIQ_SP_EQ_24_Q,
    APROC_REG_32BIQ_SP_EQ_24_GAIN,

    // band 25
    APROC_REG_32BIQ_SP_EQ_25_TYPE,
    APROC_REG_32BIQ_SP_EQ_25_FC,
    APROC_REG_32BIQ_SP_EQ_25_Q,
    APROC_REG_32BIQ_SP_EQ_25_GAIN,

    // band 26
    APROC_REG_32BIQ_SP_EQ_26_TYPE,
    APROC_REG_32BIQ_SP_EQ_26_FC,
    APROC_REG_32BIQ_SP_EQ_26_Q,
    APROC_REG_32BIQ_SP_EQ_26_GAIN,

    // band 27
    APROC_REG_32BIQ_SP_EQ_27_TYPE,
    APROC_REG_32BIQ_SP_EQ_27_FC,
    APROC_REG_32BIQ_SP_EQ_27_Q,
    APROC_REG_32BIQ_SP_EQ_27_GAIN,

    // band 28
    APROC_REG_32BIQ_SP_EQ_28_TYPE,
    APROC_REG_32BIQ_SP_EQ_28_FC,
    APROC_REG_32BIQ_SP_EQ_28_Q,
    APROC_REG_32BIQ_SP_EQ_28_GAIN,

    // band 29
    APROC_REG_32BIQ_SP_EQ_29_TYPE,
    APROC_REG_32BIQ_SP_EQ_29_FC,
    APROC_REG_32BIQ_SP_EQ_29_Q,
    APROC_REG_32BIQ_SP_EQ_29_GAIN,

    // band 30
    APROC_REG_32BIQ_SP_EQ_30_TYPE,
    APROC_REG_32BIQ_SP_EQ_30_FC,
    APROC_REG_32BIQ_SP_EQ_30_Q,
    APROC_REG_32BIQ_SP_EQ_30_GAIN,

    // band 31
    APROC_REG_32BIQ_SP_EQ_31_TYPE,
    APROC_REG_32BIQ_SP_EQ_31_FC,
    APROC_REG_32BIQ_SP_EQ_31_Q,
    APROC_REG_32BIQ_SP_EQ_31_GAIN
} APROC_ASM_POSTPROC4C_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_POSTPROC4D_T
 * Group: 0x4D ==> APROC_ASM_ID_POSTPROC_4C
 * Range: 0x9A0 ~ 0x9BF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_32BANDINITED,
} APROC_ASM_POSTPROC4D_T;


#ifdef CC_AUD_DOLBY_SUPPORT_MS12
typedef enum {
#ifdef CC_AUD_DOLBY_SUPPORT_MS12_RISCENC
    // RiscEnc Upload data to Risc
    APROC_REG_MS12_IOBUF_RISCENC_UP_START = 0x00,
    APROC_REG_MS12_IOBUF_RISCENC_UP_END,
    APROC_REG_MS12_IOBUF_RISCENC_UP_SIZE,
    APROC_REG_MS12_IOBUF_RISCENC_UP_CH,
    APROC_REG_MS12_IOBUF_RISCENC_UP_ENABLE,
    APROC_REG_MS12_IOBUF_RISCENC_UP_SI_START,
    // RiscEnc download data from Risc
    APROC_REG_MS12_IOBUF_RISCENC_DOWN_START,
    APROC_REG_MS12_IOBUF_RISCENC_DOWN_END,
    APROC_REG_MS12_IOBUF_RISCENC_DOWN_SIZE,
    APROC_REG_MS12_IOBUF_RISCENC_DOWN_CH,
    APROC_REG_MS12_IOBUF_RISCENC_DOWN_ENABLE,
#endif // CC_AUD_DOLBY_SUPPORT_MS12_RISCENC
    APROC_REG_MS12_IOBUF_NUM
} APROC_ASM_MS12_IOBUF_T;
typedef enum {
    // MS12 MS Mixer
    APROC_REG_MS12_MIXER_RISC_ENABLE = 0x00,      // Enable Risc to start MS Mixer
    APROC_REG_MS12_MIXER_INFO_ADDR,               // mixer information address
    APROC_REG_MS12_MIXER_STATE,                   //
    APROC_REG_MS12_MIXER_OUTPUT_SELECTOR,         // 0: maixed, 1:main, 2:assoc
    // MS12 PCM Renderer
    APROC_REG_MS12_PCMR_RISC_ENABLE = 0x04,       // Enable Risc to start Pcm Renderer
    APROC_REG_MS12_PCMR_INFO_ADDR,                // pcmr information address
    APROC_REG_MS12_PCMR_STATE,                    //
    // MS12 DDP Encoder
    APROC_REG_MS12_DDPENC_RISC_ENABLE = 0x8,     // [0]:Enable Risc to start DDP Encoder, [1]:Re-init Aproc-Side DDP Encoder, [2]: Re-init Risc-Side DDP Encoder
    APROC_REG_MS12_DDPENC_INFO_ADDR,              // ddpenc information address
    APROC_REG_MS12_DDPENC_STATE,                  //
    APROC_REG_MS12_DDPENC_ERRCODE,                // error code
    // MS12 PCMR SideInfo Buffer Write/Read Pointers
    APROC_REG_MS12_PCMR_SIDEINFO_WP = 0xC,
    APROC_REG_MS12_PCMR_SIDEINFO_RP,
    // Indicate if external decoded PCM
    APROC_REG_MS12_EXTERNAL_PCM, // [0]:Enable external mode(DEC0), [1]:Enable external mode(DEC1), [2]:Enable external mode(DEC2),
                                 // [3]:Dual-Mono(DEC0), [4]:Dual-Mono(DEC1), [5]:Dual-Mono[DEC2)
    // for Dolby TB11.5
    // EBU regions that have adopted the -23LKFS transmission loudness level
    // ATSC and EBU regions that have adopted the -24LKFS transmission loudness level
    // Other regions that have adopted the -20LKFS transmission loudness level
    APROC_REG_MS12_LOUDNESS, // Loudness in dB, [0:7]Disable, [8:15]Amixer0, [16:23]Amixer1, [24:31]Amixer2_AD
    // Select Channel for outBufIec
    APROC_REG_MS12_SELECT_OUTBUF, // [0:3]Hp, [4:7]IEC, [8:11]OUT; 0:dmx,1:MC0 or CH0|1, 2:MC1 or CH2|3, 3:CH4|5
    // Workaround for LFE downmix Bug of Dolby MS12 ==> miss LFE at Line mode
    APROC_REG_MS12_PCMR_ENABLE_MTK_FIX, // [0]:LFE Downmix, [1]:DDPEnc Unsupported Acmode&LFE
    APROC_REG_MS12_PCMR_LFE_DOWNMIX_MIXLEV,
    APROC_REG_MS12_OPTCTRL_ENABLE, // [0]DDP Encoder Datarate
    APROC_REG_MS12_ASSOC_DELAY,
    APROC_REG_MS12_SRC_UPLPF, // [0]Enable(1)/Disable(0)
    APROC_REG_MS12_PCMR_PURE_MIXSND_BANK, // Bank Number of Pure MixSound
    APROC_REG_MS12_DDPENC_NOCTETS, // Transcoded Data Length
#ifdef CC_AUD_DOLBY_SUPPORT_DAPv2
    APROC_REG_MS12_DAP_RISC_ENABLE = 0x18,       // Enable Risc to start DAP
    APROC_REG_MS12_DAP_INFO_ADDR,                // DAP information address
#endif // CC_AUD_DOLBY_SUPPORT_DAPv2
#ifdef CC_AUD_DEC_1STBANK_DETECT
    APROC_REG_MS12_CLEAR_1STBANK,
#endif // CC_AUD_DEC_1STBANK_DETECT
#if 1 // Lock Audio Coding Mode to 5.1
    APROC_REG_MS12_LOCK_MODE, // [0] Enable(1)/Disable(0)
#endif
#ifdef CC_AUD_DOLBY_SUPPORT_MS12_LATENCY_DBG
    APROC_REG_MS12_MEASURE_LATENCY, // for debug usage
#endif // CC_AUD_DOLBY_SUPPORT_MS12_LATENCY_DBG
#ifdef CC_AUD_RISCAOUT_SUPPORT
	APROC_REG_MS12_DEC_CH_NUM = 0x1d,
	APROC_REG_MS12_DEC_CHG0 = 0x1e,
	APROC_REG_MS12_DEC_CHG1 = 0x1f,  //0x1f
#endif

    APROC_REG_MS12_NUM
} APROC_ASM_MS12_T;
typedef enum
{
    // Thread_Amixer0
    APROC_REG_UPLOAD_AMIXER0_FLAG,                // [0]: Enable upload
                                                  // Enable bits
                                                  // [1]: amixer0Buf
                                                  // [2]: sDecSideInfo
                                                  // [3]: MD (Pcmr)
                                                  // Status bits
                                                  // [17]: amixer0Buf
                                                  // [18]: sDecSideInfo
                                                  // [19]: MD (Pcmr)
    APROC_REG_UPLOAD_AMIXER0_SAMPLERATE,          // Sample Rate
    APROC_REG_UPLOAD_AMIXER0_CHCONFIG,            // [0-15]: Channel_Config0, [16:31]: Channel_Config1
    APROC_REG_UPLOAD_AMIXER0_SAMPLES,             // Number of samples to upload
    APROC_REG_UPLOAD_AMIXER0_ADDR,                // address to upload
    // Thread_Amixer1
    APROC_REG_UPLOAD_AMIXER1_FLAG,                // [0]: Enable upload
                                                  // Enable bits
                                                  // [1]: amixer1Buf
                                                  // [2]: sDecSideInfo
                                                  // [3]: MD (Pcmr)
                                                  // Status bits
                                                  // [17]: amixer1Buf
                                                  // [18]: sDecSideInfo
                                                  // [19]: MD (Pcmr)
    APROC_REG_UPLOAD_AMIXER1_SAMPLERATE,          // Sample Rate
    APROC_REG_UPLOAD_AMIXER1_CHCONFIG,            // [0-15]: Channel_Config0, [16:31]: Channel_Config1
    APROC_REG_UPLOAD_AMIXER1_SAMPLES,             // Number of samples to upload
    APROC_REG_UPLOAD_AMIXER1_ADDR,                // address to upload
    // Thread_Amixer2_AD
    APROC_REG_UPLOAD_AMIXER2_AD_FLAG,             // [0]: Enable upload
                                                  // Enable bits
                                                  // [1]: MainBuf
                                                  // [2]: AssocBuf
                                                  // [3]: MixedBuf
                                                  // [4]: Main sDecSideInfo
                                                  // [5]: Assoc sDecSideInfo
                                                  // [6]: MMD (Mixer)
                                                  // Status bits
                                                  // [17]: MainBuf
                                                  // [18]: AssocBuf
                                                  // [19]: MixedBuf
                                                  // [20]: Main sDecSideInfo
                                                  // [21]: Assoc sDecSideInfo
                                                  // [22]: MMD (Mixer)
    APROC_REG_UPLOAD_AMIXER2_AD_M_SAMPLERATE,     // Sample Rate of main/mixed audio
    APROC_REG_UPLOAD_AMIXER2_AD_A_SAMPLERATE,     // Sample Rate of assoc audio
    APROC_REG_UPLOAD_AMIXER2_AD_M_CHCONFIG,         // [0-15]: Channel_Config0, [16:31]: Channel_Config1 of main/mixed audio
    APROC_REG_UPLOAD_AMIXER2_AD_A_CHCONFIG,         // [0-15]: Channel_Config0, [16:31]: Channel_Config1 of assoc audio
    APROC_REG_UPLOAD_AMIXER2_AD_SAMPLES,          // Number of samples to upload
    APROC_REG_UPLOAD_AMIXER2_AD_ADDR,             // address to upload
    // Thread_DSP
    // vAprocPcmr
    APROC_REG_UPLOAD_DSP_PCMR_FLAG,               // [0]: Enable upload
                                                  // Enable bits
                                                  // [1]: _gi4MS12_PCMR_IN_BUF
                                                  // [2]: _gi4MS12_PCMR_RAW_MC_OUT_BUF[0]
                                                  // [3]: _gi4MS12_PCMR_MC_OUT_BUF[0][0]
                                                  // [4]: _gi4MS12_PCMR_MC_OUT_BUF[0][1]
                                                  // [5]: _gi4MS12_PCMR_DMX_OUT_BUF[0]
                                                  // [6]: sSideInfo
                                                  // [7]: MD (Pcmr)
                                                  // [8]: Converted MD (Pcmr)
                                                  // Status bits
                                                  // [17]: _gi4MS12_PCMR_IN_BUF
                                                  // [18]: _gi4MS12_PCMR_RAW_MC_OUT_BUF[0]
                                                  // [19]: _gi4MS12_PCMR_MC_OUT_BUF[0][0]
                                                  // [20]: _gi4MS12_PCMR_MC_OUT_BUF[0][1]
                                                  // [21]: _gi4MS12_PCMR_DMX_OUT_BUF[0]
                                                  // [22]: sSideInfo
                                                  // [23]: MD (Pcmr)
                                                  // [24]: Converted MD (Pcmr)
    APROC_REG_UPLOAD_DSP_PCMR_SAMPLERATE,         // Sample Rate of input mc
    APROC_REG_UPLOAD_DSP_PCMR_CHCONFIG,           // [0-15]: Channel_Config0, [16:31]: Channel_Config1, only for MC
    APROC_REG_UPLOAD_DSP_PCMR_SAMPLES,            // Number of samples to upload
    APROC_REG_UPLOAD_DSP_PCMR_ADDR,               // address to upload
    // vAprocDDPEnc
    APROC_REG_UPLOAD_DSP_DDPENC_FLAG,             // [0]: Enable upload
                                                  // Enable bits
                                                  // [1]: _gi4MS12_DDPENC_IN_BUF
                                                  // [2]: _gi4MS12_DDPENC_OUT_BUF
                                                  // [3]: sSideInfo
                                                  // [4]: MD (Pcmr)
                                                  // [5]: Converted MD (Pcmr)
                                                  // [6]: Pass Through (from ddp decoder)
                                                  // Status bits
                                                  // [17]: _gi4MS12_DDPENC_IN_BUF
                                                  // [18]: _gi4MS12_DDPENC_OUT_BUF
                                                  // [19]: sSideInfo
                                                  // [20]: MD (Pcmr)
                                                  // [21]: Converted MD (Pcmr)
                                                  // [22]: Pass Through (from ddp decoder)
    APROC_REG_UPLOAD_DSP_DDPENC_SAMPLERATE,       // Sample Rate of input MC
    APROC_REG_UPLOAD_DSP_DDPENC_CHCONFIG,         // [0-15]: Channel_Config0, [16:31]: Channel_Config1
    APROC_REG_UPLOAD_DSP_DDPENC_SAMPLES,          // Number of samples to upload
    APROC_REG_UPLOAD_DSP_DDPENC_ADDR,             // address to upload
    // do not dump zero data
    APROC_REG_UPLOAD_NO_ZERO_DATA,
    APROC_REG_UPLOAD_NUM
} APROC_ASM_UPLOAD_T;
#endif // CC_AUD_DOLBY_SUPPORT_MS12
#ifdef CC_AUD_DOLBY_SUPPORT_DAPv2
typedef enum
{
    // Thread_DSP
    // vAprocDap
    APROC_REG_UPLOAD2_DSP_DAP_FLAG,               // [0]: Enable upload
                                                  // Enable bits
                                                  // [1]: _gi4MS12_DAP_IN_BUF
                                                  // [2]: _gi4MS12_DAP_OUT_BUF
    APROC_REG_UPLOAD2_DSP_DAP_SAMPLERATE,         // Sample Rate of input mc
    APROC_REG_UPLOAD2_DSP_DAP_CHCONFIG,           // [0-15]: Channel_Config0, [16:31]: Channel_Config1, only for MC
    APROC_REG_UPLOAD2_DSP_DAP_SAMPLES,            // Number of samples to upload
    APROC_REG_UPLOAD2_DSP_DAP_ADDR,               // address to upload
#ifdef CC_AUD_DOLBY_SUPPORT_MS12v2
    APROC_REG_UPLOAD2_DSP_DOLBY_MIXER_FLAG,               // [0]: Enable upload

    APROC_REG_UPLOAD2_DSP_DOLBY_MIXER_SAMPLERATE,         // Sample Rate of input mc
    APROC_REG_UPLOAD2_DSP_DOLBY_MIXER_CHCONFIG,           // [0-15]: Channel_Config0, [16:31]: Channel_Config1, only for MC
    APROC_REG_UPLOAD2_DSP_DOLBY_MIXER_SAMPLES,            // Number of samples to upload
    APROC_REG_UPLOAD2_DSP_DOLBY_MIXER_ADDR,               // address to upload
#endif
    // do not dump zero data
    APROC_REG_UPLOAD2_NO_ZERO_DATA,
#ifdef CC_AUD_RISCAOUT_SUPPORT
    APROC_REG_MS12_IS_LEVELED,               //0xb
    APROC_REG_MS12_IS_DIAENHANCED,
    APROC_REG_MS12_PCMR_MD_ADDR,
    APROC_REG_RISC_DECCFG_ADDR,
    APROC_REG_MS12_DAP_OPT_BANDGAIN,
    APROC_REG_RISC_DAPIN_ADDR,                     // 0x10
    APROC_REG_RISC_DAPOUT_ADDR,
#endif
    APROC_REG_RISC_DAP_CHNUM,

    APROC_REG_IOBUF_ENC_UPLOAD_RP = 0x1b,
    APROC_REG_UPLOAD2_NUM
} APROC_ASM_UPLOAD2_T;
#endif //CC_AUD_DOLBY_SUPPORT_DAPv2

typedef enum
{
    APROC_REG_IOBUF_UPLOAD0_AOUT_WP,
    APROC_REG_IOBUF_UPLOAD1_AOUT_WP,
    APROC_REG_IOBUF_UPLOAD2_AOUT_WP,
    APROC_REG_IOBUF_UPLOAD3_AOUT_WP,

    APROC_REG_IOBUF_UPLOAD3_AOUT_START,
    APROC_REG_IOBUF_UPLOAD3_AOUT_END,
    APROC_REG_IOBUF_UPLOAD3_AOUT_SIZE,
    APROC_REG_IOBUF_UPLOAD3_AOUT_CH,
}APROC_ASM_ID_UPLOAD3_T;

#ifdef CC_AUD_DOLBY_SUPPORT_MS12B
#ifdef CC_AUD_DOLBY_SUPPORT_MS12v2
typedef enum
{
    APROC_REG_MIXED_MD_DOMINANT_IDX,
    APROC_REG_MIXED_MD_ACMOD,
    APROC_REG_MIXED_MD_LFE,
    APROC_REG_MIXED_MD_PCM_MIXING_INDICATOR,
    APROC_REG_MIXED_MD_PRIMARY_PRESENT,
    APROC_REG_MIXED_MD_LEVELED,
    APROC_REG_MIXED_MD_DIALOGUE_ENHANCED,
}APROC_ASM_MIXED_MD_T;
typedef enum
{
    APROC_REG_MS12_DUAL_MAIN_MIXER_RISC_ENABLE,
    APROC_REG_MS12_SYS_MIXER_RISC_ENABLE,
    APROC_REG_MIXER_DUALMAIN_BYPASS_FLAG,//4~7 bits :0, disable; 1, enable. 0~3 bits:0: dm primary; 1: dm secodery, 2: ui snd;
    APROC_REG_MIXER_SYS_BYPASS_FLAG,//4~7 bits :0, disable; 1, enable. 0~3 bits:0:sys primary; 1:appsnd, 2: syssnd;
    APROC_REG_MIXER_AD_ENABLE_FLAG, //0: disable; 1 enbale;
    APROC_REG_MIXER_DUALMAIN_ENABLE_FLAG, //0: disable; 1 enbale;
    APROC_REG_MIXER_SYS_ENABLE_FLAG, //0: disable; 1 enbale;
    APROC_REG_MIXER_AD_MD_WP,
    APROC_REG_MIXER_AD_MD_RP,
    APROC_REG_MIXER_DUALMAIN_MD_WP,
    APROC_REG_MIXER_DUALMAIN_MD_RP,
    APROC_REG_MIXER_SYS_MD_WP,
    APROC_REG_MIXER_SYS_MD_RP,
    APROC_REG_MIXER_AD_MAIN_DONE,
    APROC_REG_MIXER_AD_ASSOC_DONE,
    APROC_REG_MIXER_AD_MAIN_BLOCK_RP,
    APROC_REG_MIXER_AD_ASSOC_BLOCK_RP,
    APROC_REG_MIXER_DUALMAIN_RISC_ENABLE,
    APROC_REG_MIXER_SYS_RISC_ENABLE
}APROC_ASM_MIXER_CTRL_T;
#endif // CC_AUD_DOLBY_SUPPORT_MS12v2
#ifdef CC_AUD_DOLBY_SUPPORT_MS12v2_FADER
typedef enum
{
    APROC_REG_FADER_ENABLE = 0x0,        // 0:Disable 1:Enable

    //AD mixer
    // Primary
    APROC_REG_AD_FADER_PRIMARY_ATTENUATION = 0x01,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_AD_FADER_PRIMARY_DURATION,      // ramp duration in milliseconds
    APROC_REG_AD_FADER_PRIMARY_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values

    // Secondary
    APROC_REG_AD_FADER_SECONDARY_ATTENUATION = 0x04,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_AD_FADER_SECONDARY_DURATION,      // ramp duration in milliseconds
    APROC_REG_AD_FADER_SECONDARY_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values

    // Secondary
    APROC_REG_AD_FADER_SYSSND_ATTENUATION = 0x07,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_AD_FADER_SYSSND_DURATION,      // ramp duration in milliseconds
    APROC_REG_AD_FADER_SYSSND_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values
    
    //dual main mixer
    // Primary
    APROC_REG_DUAL_MAIN_FADER_PRIMARY_ATTENUATION = 0x0a,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_DUAL_MAIN_FADER_PRIMARY_DURATION,      // ramp duration in milliseconds
    APROC_REG_DUAL_MAIN_FADER_PRIMARY_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values

    // Secondary
    APROC_REG_DUAL_MAIN_FADER_SECONDARY_ATTENUATION = 0x0d,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_DUAL_MAIN_FADER_SECONDARY_DURATION,      // ramp duration in milliseconds
    APROC_REG_DUAL_MAIN_FADER_SECONDARY_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values

    // Secondary
    APROC_REG_DUAL_MAIN_FADER_SYSSND_ATTENUATION = 0x10,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_DUAL_MAIN_FADER_SYSSND_DURATION,      // ramp duration in milliseconds
    APROC_REG_DUAL_MAIN_FADER_SYSSND_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values

    //sys sound mixer
    // Primary
    APROC_REG_SYSSND_FADER_PRIMARY_ATTENUATION = 0x13,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_SYSSND_FADER_PRIMARY_DURATION,      // ramp duration in milliseconds
    APROC_REG_SYSSND_FADER_PRIMARY_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values

    // Secondary
    APROC_REG_SYSSND_FADER_SECONDARY_ATTENUATION = 0x16,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_SYSSND_FADER_SECONDARY_DURATION,      // ramp duration in milliseconds
    APROC_REG_SYSSND_FADER_SECONDARY_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values

    // Secondary
    APROC_REG_SYSSND_FADER_SYSSND_ATTENUATION = 0x19,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_SYSSND_FADER_SYSSND_DURATION,      // ramp duration in milliseconds
    APROC_REG_SYSSND_FADER_SYSSND_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values

    APROC_REG_FADER_NUM
} APROC_ASM_FADER_T;
#else //CC_AUD_DOLBY_SUPPORT_MS12v2_FADER
typedef enum
{
    APROC_REG_DUAL_MAIN_FADER_ENABLE,        // 0:Disable 1:Enable
    // Primary
    APROC_REG_DUAL_MAIN_FADER_PRIMARY_ATTENUATION,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_DUAL_MAIN_FADER_PRIMARY_DURATION,      // ramp duration in milliseconds
    APROC_REG_DUAL_MAIN_FADER_PRIMARY_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values
    APROC_REG_DUAL_MAIN_FADER_PRIMARY_ATTENUATION_STEPS, //
    APROC_REG_DUAL_MAIN_FADER_PRIMARY_CURRENT_GAIN,
    // Secondary
    APROC_REG_DUAL_MAIN_FADER_SECONDARY_ATTENUATION,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_DUAL_MAIN_FADER_SECONDARY_DURATION,      // ramp duration in milliseconds
    APROC_REG_DUAL_MAIN_FADER_SECONDARY_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values
    APROC_REG_DUAL_MAIN_FADER_SECONDARY_ATTENUATION_STEPS, // 0x7fffff
    APROC_REG_DUAL_MAIN_FADER_SECONDARY_CURRENT_GAIN,
    // Mix0
    APROC_REG_DUAL_MAIN_FADER_MIX0_ATTENUATION,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_DUAL_MAIN_FADER_MIX0_DURATION,      // ramp duration in milliseconds
    APROC_REG_DUAL_MAIN_FADER_MIX0_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values
    APROC_REG_DUAL_MAIN_FADER_MIX0_ATTENUATION_STEPS, //
    APROC_REG_DUAL_MAIN_FADER_MIX0_CURRENT_GAIN,
    // Mix1
    APROC_REG_DUAL_MAIN_FADER_MIX1_ATTENUATION,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_DUAL_MAIN_FADER_MIX1_DURATION,      // ramp duration in milliseconds
    APROC_REG_DUAL_MAIN_FADER_MIX1_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values
    APROC_REG_DUAL_MAIN_FADER_MIX1_ATTENUATION_STEPS, //
    APROC_REG_DUAL_MAIN_FADER_MIX1_CURRENT_GAIN,
    // Mix2
    APROC_REG_DUAL_MAIN_FADER_MIX2_ATTENUATION,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_DUAL_MAIN_FADER_MIX2_DURATION,      // ramp duration in milliseconds
    APROC_REG_DUAL_MAIN_FADER_MIX2_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values
    APROC_REG_DUAL_MAIN_FADER_MIX2_ATTENUATION_STEPS, //
    APROC_REG_DUAL_MAIN_FADER_MIX2_CURRENT_GAIN,
    // Mix3
    APROC_REG_DUAL_MAIN_FADER_MIX3_ATTENUATION,   // target attenuation at end of ramp, -96..0dB
    APROC_REG_DUAL_MAIN_FADER_MIX3_DURATION,      // ramp duration in milliseconds
    APROC_REG_DUAL_MAIN_FADER_MIX3_TYPE,          // 0:linear 1:in-cube 2:out-cube ramp on scaler values
    APROC_REG_DUAL_MAIN_FADER_MIX3_ATTENUATION_STEPS, //
    APROC_REG_DUAL_MAIN_FADER_MIX3_CURRENT_GAIN,
    //
    APROC_REG_DUAL_MAIN_FADER_NUM
} APROC_ASM_DUAL_MAIN_FADER_T;
#endif //CC_AUD_DOLBY_SUPPORT_MS12v2_FADER
#endif // CC_AUD_DOLBY_SUPPORT_MS12B

typedef enum
{
    APROC_REG_DECINFO_FORMAT,
    APROC_REG_CLOSE_TRIM_3DB, // 0: open 1: close
    APROC_REG_M3REMAPPING_DISABLE,
    APROC_REG_DEBUG_VERSION,
    APROC_REG_GENERATE_AMIXER_PATTERN0, //0x8a4
    APROC_REG_DEBUG_RCP = 0x5,
    APROC_REG_GENERATE_DETECT_PATTERN0 = 0x6, //0x8a6 1 = after pcmr 5 = aout handler
    APROC_REG_32BANDENABLE = 0x7,
    APROC_REG_32BANDSTART,
    APROC_REG_32BANDEND,
    APROC_REG_CPUPOST_STATUS = 0xa,
    APROC_REG_CPUPOST_AOUT_DBG,
    APROC_REG_BYPASSDCCUT = 0x10,
    APROC_REG_BYPASS_SP_VOLTRIM = 0x11,
    APROC_REG_MEASURE32EQ_BYPASS_OTHER_POST = 0x12,
    APROC_REG_MS12_IS_M5_MODEL,
} APROC_ASM_DECINFO_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_DAP_PARAMETER_T
 * Group: 0x46 ==> APROC_ASM_DAP_PARAMETER
 * Range: 0x8C0 ~ 0x8DF
 * Description:
 *-----------------------------------------------------------*/
typedef enum
{
    APROC_REG_MD_ID_GAINS,
    APROC_REG_MD_ID_SURR_DEC,
    APROC_REG_MD_ID_SURR_VIR,
    APROC_REG_MD_ID_CAL_BOOST,
    APROC_REG_MD_ID_BASS_ENHANCER,
    APROC_REG_MD_ID_GEQ,
    APROC_REG_MD_ID_OPTIMIZER,
    APROC_REG_MD_ID_REGULATOR,
    APROC_REG_MD_ID_VIRTUAL_BASS,
    APROC_REG_MD_ID_MI_STEER,
    APROC_REG_MD_ID_IEQ,
    APROC_REG_MD_ID_LEVELER,
    APROC_REG_MD_ID_DIALOG_ENH
} APROC_ASM_DAP_PARAMETER_T;

#ifdef CC_EARC_SW_BYPASS
/*-----------------------------------------------------------
 * Type: APROC_ASM_M2A_ISR2_T
 * Group: 0x5C ==> APROC_ASM_ID_M2A_ISR2_FLAG
 * Range: 0xB80 ~ 0xB9F
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_M2A_ISR_AOUT3_WP,
}APROC_ASM_M2A_ISR2_FLAG_T;

/*-----------------------------------------------------------
 * Type: APROC_ASM_A2M_ISR2_T
 * Group: 0x5D ==> APROC_ASM_ID_A2M_ISR2_FLAG
 * Range: 0xBA0 ~ 0xBBF
 * Description:
 *-----------------------------------------------------------*/
typedef enum {
    APROC_REG_IOBUF_AOUT3_START,
    APROC_REG_IOBUF_AOUT3_END,
    APROC_REG_IOBUF_AOUT3_SIZE,
    APROC_REG_IOBUF_AOUT3_CH,
    APROC_REG_A2M_ISR_AOUT3_RP,
    APROC_REG_A2M_ISR_AOUT3_DELAY = 0x10,
}APROC_ASM_A2M_ISR2_FLAG_T;
#endif // CC_EARC_SW_BYPASS

#ifdef CC_TEST_PERFORMANCE
typedef enum
{
    APROC_REG_TEST_PERFORMANCE_PMU_TIMER = 0x00, // 0:CCNT only, 1:Timer only, 2:CCNT+D$, 3:CCNT+I$
    APROC_REG_TEST_PERFORMANCE_TARGET, // 0:AD Mixer, 1:PCMR, 2:DAPv2
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_00 = 0x02,
    APROC_REG_TEST_PERFORMANCE_PMNC0_00, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_00, // total cached missed
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_01 = 0x05,
    APROC_REG_TEST_PERFORMANCE_PMNC0_01, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_01, // total cached missed
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_02 = 0x08,
    APROC_REG_TEST_PERFORMANCE_PMNC0_02, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_02, // total cached missed
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_03 = 0x0b,
    APROC_REG_TEST_PERFORMANCE_PMNC0_03, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_03, // total cached missed
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_04 = 0x0e,
    APROC_REG_TEST_PERFORMANCE_PMNC0_04, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_04, // total cached missed
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_05 = 0x11,
    APROC_REG_TEST_PERFORMANCE_PMNC0_05, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_05, // total cached missed
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_06 = 0x14,
    APROC_REG_TEST_PERFORMANCE_PMNC0_06, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_06, // total cached missed
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_07 = 0x17,
    APROC_REG_TEST_PERFORMANCE_PMNC0_07, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_07, // total cached missed
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_08 = 0x1a,
    APROC_REG_TEST_PERFORMANCE_PMNC0_08, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_08, // total cached missed
    APROC_REG_TEST_PERFORMANCE_CCNT_TIMER_09 = 0x1d,
    APROC_REG_TEST_PERFORMANCE_PMNC0_09, // total cache accessed
    APROC_REG_TEST_PERFORMANCE_PMNC1_09, // total cached missed
    APROC_REG_TEST_PERFORMANCE_NUM
} APROC_ASM_TEST_PERFORMANCE_T;
#endif // CC_TEST_PERFORMANCE

typedef enum{
    APROC_REG_SILENCECTRL_SP_GAIN_MODE = 0x0,
    APROC_REG_SILENCECTRL_SP_FIX_THRESHOLD,
    APROC_REG_SILENCECTRL_SP_WAIT_NUM,
    APROC_REG_SILENCECTRL_SP_RELEASE_STEP,
    APROC_REG_SILENCECTRL_SP_ATTACK_STEP,
    APROC_REG_SILENCECTRL_SP_ATTACK_GAIN,
}APORC_ASM_ID_SILENCECTRL_T;

typedef enum {
    MIX_NONE = 0,
    MIX_SRC0_AND_SRC1,
    MIX_SRC0_AND_SRC2,
    MIX_SRC1_AND_SRC2,
    MIX_ALL,// SRC0 + SRC1 +SRC2
}APROC_INPUT_MIX_TYPE_T;

// Test tone define 
typedef enum {
    APROC_TESTTONE_1KHZ0DB = 1,
#ifdef CC_AUD_DOLBY_SUPPORT_MS12
    APROC_TESTTONE_1KHZM20DB,
    APROC_TESTTONE_1KHZM31DB,
    APROC_TESTTONE_2KHZ0DB,
    APROC_TESTTONE_2KHZM20DB,
    APROC_TESTTONE_2KHZM31DB,
#endif // CC_AUD_DOLBY_SUPPORT_MS12
    APROC_TESTTONE_3KHZ0DB,
#ifdef CC_AUD_DOLBY_SUPPORT_MS12
    APROC_TESTTONE_3KHZM20DB,
    APROC_TESTTONE_3KHZM31DB,
    APROC_TESTTONE_1KHZ2KHZ0DB,
#endif // CC_AUD_DOLBY_SUPPORT_MS12
    APROC_TESTTONE_1KHZ3KHZ0DB,
#ifdef CC_AUD_DOLBY_SUPPORT_MS12
    APROC_TESTTONE_2KHZ3KHZ0DB,
#endif // CC_AUD_DOLBY_SUPPORT_MS12
    APROC_TESTTONE_IMPULSE0DB,
    APROC_TESTTONE_NUM
} APROC_AUD_TESTTONE_T;

#endif /* _APROC_COMMON_IF_H_ */
