/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author$
 * $Date$
 * $RCSfile: dmx_api.c,v $
 * $Revision$
 *
 *---------------------------------------------------------------------------*/

/** @file gcpu_hw.c
 *  gcpu driver - hw access
 */

//-----------------------------------------------------------------------------
// Include files
//-----------------------------------------------------------------------------
#include "gcpu.h"
#include "gcpu_dram.h"
#include "x_bim.h"
#include "x_hal_926.h"
#include "x_hal_5381.h"

#if defined(CC_MT5893)
#include "gcpu_iram0_5893.h"
#elif defined(CC_MT5895)
#include "gcpu_iram0_5895.h"
#elif defined(CC_MT5883) || defined(CC_MT5891)
#include "gcpu_iram0_83.h"
#elif defined(CC_MT5886)
#include "gcpu_iram0_5886.h"
#elif defined(CC_MT5863)
#include "gcpu_iram0_5863.h"
#else 
#include "gcpu_iram0_90.h"
#endif
//#include "gcpu_iram1_98.h"
#include "tz_if.h"
#ifndef CC_MTK_LOADER
#ifndef CC_UBOOT
#ifdef CONFIG_MTK_IOMMU
#include <linux/mtk_iommu.h>
#endif
#endif
#endif


#if defined(CC_SUPPORT_STR) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
#include "dmx_drm_drvif.h"
#ifndef CC_TRUSTZONE_SUPPORT
#include "dmx.h"
#endif /* !CC_TRUSTZONE_SUPPORT */
#endif

#ifndef CC_MTK_LOADER
#ifdef __KERNEL__
#include <linux/semaphore.h>
#endif
#endif
//-----------------------------------------------------------------------------
// Configurations
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// Constant definitions
//-----------------------------------------------------------------------------
#define GCPU_TIMEOUT        1000

//#define GCPU_FLUSH_ALL_IO_BUF
//-----------------------------------------------------------------------------
// Type definitions
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// Macro definitions
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// Static variables
//-----------------------------------------------------------------------------
#ifndef CC_MTK_LOADER
static HANDLE_T _hGcpuHwSema = NULL_HANDLE;
static HANDLE_T _hGcpuIrqSema = NULL_HANDLE;
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT)
static GCPU_TZ_PARAM_T *_prGcpuTzParam = NULL;
static UINT32 _u4GcpuTzParamSize;
static GCPU_HW_CMD_T *_prGcpuHwCmd = NULL;
static UINT32 _u4GcpuHwCmdSize;
#endif /* (CC_TRUSTZONE_SUPPORT && !CC_UBOOT) */
#endif /* !CC_MTK_LOADER */
static BOOL fgPageFault = FALSE;
static UINT32 _u4Mode = 0;

#if defined(CC_SUPPORT_STR) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
#ifndef CC_TRUSTZONE_SUPPORT
static UINT32 _arSecureKeyHoles[GCPU_SECURESLOT_NUM];
static BOOL _GCPU_Hw_SaveSecureKeys(UINT32 u4SlotPtr, UINT32 u4Key);
#endif
static BOOL _GCPU_Hw_RestoreSecureKeys(void);
#endif
//-----------------------------------------------------------------------------
// Extern variables
//-----------------------------------------------------------------------------
#ifdef __KERNEL__
extern struct semaphore aes_api;
extern struct semaphore aes_sema;
extern BOOL fgNativeAESISR;
#endif

//-----------------------------------------------------------------------------
// Extern functions
//-----------------------------------------------------------------------------
extern int x_kmem_sync_table(void *ptr,size_t size);

//-----------------------------------------------------------------------------
// Static functions
//-----------------------------------------------------------------------------
#ifdef __USERDRV__
int x_kmem_sync_table(void *ptr,size_t size)
{
 //TBD
}
#endif

static BOOL _Gcpu_Hw_GetRamCode(BYTE **ppbRamCode, UINT32 *pu4RamCodeSize, BYTE **ppbTrapping, UINT32 *pu4TrapSize)
{
    if ((ppbRamCode == NULL) || (ppbTrapping == NULL) || (pu4RamCodeSize == NULL) || (pu4TrapSize == NULL))
    {
        return FALSE;
    }

    *ppbRamCode = (BYTE*) GCPU_IRAM0_CODE;
    *ppbTrapping = (BYTE*) GCPU_IRAM0_TRAPPING;

    *pu4RamCodeSize = sizeof(GCPU_IRAM0_CODE);
    *pu4TrapSize = sizeof(GCPU_IRAM0_TRAPPING);

#if defined(CC_MT5863)
    if(IS_IC_5863_ES1())
    {
	    *ppbRamCode = (BYTE*) GCPU_IRAM0_CODE_ES1;
	    *ppbTrapping = (BYTE*) GCPU_IRAM0_TRAPPING_ES1;

	    *pu4RamCodeSize = sizeof(GCPU_IRAM0_CODE_ES1);
	    *pu4TrapSize = sizeof(GCPU_IRAM0_TRAPPING_ES1);
    }
#endif
    
//lemur plus use different ram code.
#if defined(CC_MT5882)
    if(IS_IC_5885())
    {
        *ppbRamCode = (BYTE*) GCPU_IRAM0_CODE_5885;
        *ppbTrapping = (BYTE*) GCPU_IRAM0_TRAPPING_5885;
        
        *pu4RamCodeSize = sizeof(GCPU_IRAM0_CODE_5885);
        *pu4TrapSize = sizeof(GCPU_IRAM0_TRAPPING_5885);
    }
#endif 
    
    return TRUE;
}

static BOOL _Gcpu_Hw_SetResetParam(GCPU_TZ_PARAM_T *prTzParam)
{
    static UPTR u4PhyDramCodeAddr = 0;
    static UPTR u4PhyRamCodeAddr = 0;
    static UPTR u4PhyTrapAddr = 0;
    static UINT32 u4RamCodeSize = 0, u4TrapSize = 0;
    BYTE *pbRamDstCode = NULL, *pbTrappingDst = NULL;
    BYTE *pbRamSrcCode = NULL, *pbTrappingSrc = NULL;
    BYTE *pbDramCodeAddr = NULL;
    BOOL fgInitRam = FALSE, fgInitDram = FALSE;
    BOOL fgRet = TRUE;

    if (prTzParam == NULL)
    {
        return FALSE;
    }

    x_memset((void *)prTzParam, 0, sizeof(GCPU_TZ_PARAM_T)); 
    if(_u4Mode == 0)
    {
        fgInitRam = TRUE;
    }
    else
    {
        fgInitDram = TRUE;
    }
    
    prTzParam->u4InitRam = (UINT32)fgInitRam;
    prTzParam->u4InitDram = (UINT32)fgInitDram;

    if (fgInitRam)
    {
        if ((0 == u4PhyRamCodeAddr) && (0 == u4PhyTrapAddr))
        {
            fgRet = _Gcpu_Hw_GetRamCode((BYTE **)&pbRamSrcCode, (UINT32 *)&u4RamCodeSize,
                                        (BYTE **)&pbTrappingSrc, (UINT32 *)&u4TrapSize);
            
            if (!fgRet)
            {
                LOG(3, "Can't get ram and grap code\n");
                goto lbExit1;
            }

#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
            if (u4RamCodeSize > 0)
            {
                u4PhyRamCodeAddr = BSP_AllocAlignedDmaMemory(TZ_CACHE_ALIGN(u4RamCodeSize), GCPU_FIFO_ALIGNMENT);
                if (u4PhyRamCodeAddr == 0)
                {
                    fgRet = FALSE;
                    LOG(3, "Can't allocate memory for ram code\n");
                    goto lbExit1;
                }
                
                pbRamDstCode = (BYTE *)VIRTUAL(u4PhyRamCodeAddr);
                x_memcpy((void *)pbRamDstCode, (void *)pbRamSrcCode, u4RamCodeSize); 
            
                HalFlushInvalidateDCacheMultipleLine((UPTR)pbRamDstCode, TZ_CACHE_ALIGN(u4RamCodeSize));
            }

            if (u4TrapSize > 0)
            {
                u4PhyTrapAddr = BSP_AllocAlignedDmaMemory(TZ_CACHE_ALIGN(u4TrapSize), GCPU_FIFO_ALIGNMENT);
                if (u4PhyTrapAddr == 0)
                {
                    fgRet = FALSE;
                    LOG(3, "Can't allocate memory for trapping\n");
                    goto lbExit1;
                }
                
                pbTrappingDst = (BYTE *)VIRTUAL(u4PhyTrapAddr);
                x_memcpy((void *)pbTrappingDst, (void *)pbTrappingSrc, u4TrapSize);

                HalFlushInvalidateDCacheMultipleLine((UPTR)pbTrappingDst, TZ_CACHE_ALIGN(u4TrapSize));
            }
#else /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT && !CC_MTK_LOADER) */
            u4PhyRamCodeAddr = (UPTR)pbRamSrcCode;
            u4PhyTrapAddr = (UPTR)pbTrappingSrc;
#endif /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT && !CC_MTK_LOADER) */
        }

        prTzParam->u4RamCodeAddr = u4PhyRamCodeAddr; 
        prTzParam->u4TrappingAddr = u4PhyTrapAddr ; 
        prTzParam->u4RamCodeSize = u4RamCodeSize / 4;
        prTzParam->u4TrapSize = u4TrapSize / 4;
    }
    
#ifndef CC_MTK_LOADER
    if (fgInitDram)
    {
        if (u4PhyDramCodeAddr == 0)
        { 
            u4PhyDramCodeAddr = BSP_AllocAlignedDmaMemory(GCPU_DRAM_LEN, GCPU_FIFO_ALIGNMENT);
            if (u4PhyDramCodeAddr == 0)
            {
                fgRet = FALSE;
                LOG(3, "Can't allocate memory for Dram code\n");
            }
        }
       
        if (fgRet)
        {
            prTzParam->u4PhyDramCodeAddr = u4PhyDramCodeAddr;
            pbDramCodeAddr = (BYTE *)VIRTUAL(u4PhyDramCodeAddr);
            x_memcpy((void *)pbDramCodeAddr, (void *)GCPU_DRAM_CODE, GCPU_DRAM_LEN);
            HalFlushInvalidateDCacheMultipleLine((UPTR)pbDramCodeAddr, GCPU_DRAM_LEN);
        }
    }
#endif
    UNUSED(u4PhyDramCodeAddr);
    UNUSED(pbDramCodeAddr);
    UNUSED(GCPU_DRAM_CODE);
    UNUSED(u4PhyRamCodeAddr);
    UNUSED(u4PhyTrapAddr);
    UNUSED(pbTrappingDst);
    UNUSED(pbRamDstCode);

    return TRUE;

lbExit1:

#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
    if (u4PhyTrapAddr)
    {
        VERIFY(BSP_FreeAlignedDmaMemory(u4PhyTrapAddr));
        u4PhyTrapAddr = 0;
    }

    if (u4PhyRamCodeAddr)
    {
        VERIFY(BSP_FreeAlignedDmaMemory(u4PhyRamCodeAddr));
        u4PhyRamCodeAddr = 0;
    }

    if (u4PhyDramCodeAddr)
    {
        VERIFY(BSP_FreeAlignedDmaMemory(u4PhyDramCodeAddr));
        u4PhyDramCodeAddr = 0;
    }
#endif

    return fgRet;
}

//-----------------------------------------------------------------------------
/** _GcpuHWReset
 *  Reset GCPU HW
 */
//-----------------------------------------------------------------------------
#if !defined(CC_TRUSTZONE_SUPPORT) || defined(CC_UBOOT) || defined(CC_MTK_LOADER) 
static INT32 _Gcpu_Hw_Reset(GCPU_TZ_PARAM_T *prTzParam)
{
    UINT32 u4Value = 0;
    UINT32 *pu4RamCode = NULL, *pu4Trapping = NULL;
    UINT32 u4RamCodeSize = 0, u4TrapSize = 0;
    UINT64 u4PhyDramCodeAddr = 0;
    BOOL fgInitRam, fgInitDram;
    UINT32 i;

    if (prTzParam == NULL)
    {
        return E_GCPU_PARAM_WRONG;
    }

	LOG(3, "hw reset\n");
    pu4RamCode = (UINT32 *)(UPTR)VIRTUAL(prTzParam->u4RamCodeAddr);
    pu4Trapping = (UINT32 *)(UPTR)VIRTUAL(prTzParam->u4TrappingAddr);
    u4RamCodeSize = prTzParam->u4RamCodeSize;
    u4TrapSize = prTzParam->u4TrapSize;
    u4PhyDramCodeAddr = prTzParam->u4PhyDramCodeAddr;
    fgInitRam = (BOOL)prTzParam->u4InitRam;
    fgInitDram = (BOOL)prTzParam->u4InitDram;

    u4Value = GCPUCMD_READ32(GCPU_REG_CTL);
    u4Value &= ~(0x7);
    GCPUCMD_WRITE32(GCPU_REG_CTL, u4Value);
    u4Value &= ~(0x8);
    GCPUCMD_WRITE32(GCPU_REG_CTL, u4Value);
	
#if defined(CC_MT5863) || defined(CC_MT5893) || defined(CC_MT5895)
    u4Value &= ~(0x10);
	GCPUCMD_WRITE32(GCPU_REG_CTL, u4Value);

    u4Value |= 0x1F;
	GCPUCMD_WRITE32(GCPU_REG_CTL, u4Value);
#else
    u4Value |= 0xF;
    GCPUCMD_WRITE32(GCPU_REG_CTL, u4Value);
#endif 

	//Init Ram Code
    if ((fgInitRam) && 
        (pu4RamCode != NULL) && (u4RamCodeSize != 0))
    {
        // clear
        GCPUCMD_WRITE32(GCPU_REG_MEM_ADDR, 0x80002000);
        for (i = 0; i < 1024; i++)
        {
            GCPUCMD_WRITE32(GCPU_REG_MEM_DATA, 0);
        }
    
        GCPUCMD_WRITE32(GCPU_REG_MEM_ADDR, 0x80002000);
        for (i = 0; i < u4RamCodeSize; i++)
        {
            GCPUCMD_WRITE32(GCPU_REG_MEM_DATA, *(pu4RamCode + i));
        }
    }

    if ((fgInitRam) && 
        (pu4Trapping != NULL) && (u4TrapSize != 0))
    {
        // trapping
        for (i = 0; i < u4TrapSize; i++)
        {
            GCPUCMD_WRITE32((GCPU_REG_TRAP_START + i), *(pu4Trapping + i));
        }
    }

#ifndef CC_MTK_LOADER
    if ((fgInitDram) && (u4PhyDramCodeAddr != 0))
    {
        //Init Dram Code
        GCPUCMD_WRITE32(GCPU_REG_MSC, GCPUCMD_READ32(GCPU_REG_MSC) | (1 << 12));
        GCPUCMD_WRITE32(GCPU_REG_DRAM_INST_BASE, u4PhyDramCodeAddr);
    }
#else
    UNUSED(fgInitDram);
    UNUSED(u4PhyDramCodeAddr );
#endif

#ifdef CC_MT5895
    GCPUCMD_WRITE32(GCPU_RSA_MMPRO_R1_CON, 1);
    GCPUCMD_WRITE32(GCPU_RSA_MMPRO_PS_CON, 0);
#endif

    return S_GCPU_OK;
}
#endif  /* (!CC_TRUSTZONE_SUPPORT || CC_UBOOT || CC_MTK_LOADER) */


void GCPU_HW_LOCK(void)
{
#ifndef CC_MTK_LOADER
    #ifdef __KERNEL__
    if(fgNativeAESISR)
    {
        down(&aes_api);
    }
    else
    #endif
    {
        VERIFY(x_sema_lock(_hGcpuHwSema, X_SEMA_OPTION_WAIT) == OSR_OK);
    }
#endif
}


void GCPU_HW_UNLOCK(void)
{
#ifndef CC_MTK_LOADER
    #ifdef __KERNEL__
    if(fgNativeAESISR)
    {
        up(&aes_api);
    }
    else
    #endif
    {
        VERIFY(x_sema_unlock(_hGcpuHwSema) == OSR_OK);
    }
#endif
}


static void GCPU_IRQ_LOCK(void)
{
#ifndef CC_MTK_LOADER
#ifdef __KERNEL__
#if !defined(CC_TRUSTZONE_SUPPORT) || defined(CC_UBOOT)
    GCPU_TZ_PARAM_T rTzParam;
#endif

    if(fgNativeAESISR)
    {
        if(down_timeout(&aes_sema, GCPU_TIMEOUT/5) != 0)    // 1 tick = 5 ms
        {
            LOG(3, "Timeout\n");
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT)
            if (_Gcpu_Hw_SetResetParam(_prGcpuTzParam))
            {
                TZ_GCPU_Hw_Reset(_prGcpuTzParam, _u4GcpuTzParamSize);
            }
            else
            {
                LOG(3, "GCPU invalid reset parameters\n");
            }
#else  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT) */
            if (_Gcpu_Hw_SetResetParam(&rTzParam))
            {
                _Gcpu_Hw_Reset(&rTzParam);
            }
            else
            {
                LOG(3, "GCPU invalid reset parameters\n");
            }
#endif  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT) */
        }
    }
    else
#endif // __KERNEL__
    {
        VERIFY(x_sema_lock(_hGcpuIrqSema, X_SEMA_OPTION_WAIT) == OSR_OK);
        /*
        INT32 i4Ret;
        i4Ret = x_sema_lock_timeout(_hGcpuIrqSema, GCPU_TIMEOUT);
        if(i4Ret != OSR_OK)
        {
            if(i4Ret == OSR_TIMEOUT)
            {
                LOG(3, "Timeout\n");
                _Gcpu_Hw_Reset();
            }
            else
            {
                ASSERT(0);
            }
        }
        */
    }

#else
    while((GCPUCMD_READ32(GCPU_REG_INT_SET) & 0x1) == 0x0);
    GCPUCMD_WRITE32(GCPU_REG_INT_CLR, GCPUCMD_READ32(GCPU_REG_INT_CLR));
    GCPUCMD_WRITE32(GCPU_REG_INT_EN, 0);
#endif //CC_MTK_LOADER
}


#ifndef CC_MTK_LOADER
static void GCPU_IRQ_UNLOCK(void)
{
    VERIFY(x_sema_unlock(_hGcpuIrqSema) == OSR_OK);
}
#endif

//-----------------------------------------------------------------------------
/** _GCPU_IrqHandle()
 *  @param u2Vector: The IRQ vector, must be VECTOR_UP0
 */
//-----------------------------------------------------------------------------
#ifndef CC_MTK_LOADER
static VOID _Gcpu_IrqHandle(UINT16 u2Vector)
{
#if !defined(CC_TRUSTZONE_SUPPORT) || defined(CC_UBOOT)
    GCPU_TZ_PARAM_T rTzParam;
#endif
    ASSERT(u2Vector == VECTOR_UP0);
    
#if !defined(CC_MT5886) && !defined(CC_MT5863) && !defined(CC_MT5893) && !defined(CC_MT5895)
    if (!BIM_IsIrqPending(VECTOR_UP0))
    {
        LOG(3, "Spurious gcpu global interrupt!\n");
        return;
    }
#endif

#if !defined(__linux__)
    // Check if it's aes interrupt
    while (BIM_IsIrqPending(VECTOR_UP0))
#endif
    {
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT)
        if (_Gcpu_Hw_SetResetParam(_prGcpuTzParam))
        {
            TZ_GCPU_IrqHandle(_prGcpuTzParam, _u4GcpuTzParamSize);

            if (_prGcpuTzParam->u4ReturnedValue != 0)
            {
                LOG(0, "invalid command\n");
            }
            else
            {
                GCPU_IRQ_UNLOCK();
            }
 #ifndef CC_NO_BIM_INTR           
            VERIFY(BIM_ClearIrq(VECTOR_UP0));
 #endif
        }
        else
        {
            LOG(3, "GCPU invalid reset parameters\n");
            // Clear interrupt
            TZ_GCPU_ISR_ClearIRQ();
            VERIFY(BIM_ClearIrq(VECTOR_UP0));
            GCPU_IRQ_UNLOCK();
        }
#else  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT) */
        if (_Gcpu_Hw_SetResetParam(&rTzParam))
        {
            if(GCPUCMD_READ32(GCPU_REG_INT_CLR) & 0x80000000)
            {
                LOG(0, "invalid command\n");
                _Gcpu_Hw_Reset(&rTzParam);
                #ifndef CC_NO_BIM_INTR 
                VERIFY(BIM_ClearIrq(VECTOR_UP0));
                #endif
                // Clear/Enable GCPU Interrupt
                GCPUCMD_WRITE32(GCPU_REG_INT_CLR, GCPUCMD_READ32(GCPU_REG_INT_CLR));
                GCPUCMD_WRITE32(GCPU_REG_INT_EN, GCPU_INT_MASK);

                // GCPU PC
                GCPUCMD_WRITE32(GCPU_REG_PC_CTL, 0x0);
            }
            else
            {
                // Clear interrupt
                GCPUCMD_WRITE32(GCPU_REG_INT_CLR, GCPUCMD_READ32(GCPU_REG_INT_CLR));
                GCPUCMD_WRITE32(GCPU_REG_INT_EN, 0);
                #ifndef CC_NO_BIM_INTR 
                VERIFY(BIM_ClearIrq(VECTOR_UP0));
                #endif
                GCPU_IRQ_UNLOCK();
            }
        }
        else
        {
            LOG(3, "GCPU invalid reset parameters\n");
            // Clear interrupt
            GCPUCMD_WRITE32(GCPU_REG_INT_CLR, GCPUCMD_READ32(GCPU_REG_INT_CLR));
            GCPUCMD_WRITE32(GCPU_REG_INT_EN, 0);
            #ifndef CC_NO_BIM_INTR 
            VERIFY(BIM_ClearIrq(VECTOR_UP0));
            #endif
            GCPU_IRQ_UNLOCK();
        }
#endif  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT) */
    }
}
#endif

#ifndef CC_MTK_LOADER
static void _Gcpu_IOMMU_IrqHandle(UINT16 u2Vector)
{
#if !defined(CC_TRUSTZONE_SUPPORT) || defined(CC_UBOOT)
    GCPU_TZ_PARAM_T rTzParam;
#endif

    ASSERT(u2Vector == VECTOR_MMU_GCPU);

#if !defined(CC_MT5886) && !defined(CC_MT5863) && !defined(CC_MT5893) && !defined(CC_MT5895)
    if (!BIM_IsIrqPending(VECTOR_MMU_GCPU))
    {
        LOG(3, "Spurious gcpu iommu global interrupt!\n");
        return;
    }
#endif

#if 0
	{
		UINT32 u4Reg;

		printf("IOMMU PAGE FAULT.\n");

		u4Reg = 0x00100A0A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);
		printf("write CFG4 0x%08x, read CFG8 0x%08x\n", u4Reg, IOMMU_GCPU_READ32(REG_IOMMU_CFG8));

		u4Reg = 0x0010090A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);
		printf("write CFG4 0x%08x, read CFG8 0x%08x\n", u4Reg, IOMMU_GCPU_READ32(REG_IOMMU_CFG8));

		u4Reg = 0x0010080A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);
		printf("write CFG4 0x%08x, read CFG8 0x%08x\n", u4Reg, IOMMU_GCPU_READ32(REG_IOMMU_CFG8));

		u4Reg = 0x00100c0A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);
		printf("write CFG4 0x%08x, read CFG8 0x%08x\n", u4Reg, IOMMU_GCPU_READ32(REG_IOMMU_CFG8));

		u4Reg = 0x0010012A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010112A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010212A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010312A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010412A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010512A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010A12A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010B12A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010C12A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010D12A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010E12A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));

		u4Reg = 0x0010F12A;
    	IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, u4Reg);		
		printf("write CFG4 0x%08x, read CFG6/7/8/13/14 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", u4Reg, 
								IOMMU_GCPU_READ32(REG_IOMMU_CFG6),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG7),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG8),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG13),
								IOMMU_GCPU_READ32(REG_IOMMU_CFG14));
		
	}
#endif

#if !defined(__linux__)
    // Check if it's aes interrupt
    while (BIM_IsIrqPending(VECTOR_MMU_GCPU))
#endif
    {
        fgPageFault = TRUE;
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT)
        if (_Gcpu_Hw_SetResetParam(_prGcpuTzParam))
        {
            TZ_GCPU_IOMMU_IrqHandle(_prGcpuTzParam, _u4GcpuTzParamSize);
        }
        else
        {
            LOG(3, "GCPU invalid reset parameters\n");
            TZ_GCPU_ISR_ClearIommuIRQ();
        }
        #ifndef CC_NO_BIM_INTR 
        VERIFY(BIM_ClearIrq(u2Vector));
        #endif
        GCPU_IRQ_UNLOCK();
#else  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT) */
        if (_Gcpu_Hw_SetResetParam(&rTzParam))
        {
            _Gcpu_Hw_Reset(&rTzParam);
        }
        else
        {
            LOG(3, "GCPU invalid reset parameters\n");
        }
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, IOMMU_GCPU_READ32(REG_IOMMU_CFG4) | 0x06000005);
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, IOMMU_GCPU_READ32(REG_IOMMU_CFG4) & ~(0x0610000F));
        #ifndef CC_NO_BIM_INTR 
        VERIFY(BIM_ClearIrq(u2Vector));
        #endif

        GCPU_IRQ_UNLOCK();
#endif  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT) */
    }
}
#endif

//-----------------------------------------------------------------------------
/** _GCPU_InitIsr
*/
//-----------------------------------------------------------------------------
static void _Gcpu_InitIsr(void)
{
#ifndef CC_MTK_LOADER
    static BOOL _fgInit = FALSE;
    x_os_isr_fct pfnOldIsr;

    if(!_fgInit)
    {
        #ifdef __KERNEL__
        if(!fgNativeAESISR) // only initial ISR when native AES did not do it
        #endif
        {
            VERIFY(OSR_OK == x_sema_create(&_hGcpuIrqSema,
                X_SEMA_TYPE_BINARY, X_SEMA_STATE_LOCK));

            // GCPU interrupt
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT)
            TZ_GCPU_ClearIRQ();
#else
            GCPUCMD_WRITE32(GCPU_REG_INT_CLR, GCPUCMD_READ32(GCPU_REG_INT_CLR));
            GCPUCMD_WRITE32(GCPU_REG_INT_EN, 0);
#endif
            #ifndef CC_NO_BIM_INTR 
            BIM_ClearIrq(VECTOR_UP0);
            #endif
            if (x_reg_isr(VECTOR_UP0, _Gcpu_IrqHandle, &pfnOldIsr) != OSR_OK)
            {
                LOG(3, "Error: fail to register GCPU ISR!\n");
            }

            // GCPU IOMMU interrupt
            #ifndef CC_NO_BIM_INTR 
            BIM_ClearIrq(VECTOR_MMU_GCPU);
            #endif 
            if (x_reg_isr(VECTOR_MMU_GCPU, _Gcpu_IOMMU_IrqHandle, &pfnOldIsr) != OSR_OK)
            {
                LOG(3, "Error: fail to register GCPU IOMMU ISR!\n");
            }
        }

        UNUSED(pfnOldIsr);

        _fgInit = TRUE;
    }
    else
    {
        #ifdef __KERNEL__
        if(!fgNativeAESISR) // only initial ISR when native AES did not do it
        #endif
        {
            INT32 i4Ret;
            // Make sure the semaphore is reset to the locked state.
            i4Ret = x_sema_lock(_hGcpuIrqSema, X_SEMA_OPTION_NOWAIT);
            if (i4Ret == OSR_OK)
            {
                LOG(6, "Reset GCPU semaphore to the Locked state!\n");
            }
            else if (i4Ret == OSR_WOULD_BLOCK)
            {
                LOG(6, "GCPU semaphore is in the Locked state!\n");
            }
            else
            {
                LOG(6, "%d: Semaphore API failed!\n", __LINE__);
            }
        }
    }
#endif
}

static INT32 _GCPU_Hw_RunCmd(GCPU_HW_CMD_T *prHwCmd)
{
    UINT32 i;
    INT32 i4Result = S_GCPU_OK;
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd\n", __FUNCTION__, __LINE__);
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
    *_prGcpuHwCmd = *prHwCmd;
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd\n", __FUNCTION__, __LINE__);
    if (!TZ_GCPU_Hw_CmdRun(_prGcpuHwCmd, _u4GcpuHwCmdSize))
    {
        LOG(3, "%s - TZ run error\n", __FUNCTION__);
        i4Result = E_GCPU_CMD_FAIL;
        goto lbExit1;
    }
#else
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd\n", __FUNCTION__, __LINE__);
    // Setup Parameter
    for(i = 1; i < GCPU_PARAM_NUM; i++)
    {
        GCPUCMD_WRITE32(GCPU_REG_MEM_CMD + i, prHwCmd->u4Param[i]);
    }

    // Clear/Enable GCPU Interrupt
    GCPUCMD_WRITE32(GCPU_REG_INT_CLR, GCPUCMD_READ32(GCPU_REG_INT_CLR));
    GCPUCMD_WRITE32(GCPU_REG_INT_EN, GCPU_INT_MASK);

    // GCPU Decryption Mode
    GCPUCMD_WRITE32(GCPU_REG_MEM_CMD, prHwCmd->u4Param[0]);

    // GCPU PC
    GCPUCMD_WRITE32(GCPU_REG_PC_CTL, 0x0);
#endif
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd\n", __FUNCTION__, __LINE__);
    GCPU_IRQ_LOCK();
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd\n", __FUNCTION__, __LINE__);    
    if(fgPageFault == TRUE)
    {
        LOG(3, "GCPU IOMMU has page fault!\n");
        fgPageFault = FALSE;
        i4Result = E_GCPU_PAGE_FAULT;
        goto lbExit1;
    }
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd\n", __FUNCTION__, __LINE__);
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
    LOG(2, "%s(%d), TZ_GCPU_Hw_CmdReturn\n", __FUNCTION__, __LINE__);

    if (!TZ_GCPU_Hw_CmdReturn(_prGcpuHwCmd, _u4GcpuHwCmdSize))
    {
        LOG(3, "%s - TZ return error\n", __FUNCTION__);
        i4Result = E_GCPU_CMD_FAIL;
        goto lbExit1;
    }

    *prHwCmd = *_prGcpuHwCmd;
#else  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT && !CC_MTK_LOADER) */
    // read back param 0 - 31
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd\n", __FUNCTION__, __LINE__);
    for(i = 0; i < 32; i++)
    {
        prHwCmd->u4Param[i] = GCPUCMD_READ32(GCPU_REG_MEM_CMD + i);
    }

    // read back param 32 - 47
    for(i = GCPU_PARAM_RET_PTR; i < GCPU_PARAM_RET_PTR + GCPU_PARAM_RET_NUM; i++)
    {
        prHwCmd->u4Param[i] = GCPUCMD_READ32(GCPU_REG_MEM_CMD + i);
    }
#endif  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT && !CC_MTK_LOADER) */
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd\n", __FUNCTION__, __LINE__);
    UNUSED(i);

lbExit1:
    return i4Result;
}

//-----------------------------------------------------------------------------
// Inter-file functions
//-----------------------------------------------------------------------------
INT32 _GCPU_EnableIOMMU(UPTR u4Src1Start, UPTR u4Src1End, UPTR u4Src2Start, UPTR u4Src2End, UINT32 u4MmuTblAddr)
{
    INT32 i4Ret = S_GCPU_OK;

#ifndef CC_MTK_LOADER	 
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT)
#else
	#if defined(CONFIG_64BIT)
	UINT32 u4Reg = 0;
    UINT8 u1ST1, u1SE1, u1ST2, u1SE2; 
	#endif
#endif
    UINT32 u4TmpMmuTblAddr;

    LOG(2, "%s(%d), u4Src1Start:0x%llx, u4Src1End:0x%llx\n",
            __FUNCTION__, __LINE__, u4Src1Start, u4Src1End);
    LOG(2, "%s(%d), u4Src2Start:0x%llx, u4Src2End:0x%llx, u4MmuTblAddr:0x%x\n",
            __FUNCTION__, __LINE__, u4Src2Start, u4Src2End, u4MmuTblAddr);
    if(u4MmuTblAddr == 0)
    {
        u4TmpMmuTblAddr = HalGetMMUTableAddress();    
    }
    else
    {
        u4TmpMmuTblAddr = u4MmuTblAddr;
    }

#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT)
	//Printf("TZ _GCPU_EnableIOMMU\n");
    x_memset((void *)_prGcpuTzParam, 0, sizeof(GCPU_TZ_PARAM_T));

    #if !defined(CONFIG_64BIT)         //32bit iommu
    LOG(2, "%s(%d)\n", __FUNCTION__, __LINE__);
	_prGcpuTzParam->eIommuMode = IOMMU_32BIT;
    #elif defined(CONFIG_ARM64_64K_PAGES) //64bit-64k iommu
    if(u4MmuTblAddr != 0)
    {
        LOG(2, "%s(%d)\n", __FUNCTION__, __LINE__);
	    _prGcpuTzParam->eIommuMode = IOMMU_32BIT;
    }
    else
    {
        LOG(2, "%s(%d)\n", __FUNCTION__, __LINE__);
	_prGcpuTzParam->eIommuMode = IOMMU_39BIT_64K;
    }
	#else  //64bit-4k iommu
    if(u4MmuTblAddr == 0)
    {
        LOG(2, "%s(%d)\n", __FUNCTION__, __LINE__);
	_prGcpuTzParam->eIommuMode = IOMMU_39BIT_4K;
    }
    else
    {
        LOG(2, "%s(%d)\n", __FUNCTION__, __LINE__);
        _prGcpuTzParam->eIommuMode = IOMMU_32BIT;
    }
	#endif
		
    _prGcpuTzParam->u4MmuSrc1Start = u4Src1Start;
    _prGcpuTzParam->u4MmuSrc1End = u4Src1End;
    _prGcpuTzParam->u4MmuSrc2Start = u4Src2Start;
    _prGcpuTzParam->u4MmuSrc2End = u4Src2End;
    _prGcpuTzParam->u4MmuTblAddr = u4TmpMmuTblAddr;

    LOG(2, "%s(%d), u4MmuSrc1Start:0x%llx, u4MmuSrc1End:0x%llx, u4MmuTblAddr:0x%llx, eIommuMode:%d.\n",
            __FUNCTION__, __LINE__, _prGcpuTzParam->u4MmuSrc1Start, _prGcpuTzParam->u4MmuSrc1End, _prGcpuTzParam->u4MmuTblAddr, _prGcpuTzParam->eIommuMode);

    if (!TZ_GCPU_EnableIOMMU(_prGcpuTzParam, _u4GcpuTzParamSize))
    {
        LOG(3, "Enable GCPI fails\n");
        i4Ret = E_GCPU_FAIL;
    }
#else
	//Printf("_GCPU_EnableIOMMU\n");

   #if defined(CONFIG_64BIT)
    //keep 32~38bit
    u1ST1 = (UINT8)(u4Src1Start >> 32) & 0x7F;
    u1SE1 = (UINT8)(u4Src1End >> 32) & 0x7F;
    u1ST2 = (UINT8)(u4Src2Start >> 32) & 0x7F;
    u1SE2 = (UINT8)(u4Src2End >> 32) & 0x7F;
    #endif	

    // setup IOMMU
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, 0x0603000A);

    #if !defined(CONFIG_64BIT)         //32bit iommu
	LOG(3, "_GCPU_EnableIOMMU 32bit\n");
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, 0x0010000A);
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG0, 0xFE | (0x01 << 0));
    #elif defined(CONFIG_ARM64_64K_PAGES) //64bit-64k iommu
	LOG(3, "_GCPU_EnableIOMMU 64bit-64k\n");
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, 0x0030002A);
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG0, 0xFF | (0x02 << 8));
    #else  //64bit-4k iommu
    LOG(3, "_GCPU_EnableIOMMU 64bit-4k\n");

    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, 0x0030002A);
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG0, 0xFF | (0x03 << 8));
    #endif
    
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG1, u4TmpMmuTblAddr);
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG2, 0x00130011);
    #if !defined(CONFIG_64BIT)         //32bit iommu
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG9, (u4Src1Start & 0xfffff000) | 0x3);
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFGA, (u4Src1End - 1) & 0xfffff000);
    #else
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG9, ((UINT32)u4Src1Start & 0xfffff000) | 0x3);
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFGA, ((UINT32)u4Src1End - 1) & 0xfffff000);
    #endif

    if(u4Src2Start == 0 || u4Src2End == 0)
    {
        #if !defined(CONFIG_64BIT)
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFGB, (u4Src1Start & 0xfffff000) | 0x1);
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFGC, (u4Src1End - 1) & 0xfffff000);
        #else
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFGB, ((UINT32)u4Src1Start & 0xfffff000) | 0x1);
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFGC, ((UINT32)u4Src1End - 1) & 0xfffff000);
        
        u4Reg = (u1ST1 << 24) | (u1SE1 << 16) | (u1ST1 << 8) | u1SE1;        
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFG11, u4Reg);
        #endif
    }
    else
    {
        #if !defined(CONFIG_64BIT)
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFGB, (u4Src2Start & 0xfffff000) | 0x1);
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFGC, (u4Src2End - 1) & 0xfffff000);
        #else
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFGB, ((UINT32)u4Src2Start & 0xfffff000) | 0x1);
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFGC, ((UINT32)u4Src2End - 1) & 0xfffff000);        

        u4Reg = (u1ST1 << 24) | (u1SE1 << 16) | (u1ST2 << 8) | u1SE2;  
        IOMMU_GCPU_WRITE32(REG_IOMMU_CFG11, u4Reg);
        #endif
    }

    //fire IOMMU cache
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG4, IOMMU_GCPU_READ32(REG_IOMMU_CFG4) | (1U << 31));
    while((IOMMU_GCPU_READ32(REG_IOMMU_CFG8) & (1 << 29)) != 0);
#endif
#endif  //end of CC_MTK_LOADER
    return i4Ret;
}

INT32 _GCPU_DisableIOMMU(void)
{
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
    TZ_GCPU_DisableIOMMU();
#else
    IOMMU_GCPU_WRITE32(REG_IOMMU_CFG0, 0);
#endif

    return S_GCPU_OK;
}


INT32 _GCPU_GetRomCodeChecksum(void)
{
    INT32 res = 0;

#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
    GCPU_HW_LOCK();
    
    if (_Gcpu_Hw_SetResetParam(_prGcpuTzParam))
    {
        TZ_GCPU_GetRomCodeChecksum(_prGcpuTzParam, _u4GcpuTzParamSize);
        res = (INT32)_prGcpuTzParam->u4ReturnedValue;
    }
    
    GCPU_HW_UNLOCK();
#else  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT && !CC_MTK_LOADER) */
    GCPU_TZ_PARAM_T rTzParam;
    INT32 i, tmp, d0, d1, d2, mask;

    GCPU_HW_LOCK();

    if (_Gcpu_Hw_SetResetParam(&rTzParam))
    {
        _Gcpu_Hw_Reset(&rTzParam);
    }
    else
    {
        LOG(3, "GCPU invalid reset parameters\n");
    }

    _GCPU_Lock();

    mask = 255; //0xff
    res = 0;

    GCPUCMD_WRITE32(GCPU_REG_MEM_ADDR, 0x00000000);

    for (i = 1; i <= GCPU_IMEM_ROM_SIZE; i++)
    {
        tmp = GCPUCMD_READ32(GCPU_REG_MEM_DATA);
        //LOG(0, "%04d:%08x\n", i, tmp);

        d0 = tmp & mask;
        d1 = (tmp >> 8) & mask;
        d2 = (tmp >> 16) & mask;
        if((i % 4) == 0)
        {
            tmp = (d2 << 16) + (d1 << 8) + d0;
        }
        if((i % 4) == 1)
        {
            tmp = (d1 << 16) + (d0 << 8) + d2;
        }
        if((i % 4) == 2)
        {
            tmp = (d0 << 16) + (d2 << 8) + d1;
        }
        if((i % 4) == 3)
        {
            tmp = (d0 << 16) + (d1 << 8) + d2;
        }

        res = res ^ tmp;
    }

    _GCPU_Unlock();

    LOG(5, "%x\n", res);

    GCPU_HW_UNLOCK();
#endif  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT && !CC_MTK_LOADER) */

    return res;
}


//-----------------------------------------------------------------------------
/** _GCPU_Hw_Init
 *  Init GCPU HW
 */
//-----------------------------------------------------------------------------
INT32 _GCPU_Hw_Init(UINT32 u4Mode, BOOL fgIsLocked)
{
#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
    UINT32 u4BufPAddr;
#else
    GCPU_TZ_PARAM_T rTzParam;
#endif

    #ifndef CC_MTK_LOADER
    // create a semaphore
    if (0 == _hGcpuHwSema)
    {
        if(x_sema_create(&_hGcpuHwSema, X_SEMA_TYPE_MUTEX, X_SEMA_STATE_UNLOCK) != OSR_OK)
        {
            LOG(1, "Fail to create HW semaphore\n");
            return E_GCPU_OS_OPERA_FAIL;
        }
    }
    #if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT)
    if (!_prGcpuTzParam)
    {
        _u4GcpuTzParamSize = TZ_CACHE_ALIGN(sizeof(GCPU_TZ_PARAM_T));
        u4BufPAddr = (UINT32)BSP_AllocAlignedDmaMemory(_u4GcpuTzParamSize, TZ_CACHE_LINE_SIZE);
        _prGcpuTzParam = (GCPU_TZ_PARAM_T *)VIRTUAL(u4BufPAddr);
        if (!_prGcpuTzParam)
        {
            LOG(1, "Unable to allocate GCPU_TZ_PARAM_T\n");
            return E_GCPU_OS_OPERA_FAIL;
        }
    }
    
    if (!_prGcpuHwCmd)
    {
        _u4GcpuHwCmdSize = TZ_CACHE_ALIGN(sizeof(GCPU_HW_CMD_T));
        u4BufPAddr = (UINT32)BSP_AllocAlignedDmaMemory(_u4GcpuHwCmdSize, TZ_CACHE_LINE_SIZE);
        _prGcpuHwCmd = (GCPU_HW_CMD_T *)VIRTUAL(u4BufPAddr);
        if (!_prGcpuHwCmd)
        {
            BSP_FreeAlignedDmaMemory(PHYSICAL((UPTR)_prGcpuTzParam));
            LOG(1, "Unable to allocate GCPU_HW_CMD_T\n");
            return E_GCPU_OS_OPERA_FAIL;
        }
    }
    #endif  /* (CC_TRUSTZONE_SUPPORT && !CC_UBOOT) */
    #endif  /* CC_MTK_LOADER */

    if (!fgIsLocked)
    {
        GCPU_HW_LOCK();
    }

    CKGEN_WRITE32(0x1C8, CKGEN_READ32(0x1C8) | (1 << 20));

    #if defined(CC_DMX_A1) || defined(CC_MT5886) || defined(CC_MT5863) || defined(CC_MT5893)
    CKGEN_WRITE32(0x39C, 0x1);  // GCPU Max clock
    #elif defined(CC_MT5895)
    CKGEN_WRITE32(0x39C, 0x8);  // GCPU Max clock
    #else
    CKGEN_WRITE32(0x39C, 0x2);
    #endif

    // Enable GCPU
    _u4Mode = u4Mode;

#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
    if (_Gcpu_Hw_SetResetParam(_prGcpuTzParam))
    {
        TZ_GCPU_Hw_Reset(_prGcpuTzParam, _u4GcpuTzParamSize);
    }
    else
    {
        LOG(3, "GCPU invalid reset parameters\n");
    }
#else  /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT && !CC_MTK_LOADER) */
    if (_Gcpu_Hw_SetResetParam(&rTzParam))
    {
        _Gcpu_Hw_Reset(&rTzParam);
    }
    else
    {
        LOG(3, "GCPU invalid reset parameters\n");
    }
#endif /* !(CC_TRUSTZONE_SUPPORT && !CC_UBOOT && !CC_MTK_LOADER) */

    _Gcpu_InitIsr();

    if (!fgIsLocked)
    {
        GCPU_HW_UNLOCK();
    }

    return S_GCPU_OK;
}


INT32 _GCPU_Hw_SetSlot(UINT32 u4Idx, UINT32 u4Data)
{
    GCPU_HW_LOCK();

#if defined(CC_SUPPORT_STR) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER) && !defined(CC_TRUSTZONE_SUPPORT) 
    _GCPU_Hw_SaveSecureKeys(u4Idx, u4Data);
#endif

#if defined(CC_TRUSTZONE_SUPPORT) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
    x_memset((void *)_prGcpuTzParam, 0, sizeof(GCPU_TZ_PARAM_T));
    
    _prGcpuTzParam->u4SlotIdx = u4Idx;
    _prGcpuTzParam->u4SlotData = u4Data;

    TZ_GCPU_Hw_SetSlot(_prGcpuTzParam, _u4GcpuTzParamSize);
#else
    GCPUCMD_WRITE32(GCPU_REG_MEM_CMD + u4Idx, u4Data);
#endif

    GCPU_HW_UNLOCK();

    return S_GCPU_OK;
}


INT32 _GCPU_Hw_Cmd(GCPU_HW_CMD_T *prHwCmd)
{
    INT32 i4Result = S_GCPU_OK;

    if (prHwCmd == NULL)
    {
        return E_GCPU_PARAM_WRONG;
    } 
  
    GCPU_HW_LOCK();
    
    i4Result = _GCPU_Hw_RunCmd(prHwCmd);

    GCPU_HW_UNLOCK();

    return i4Result;
}

INT32 _GCPU_Hw_CmdEx(GCPU_HW_CMD_T *prHwCmd, const GCPU_IO_BUF_T *prBuf, UINT32 u4Flags) 
{
    INT32 i4Result = S_GCPU_OK;
    BOOL fgUsrland;

    if ((prHwCmd == NULL) || (prBuf == NULL))
    {
        return E_GCPU_PARAM_WRONG;
    }

#if 0//!defined(CC_UBOOT) && !defined(CC_MTK_LOADER) && !defined(CC_DRIVER_BUILD)
  #ifdef CONFIG_64BIT
    fgUsrland = (PHYSICAL(prBuf->u4InBufStart) == (prBuf->u4InBufStart)) ? TRUE : FALSE;
  #else
    fgUsrland = ((prBuf->u4InBufStart > 0) && (prBuf->u4InBufStart < 0xBF000000)) ? TRUE : FALSE;
  #endif
#else
    fgUsrland = FALSE;
#endif

    GCPU_HW_LOCK();

    if (u4Flags & GCPU_HWCMD_FLAG_IOMMU)
    {
        LOG(2, "%s(%d), u4IommuSrc1Start:0x%llx, u4IommuSrc1End:0x%llx, u4MmuTblAddr:0x%x\n", 
                    __FUNCTION__, __LINE__, prBuf->u4IommuSrc1Start, prBuf->u4IommuSrc1End, prBuf->u4MmuTblAddr);
        _GCPU_EnableIOMMU(prBuf->u4IommuSrc1Start, prBuf->u4IommuSrc1End,
                          prBuf->u4IommuSrc2Start, prBuf->u4IommuSrc2End, prBuf->u4MmuTblAddr);
    }
    else
    {
        _GCPU_DisableIOMMU();
    }

    if (u4Flags & GCPU_HWCMD_FLAG_CLEAR_CACHE)
    {
        HalFlushInvalidateDCache();
    }
    else if (!fgUsrland && (u4Flags & GCPU_HWCMD_FLAG_DMA_BUF))
    {
        LOG(2, "%s(%d), u4InAddr:0x%llx, u4InDataSize:0x%x\n", __FUNCTION__, __LINE__, prBuf->u4InAddr, prBuf->u4InDataSize);
#ifndef CC_MTK_LOADER
#ifndef CC_UBOOT
#ifdef CONFIG_MTK_IOMMU
        if((u4Flags & GCPU_HWCMD_FLAG_IOMMU) && prBuf->u4MmuTblAddr)
        {

            if(prBuf->u4InDataSize != 0)
            {
                void*   devaddr = NULL;
                UPTR    u4BytesAddr = 0;
                
                devaddr = MtkIommuGetDevAddr(MTK_IOMMU_DEVICE_GCPU);
                u4BytesAddr = (UPTR)MtkIommuMapIova(devaddr, prBuf->u4InAddr, prBuf->u4InDataSize);
                LOG(2, "%s(%d), u4InAddr:0x%llx, u4InDataSize:0x%x, u4BytesAddr:0x%llx, data:0x%llx\n", 
                            __FUNCTION__, __LINE__, prBuf->u4InAddr, prBuf->u4InDataSize, u4BytesAddr, *((UINT64*)u4BytesAddr));
                HalFlushInvalidateDCacheMultipleLine(u4BytesAddr, prBuf->u4InDataSize);
                MtkIommuUnMapIova((void *)u4BytesAddr, prBuf->u4InDataSize);
            }

            if(prBuf->u4OutDataSize != 0)
            {
                void*   devaddr = NULL;
                UPTR    u4BytesAddr = 0;
                
                devaddr = MtkIommuGetDevAddr(MTK_IOMMU_DEVICE_GCPU);
                u4BytesAddr = (UPTR)MtkIommuMapIova(devaddr, prBuf->u4OutAddr, prBuf->u4OutDataSize);
                LOG(2, "%s(%d), u4OutAddr:0x%llx, u4OutDataSize:0x%x, u4BytesAddr:0x%llx, data:0x%llx\n", 
                            __FUNCTION__, __LINE__, prBuf->u4OutAddr, prBuf->u4OutDataSize, u4BytesAddr, *((UINT64*)u4BytesAddr));
                HalFlushInvalidateDCacheMultipleLine(u4BytesAddr, prBuf->u4OutDataSize);
                MtkIommuUnMapIova((void *)u4BytesAddr, prBuf->u4OutDataSize);
            }
        }
        else
#endif
#endif
#endif
        {
#ifndef GCPU_FLUSH_ALL_IO_BUF
       if ((prBuf->u4InBufStart != 0 && prBuf->u4InBufEnd !=0) &&
            (prBuf->u4InBufStart <= prBuf->u4InAddr && prBuf->u4InAddr < prBuf->u4InBufEnd) &&
            (prBuf->u4InDataSize <= prBuf->u4InBufSize))
        {
            if (prBuf->u4InAddr + prBuf->u4InDataSize > prBuf->u4InBufEnd)
            {
                #if !defined(CC_UBOOT) && !defined(CC_MTK_LOADER) && !defined(CC_DRIVER_BUILD)
                x_kmem_sync_table((void *)prBuf->u4InAddr, prBuf->u4InBufEnd - prBuf->u4InAddr);
                x_kmem_sync_table((void *)prBuf->u4InBufStart, prBuf->u4InAddr + prBuf->u4InDataSize - prBuf->u4InBufEnd);
                #endif
                
                HalDmaBufferStart((void *)prBuf->u4InAddr, prBuf->u4InBufEnd - prBuf->u4InAddr, HAL_DMA_BIDIRECTION);
                HalDmaBufferStart((void *)prBuf->u4InBufStart, prBuf->u4InAddr + prBuf->u4InDataSize - prBuf->u4InBufEnd, HAL_DMA_BIDIRECTION);
            }
            else
            {     
                #if !defined(CC_UBOOT) && !defined(CC_MTK_LOADER) && !defined(CC_DRIVER_BUILD)
                x_kmem_sync_table((void *)prBuf->u4InAddr, prBuf->u4InDataSize);
                #endif
                
                HalDmaBufferStart((void *)prBuf->u4InAddr, prBuf->u4InDataSize, HAL_DMA_BIDIRECTION);
            }
        }

        if ((prBuf->u4OutBufStart != 0 && prBuf->u4OutBufEnd !=0) &&
            (prBuf->u4OutBufStart <= prBuf->u4OutAddr && prBuf->u4OutAddr < prBuf->u4OutBufEnd) &&
            (prBuf->u4OutDataSize <= prBuf->u4OutBufSize))
        {
            if (prBuf->u4OutAddr + prBuf->u4OutDataSize > prBuf->u4OutBufEnd)
            {
                #if !defined(CC_UBOOT) && !defined(CC_MTK_LOADER) && !defined(CC_DRIVER_BUILD)
                x_kmem_sync_table((void *)prBuf->u4OutAddr, prBuf->u4OutBufEnd - prBuf->u4OutAddr);
                x_kmem_sync_table((void *)prBuf->u4OutBufStart, prBuf->u4OutAddr + prBuf->u4OutDataSize - prBuf->u4OutBufEnd);
                #endif
                
                HalDmaBufferStart((void *)prBuf->u4OutAddr, prBuf->u4OutBufEnd - prBuf->u4OutAddr, HAL_DMA_BIDIRECTION);
                HalDmaBufferStart((void *)prBuf->u4OutBufStart, prBuf->u4OutAddr + prBuf->u4OutDataSize - prBuf->u4OutBufEnd, HAL_DMA_BIDIRECTION);
            }
            else
            {     
                #if !defined(CC_UBOOT) && !defined(CC_MTK_LOADER) && !defined(CC_DRIVER_BUILD)
                x_kmem_sync_table((void *)prBuf->u4OutAddr, prBuf->u4OutDataSize);
                #endif
                
                HalDmaBufferStart((void *)prBuf->u4OutAddr, prBuf->u4OutDataSize, HAL_DMA_BIDIRECTION);
            }
        }
#else
        if ((prBuf->u4InBufStart != 0) && (prBuf->u4InBufSize != 0))
        {
            #if !defined(CC_UBOOT) && !defined(CC_MTK_LOADER) && !defined(CC_DRIVER_BUILD)
            x_kmem_sync_table((void *)prBuf->u4InBufStart, prBuf->u4InBufSize);
            #endif
            HalDmaBufferStart((void *)prBuf->u4InBufStart, prBuf->u4InBufSize, HAL_DMA_BIDIRECTION);
        }
        
        if ((prBuf->u4OutBufStart != 0) && (prBuf->u4OutBufSize != 0))
        {
            #if !defined(CC_UBOOT) && !defined(CC_MTK_LOADER) && !defined(CC_DRIVER_BUILD)
            x_kmem_sync_table((void *)prBuf->u4OutBufStart, prBuf->u4OutBufSize);
            #endif
            HalDmaBufferStart((void *)prBuf->u4OutBufStart, prBuf->u4OutBufSize, HAL_DMA_BIDIRECTION);
        } 
#endif
    }
    }
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd\n", __FUNCTION__, __LINE__);
    i4Result = _GCPU_Hw_RunCmd(prHwCmd);
    LOG(2, "%s(%d), _GCPU_Hw_RunCmd return %d\n", __FUNCTION__, __LINE__, i4Result);
    if (u4Flags & GCPU_HWCMD_FLAG_CLEAR_CACHE)
    {
        HalFlushInvalidateDCache();
    }
    else if (!fgUsrland && (u4Flags & GCPU_HWCMD_FLAG_DMA_BUF))
    {
        LOG(2, "%s(%d), u4InAddr:0x%llx, u4InDataSize:0x%x\n", __FUNCTION__, __LINE__, prBuf->u4InAddr, prBuf->u4InDataSize);
        
#ifndef CC_MTK_LOADER
#ifndef CC_UBOOT
#ifdef CONFIG_MTK_IOMMU
        if((u4Flags & GCPU_HWCMD_FLAG_IOMMU) && prBuf->u4MmuTblAddr)
        {
            if(prBuf->u4InDataSize != 0)
            {
                void*   devaddr = NULL;
                UPTR    u4BytesAddr = 0;
                
                devaddr = MtkIommuGetDevAddr(MTK_IOMMU_DEVICE_GCPU);
                u4BytesAddr = (UPTR)MtkIommuMapIova(devaddr, prBuf->u4InAddr, prBuf->u4InDataSize);
                LOG(2, "%s(%d), u4InAddr:0x%llx, u4InDataSize:0x%x, u4BytesAddr:0x%llx\n", 
                            __FUNCTION__, __LINE__, prBuf->u4InAddr, prBuf->u4InDataSize, u4BytesAddr);
                HalFlushInvalidateDCacheMultipleLine(u4BytesAddr, prBuf->u4InDataSize);
                MtkIommuUnMapIova((void *)u4BytesAddr, prBuf->u4InDataSize);
            }

            if(prBuf->u4OutDataSize != 0)
            {
                void*   devaddr = NULL;
                UPTR    u4BytesAddr = 0;
                
                devaddr = MtkIommuGetDevAddr(MTK_IOMMU_DEVICE_GCPU);
                u4BytesAddr = (UPTR)MtkIommuMapIova(devaddr, prBuf->u4OutAddr, prBuf->u4OutDataSize);
                LOG(2, "%s(%d), u4OutAddr:0x%llx, u4OutDataSize:0x%x, u4BytesAddr:0x%llx, data:0x%llx\n", 
                            __FUNCTION__, __LINE__, prBuf->u4OutAddr, prBuf->u4OutDataSize, u4BytesAddr, *((UINT64*)u4BytesAddr));
                HalFlushInvalidateDCacheMultipleLine(u4BytesAddr, prBuf->u4OutDataSize);
                MtkIommuUnMapIova((void *)u4BytesAddr, prBuf->u4OutDataSize);
            }
        }
        else
#endif
#endif
#endif
        {
#ifndef GCPU_FLUSH_ALL_IO_BUF        
        if ((prBuf->u4InBufStart != 0 && prBuf->u4InBufEnd !=0) &&
            (prBuf->u4InBufStart <= prBuf->u4InAddr && prBuf->u4InAddr < prBuf->u4InBufEnd) &&
            (prBuf->u4InDataSize <= prBuf->u4InBufSize))
        {
            if (prBuf->u4InAddr + prBuf->u4InDataSize > prBuf->u4InBufEnd)
            {
                HalDmaBufferDone((void *)prBuf->u4InAddr, prBuf->u4InBufEnd - prBuf->u4InAddr, HAL_DMA_BIDIRECTION);
                HalDmaBufferDone((void *)prBuf->u4InBufStart, prBuf->u4InAddr + prBuf->u4InDataSize - prBuf->u4InBufEnd, HAL_DMA_BIDIRECTION);
            }
            else
            {     
                
                HalDmaBufferDone((void *)prBuf->u4InAddr, prBuf->u4InDataSize, HAL_DMA_BIDIRECTION);
            }
        }

        if ((prBuf->u4OutBufStart != 0 && prBuf->u4OutBufEnd !=0) &&
            (prBuf->u4OutBufStart <= prBuf->u4OutAddr && prBuf->u4OutAddr < prBuf->u4OutBufEnd) &&
            (prBuf->u4OutDataSize <= prBuf->u4OutBufSize))
        {
            if (prBuf->u4OutAddr + prBuf->u4OutDataSize > prBuf->u4OutBufEnd)
            {
                
                HalDmaBufferDone((void *)prBuf->u4OutAddr, prBuf->u4OutBufEnd - prBuf->u4OutAddr, HAL_DMA_BIDIRECTION);
                HalDmaBufferDone((void *)prBuf->u4OutBufStart, prBuf->u4OutAddr + prBuf->u4OutDataSize - prBuf->u4OutBufEnd, HAL_DMA_BIDIRECTION);
            }
            else
            {     
                
                HalDmaBufferDone((void *)prBuf->u4OutAddr, prBuf->u4OutDataSize, HAL_DMA_BIDIRECTION);
            }
        }
#else
        if ((prBuf->u4InBufStart != 0) && (prBuf->u4InBufSize != 0))
        {
            HalDmaBufferDone((void *)prBuf->u4InBufStart, prBuf->u4InBufSize, HAL_DMA_BIDIRECTION);
        }
        
        if ((prBuf->u4OutBufStart != 0) && (prBuf->u4OutBufSize != 0))
        {
            HalDmaBufferDone((void *)prBuf->u4OutBufStart, prBuf->u4OutBufSize, HAL_DMA_BIDIRECTION);
        }
#endif
        }    
    }

    GCPU_HW_UNLOCK();

    return i4Result;
}


#if defined(CC_SUPPORT_STR) && !defined(CC_UBOOT) && !defined(CC_MTK_LOADER)
#ifndef CC_TRUSTZONE_SUPPORT
static BOOL _GCPU_Hw_SaveSecureKeys(UINT32 u4SlotPtr, UINT32 u4Key)
{
    UINT32 u4Idx;

    if (u4SlotPtr >= GCPU_SECURESLOT_PTR + GCPU_SECURESLOT_NUM)
    {
        return FALSE;
    }
    
    u4Idx = u4SlotPtr - GCPU_SECURESLOT_PTR;
    _arSecureKeyHoles[u4Idx] = u4Key;

    return TRUE;
}
#endif

static BOOL _GCPU_Hw_RestoreSecureKeys(void)
{
#ifdef CC_TRUSTZONE_SUPPORT
    TZ_GCPU_Hw_RestoreSecureKeys();
#else  /* !CC_TRUSTZONE_SUPPORT */
    INT32 i;
    UINT32 u4Data;
    UINT8 *p;
    UINT8 au1Key[16] = {};

    _DMX_GetMtdSecureKey(au1Key);

    for (i = 0; i < GCPU_SECURESLOT_NUM; i++)
    {
        u4Data = _arSecureKeyHoles[i];
        GCPUCMD_WRITE32(GCPU_REG_MEM_CMD + GCPU_SECURESLOT_PTR + i, u4Data);
    }

    for(i = 0; i < 4; i++)
    {
        p = au1Key + i * 4;
        u4Data = KEY_WRAPPER(p);
        GCPUCMD_WRITE32(GCPU_REG_MEM_CMD + AES_MTD_SECURE_KEY_PTR + i, u4Data);
    }
#endif /* !CC_TRUSTZONE_SUPPORT */
    
    return TRUE;
}

//#define CC_GCPU_SLOW_DOWN_CLOCK     // we don't really power down gcpu, due to NAND/native driver relation
void _GCPU_pm_str_suspend(void)
{
    #ifdef CC_GCPU_SLOW_DOWN_CLOCK
    CKGEN_WRITE32(0x39C, 0x0);  // GCPU XTAL clock
    #else
    // disable IRQ
    GCPU_HW_LOCK();
    GCPUCMD_WRITE32(GCPU_REG_INT_CLR, GCPUCMD_READ32(GCPU_REG_INT_CLR));
    GCPUCMD_WRITE32(GCPU_REG_INT_EN, 0);

    if (!BIM_DisableIrq(VECTOR_UP0))
    {
        LOG(1, "Disable GCPU isr fail\n");
    }

    if (!BIM_DisableIrq(VECTOR_MMU_GCPU))
    {
        LOG(1, "Disable GCPU IOMMU isr fail\n");
    }

    // power off
    CKGEN_WRITE32(0x1C8, CKGEN_READ32(0x1C8) & ~(1U << 20));
    #endif
}

void _GCPU_pm_str_resume(void)
{
    #ifdef CC_GCPU_SLOW_DOWN_CLOCK
    CKGEN_WRITE32(0x39C, 0x2);  // GCPU Max clock
    #else
    // power on
    _GCPU_Hw_Init(0, TRUE);
    
    _GCPU_Hw_RestoreSecureKeys();

    if (!BIM_EnableIrq(VECTOR_UP0))
    {
        LOG(3, "Eanble GCPU isr fail\n");
    }

    if (!BIM_EnableIrq(VECTOR_MMU_GCPU))
    {
        LOG(3, "Eanble GCPU IOMMU isr fail\n");
    }

    GCPU_HW_UNLOCK();

    // IRQ will be enalbed when executing GCPU command
    // do nothing here
    #endif
}
#endif // CC_SUPPORT_STR

