/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: x-kentarous $
 * $Date: 2017/10/13 $
 * $RCSfile: aud_cust_amp_5782.c,v $
 * $Revision: #1 $
 *
 *---------------------------------------------------------------------------*/

//---------------------------------------------------------------------------
// Include files
//---------------------------------------------------------------------------

/* =======================================================
 [**CAUTION**] 
 You can only include header files in 
 \target\mtxxxx\xxxx_driver\drv_inc\  
 or files in \vm_linux\output\sysbuild\xxxx\rel or debug\inc\drv_inc\
 or files in the same directory.
========================================================= */
#include "aud_cust_amp_if.h"
#include "sif_if.h"
#include "aud_if.h"
#include "drvcust_if.h"
#include "sakura_aud_aq_data.h"

//---------------------------------------------------------------------------
// Configurations
//---------------------------------------------------------------------------

//---------------------------------------------------------------------------
// Constant definitions
//---------------------------------------------------------------------------
#define NTFY_ERR_NUM_5782   (352)

#define AMP_5782_SYS_BOOK	(0x00)
#define AMP_5782_DSP_BOOK	(0x8C)

//---------------------------------------------------------------------------
// Type definitions
//---------------------------------------------------------------------------
typedef enum {
    DA_5782_TYPE_NONE,
    DA_5782_TYPE_1,
    DA_5782_TYPE_2,
    DA_5782_TYPE_3,
    DA_5782_TYPE_4,
    DA_5782_TYPE_MAX
} Da5782Type;

//---------------------------------------------------------------------------
// Macro definitions
//---------------------------------------------------------------------------
#define _AMP_5782_SET_4(dst, src) \
	dst[0] = ((src & 0xFF000000) >> 24); \
	dst[1] = ((src & 0x00FF0000) >> 16); \
	dst[2] = ((src & 0x0000FF00) >>  8); \
	dst[3] = ((src & 0x000000FF)      );

//---------------------------------------------------------------------------
// Imported variables
//---------------------------------------------------------------------------

//---------------------------------------------------------------------------
// Imported functions
//---------------------------------------------------------------------------

//---------------------------------------------------------------------------
// Static function forward declarations
//---------------------------------------------------------------------------

//---------------------------------------------------------------------------
// Static variables
//---------------------------------------------------------------------------
//static BOOL fgIs5782Shutdown = FALSE;

//---------------------------------------------------------------------------
// Static functions
//---------------------------------------------------------------------------

static int _AMP_5782_Change_Book_And_Page(AMP_DATA_T *pAmp, UINT8 book, UINT8 page)
{
	UINT8 REG_VAL;

	// w 90 00 00
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x00, &REG_VAL, 1);
	// w 90 7F XX  -> XX = Book
	AUD_CUST_AMP_RegWrite(pAmp, 0x7F, &book, 1);
	// w 90 00 YY  -> YY = Page
	AUD_CUST_AMP_RegWrite(pAmp, 0x00, &page, 1);

	return 0;
}

static int _AMP_5782_Set_SWAP_FLAG(AMP_DATA_T *pAmp)
{
	UINT8 REG_VAL[4];

	// DSP Register : Book=AMP_5782_DSP_BOOK Page=0x23
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x23);

	// Swap flag : 0x00000001
	REG_VAL[0] = 0x00;
	REG_VAL[1] = 0x00;
	REG_VAL[2] = 0x00;
	REG_VAL[3] = 0x01;
	// write Address : 0x14
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);

	return 0;
}

static int _AMP_5782_Set_DSP_Enable(AMP_DATA_T *pAmp)
{
	UINT8 REG_VAL;

	// System Register : Book=AMP_5782_SYS_BOOK Page=0x00
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_SYS_BOOK, 0x00);

	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x02, &REG_VAL, 1);	// 0x00 -> Addr(0x02:Register2)

	return 0;
}

static int _AMP_5782_Mute(AMP_DATA_T *pAmp, bool bIsMuteOn)
{
	UINT8 REG_VAL;

	// System Register : Book=AMP_5782_SYS_BOOK Page=0x00
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_SYS_BOOK, 0x00);

	if (bIsMuteOn != false) {
		REG_VAL = 0x11;
	} else {
		REG_VAL = 0x00;
	}
	AUD_CUST_AMP_RegWrite(pAmp, 0x03, &REG_VAL, 1);	// 0xXX -> Addr(0x02:Register3)

	return 0;
}

static int _AMP_5782_PowerDown(AMP_DATA_T *pAmp)
{
	UINT8 REG_VAL;

	// System Register : Book=AMP_5782_SYS_BOOK Page=0x00
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_SYS_BOOK, 0x00);

	REG_VAL = 0x01;
	AUD_CUST_AMP_RegWrite(pAmp, 0x02, &REG_VAL, 1);	// 0x01 -> Addr(0x02:Register2)

	return 0;
}

static int _AMP_5782_Set_System_Reg(AMP_DATA_T *pAmp)
{
	UINT8 REG_VAL;

	// ====== Book:0x00 Page:0x00 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_SYS_BOOK, 0x00);

	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x01, &REG_VAL, 1);	// 0x00 -> Addr(0x01:Register1)
	REG_VAL = 0x80;
	AUD_CUST_AMP_RegWrite(pAmp, 0x02, &REG_VAL, 1);	// 0x80 -> Addr(0x02:Register2)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x03, &REG_VAL, 1);	// 0x00 -> Addr(0x03:Register3)
	REG_VAL = 0x01;
	AUD_CUST_AMP_RegWrite(pAmp, 0x04, &REG_VAL, 1);	// 0x01 -> Addr(0x04:Register4)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x06, &REG_VAL, 1);	// 0x00 -> Addr(0x06:Register6)
	REG_VAL = 0x01;
	AUD_CUST_AMP_RegWrite(pAmp, 0x07, &REG_VAL, 1);	// 0x01 -> Addr(0x07:Register7)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, &REG_VAL, 1);	// 0x00 -> Addr(0x08:Register8)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x09, &REG_VAL, 1);	// 0x00 -> Addr(0x09:Register9)
	REG_VAL = 0x7C;
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, &REG_VAL, 1);	// 0x7C -> Addr(0x0C:Register12)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x0D, &REG_VAL, 1);	// 0x00 -> Addr(0x0D:Register13)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x0E, &REG_VAL, 1);	// 0x00 -> Addr(0x0E:Register14)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x0F, &REG_VAL, 1);	// 0x00 -> Addr(0x0F:Register15)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, &REG_VAL, 1);	// 0x00 -> Addr(0x10:Register16)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x11, &REG_VAL, 1);	// 0x00 -> Addr(0x11:Register17)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x12, &REG_VAL, 1);	// 0x00 -> Addr(0x12:Register18)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, &REG_VAL, 1);	// 0x00 -> Addr(0x14:Register20)
	REG_VAL = 0x08;
	AUD_CUST_AMP_RegWrite(pAmp, 0x15, &REG_VAL, 1);	// 0x08 -> Addr(0x15:Register21)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x16, &REG_VAL, 1);	// 0x00 -> Addr(0x16:Register22)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x17, &REG_VAL, 1);	// 0x00 -> Addr(0x17:Register23)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, &REG_VAL, 1);	// 0x00 -> Addr(0x18:Register24)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x1B, &REG_VAL, 1);	// 0x00 -> Addr(0x1B:Register27)
	REG_VAL = 0x01;
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, &REG_VAL, 1);	// 0x01 -> Addr(0x1C:Register28)
	REG_VAL = 0x01;
	AUD_CUST_AMP_RegWrite(pAmp, 0x1D, &REG_VAL, 1);	// 0x01 -> Addr(0x1D:Register29)
	REG_VAL = 0x01;
	AUD_CUST_AMP_RegWrite(pAmp, 0x1E, &REG_VAL, 1);	// 0x01 -> Addr(0x1E:Register30)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, &REG_VAL, 1);	// 0x00 -> Addr(0x20:Register32)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x21, &REG_VAL, 1);	// 0x00 -> Addr(0x21:Register33)
	REG_VAL = 0x04;
	AUD_CUST_AMP_RegWrite(pAmp, 0x22, &REG_VAL, 1);	// 0x04 -> Addr(0x22:Register34)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x25, &REG_VAL, 1);	// 0x00 -> Addr(0x25:Register37)
	REG_VAL = 0x03;
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, &REG_VAL, 1);	// 0x03 -> Addr(0x28:Register40)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x29, &REG_VAL, 1);	// 0x00 -> Addr(0x29:Register41)
	REG_VAL = 0x11;
	AUD_CUST_AMP_RegWrite(pAmp, 0x2A, &REG_VAL, 1);	// 0x11 -> Addr(0x2A:Register42)
	REG_VAL = 0x01;
	AUD_CUST_AMP_RegWrite(pAmp, 0x2B, &REG_VAL, 1);	// 0x01 -> Addr(0x2B:Register43)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, &REG_VAL, 1);	// 0x00 -> Addr(0x2C:Register44)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x3B, &REG_VAL, 1);	// 0x00 -> Addr(0x3B:Register59)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, &REG_VAL, 1);	// 0x00 -> Addr(0x3C:Register60)
	REG_VAL = 0x30;
	AUD_CUST_AMP_RegWrite(pAmp, 0x3D, &REG_VAL, 1);	// 0x30 -> Addr(0x3D:Register61)
	REG_VAL = 0x30;
	AUD_CUST_AMP_RegWrite(pAmp, 0x3E, &REG_VAL, 1);	// 0x30 -> Addr(0x3E:Register62)
	REG_VAL = 0x11;
	AUD_CUST_AMP_RegWrite(pAmp, 0x3F, &REG_VAL, 1);	// 0x11 -> Addr(0x3F:Register63)
	REG_VAL = 0x10;
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, &REG_VAL, 1);	// 0x10 -> Addr(0x40:Register64)
	REG_VAL = 0x07;
	AUD_CUST_AMP_RegWrite(pAmp, 0x41, &REG_VAL, 1);	// 0x07 -> Addr(0x41:Register65)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x43, &REG_VAL, 1);	// 0x00 -> Addr(0x43:Register67)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, &REG_VAL, 1);	// 0x00 -> Addr(0x44:Register68)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x45, &REG_VAL, 1);	// 0x00 -> Addr(0x45:Register69)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x46, &REG_VAL, 1);	// 0x00 -> Addr(0x46:Register70)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x47, &REG_VAL, 1);	// 0x00 -> Addr(0x47:Register71)
	REG_VAL = 0x55;
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, &REG_VAL, 1);	// 0x55 -> Addr(0x48:Register72)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x49, &REG_VAL, 1);	// 0x00 -> Addr(0x49:Register73)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x4A, &REG_VAL, 1);	// 0x00 -> Addr(0x4A:Register74)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x4B, &REG_VAL, 1);	// 0x00 -> Addr(0x4B:Register75)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x4C, &REG_VAL, 1);	// 0x00 -> Addr(0x4C:Register76)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x4E, &REG_VAL, 1);	// 0x00 -> Addr(0x4E:Register78)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x4F, &REG_VAL, 1);	// 0x00 -> Addr(0x4F:Register79)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x53, &REG_VAL, 1);	// 0x00 -> Addr(0x53:Register83)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x55, &REG_VAL, 1);	// 0x00 -> Addr(0x55:Register85)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x56, &REG_VAL, 1);	// 0x00 -> Addr(0x56:Register86)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x57, &REG_VAL, 1);	// 0x00 -> Addr(0x57:Register87)

	// ====== Book:0x00 Page:0x01 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_SYS_BOOK, 0x01);

	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x01, &REG_VAL, 1);	// 0x00 -> Addr(0x01:Register1)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x02, &REG_VAL, 1);	// 0x00 -> Addr(0x02:Register2)
	REG_VAL = 0x01;
	AUD_CUST_AMP_RegWrite(pAmp, 0x06, &REG_VAL, 1);	// 0x01 -> Addr(0x06:Register6)
	REG_VAL = 0x00;
	AUD_CUST_AMP_RegWrite(pAmp, 0x07, &REG_VAL, 1);	// 0x00 -> Addr(0x07:Register7)
	REG_VAL = 0x01;
	AUD_CUST_AMP_RegWrite(pAmp, 0x09, &REG_VAL, 1);	// 0x01 -> Addr(0x09:Register9)

	return 0;
}

static int _AMP_5782_Refresh_DSP_Reg(AMP_DATA_T *pAmp)
{
	AQDataDa15782General *gen = NULL;
	AQDataDa15782Drc *drc = NULL;
	AQDataDa15782Dpeq *dpeq = NULL;
	AQDataDa15782Bq *bq = NULL;
	AQDataDa15782Vol *vol = NULL;
	AQDataDa15782General gen1 = {0};
	AQDataDa15782Drc drc1 = {0};
	AQDataDa15782Dpeq dpeq1 = {0};
	AQDataDa15782Bq bq1 = {0};
	AQDataDa15782Vol vol1 = {0};
	AQDataDa25782General gen2 = {0};
	AQDataDa25782Drc drc2 = {0};
	AQDataDa25782Dpeq dpeq2 = {0};
	AQDataDa25782Bq bq2 = {0};
	AQDataDa25782Vol vol2 = {0};
	AQDataDa35782General gen3 = {0};
	AQDataDa35782Drc drc3 = {0};
	AQDataDa35782Dpeq dpeq3 = {0};
	AQDataDa35782Bq bq3 = {0};
	AQDataDa35782Vol vol3 = {0};
	AQDataDa45782General gen4 = {0};
	AQDataDa45782Drc drc4 = {0};
	AQDataDa45782Dpeq dpeq4 = {0};
	AQDataDa45782Bq bq4 = {0};
	AQDataDa45782Vol vol4 = {0};
	UINT8 REG_VAL[4];

    switch (pAmp->u1AmpTable) {
    case DA_5782_TYPE_1:
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA1_5782_GENERAL, &gen1, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA1_5782_DRC, &drc1, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA1_5782_DPEQ, &dpeq1, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA1_5782_BQ, &bq1, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA1_5782_VOL, &vol1, 0, _gu4CurrentAqKey, 0);
        gen = (AQDataDa15782General *)(&gen1);
        drc = (AQDataDa15782Drc *)(&drc1);
        dpeq = (AQDataDa15782Dpeq *)(&dpeq1);
        bq = (AQDataDa15782Bq *)(&bq1);
        vol = (AQDataDa15782Vol *)(&vol1);
        break;
    case DA_5782_TYPE_2:
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA2_5782_GENERAL, &gen2, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA2_5782_DRC, &drc2, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA2_5782_DPEQ, &dpeq2, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA2_5782_BQ, &bq2, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA2_5782_VOL, &vol2, 0, _gu4CurrentAqKey, 0);
        // AQDataDa15782* and AQDataDa25782* are always the same structure, so can cast.
        gen = (AQDataDa15782General *)(&gen2);
        drc = (AQDataDa15782Drc *)(&drc2);
        dpeq = (AQDataDa15782Dpeq *)(&dpeq2);
        bq = (AQDataDa15782Bq *)(&bq2);
        vol = (AQDataDa15782Vol *)(&vol2);
        break;
    case DA_5782_TYPE_3:
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA3_5782_GENERAL, &gen3, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA3_5782_DRC, &drc3, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA3_5782_DPEQ, &dpeq3, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA3_5782_BQ, &bq3, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA3_5782_VOL, &vol3, 0, _gu4CurrentAqKey, 0);
        // AQDataDa15782* and AQDataDa35782* are always the same structure, so can cast.
        gen = (AQDataDa15782General *)(&gen3);
        drc = (AQDataDa15782Drc *)(&drc3);
        dpeq = (AQDataDa15782Dpeq *)(&dpeq3);
        bq = (AQDataDa15782Bq *)(&bq3);
        vol = (AQDataDa15782Vol *)(&vol3);
        break;
    case DA_5782_TYPE_4:
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA4_5782_GENERAL, &gen4, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA4_5782_DRC, &drc4, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA4_5782_DPEQ, &dpeq4, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA4_5782_BQ, &bq4, 0, _gu4CurrentAqKey, 0);
        DrvCust_AQ_SetGet(AUD_DrvCust_AQ_Get_DA4_5782_VOL, &vol4, 0, _gu4CurrentAqKey, 0);
        // AQDataDa15782* and AQDataDa45782* are always the same structure, so can cast.
        gen = (AQDataDa15782General *)(&gen4);
        drc = (AQDataDa15782Drc *)(&drc4);
        dpeq = (AQDataDa15782Dpeq *)(&dpeq4);
        bq = (AQDataDa15782Bq *)(&bq4);
        vol = (AQDataDa15782Vol *)(&vol4);
        break;
    default:
        LOG(1, "[DAMP] invalid AmpTable=%d\n", pAmp->u1AmpTable);
        return -1;
    }
#if 0
    LOG(0, "---[DAMP]--------------------------------------\n");
    LOG(0, " gen->m_Da1GeneralBmmBq1B0 = 0x%08X\n", gen->m_Da1GeneralBmmBq1B0);
    LOG(0, " drc->m_Da1Drc1BqB0 = 0x%08X\n", drc->m_Da1Drc1BqB0);
    LOG(0, " dpeq->m_Da1DpeqBq1B0 = 0x%08X\n", dpeq->m_Da1DpeqBq1B0);
    LOG(0, " bq->m_Da1Bq1B0 = 0x%08X\n", bq->m_Da1Bq1B0);
    LOG(0, " vol->m_Da1ChVolume = 0x%08X\n", vol->m_Da1ChVolume);
    LOG(0, "---[DAMP]--------------------------------------\n");
#endif

	// ====== Book:0x8C Page:0x11 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x11);

	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmBq1B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:BQ 1 B0)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmBq1B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:BQ 1 B1)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmBq1B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:BQ 1 B2)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmBq1A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:BQ 1 A1)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmBq1A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:BQ 1 A2)

	// ====== Book:0x8C Page:0x12 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x12);

	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmSubBq1B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:CH-Sub BQ 1 B0)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmSubBq1B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:CH-Sub BQ 1 B1)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmSubBq1B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x4C, REG_VAL, 4);	// Addr(0x4C:CH-Sub BQ 1 B2)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmSubBq1A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x50, REG_VAL, 4);	// Addr(0x50:CH-Sub BQ 1 A1)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralBmmSubBq1A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x54, REG_VAL, 4);	// Addr(0x54:CH-Sub BQ 1 A2)

	// ====== Book:0x8C Page:0x13 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x13);

	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1BqB0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x30, REG_VAL, 4);	// Addr(0x30:BQ_B0)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1BqB1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x34, REG_VAL, 4);	// Addr(0x34:BQ_B1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1BqB2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:BQ_B2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1BqA1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, REG_VAL, 4);	// Addr(0x3C:BQ_A1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1BqA2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, REG_VAL, 4);	// Addr(0x40:BQ_A2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3BqB0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:BQ_B0)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3BqB1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:BQ_B1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3BqB2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:BQ_B2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3BqA1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:BQ_A1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3BqA2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:BQ_A2)

	// ====== Book:0x8C Page:0x14 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x14);

	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq1B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, REG_VAL, 4);	// Addr(0x08:BQ_1_B0)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq1B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, REG_VAL, 4);	// Addr(0x0C:BQ_1_B1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq1B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:BQ_1_B2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq1A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:BQ_1_A1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq1A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:BQ_1_A2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq2B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:BQ_2_B0)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq2B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:BQ_2_B1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq2B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:BQ_2_B2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq2A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:BQ_2_A1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Bq2A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:BQ_2_A2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq1B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:BQ 1 B0)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq1B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:BQ 1 B1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq1B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:BQ 1 B2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq1A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:BQ 1 A1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq1A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:BQ 1 A2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq2B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x6C, REG_VAL, 4);	// Addr(0x6C:BQ 2 B0)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq2B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x70, REG_VAL, 4);	// Addr(0x70:BQ 2 B1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq2B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x74, REG_VAL, 4);	// Addr(0x74:BQ 2 B2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq2A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x78, REG_VAL, 4);	// Addr(0x78:BQ 2 A1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqBq2A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x7C, REG_VAL, 4);	// Addr(0x7C:BQ 2 A2)

	// ====== Book:0x8C Page:0x15 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x15);

	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq1B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, REG_VAL, 4);	// Addr(0x08:BQ 1 B0)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq1B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, REG_VAL, 4);	// Addr(0x0C:BQ 1 B1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq1B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:BQ 1 B2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq1A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:BQ 1 A1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq1A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:BQ 1 A2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq2B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:BQ 2 B0)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq2B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:BQ 2 B1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq2B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:BQ 2 B2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq2A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:BQ 2 A1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLBq2A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:BQ 2 A2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq1B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x30, REG_VAL, 4);	// Addr(0x30:BQ 1 B0)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq1B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x34, REG_VAL, 4);	// Addr(0x34:BQ 1 B1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq1B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:BQ 1 B2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq1A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, REG_VAL, 4);	// Addr(0x3C:BQ 1 A1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq1A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, REG_VAL, 4);	// Addr(0x40:BQ 1 A2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq2B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:BQ 2 B0)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq2B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:BQ 2 B1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq2B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x4C, REG_VAL, 4);	// Addr(0x4C:BQ 2 B2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq2A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x50, REG_VAL, 4);	// Addr(0x50:BQ 2 A1)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHBq2A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x54, REG_VAL, 4);	// Addr(0x54:BQ 2 A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:CH-L_BQ_1_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:CH-L_BQ_1_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:CH-L_BQ_1_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:CH-L_BQ_1_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:CH-L_BQ_1_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x6C, REG_VAL, 4);	// Addr(0x6C:CH-L_BQ_2_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x70, REG_VAL, 4);	// Addr(0x70:CH-L_BQ_2_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x74, REG_VAL, 4);	// Addr(0x74:CH-L_BQ_2_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x78, REG_VAL, 4);	// Addr(0x78:CH-L_BQ_2_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x7C, REG_VAL, 4);	// Addr(0x7C:CH-L_BQ_2_A2)

	// ====== Book:0x8C Page:0x16 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x16);

	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, REG_VAL, 4);	// Addr(0x08:CH-L_BQ_3_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, REG_VAL, 4);	// Addr(0x0C:CH-L_BQ_3_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:CH-L_BQ_3_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:CH-L_BQ_3_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:CH-L_BQ_3_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:CH-L_BQ_4_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:CH-L_BQ_4_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:CH-L_BQ_4_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:CH-L_BQ_4_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:CH-L_BQ_4_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x30, REG_VAL, 4);	// Addr(0x30:CH-L_BQ_5_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x34, REG_VAL, 4);	// Addr(0x34:CH-L_BQ_5_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:CH-L_BQ_5_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, REG_VAL, 4);	// Addr(0x3C:CH-L_BQ_5_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, REG_VAL, 4);	// Addr(0x40:CH-L_BQ_5_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:CH-L_BQ_6_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:CH-L_BQ_6_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x4C, REG_VAL, 4);	// Addr(0x4C:CH-L_BQ_6_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x50, REG_VAL, 4);	// Addr(0x50:CH-L_BQ_6_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x54, REG_VAL, 4);	// Addr(0x54:CH-L_BQ_6_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:CH-L_BQ_7_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:CH-L_BQ_7_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:CH-L_BQ_7_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:CH-L_BQ_7_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:CH-L_BQ_7_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x6C, REG_VAL, 4);	// Addr(0x6C:CH-L_BQ_8_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x70, REG_VAL, 4);	// Addr(0x70:CH-L_BQ_8_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x74, REG_VAL, 4);	// Addr(0x74:CH-L_BQ_8_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x78, REG_VAL, 4);	// Addr(0x78:CH-L_BQ_8_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x7C, REG_VAL, 4);	// Addr(0x7C:CH-L_BQ_8_A2)

	// ====== Book:0x8C Page:0x17 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x17);

	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, REG_VAL, 4);	// Addr(0x08:CH-L_BQ_9_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, REG_VAL, 4);	// Addr(0x0C:CH-L_BQ_9_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:CH-L_BQ_9_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:CH-L_BQ_9_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:CH-L_BQ_9_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:CH-L_BQ_10_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:CH-L_BQ_10_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:CH-L_BQ_10_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:CH-L_BQ_10_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:CH-L_BQ_10_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x30, REG_VAL, 4);	// Addr(0x30:CH-L_BQ_11_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x34, REG_VAL, 4);	// Addr(0x34:CH-L_BQ_11_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:CH-L_BQ_11_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, REG_VAL, 4);	// Addr(0x3C:CH-L_BQ_11_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, REG_VAL, 4);	// Addr(0x40:CH-L_BQ_11_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:CH-L_BQ_12_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:CH-L_BQ_12_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x4C, REG_VAL, 4);	// Addr(0x4C:CH-L_BQ_12_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x50, REG_VAL, 4);	// Addr(0x50:CH-L_BQ_12_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x54, REG_VAL, 4);	// Addr(0x54:CH-L_BQ_12_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:CH-L_BQ_13_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:CH-L_BQ_13_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:CH-L_BQ_13_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:CH-L_BQ_13_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:CH-L_BQ_13_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x6C, REG_VAL, 4);	// Addr(0x6C:CH-L_BQ_14_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x70, REG_VAL, 4);	// Addr(0x70:CH-L_BQ_14_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x74, REG_VAL, 4);	// Addr(0x74:CH-L_BQ_14_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x78, REG_VAL, 4);	// Addr(0x78:CH-L_BQ_14_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x7C, REG_VAL, 4);	// Addr(0x7C:CH-L_BQ_14_A2)

	// ====== Book:0x8C Page:0x18 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x18);

	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, REG_VAL, 4);	// Addr(0x08:CH-L_BQ_15_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, REG_VAL, 4);	// Addr(0x0C:CH-L_BQ_15_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:CH-L_BQ_15_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:CH-L_BQ_15_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:CH-L_BQ_15_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:CH-R_BQ_1_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:CH-R_BQ_1_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:CH-R_BQ_1_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:CH-R_BQ_1_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq1A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:CH-R_BQ_1_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x30, REG_VAL, 4);	// Addr(0x30:CH-R_BQ_2_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x34, REG_VAL, 4);	// Addr(0x34:CH-R_BQ_2_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:CH-R_BQ_2_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, REG_VAL, 4);	// Addr(0x3C:CH-R_BQ_2_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq2A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, REG_VAL, 4);	// Addr(0x40:CH-R_BQ_2_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:CH-R_BQ_3_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:CH-R_BQ_3_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x4C, REG_VAL, 4);	// Addr(0x4C:CH-R_BQ_3_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x50, REG_VAL, 4);	// Addr(0x50:CH-R_BQ_3_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq3A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x54, REG_VAL, 4);	// Addr(0x54:CH-R_BQ_3_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:CH-R_BQ_4_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:CH-R_BQ_4_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:CH-R_BQ_4_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:CH-R_BQ_4_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq4A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:CH-R_BQ_4_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x6C, REG_VAL, 4);	// Addr(0x6C:CH-R_BQ_5_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x70, REG_VAL, 4);	// Addr(0x70:CH-R_BQ_5_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x74, REG_VAL, 4);	// Addr(0x74:CH-R_BQ_5_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x78, REG_VAL, 4);	// Addr(0x78:CH-R_BQ_5_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq5A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x7C, REG_VAL, 4);	// Addr(0x7C:CH-R_BQ_5_A2)

	// ====== Book:0x8C Page:0x19 ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x19);

	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, REG_VAL, 4);	// Addr(0x08:CH-R_BQ_6_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, REG_VAL, 4);	// Addr(0x0C:CH-R_BQ_6_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:CH-R_BQ_6_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:CH-R_BQ_6_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq6A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:CH-R_BQ_6_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:CH-R_BQ_7_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:CH-R_BQ_7_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:CH-R_BQ_7_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:CH-R_BQ_7_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq7A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:CH-R_BQ_7_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x30, REG_VAL, 4);	// Addr(0x30:CH-R_BQ_8_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x34, REG_VAL, 4);	// Addr(0x34:CH-R_BQ_8_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:CH-R_BQ_8_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, REG_VAL, 4);	// Addr(0x3C:CH-R_BQ_8_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq8A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, REG_VAL, 4);	// Addr(0x40:CH-R_BQ_8_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:CH-R_BQ_9_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:CH-R_BQ_9_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x4C, REG_VAL, 4);	// Addr(0x4C:CH-R_BQ_9_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x50, REG_VAL, 4);	// Addr(0x50:CH-R_BQ_9_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq9A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x54, REG_VAL, 4);	// Addr(0x54:CH-R_BQ_9_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:CH-R_BQ_10_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:CH-R_BQ_10_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:CH-R_BQ_10_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:CH-R_BQ_10_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq10A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:CH-R_BQ_10_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x6C, REG_VAL, 4);	// Addr(0x6C:CH-R_BQ_11_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x70, REG_VAL, 4);	// Addr(0x70:CH-R_BQ_11_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x74, REG_VAL, 4);	// Addr(0x74:CH-R_BQ_11_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x78, REG_VAL, 4);	// Addr(0x78:CH-R_BQ_11_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq11A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x7C, REG_VAL, 4);	// Addr(0x7C:CH-R_BQ_11_A2)

	// ====== Book:0x8C Page:0x1A ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x1A);

	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, REG_VAL, 4);	// Addr(0x08:CH-R_BQ_12_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, REG_VAL, 4);	// Addr(0x0C:CH-R_BQ_12_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:CH-R_BQ_12_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:CH-R_BQ_12_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq12A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:CH-R_BQ_12_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:CH-R_BQ_13_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:CH-R_BQ_13_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:CH-R_BQ_13_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:CH-R_BQ_13_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq13A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:CH-R_BQ_13_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x30, REG_VAL, 4);	// Addr(0x30:CH-R_BQ_14_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x34, REG_VAL, 4);	// Addr(0x34:CH-R_BQ_14_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:CH-R_BQ_14_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, REG_VAL, 4);	// Addr(0x3C:CH-R_BQ_14_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq14A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, REG_VAL, 4);	// Addr(0x40:CH-R_BQ_14_A2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:CH-R_BQ_15_B0)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:CH-R_BQ_15_B1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x4C, REG_VAL, 4);	// Addr(0x4C:CH-R_BQ_15_B2)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x50, REG_VAL, 4);	// Addr(0x50:CH-R_BQ_15_A1)
	_AMP_5782_SET_4(REG_VAL, bq->m_Da1Bq15A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x54, REG_VAL, 4);	// Addr(0x54:CH-R_BQ_15_A2)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralVolAlpha);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:Softening_Filter_Alpha)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralPseudo);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:pseudo96k)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1Energy);
	AUD_CUST_AMP_RegWrite(pAmp, 0x6C, REG_VAL, 4);	// Addr(0x6C:DRC1_Energy)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1Attack);
	AUD_CUST_AMP_RegWrite(pAmp, 0x70, REG_VAL, 4);	// Addr(0x70:DRC1_Attack)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1Decay);
	AUD_CUST_AMP_RegWrite(pAmp, 0x74, REG_VAL, 4);	// Addr(0x74:DRC1_Decay)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1K0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x78, REG_VAL, 4);	// Addr(0x78:K0_1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1K1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x7C, REG_VAL, 4);	// Addr(0x7C:K1_1)

	// ====== Book:0x8C Page:0x1B ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x1B);

	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1K2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, REG_VAL, 4);	// Addr(0x08:K2_1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1T1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, REG_VAL, 4);	// Addr(0x0C:T1_1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1T2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:T2_1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1Off1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:off1_1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1Off2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:off2_1)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Energy);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:DRC2_Energy)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Attack);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:DRC2_Attack)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Decay);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:DRC2_Decay)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2K0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:K0_2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2K1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:K1_2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2K2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x30, REG_VAL, 4);	// Addr(0x30:K2_2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2T1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x34, REG_VAL, 4);	// Addr(0x34:T1_2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2T2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:T2_2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Off1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, REG_VAL, 4);	// Addr(0x3C:off1_2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2Off2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, REG_VAL, 4);	// Addr(0x40:off2_2)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3Energy);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:DRC3_Energy)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3Attack);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:DRC3_Attack)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3Decay);
	AUD_CUST_AMP_RegWrite(pAmp, 0x4C, REG_VAL, 4);	// Addr(0x4C:DRC3_Decay)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3K0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x50, REG_VAL, 4);	// Addr(0x50:K0_3)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3K1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x54, REG_VAL, 4);	// Addr(0x54:K1_3)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3K2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:K2_3)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3T1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:T1_3)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3T2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:T2_3)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3Off1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:off_1_3)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3Off2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:off_2_3)

	// ====== Book:0x8C Page:0x1C ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x1C);

	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq1B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x6C, REG_VAL, 4);	// Addr(0x6C:BQ 1 B0)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq1B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x70, REG_VAL, 4);	// Addr(0x70:BQ 1 B1)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq1B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x74, REG_VAL, 4);	// Addr(0x74:BQ 1 B2)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq1A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x78, REG_VAL, 4);	// Addr(0x78:BQ 1 A1)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq1A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x7C, REG_VAL, 4);	// Addr(0x7C:BQ 1 A2)

	// ====== Book:0x8C Page:0x1D ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x1D);

	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq2B0);
	AUD_CUST_AMP_RegWrite(pAmp, 0x08, REG_VAL, 4);	// Addr(0x08:BQ 2 B0)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq2B1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x0C, REG_VAL, 4);	// Addr(0x0C:BQ 2 B1)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq2B2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:BQ 2 B2)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq2A1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:BQ 2 A1)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpBq2A2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:BQ 2 A2)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqAlpha);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:Alpha)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqGain);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:Gain)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqOffset);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:Offset)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSubCh);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:No Sub)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralThdBoost);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:CH-LR THD Boost)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralThdLVol);
	AUD_CUST_AMP_RegWrite(pAmp, 0x34, REG_VAL, 4);	// Addr(0x34:CH-L Fine Volume)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralThdRVol);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:CH-R Fine Volume)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc1MixerGain);
	AUD_CUST_AMP_RegWrite(pAmp, 0x40, REG_VAL, 4);	// Addr(0x40:DRC 1 Mixer Gain)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc2MixerGain);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:DRC 2 Mixer Gain)
	_AMP_5782_SET_4(REG_VAL, drc->m_Da1Drc3MixerGain);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:DRC 3 Mixer Gain)
	_AMP_5782_SET_4(REG_VAL, 0x00000000);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:Gang LR EQ)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralL2l);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:Left to Left)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralR2l);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:Right to Left)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralL2r);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:Left to Right)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralR2r);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:Right to Right)

	// ====== Book:0x8C Page:0x1E ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x1E);

	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralSpLv);
	AUD_CUST_AMP_RegWrite(pAmp, 0x10, REG_VAL, 4);	// Addr(0x10:Spatializer Level)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralDLfl);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:Digital Left from Left)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralDLfr);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:Digital Left from Right)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralDRfl);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:Digital Right from Left)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralDRfr);
	AUD_CUST_AMP_RegWrite(pAmp, 0x24, REG_VAL, 4);	// Addr(0x24:Digital Right from Right)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralALfl);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:Analog Left from Left)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralALfr);
	AUD_CUST_AMP_RegWrite(pAmp, 0x30, REG_VAL, 4);	// Addr(0x30:Analog Left from Right)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralARfl);
	AUD_CUST_AMP_RegWrite(pAmp, 0x38, REG_VAL, 4);	// Addr(0x38:Analog Right from Left)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralARfr);
	AUD_CUST_AMP_RegWrite(pAmp, 0x3C, REG_VAL, 4);	// Addr(0x3C:Analog Right from Right)
	_AMP_5782_SET_4(REG_VAL, vol->m_Da1ChVolume);
	AUD_CUST_AMP_RegWrite(pAmp, 0x44, REG_VAL, 4);	// Addr(0x44:CH-L_Volume)
	_AMP_5782_SET_4(REG_VAL, vol->m_Da1ChVolume);
	AUD_CUST_AMP_RegWrite(pAmp, 0x48, REG_VAL, 4);	// Addr(0x48:CH-R Volume)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqSenseScale);
	AUD_CUST_AMP_RegWrite(pAmp, 0x50, REG_VAL, 4);	// Addr(0x50:DPEQ Sense Scale)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqLowScale);
	AUD_CUST_AMP_RegWrite(pAmp, 0x54, REG_VAL, 4);	// Addr(0x54:DPEQ Low Scale)
	_AMP_5782_SET_4(REG_VAL, dpeq->m_Da1DpeqHighScale);
	AUD_CUST_AMP_RegWrite(pAmp, 0x58, REG_VAL, 4);	// Addr(0x58:DPEQ High Scale)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralThermal1);
	AUD_CUST_AMP_RegWrite(pAmp, 0x5C, REG_VAL, 4);	// Addr(0x5C:Thermal)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralThermal2);
	AUD_CUST_AMP_RegWrite(pAmp, 0x60, REG_VAL, 4);	// Addr(0x60:Thermal)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralThermal3);
	AUD_CUST_AMP_RegWrite(pAmp, 0x64, REG_VAL, 4);	// Addr(0x64:Thermal)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralThermal4);
	AUD_CUST_AMP_RegWrite(pAmp, 0x68, REG_VAL, 4);	// Addr(0x68:Thermal)

	// ====== Book:0x8C Page:0x1F ======
	_AMP_5782_Change_Book_And_Page(pAmp, AMP_5782_DSP_BOOK, 0x1F);

	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralAglAtkTh);
	AUD_CUST_AMP_RegWrite(pAmp, 0x14, REG_VAL, 4);	// Addr(0x14:Attack Threshold)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralAglSfa);
	AUD_CUST_AMP_RegWrite(pAmp, 0x18, REG_VAL, 4);	// Addr(0x18:Softening Filter Alpha)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralAglAtk);
	AUD_CUST_AMP_RegWrite(pAmp, 0x1C, REG_VAL, 4);	// Addr(0x1C:Attack Rate)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralAglEnable);
	AUD_CUST_AMP_RegWrite(pAmp, 0x20, REG_VAL, 4);	// Addr(0x20:AGL Enable)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralAglSfo);
	AUD_CUST_AMP_RegWrite(pAmp, 0x28, REG_VAL, 4);	// Addr(0x28:Softening Filter Omega)
	_AMP_5782_SET_4(REG_VAL, gen->m_Da1GeneralAglRel);
	AUD_CUST_AMP_RegWrite(pAmp, 0x2C, REG_VAL, 4);	// Addr(0x2C:Release Rate)

	_AMP_5782_Set_SWAP_FLAG(pAmp);

	return 0;
}

void AUD_CUST_AMP_5782_Init(AMP_DATA_T *pAmp)
{
//    LOG(0, "===== Enter: AUD_CUST_AMP_5782_Init() Ver.1.06\n");

    // wait 165ms before powersequence "DSP_Enable"
    x_thread_delay(165);

    // powersequence "DSP_Enable"
    _AMP_5782_Set_DSP_Enable(pAmp);

    // wait 50ms before powersequence "System_Reg"
    x_thread_delay(50);

    // powersequence "System_Reg"
    _AMP_5782_Set_System_Reg(pAmp);

    // wait 10ms before powersequence "DSP_Reg"
    x_thread_delay(10);

    // powersequence "DSP_Reg"
    _AMP_5782_Refresh_DSP_Reg(pAmp);

    // power up D-AMP
    _AMP_5782_Set_DSP_Enable(pAmp);
}

void AUD_CUST_AMP_5782_Mute(AMP_DATA_T *pAmp, AUD_CUST_AMP_MUTE_T mute)
{
    bool bIsMuteOn = false;

//    LOG(0, "@@@@@ Enter AUD_CUST_AMP_5782_Mute(%d)\n", mute);
    if (mute == AUD_CUST_AMP_MUTE) {
        bIsMuteOn = true;
	} else if (mute == AUD_CUST_AMP_UNMUTE) {
        bIsMuteOn = false;
	}
    _AMP_5782_Mute(pAmp, bIsMuteOn);
}

void AUD_CUST_AMP_5782_Refresh(AMP_DATA_T *pAmp)
{
    LOG(2, "Amp type is 5782\n");
    _AMP_5782_Refresh_DSP_Reg(pAmp);
}

void AUD_CUST_AMP_5782_Suspend(AMP_DATA_T *pAmp)
{
    LOG(0, "[DAMP] AUD_CUST_AMP_5782_Suspend()\n");
    _AMP_5782_PowerDown(pAmp);
}

static struct aud_cust_amp_func_tbl _r5782Funcs = 
{
    AUD_CUST_AMP_5782_Init,     //pfnCustInit;
    AUD_CUST_AMP_5782_Suspend,  //pfnCustSuspend;
    NULL,                       //pfnCustResume;
    AUD_CUST_AMP_5782_Mute,     //pfnCustMute;
    AUD_CUST_AMP_5782_Refresh,  //pfnCustRefresh
};

void AUD_CUST_AMP_RegistAmp_5782(AMP_DATA_T *pAmp)
{
    strncpy(pAmp->name, "T5782", sizeof(pAmp->name) - 1);
    pAmp->u4NotifyErrThreshold = NTFY_ERR_NUM_5782;

    pAmp->funcTbl = &_r5782Funcs;
}

// EOF
