#ifndef _HW_IFPLL_H_
#define _HW_IFPLL_H_

//Page HISTORY
#define IO_IFPLL_BASE (IO_VIRT + 0x33000)

//Page TABLE
// IFPLL
#define REG_IFPLL_CFG0 (IO_IFPLL_BASE + 0x500)
    #define FLD_RG_DMPLL_EN_LDO_TEST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_DMPLL_AMUX_SEL Fld(2,29,AC_MSKB3)//[30:29]
    #define FLD_RG_DMPLL_EN_AMUX Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_DMPLL_TEST Fld(9,19,AC_MSKW32)//[27:19]
    #define FLD_RG_DMPLL_PULL_H Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_DMPLL_PULL_L Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_DMPLL_PD_CLK_TAGC Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_DMPLL_EN_CP_TURBO Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_RG_SIF_CLK_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_RG_XBIST_TEST_LV Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_RG_XBIST_MUX_SEL_LV Fld(3,10,AC_MSKB1)//[12:10]
    #define FLD_RG_XBIST_PT_EN_LV Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_RG_DMPLL_PD_HV Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_RG_DMPLL_PD_LV Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_PD_BLOCK Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_PD_CLK_PDIV Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_PD_CLK_DIV14 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_PD_CLK_DIV10 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_RG_PD_CLK_DIV8 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_PD_CLK_DIV7 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_PD_CLK_DIV6 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_IFPLL_CFG1 (IO_IFPLL_BASE + 0x504)
    #define FLD_RG_PD_CLK_DIV5 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_PD_CLK_DIV4 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_PD_CLK_DIV3P5 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_PD_CLK_DIV3 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_PD_CLK_DIV2P5 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_PD_CLK_DIV2 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_PD_CLK_DIV1 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_DMPLL_REG_REF_SEL Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_DMPLL_PORST Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_DMPLL_EN_TESTVCO Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_DMPLL_ICTRL Fld(3,19,AC_MSKB2)//[21:19]
    #define FLD_RG_DMPLL_XTAL2ADC_SEL Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_DMPLL_ADC_CLK_PD Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_DMPLL_ADC_CLK_CC_MODE Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_DMPLL_ADC_CLK_DIVN Fld(6,10,AC_MSKB1)//[15:10]
    #define FLD_RG_DMPLL_LOOP_DIV_FIRST Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_RG_DMPLL_LOOP_DIVN Fld(8,1,AC_MSKW10)//[8:1]
    #define FLD_RG_DMPLL_OUTPUT_DIV_FIRST Fld(1,0,AC_MSKB0)//[0:0]
#define REG_IFPLL_CFG2 (IO_IFPLL_BASE + 0x508)
    #define FLD_RG_DMPLL_OUTPUT_DIV_SECOND Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_DMPLL_EN_LCKDET Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_DMPLL_REF_MODE Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_DMPLL_EN_DISC Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_DMPLL_CLK_RF_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_DMPLL_CLK_RF_SEL Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_RG_DMPLL_CLK_RF_TST Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_DMPLL_DIS_BGBIAS Fld(1,17,AC_MSKB2)//[17:17]
#define RGS_IFPLL_CFG0 (IO_IFPLL_BASE + 0x50C)
    #define FLD_RGS_LOCK Fld(1,31,AC_MSKB3)//[31:31]

// IFTOP
#define REG_IFTOP_CFG0 (IO_IFPLL_BASE + 0x600)
    #define FLD_RG_IFBGR_PI_PWD Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_IFV2I_ISEL Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_IFBGR_SEL Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_RG_TRIM_IFV2I Fld(5,16,AC_MSKB2)//[20:16]
    #define FLD_RG_IFBGR_RSV Fld(8,8,AC_FULLB1)//[15:8]
#define REG_IFTOP_CFG1 (IO_IFPLL_BASE + 0x604)
    #define FLD_RG_DMTOP_BG_PWD Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_RG_DMTOP_XTAL_GATING Fld(8,0,AC_FULLB0)//[7:0]
#define REG_IFTOP_CFG2 (IO_IFPLL_BASE + 0x608)
    #define FLD_RG_DMTOP_REV1 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_RG_DMTOP_REV0 Fld(16,0,AC_FULLW10)//[15:0]

#endif /* _HW_IFPLL_H_ */

