/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: brianpc.huang $
 * $Date: 2015/05/29 $
 * $RCSfile: drv_adcset.h,v $
 * $Revision: #1 $
 *
 *---------------------------------------------------------------------------*/

#ifndef _ADCSET_H_
#define _ADCSET_H_


/******************************************************************************
 * Header Files
 *****************************************************************************/
#include "typedef.h"
#include "feature.h"
#include "hw_vfe.h"

//#define ADAPTIVE_SLICER_TSET 1
#define CLI_CVBS 1
#define PD_ADC_ENABLE 1

//===================================================================
//  VFE GPIO Debug Monitor
//===================================================================
//#define VFE_GPIODEBUG 0
/*#if VFE_GPIODEBUG
// MT5388M1V1 Setting Pin setting refer driver/ckgen/Pinmux.c
#define VFE_GPIONum 4
#define VFE_GPIO_00 83 // O0N(GPIO83) NJP1 Pin01
#define VFE_GPIO_01 82 // O0P(GPIO82) NJP1 Pin02
#define VFE_GPIO_02 85 // O1N(GPIO85) NJP1 Pin03
#define VFE_GPIO_03 84 // O1P(GPIO84) NJP1 Pin04
INT32 VFE_GPIOPINTbl[VFE_GPIONum]={VFE_GPIO_00,VFE_GPIO_01,VFE_GPIO_02,VFE_GPIO_03};
#endif*/

enum {
	DISABLE,
	ENABLE
};
enum {
	SPREAD_CENTER,
	SPREAD_DOWN,
	SPREAD_UP
};
enum {
	POWER_ON,
	POWER_DOWN
};
enum {
	CLK_OF_CLKIN,
	CLK_OF_XTAL
};
enum {
	ADC0_CH0,
	ADC0_CH1
};

enum {
    CLAMP_OF_ALWAYS,
    CLAMP_OF_TVD3D,
    CLAMP_OF_HDTV,
    CLAMP_OF_VGA
};
enum {
    ADAPTIVE_SLICER_INI,
    ADAPTIVE_SLICER_STATE0,
    ADAPTIVE_SLICER_STATE1,
    ADAPTIVE_SLICER_STATE2,
    ADAPTIVE_SLICER_STATE3,
    ADAPTIVE_SLICER_STATE4,
    ADAPTIVE_SLICER_STATE5,
    ADAPTIVE_SLICER_STATE6,
    ADAPTIVE_SLICER_STATE7
};
enum {
    IPS_OTHER,		//input source don't use AD
    IPS_ATV,		//input source is ATV
    IPS_ATD,		//input source is ATD
    IPS_DTV,		//input source is DTV
    IPS_DTD,		//input source is DTD
    IPS_CVBS_A,		//input source is CVBS_A
    IPS_CVBS_B,		//input source is CVBS_B
    IPS_CVBS_A_B,		//input source is CVBS_A/CVBS_B
    IPS_MAX		//end of enum
};

//************************************************************************
//TVD AGC, 0x47 set Ch0 gain control from AGC_TVD3D
#define TVD3D_AGC 0x544
#define vDrvPGA0(bVAL) vWriteVDOINMsk(TVD3D_AGC,bVAL , 0xFF, 2)
#define vDrvPGA0A(bVAL) vWriteVDOINMsk(TVD3D_AGC,bVAL , 0xFF, 2)


extern UINT8 bAdaptiveSlicerStateMachine;	//set initial value in mode detect done

//********Function define ************************************/

void vDrvSetHDTVMux(UINT8 bVDOINPUT) ;
void vDrvSVdoEnable(void) ;
void vDrvSVdoDisable(void) ;
void vDrvBypPD(void);
void vDrvAvByp(void);
void vDrvSVdoByp(void);
void vDrvSetTVADC(UINT8 bVDOINPUT) ;
void vDrvADCDefaultSetting(void) ;
#if CLI_CVBS
void vDrvCVBSPGACheck(void);
void vDrvTargetBlankCheck(void);
void vDrvIOOffsetBlankCheck(void);
void vDrvPeakLimitCheck(UINT8 PYC);
void vDrvSVFTest(void);
#endif

void vDrvChACalonblank(void);
#ifdef __MODEL_slt__
extern BOOL fgCVBSFail;
#endif

void vDrvCVBSOffsetTest(void);
void vDrvADCOffsetCal(void) ;
void vDrvTVADCDefaultSetting(void) ;
void vDrvTVADCOffsetCal(void) ;
void vDrvCvbsAdcPD(void) ;
void vDrvCvbsVfePD(void) ;
void vDrvCvbsAdcPWON(void) ;
void vDrvCvbsVfePWON(void) ;
void vDrvCvbsAdcCal(void) ;
void	vDrvCvbsoffsetCal(void);
void vDrvHDTVADCDefaultSetting(void) ;
void vDrvHDTVADCOffsetCalDo(UINT8 bType) ;
void vDrvVGAPD(void);
void vDrvVGAPWON(void);
UINT8 bDrvHDADCGetVal(UINT8 bADC) ;

void vDrvSetHDTVADC(UINT8 bVDOINPUT) ;
void vDrvSetHDTVMux(UINT8 bVDOINPUT) ;
void vDrvHDTVADCOffsetCal(void) ;
void vDrvSetHDADCGainSrcDef(void) ;
void vDrvAllHDADCPow(UINT8 bPow) ;
UINT16 vDrvReadADC0(UINT8 bCH) ;

void vDrvReadADC0Register(void) ;

void vDrvTVADCOffsetCal(void) ;
void vDrvTVADC0CH0ClampOnBlankOffsetCal(void) ;
void vDrvTVADC0CH1ClampOnBottomOffsetCal(void) ;
#ifdef CC_SUPPORT_SIF_BYPASS
BOOL vDrvSetSIFADC(void);
void vScartSVInRFE(UINT8 status);
#endif
UINT16 wDrvOutputOffsetCal(UINT8 bCH,UINT16 wCLAMP) ;
void vDrvDFE(UINT16 wTARGET_BLANK) ;
//#ifdef CC_CLI
void vDrvTVDBlankLevel(UINT16 wTARGET_BLANK) ;
//#endif
void vDrvCalibrationDisable(UINT8 bCH, UINT8 bCLAMP) ;
void vDrvCalibrationEnable(UINT8 bCH, UINT8 bCLAMP) ;
void vDrvAAFCalibration(void) ;
//for lint
UINT16 wDrvReadADCBlank(void);
UINT16 wDrvReadADCBlankAve(void);
void vDrvSetPGAMauGainAGC2(void);
void vDrvPGAMaxGainMauAGC2(void);
void vDrvPGAMidGainMauAGC2(void);
void vDrvPGAMinGainMauAGC2(void);
void vDrvSetPGAAutoGainAGC2(void);
void vDrvChACalonBlankEnb(void);
void vDrvChACalonBlankDsb(void);
void vDrvInputOffsetCal(void);
void vDrvOutputOffsetCalNew(UINT16 wCLAMP);
void vDrvChACalonblank(void);


void vCust_R_Offset_Update(UINT8 bOffset) ;
void vCust_G_Offset_Update(UINT8 bOffset) ;
void vCust_B_Offset_Update(UINT8 bOffset) ;
void vCust_R_Gain_Update(UINT8 bGain) ;
void vCust_G_Gain_Update(UINT8 bGain) ;
void vCust_B_Gain_Update(UINT8 bGain) ;
void vCust_EBGain_OverRule_Update(UINT8 bNum) ; //kaloverrule
void vCust_Embedded_Gain(UINT8 bType);
UINT8 vCust_Get_Embedded_Gain(UINT8 Type,UINT8 Ch);


void vCust_Gain_OFFSet_Update(void);

UINT8 vCust_Current_Use_ADC_Read(UINT8 bType);
UINT8 vCust_R_Offset_Read(void) ;
UINT8 vCust_G_Offset_Read(void) ;
UINT8 vCust_B_Offset_Read(void) ;
UINT8 vCust_R_Gain_Read(void) ;
UINT8 vCust_G_Gain_Read(void) ;
UINT8 vCust_B_Gain_Read(void) ;
UINT8 vCust_R_MAX_Read(void);
UINT8 vCust_G_MAX_Read(void);
UINT8 vCust_B_MAX_Read(void);
UINT16 vCust_B_Blank_Read(void);
UINT16 vCust_G_Blank_Read(void);
UINT16 vCust_R_Blank_Read(void);
UINT16 vCust_B_Max_Read(void);
UINT16 vCust_G_Max_Read(void);
UINT16 vCust_R_Max_Read(void);
UINT8 vCust_EBGain_OverRule_Read(void) ; //kaloverrule

void vCust_R_MAX_Update(UINT8 value);
void vCust_G_MAX_Update(UINT8 value);
void vCust_B_MAX_Update(UINT8 value);
void vCust_clear_eeprom(UINT8 bValue);
void vCust_SOGY_VTH_Set(UINT32 dwLevel);
void vCust_SOGY_VTL_Set(UINT32 dwLevel);
void MTAL_SOGY_VTH_Set(UINT8 bLevel);
void MTAL_SOGY_VTL_Set(UINT8 bLevel);
BOOL MTAL_SetPGAGainOffsetInitVal(void);


void vCust_AutoColor_EEPROM_Enable(UINT8 bEnable);
UINT16 vCust_EEPROM_VGA_B_Gain_Read(void);
UINT16 vCust_EEPROM_VGA_G_Gain_Read(void);
UINT16 vCust_EEPROM_VGA_R_Gain_Read(void);
UINT16 vCust_EEPROM_VGA_B_Offset_Read(void);
UINT16 vCust_EEPROM_VGA_G_Offset_Read(void);
UINT16 vCust_EEPROM_VGA_R_Offset_Read(void);
UINT16 vCust_EEPROM_CMP_Y_Gain_Read(void);
UINT16 vCust_EEPROM_CMP_PB_Gain_Read(void);
UINT16 vCust_EEPROM_CMP_PR_Gain_Read(void);
UINT16 vCust_EEPROM_CMP_Y_Offset_Read(void);
UINT16 vCust_EEPROM_CMP_PB_Offset_Read(void);
UINT16 vCust_EEPROM_CMP_PR_Offset_Read(void);
UINT16 vCust_EEPROM_SCART_B_Gain_Read(void);
UINT16 vCust_EEPROM_SCART_G_Gain_Read(void);
UINT16 vCust_EEPROM_SCART_R_Gain_Read(void);
UINT16 vCust_EEPROM_SCART_B_Offset_Read(void);
UINT16 vCust_EEPROM_SCART_G_Offset_Read(void);
UINT16 vCust_EEPROM_SCART_R_Offset_Read(void);
UINT8 vCust_EEPROM_CMP_STATUS(void);
UINT8 vCust_EEPROM_VGA_STATUS(void);
UINT8 vCust_EEPROM_SCART_STATUS(void);

extern void vTvd3dATDInit(UINT8 bATDOnOff);

void vDrvHDTVADCDefaultSetting(void);


/*    AD control safe  routine */
INT32 AD_AcquireControl(void);
INT32 AD_ReleaseControl(void);


/*	Scart Setting for drv_scart.c		*/
void vScartVfeConnect(void) ;
void vScartVfeDisconnect(void) ;
void vScartMix(void) ;
void vScartSvConnect(void) ;


void vDrvAdativeSlicerState(void);
void vVFESLT_slicer_test_verC(void);

UINT16 AD_QueryInputSource(void);

extern UINT8 _bPGAGainOffsetHistory[4];
extern UINT8 _bEFUSE_AUTOCOLOR_READY;


#if SUPPORT_SET_SLICER
extern void vSetSOGSlicer(UINT8 pair) ;//wu add
#endif


#if ADAPTIVE_SLICER_ENABLE
extern UINT8 check_quaity_state;
extern void  vSliceQuality536x(void);
extern void vSetDefaultSlicer(void) ;
extern void vNextSlicer(UINT16 wTimeout) ;
extern void vResetSliceTimer(void) ;
#if (defined(ADAPTIVE_SLICER_DEFAULT_SETTING) || defined(ADAPTIVE_MONITOR_SLICER_MEASURE))
extern UINT8 _bCurSlicerIdx;
extern UINT8 _bCurSlicerIdx_best;
#endif
#if ADAPTIVE_MONITOR_SLICER_MEASURE
extern void vSetMONSlicer(UINT8 pair);
extern void vResetVLenSP0(void);
extern void vResetVLenSP2(void);
extern void vSetMONSlicer_Matrix(void);
//#if ADAPTIVE_MONITOR_SLICER_MEASURE_DEBUG
extern UINT8 bReadMONSlicer(void);
extern UINT8 bReadNewSlicer(void);
//#endif
#endif

#endif
#ifdef  ADAPTIVE_SINK_BTM_SETTING

extern UINT8 _bCurSinkIdx ;
extern UINT8 _bCurBTMIdx ;
void vSetDefaultSinkBTM(void);
void vResetSinkBTMTimer(void);
void vNextSinkBTMSetting(UINT16 wTimeout);

#endif

extern void vDrvSYNCSlicerWakeup(UINT8 bPow);


void vDrvSOY0EN(UINT8 bEn);
//void vDrvSOY1EN(UINT8 bEn);
void vDrvSOGEN(UINT8 bEn);

/*#if VFE_GPIODEBUG
extern void GPIO_H(UINT8 u1GpioNumIdx);
extern void GPIO_L(UINT8 u1GpioNumIdx);
#endif*/

//ChB AP control API
void vDrvSetTVDCHBSrcMux(UINT8 value);
void vDrvSetTVDCHBGain(UINT8 value);

#endif


