#ifndef _HW_HDCP22_H_
#define _HW_HDCP22_H_
#include "x_hal_5381.h"


/********************************IO_HDCPKEY_BASE**************************************/
#define IO_HDCPKEY_BASE (IO_VIRT+0x00600000+0x1000)


//Page HDMI21_HDCP_1
#define RX_1400_HDCPKEY (IO_HDCPKEY_BASE + 0x400)
    #define RX_1400_HDCPKEY_REG_HDCPKEY_RESERVED_00 Fld(6,10,AC_MSKB1)//[15:10]
    #define RX_1400_HDCPKEY_REG_XIU2HDCPKEY_ADR Fld(10,0,AC_MSKW10)//[9:0]
#define RX_1404_HDCPKEY (IO_HDCPKEY_BASE + 0x404)
    #define RX_1404_HDCPKEY_REG_HDCPKEY_RESERVED_01 Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_1404_HDCPKEY_REG_XIU2HDCPKEY_WD Fld(8,0,AC_FULLB0)//[7:0]
#define RX_1408_HDCPKEY (IO_HDCPKEY_BASE + 0x408)
    #define RX_1408_HDCPKEY_REG_HDCPKEY_RESERVED_02 Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_1408_HDCPKEY_REG_HDCPKEY2XIU_RD Fld(8,0,AC_FULLB0)//[7:0]
#define RX_1410_HDCPKEY (IO_HDCPKEY_BASE + 0x410)
    #define RX_1410_HDCPKEY_REG_XIU2MEM_ADDR0 Fld(10,0,AC_MSKW10)//[9:0]
#define RX_1414_HDCPKEY (IO_HDCPKEY_BASE + 0x414)
    #define RX_1414_HDCPKEY_REG_XIU2MEM_WDAT0 Fld(8,0,AC_FULLB0)//[7:0]
#define RX_1418_HDCPKEY (IO_HDCPKEY_BASE + 0x418)
    #define RX_1418_HDCPKEY_REG_XIU2MEM_ADDR1 Fld(10,0,AC_MSKW10)//[9:0]
#define RX_141C_HDCPKEY (IO_HDCPKEY_BASE + 0x41C)
    #define RX_141C_HDCPKEY_REG_XIU2MEM_WDAT1 Fld(8,0,AC_FULLB0)//[7:0]
#define RX_1438_HDCPKEY (IO_HDCPKEY_BASE + 0x438)
    #define RX_1438_HDCPKEY_REG_MEM2XIU_RDAT0 Fld(8,0,AC_FULLB0)//[7:0]
#define RX_143C_HDCPKEY (IO_HDCPKEY_BASE + 0x43C)
    #define RX_143C_HDCPKEY_REG_MEM2XIU_RDAT1 Fld(8,0,AC_FULLB0)//[7:0]


/********************************IO_HDCP_P0_BASE**************************************/
#define IO_HDCP_P0_BASE (IO_VIRT+0x00600000+0x2000)


#define RX_2400_HDCP_P0 (IO_HDCP_P0_BASE + 0x400)
    #define RX_2400_HDCP_P0_REG_HDCP_TESTBUS_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define RX_2400_HDCP_P0_REG_HDCP_IRQ_OUTPUT_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_2400_HDCP_P0_REG_HDCP_OESS_ENCEN_OPTION Fld(3,8,AC_MSKB1)//[10:8]
    #define RX_2400_HDCP_P0_REG_HDCP_CLEAR_RI Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_2400_HDCP_P0_REG_HDCP_800U_CNT_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_2400_HDCP_P0_REG_HDCP_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_2400_HDCP_P0_REG_EDGE_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_2400_HDCP_P0_REG_DDC_MASTER_FINISH Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_2400_HDCP_P0_REG_FILTER_ON Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_2400_HDCP_P0_REG_EN_SRAM_RD Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_2400_HDCP_P0_REG_HDCP_PIXCNT_INIT_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define RX_2404_HDCP_P0 (IO_HDCP_P0_BASE + 0x404)
    #define RX_2404_HDCP_P0_REG_HDCP_WR_CLEAR_RESERVE_0 Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_2404_HDCP_P0_REG_HDCP_WR_CLEAR_RESERVE_1 Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_2404_HDCP_P0_REG_READ_RI Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2404_HDCP_P0_REG_READ_R0 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_2404_HDCP_P0_REG_READ_BKSV Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_2404_HDCP_P0_REG_KM_GENERATED Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_2404_HDCP_P0_REG_AN_RCV Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_2404_HDCP_P0_REG_AKSV_RCV Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_2404_HDCP_P0_REG_STATUS_AUTH_ATTEMPT Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_2404_HDCP_P0_REG_STATUS_AUTH_FLAG Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_2404_HDCP_P0_REG_STATUS_HDCP_ENCDIS Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_2404_HDCP_P0_REG_STATUS_HDCP_ENCEN Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_2404_HDCP_P0_REG_STATUS_AVMUTE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_2404_HDCP_P0_REG_STATUS_HDCP_VERSION Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_2404_HDCP_P0_REG_STATUS_NEWAKSV_OR_RI Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_2404_HDCP_P0_REG_STATUS_HDMI_MODE_RPT Fld(1,0,AC_MSKB0)//[0:0]
#define RX_2408_HDCP_P0 (IO_HDCP_P0_BASE + 0x408)
    #define RX_2408_HDCP_P0_REG_WIN_END Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_2408_HDCP_P0_REG_WIN_START Fld(8,0,AC_FULLB0)//[7:0]
#define RX_240C_HDCP_P0 (IO_HDCP_P0_BASE + 0x40C)
    #define RX_240C_HDCP_P0_REG_HDCP_800U_CNT_VAL Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_240C_HDCP_P0_REG_SEL_76_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_240C_HDCP_P0_REG_ENABLE_FLAG_HYS_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_240C_HDCP_P0_REG_74PORT_DEBUG_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_240C_HDCP_P0_REG_HDCP_XOR_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_240C_HDCP_P0_REG_VSYNC_PROTECT_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_240C_HDCP_P0_REG_FRAME128_UPDATE_RI_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_240C_HDCP_P0_REG_VSYNC_POLARITY_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_240C_HDCP_P0_REG_HSYNC_POLARITY_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define RX_2424_HDCP_P0 (IO_HDCP_P0_BASE + 0x424)
    #define RX_2424_HDCP_P0_REG_HDCP_PACKEDPIXEL_MODE_CIPHER_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_2424_HDCP_P0_REG_HDCP_RESERVE_1 Fld(15,1,AC_MSKW10)//[15:1]
#define RX_2428_HDCP_P0 (IO_HDCP_P0_BASE + 0x428)
    #define RX_2428_HDCP_P0_REG_STATUS_HDCP_KM_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_242C_HDCP_P0 (IO_HDCP_P0_BASE + 0x42C)
    #define RX_242C_HDCP_P0_REG_STATUS_HDCP_KM_31_16 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2430_HDCP_P0 (IO_HDCP_P0_BASE + 0x430)
    #define RX_2430_HDCP_P0_REG_STATUS_HDCP_KM_47_32 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2434_HDCP_P0 (IO_HDCP_P0_BASE + 0x434)
    #define RX_2434_HDCP_P0_REG_STATUS_HDCP_KM_55_48 Fld(8,0,AC_FULLB0)//[7:0]
#define RX_2438_HDCP_P0 (IO_HDCP_P0_BASE + 0x438)
    #define RX_2438_HDCP_P0_REG_STATUS_HDCP_M0_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_243C_HDCP_P0 (IO_HDCP_P0_BASE + 0x43C)
    #define RX_243C_HDCP_P0_REG_STATUS_HDCP_M0_31_16 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2440_HDCP_P0 (IO_HDCP_P0_BASE + 0x440)
    #define RX_2440_HDCP_P0_REG_STATUS_HDCP_M0_47_32 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2444_HDCP_P0 (IO_HDCP_P0_BASE + 0x444)
    #define RX_2444_HDCP_P0_REG_STATUS_HDCP_M0_63_48 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2448_HDCP_P0 (IO_HDCP_P0_BASE + 0x448)
    #define RX_2448_HDCP_P0_REG_STATUS_HDCP_R0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_244C_HDCP_P0 (IO_HDCP_P0_BASE + 0x44C)
    #define RX_244C_HDCP_P0_REG_STATUS_HDCP_RI Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2450_HDCP_P0 (IO_HDCP_P0_BASE + 0x450)
    #define RX_2450_HDCP_P0_REG_STATUS_HDCP_PJ Fld(8,0,AC_FULLB0)//[7:0]
#define RX_2454_HDCP_P0 (IO_HDCP_P0_BASE + 0x454)
    #define RX_2454_HDCP_P0_REG_MASK_IRQ_LEVEL Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_2454_HDCP_P0_REG_MASK_IRQ_EDGE Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_2454_HDCP_P0_REG_MASK_IRQ_READ_RI Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2454_HDCP_P0_REG_MASK_IRQ_READ_R0 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_2454_HDCP_P0_REG_MASK_IRQ_READ_BKSV Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_2454_HDCP_P0_REG_MASK_IRQ_KM_GENERATED Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_2454_HDCP_P0_REG_MASK_IRQ_WRITE_AN Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_2454_HDCP_P0_REG_MASK_IRQ_WRITE_AKSV Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_2454_HDCP_P0_REG_HDCP_X74_INT_FINAL_STATUS Fld(2,6,AC_MSKB0)//[7:6]
    #define RX_2454_HDCP_P0_REG_HDCP_X74_INT_MASK Fld(2,4,AC_MSKB0)//[5:4]
    #define RX_2454_HDCP_P0_REG_HDCP_X74_INT_FORCE Fld(2,2,AC_MSKB0)//[3:2]
    #define RX_2454_HDCP_P0_REG_HDCP_X74_INT_CLR Fld(2,0,AC_MSKB0)//[1:0]
#define RX_2458_HDCP_P0 (IO_HDCP_P0_BASE + 0x458)
    #define RX_2458_HDCP_P0_REG_INT_ID1 Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_2458_HDCP_P0_REG_INT_ID0 Fld(8,0,AC_FULLB0)//[7:0]
#define RX_245C_HDCP_P0 (IO_HDCP_P0_BASE + 0x45C)
    #define RX_245C_HDCP_P0_REG_HDCP_RESERVE_3 Fld(2,14,AC_MSKB1)//[15:14]
    #define RX_245C_HDCP_P0_REG_NO_INPUT_RST_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_245C_HDCP_P0_REG_CLK_UNSTABLE_RST_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_245C_HDCP_P0_REG_DE_UNSTABLE_RST_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_245C_HDCP_P0_REG_DDC_HDCP_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_245C_HDCP_P0_REG_CPU_ADR_REG Fld(10,0,AC_MSKW10)//[9:0]
#define RX_2460_HDCP_P0 (IO_HDCP_P0_BASE + 0x460)
    #define RX_2460_HDCP_P0_REG_HDCP_DATA_PORT_RD Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_2460_HDCP_P0_REG_CPU_WDATA_REG Fld(8,0,AC_FULLB0)//[7:0]
#define RX_2464_HDCP_P0 (IO_HDCP_P0_BASE + 0x464)
    #define RX_2464_HDCP_P0_REG_ENWRITE_HDCP Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_2464_HDCP_P0_REG_HDCP_SRAM_ACCESS Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_2464_HDCP_P0_REG_DDC_FILTER_ON Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2464_HDCP_P0_REG_FILTER_MSB Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_2464_HDCP_P0_REG_CHK_START Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_2464_HDCP_P0_REG_DDC_BUSY Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_2464_HDCP_P0_REG_SLEW_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define RX_2464_HDCP_P0_REG_CPU_WR_BUSY_HDCP Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_2464_HDCP_P0_REG_CPU_RD_BUSY_HDCP Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_2464_HDCP_P0_REG_LOAD_ADR_P Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_2464_HDCP_P0_REG_HDCP_DATA_WR_P Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_2464_HDCP_P0_REG_HDCP_DATA_RD_P Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_2464_HDCP_P0_REG_HDCP_RESERVED_1 Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_2464_HDCP_P0_REG_XIU2HDCPKEY_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_2464_HDCP_P0_REG_FIX_NO_HSYNC Fld(1,0,AC_MSKB0)//[0:0]
#define RX_2468_HDCP_P0 (IO_HDCP_P0_BASE + 0x468)
    #define RX_2468_HDCP_P0_REG_STATUS_HDCP_RESERVE_3 Fld(2,14,AC_MSKB1)//[15:14]
    #define RX_2468_HDCP_P0_REG_WIN_OF_OPP_STATUS Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2468_HDCP_P0_REG_HDCP_FSM_STATUS Fld(5,8,AC_MSKB1)//[12:8]
    #define RX_2468_HDCP_P0_REG_HDCP_FRAME_CNT_STATUS Fld(7,1,AC_MSKB0)//[7:1]
    #define RX_2468_HDCP_P0_REG_HDCP_KEY_SRAM_BIST_STATUS Fld(1,0,AC_MSKB0)//[0:0]
#define RX_246C_HDCP_P0 (IO_HDCP_P0_BASE + 0x46C)
    #define RX_246C_HDCP_P0_REG_STATUS_HDCP_RESERVE_4 Fld(4,12,AC_MSKB1)//[15:12]
    #define RX_246C_HDCP_P0_REG_VSYNC_DET_STATUS Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_246C_HDCP_P0_REG_HSYNC_DET_STATUS Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_246C_HDCP_P0_REG_ENC_EN_STATUS Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_246C_HDCP_P0_REG_ENC_DIS_STATUS Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_246C_HDCP_P0_REG_HDCP_WIN_OPP_CNT Fld(8,0,AC_FULLB0)//[7:0]
#define RX_2470_HDCP_P0 (IO_HDCP_P0_BASE + 0x470)
    #define RX_2470_HDCP_P0_REG_ISLAND_CNT_ERR Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_2470_HDCP_P0_REG_ISLAND_CNT Fld(8,0,AC_FULLB0)//[7:0]
#define RX_2474_HDCP_P0 (IO_HDCP_P0_BASE + 0x474)
    #define RX_2474_HDCP_P0_REG_HDCP_MODE_CHANGE_EXIT_FSM Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2474_HDCP_P0_REG_HDCP_REKEY_FAIL_CYCLE_LT56 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_2474_HDCP_P0_REG_HDCP_REKEY_CNT Fld(12,0,AC_MSKW10)//[11:0]
#define RX_2478_HDCP_P0 (IO_HDCP_P0_BASE + 0x478)
    #define RX_2478_HDCP_P0_REG_HDCP_AUTH_MASK_ODD_DE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_2478_HDCP_P0_REG_CIPHER_57T_SUPPORT Fld(1,1,AC_MSKB0)//[1:1]
#define RX_247C_HDCP_P0 (IO_HDCP_P0_BASE + 0x47C)
    #define RX_247C_HDCP_P0_REG_HDCP_DBG_TST Fld(8,8,AC_FULLB1)//[15:8]
#define RX_2530_HDCP_P0 (IO_HDCP_P0_BASE + 0x530)
    #define RX_2530_HDCP_P0_REG_DEBUG_BUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2534_HDCP_P0 (IO_HDCP_P0_BASE + 0x534)
    #define RX_2534_HDCP_P0_REG_DEBUG_BUS_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_2534_HDCP_P0_REG_DEBUG_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define RX_2538_HDCP_P0 (IO_HDCP_P0_BASE + 0x538)
    #define RX_2538_HDCP_P0_REG_HDCP22_SKE_SETTING Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_2538_HDCP_P0_REG_ENB_AKE_INIT_AT_CLR_SKE_STATUS Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_2538_HDCP_P0_REG_ENB_NO_HDCP22_CAPABILITY_AT_CLR_SKE_STATUS Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_2538_HDCP_P0_REG_HDCP22_KEYFIFO_EVER_OVERFLOW_CLEAR Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_2538_HDCP_P0_REG_HDCP22_CIPHER_STATUS_CLEAR Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_2538_HDCP_P0_REG_HDCP22_AES_CIPHER_KEY_CHANNEL_ORDER_SWAP Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_2538_HDCP_P0_REG_HDCP22_AES_CIPHER_KEY_BYTE_ORDER_SWAP Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_2538_HDCP_P0_REG_COUNT_LD Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_2538_HDCP_P0_REG_COUNT_SW Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_2538_HDCP_P0_REG_CPPKT_BYTE_SWAP Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_2538_HDCP_P0_REG_EN_RESET_AES_AT_FRAME_KEY Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_2538_HDCP_P0_REG_HDCP22_FSM_NOT_IN_SPEC_DIS Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_2538_HDCP_P0_REG_HDCP22_ASKV_INIT_CLR_AUTH_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_2538_HDCP_P0_REG_HDCP22_TX_5V_RST_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2538_HDCP_P0_REG_HDCP22_AKE_STOP_CNT_BCHERR_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_2538_HDCP_P0_REG_RESERVED Fld(1,15,AC_MSKB1)//[15:15]
#define RX_253C_HDCP_P0 (IO_HDCP_P0_BASE + 0x53C)
    #define RX_253C_HDCP_P0_REG_HDCP22_AUTH_STATUS Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_253C_HDCP_P0_REG_HDCP22_KEYFIFO_EVER_OVERFLOW Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_253C_HDCP_P0_REG_ST_EVER_AVMUTE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_253C_HDCP_P0_REG_ST_EVER_ENC_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_253C_HDCP_P0_REG_ST_EVER_ENC_DIS Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_253C_HDCP_P0_REG_ST_EVER_CLR_FRAMECTR Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_253C_HDCP_P0_REG_ST_EVER_UPD_INPUTCTR Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_253C_HDCP_P0_REG_STREAM_ID Fld(3,7,AC_MSKW10)//[9:7]
    #define RX_253C_HDCP_P0_REG_ST_EVER_HD22_KEYFIFO_UF Fld(1,10,AC_MSKB1)//[10:10]
#define RX_2540_HDCP_P0 (IO_HDCP_P0_BASE + 0x540)
    #define RX_2540_HDCP_P0_REG_INPUT_CNT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2544_HDCP_P0 (IO_HDCP_P0_BASE + 0x544)
    #define RX_2544_HDCP_P0_REG_INPUT_CNT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2548_HDCP_P0 (IO_HDCP_P0_BASE + 0x548)
    #define RX_2548_HDCP_P0_REG_INPUT_CNT_2 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_254C_HDCP_P0 (IO_HDCP_P0_BASE + 0x54C)
    #define RX_254C_HDCP_P0_REG_INPUT_CNT_3 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2550_HDCP_P0 (IO_HDCP_P0_BASE + 0x550)
    #define RX_2550_HDCP_P0_REG_STREAM_CNT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2554_HDCP_P0 (IO_HDCP_P0_BASE + 0x554)
    #define RX_2554_HDCP_P0_REG_STREAM_CNT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2558_HDCP_P0 (IO_HDCP_P0_BASE + 0x558)
    #define RX_2558_HDCP_P0_REG_DIS_UPD_FRAMECNT_BY_CPPKT Fld(1,0,AC_MSKB0)//[0:0]
#define RX_2568_HDCP_P0 (IO_HDCP_P0_BASE + 0x568)
    #define RX_2568_HDCP_P0_REG_MESSAGE_LENGTH_CNT_UPDATE_SEL Fld(2,0,AC_MSKB0)//[1:0]
    #define RX_2568_HDCP_P0_REG_MESSAGE_LENGTH_MASK_CTRL Fld(2,2,AC_MSKB0)//[3:2]
    #define RX_2568_HDCP_P0_REG_MESSAGE_LENGTH_UPDATE_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_2568_HDCP_P0_REG_MESSAGE_LENGTH_UPDATE_PULSE_QUEUE Fld(1,15,AC_MSKB1)//[15:15]
#define RX_256C_HDCP_P0 (IO_HDCP_P0_BASE + 0x56C)
    #define RX_256C_HDCP_P0_REG_MESSAGE_LENGTH_TIME_OUT_VAL Fld(16,0,AC_FULLW10)//[15:0]
#define RX_2580_HDCP_P0 (IO_HDCP_P0_BASE + 0x580)
    #define RX_2580_HDCP_P0_REG_WCMD_LENGTH Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_2580_HDCP_P0_REG_SRAM_SD_EN_MSG_FIFO Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2580_HDCP_P0_REG_RST_REQ Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_2580_HDCP_P0_REG_RST_SM Fld(1,15,AC_MSKB1)//[15:15]
#define RX_2584_HDCP_P0 (IO_HDCP_P0_BASE + 0x584)
    #define RX_2584_HDCP_P0_REG_RCMD_LENGTH Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_2584_HDCP_P0_REG_MSG_FIFO_BIST_FAIL Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2584_HDCP_P0_REG_DIS_IIC Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_2584_HDCP_P0_REG_DIS_XIU Fld(1,15,AC_MSKB1)//[15:15]
#define RX_2588_HDCP_P0 (IO_HDCP_P0_BASE + 0x588)
    #define RX_2588_HDCP_P0_REG_HDCP_V22_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_2588_HDCP_P0_REG_HDCP_V22_OV_VALUE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_2588_HDCP_P0_REG_ADVANCE_CIPHER_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_2588_HDCP_P0_REG_ADVANCE_CIPHER_OV_VALUE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_2588_HDCP_P0_REG_MESSAGE_BURST_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_2588_HDCP_P0_REG_MESSAGE_READ_ABORT_REAUTH Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_2588_HDCP_P0_REG_HDCP_V22_CLR Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_2588_HDCP_P0_REG_HDCP_V22_READY Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_2588_HDCP_P0_REG_MESSAGE_ID Fld(8,8,AC_FULLB1)//[15:8]
#define RX_258C_HDCP_P0 (IO_HDCP_P0_BASE + 0x58C)
    #define RX_258C_HDCP_P0_REG_MESSAGE_LENGTH Fld(10,0,AC_MSKW10)//[9:0]
#define RX_2590_HDCP_P0 (IO_HDCP_P0_BASE + 0x590)
    #define RX_2590_HDCP_P0_REG_MESSAGE_LENGTH_RECEIVE Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_2590_HDCP_P0_REG_REAUTH_SET Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_2590_HDCP_P0_REG_MESSAGE_LENGTH_CLR_BY_AKE_INT Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2590_HDCP_P0_REG_MESSAGE_READ_AUTO_CLR_READY_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_2590_HDCP_P0_REG_MESSAGE_LENGTH_UPDATE Fld(1,15,AC_MSKB1)//[15:15]
#define RX_2594_HDCP_P0 (IO_HDCP_P0_BASE + 0x594)
    #define RX_2594_HDCP_P0_REG_BCH_ERROR_CNT_THR Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_2594_HDCP_P0_REG_BCH_ERROR_CNT_CLR Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_2594_HDCP_P0_REG_LINK_INTEGRITY_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_2594_HDCP_P0_REG_REAUTH_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_2594_HDCP_P0_REG_REAUTH_OV_VALUE Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_2594_HDCP_P0_REG_REAUTH_CLR Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_2594_HDCP_P0_REG_NO_INPUT_REAUTH Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_2594_HDCP_P0_REG_KSV_FIFO_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_2594_HDCP_P0_REG_CROSS_ADR_READ_EN Fld(1,15,AC_MSKB1)//[15:15]
#define RX_2598_HDCP_P0 (IO_HDCP_P0_BASE + 0x598)
    #define RX_2598_HDCP_P0_REG_ACK_MESSAGE_FIFO_READ_ABORT Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_2598_HDCP_P0_REG_ACK_AKE_INIT Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_2598_HDCP_P0_REG_ACK_MESSAGE_WRITE_DONE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_2598_HDCP_P0_REG_ACK_MESSAGE_READ_DONE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_2598_HDCP_P0_REG_ACK_MESSAGE_WRITE_START Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_2598_HDCP_P0_REG_ACK_MESSAGE_READ_START Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_2598_HDCP_P0_REG_PKT_OVERLAP_KEEPOUT Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_2598_HDCP_P0_REG_READ_HDCP2_VER Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_2598_HDCP_P0_REG_HDCP_V22_INTERRUPT_STATUS_RESERVED Fld(8,8,AC_FULLB1)//[15:8]
#define RX_259C_HDCP_P0 (IO_HDCP_P0_BASE + 0x59C)
    #define RX_259C_HDCP_P0_REG_ACK_MESSAGE_FIFO_READ_ABORT_MASK Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_259C_HDCP_P0_REG_ACK_AKE_INIT_MASK Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_259C_HDCP_P0_REG_ACK_MESSAGE_WRITE_DONE_MASK Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_259C_HDCP_P0_REG_ACK_MESSAGE_READ_DONE_MASK Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_259C_HDCP_P0_REG_ACK_MESSAGE_WRITE_START_MASK Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_259C_HDCP_P0_REG_ACK_MESSAGE_READ_START_MASK Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_259C_HDCP_P0_REG_PKT_OVERLAP_KEEPOUT_MASK Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_259C_HDCP_P0_REG_READ_HDCP2_VER_MASK Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_259C_HDCP_P0_REG_HDCP_V22_INTERRUPT_MASK_RESERVED Fld(8,8,AC_FULLB1)//[15:8]
#define RX_25A0_HDCP_P0 (IO_HDCP_P0_BASE + 0x5A0)
    #define RX_25A0_HDCP_P0_REG_IIC2MEM_RADDR_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_25A0_HDCP_P0_REG_IIC2MEM_RADDR Fld(10,0,AC_MSKW10)//[9:0]
#define RX_25EC_HDCP_P0 (IO_HDCP_P0_BASE + 0x5EC)
    #define RX_25EC_HDCP_P0_REG_8P_HDMI_MODE_TIMEOUT_TH Fld(4,0,AC_MSKB0)//[3:0]
    #define RX_25EC_HDCP_P0_REG_HDCP_V22_ENABLE Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_25EC_HDCP_P0_REG_PKT_EVENT_SRC Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_25EC_HDCP_P0_REG_HDCP22_NO_INPUT_RST_EN Fld(1,15,AC_MSKB1)//[15:15]
#define RX_25F0_HDCP_P0 (IO_HDCP_P0_BASE + 0x5F0)
    #define RX_25F0_HDCP_P0_REG_8P_DE_PERIOD Fld(14,0,AC_MSKW10)//[13:0]
    #define RX_25F0_HDCP_P0_REG_8P_DE_CHANGE Fld(1,14,AC_MSKB1)//[14:14]
#define RX_25F4_HDCP_P0 (IO_HDCP_P0_BASE + 0x5F4)
    #define RX_25F4_HDCP_P0_REG_HDCP_8P_HW_CONTROL Fld(16,0,AC_FULLW10)//[15:0]
#define RX_25F8_HDCP_P0 (IO_HDCP_P0_BASE + 0x5F8)
    #define RX_25F8_HDCP_P0_REG_8P_DEBUG_BUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_25FC_HDCP_P0 (IO_HDCP_P0_BASE + 0x5FC)
    #define RX_25FC_HDCP_P0_REG_8P_DEBUG_BUS_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_25FC_HDCP_P0_REG_8P_DEBUG_SEL Fld(8,8,AC_FULLB1)//[15:8]


/********************************IO_HDCP_P1_BASE**************************************/
#define IO_HDCP_P1_BASE (IO_VIRT+0x00600000+0x3000)


#define RX_3A00_HDCP_P1 (IO_HDCP_P1_BASE + 0xA00)
    #define RX_3A00_HDCP_P1_REG_HDCP_TESTBUS_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define RX_3A00_HDCP_P1_REG_HDCP_IRQ_OUTPUT_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_3A00_HDCP_P1_REG_HDCP_OESS_ENCEN_OPTION Fld(3,8,AC_MSKB1)//[10:8]
    #define RX_3A00_HDCP_P1_REG_HDCP_CLEAR_RI Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_3A00_HDCP_P1_REG_HDCP_800U_CNT_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_3A00_HDCP_P1_REG_HDCP_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_3A00_HDCP_P1_REG_EDGE_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_3A00_HDCP_P1_REG_DDC_MASTER_FINISH Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_3A00_HDCP_P1_REG_FILTER_ON Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_3A00_HDCP_P1_REG_EN_SRAM_RD Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_3A00_HDCP_P1_REG_HDCP_PIXCNT_INIT_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define RX_3A04_HDCP_P1 (IO_HDCP_P1_BASE + 0xA04)
    #define RX_3A04_HDCP_P1_REG_HDCP_WR_CLEAR_RESERVE_0 Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_3A04_HDCP_P1_REG_HDCP_WR_CLEAR_RESERVE_1 Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_3A04_HDCP_P1_REG_READ_RI Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3A04_HDCP_P1_REG_READ_R0 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_3A04_HDCP_P1_REG_READ_BKSV Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_3A04_HDCP_P1_REG_KM_GENERATED Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_3A04_HDCP_P1_REG_AN_RCV Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_3A04_HDCP_P1_REG_AKSV_RCV Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_3A04_HDCP_P1_REG_STATUS_AUTH_ATTEMPT Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_3A04_HDCP_P1_REG_STATUS_AUTH_FLAG Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_3A04_HDCP_P1_REG_STATUS_HDCP_ENCDIS Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_3A04_HDCP_P1_REG_STATUS_HDCP_ENCEN Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_3A04_HDCP_P1_REG_STATUS_AVMUTE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_3A04_HDCP_P1_REG_STATUS_HDCP_VERSION Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_3A04_HDCP_P1_REG_STATUS_NEWAKSV_OR_RI Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_3A04_HDCP_P1_REG_STATUS_HDMI_MODE_RPT Fld(1,0,AC_MSKB0)//[0:0]
#define RX_3A08_HDCP_P1 (IO_HDCP_P1_BASE + 0xA08)
    #define RX_3A08_HDCP_P1_REG_WIN_END Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_3A08_HDCP_P1_REG_WIN_START Fld(8,0,AC_FULLB0)//[7:0]
#define RX_3A0C_HDCP_P1 (IO_HDCP_P1_BASE + 0xA0C)
    #define RX_3A0C_HDCP_P1_REG_HDCP_800U_CNT_VAL Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_3A0C_HDCP_P1_REG_SEL_76_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_3A0C_HDCP_P1_REG_ENABLE_FLAG_HYS_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_3A0C_HDCP_P1_REG_74PORT_DEBUG_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_3A0C_HDCP_P1_REG_HDCP_XOR_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_3A0C_HDCP_P1_REG_VSYNC_PROTECT_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_3A0C_HDCP_P1_REG_FRAME128_UPDATE_RI_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_3A0C_HDCP_P1_REG_VSYNC_POLARITY_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_3A0C_HDCP_P1_REG_HSYNC_POLARITY_SEL Fld(1,0,AC_MSKB0)//[0:0]

    //Page HDMI21_HDCP_2
#define RX_3A24_HDCP_P1 (IO_HDCP_P1_BASE + 0xA24)
    #define RX_3A24_HDCP_P1_REG_HDCP_PACKEDPIXEL_MODE_CIPHER_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_3A24_HDCP_P1_REG_HDCP_RESERVE_1 Fld(15,1,AC_MSKW10)//[15:1]
#define RX_3A28_HDCP_P1 (IO_HDCP_P1_BASE + 0xA28)
    #define RX_3A28_HDCP_P1_REG_STATUS_HDCP_KM_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3A2C_HDCP_P1 (IO_HDCP_P1_BASE + 0xA2C)
    #define RX_3A2C_HDCP_P1_REG_STATUS_HDCP_KM_31_16 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3A30_HDCP_P1 (IO_HDCP_P1_BASE + 0xA30)
    #define RX_3A30_HDCP_P1_REG_STATUS_HDCP_KM_47_32 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3A34_HDCP_P1 (IO_HDCP_P1_BASE + 0xA34)
    #define RX_3A34_HDCP_P1_REG_STATUS_HDCP_KM_55_48 Fld(8,0,AC_FULLB0)//[7:0]
#define RX_3A38_HDCP_P1 (IO_HDCP_P1_BASE + 0xA38)
    #define RX_3A38_HDCP_P1_REG_STATUS_HDCP_M0_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3A3C_HDCP_P1 (IO_HDCP_P1_BASE + 0xA3C)
    #define RX_3A3C_HDCP_P1_REG_STATUS_HDCP_M0_31_16 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3A40_HDCP_P1 (IO_HDCP_P1_BASE + 0xA40)
    #define RX_3A40_HDCP_P1_REG_STATUS_HDCP_M0_47_32 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3A44_HDCP_P1 (IO_HDCP_P1_BASE + 0xA44)
    #define RX_3A44_HDCP_P1_REG_STATUS_HDCP_M0_63_48 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3A48_HDCP_P1 (IO_HDCP_P1_BASE + 0xA48)
    #define RX_3A48_HDCP_P1_REG_STATUS_HDCP_R0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3A4C_HDCP_P1 (IO_HDCP_P1_BASE + 0xA4C)
    #define RX_3A4C_HDCP_P1_REG_STATUS_HDCP_RI Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3A50_HDCP_P1 (IO_HDCP_P1_BASE + 0xA50)
    #define RX_3A50_HDCP_P1_REG_STATUS_HDCP_PJ Fld(8,0,AC_FULLB0)//[7:0]
#define RX_3A54_HDCP_P1 (IO_HDCP_P1_BASE + 0xA54)
    #define RX_3A54_HDCP_P1_REG_MASK_IRQ_LEVEL Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_3A54_HDCP_P1_REG_MASK_IRQ_EDGE Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_3A54_HDCP_P1_REG_MASK_IRQ_READ_RI Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3A54_HDCP_P1_REG_MASK_IRQ_READ_R0 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_3A54_HDCP_P1_REG_MASK_IRQ_READ_BKSV Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_3A54_HDCP_P1_REG_MASK_IRQ_KM_GENERATED Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_3A54_HDCP_P1_REG_MASK_IRQ_WRITE_AN Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_3A54_HDCP_P1_REG_MASK_IRQ_WRITE_AKSV Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_3A54_HDCP_P1_REG_HDCP_X74_INT_FINAL_STATUS Fld(2,6,AC_MSKB0)//[7:6]
    #define RX_3A54_HDCP_P1_REG_HDCP_X74_INT_MASK Fld(2,4,AC_MSKB0)//[5:4]
    #define RX_3A54_HDCP_P1_REG_HDCP_X74_INT_FORCE Fld(2,2,AC_MSKB0)//[3:2]
    #define RX_3A54_HDCP_P1_REG_HDCP_X74_INT_CLR Fld(2,0,AC_MSKB0)//[1:0]
#define RX_3A58_HDCP_P1 (IO_HDCP_P1_BASE + 0xA58)
    #define RX_3A58_HDCP_P1_REG_INT_ID1 Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_3A58_HDCP_P1_REG_INT_ID0 Fld(8,0,AC_FULLB0)//[7:0]
#define RX_3A5C_HDCP_P1 (IO_HDCP_P1_BASE + 0xA5C)
    #define RX_3A5C_HDCP_P1_REG_HDCP_RESERVE_3 Fld(2,14,AC_MSKB1)//[15:14]
    #define RX_3A5C_HDCP_P1_REG_NO_INPUT_RST_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3A5C_HDCP_P1_REG_CLK_UNSTABLE_RST_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_3A5C_HDCP_P1_REG_DE_UNSTABLE_RST_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_3A5C_HDCP_P1_REG_DDC_HDCP_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_3A5C_HDCP_P1_REG_CPU_ADR_REG Fld(10,0,AC_MSKW10)//[9:0]
#define RX_3A60_HDCP_P1 (IO_HDCP_P1_BASE + 0xA60)
    #define RX_3A60_HDCP_P1_REG_HDCP_DATA_PORT_RD Fld(8,8,AC_FULLB1)//[15:8]
    #define RX_3A60_HDCP_P1_REG_CPU_WDATA_REG Fld(8,0,AC_FULLB0)//[7:0]
#define RX_3A64_HDCP_P1 (IO_HDCP_P1_BASE + 0xA64)
    #define RX_3A64_HDCP_P1_REG_ENWRITE_HDCP Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_3A64_HDCP_P1_REG_HDCP_SRAM_ACCESS Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_3A64_HDCP_P1_REG_DDC_FILTER_ON Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3A64_HDCP_P1_REG_FILTER_MSB Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_3A64_HDCP_P1_REG_CHK_START Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_3A64_HDCP_P1_REG_DDC_BUSY Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_3A64_HDCP_P1_REG_SLEW_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define RX_3A64_HDCP_P1_REG_CPU_WR_BUSY_HDCP Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_3A64_HDCP_P1_REG_CPU_RD_BUSY_HDCP Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_3A64_HDCP_P1_REG_LOAD_ADR_P Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_3A64_HDCP_P1_REG_HDCP_DATA_WR_P Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_3A64_HDCP_P1_REG_HDCP_DATA_RD_P Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_3A64_HDCP_P1_REG_HDCP_RESERVED_1 Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_3A64_HDCP_P1_REG_XIU2HDCPKEY_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_3A64_HDCP_P1_REG_FIX_NO_HSYNC Fld(1,0,AC_MSKB0)//[0:0]
#define RX_3A68_HDCP_P1 (IO_HDCP_P1_BASE + 0xA68)
    #define RX_3A68_HDCP_P1_REG_STATUS_HDCP_RESERVE_3 Fld(2,14,AC_MSKB1)//[15:14]
    #define RX_3A68_HDCP_P1_REG_WIN_OF_OPP_STATUS Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3A68_HDCP_P1_REG_HDCP_FSM_STATUS Fld(5,8,AC_MSKB1)//[12:8]
    #define RX_3A68_HDCP_P1_REG_HDCP_FRAME_CNT_STATUS Fld(7,1,AC_MSKB0)//[7:1]
    #define RX_3A68_HDCP_P1_REG_HDCP_KEY_SRAM_BIST_STATUS Fld(1,0,AC_MSKB0)//[0:0]
#define RX_3A6C_HDCP_P1 (IO_HDCP_P1_BASE + 0xA6C)
    #define RX_3A6C_HDCP_P1_REG_STATUS_HDCP_RESERVE_4 Fld(4,12,AC_MSKB1)//[15:12]
    #define RX_3A6C_HDCP_P1_REG_VSYNC_DET_STATUS Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_3A6C_HDCP_P1_REG_HSYNC_DET_STATUS Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_3A6C_HDCP_P1_REG_ENC_EN_STATUS Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_3A6C_HDCP_P1_REG_ENC_DIS_STATUS Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_3A6C_HDCP_P1_REG_HDCP_WIN_OPP_CNT Fld(8,0,AC_FULLB0)//[7:0]
#define RX_3A70_HDCP_P1 (IO_HDCP_P1_BASE + 0xA70)
    #define RX_3A70_HDCP_P1_REG_ISLAND_CNT_ERR Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_3A70_HDCP_P1_REG_ISLAND_CNT Fld(8,0,AC_FULLB0)//[7:0]
#define RX_3A74_HDCP_P1 (IO_HDCP_P1_BASE + 0xA74)
    #define RX_3A74_HDCP_P1_REG_HDCP_MODE_CHANGE_EXIT_FSM Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3A74_HDCP_P1_REG_HDCP_REKEY_FAIL_CYCLE_LT56 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_3A74_HDCP_P1_REG_HDCP_REKEY_CNT Fld(12,0,AC_MSKW10)//[11:0]
#define RX_3A78_HDCP_P1 (IO_HDCP_P1_BASE + 0xA78)
    #define RX_3A78_HDCP_P1_REG_HDCP_AUTH_MASK_ODD_DE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_3A78_HDCP_P1_REG_CIPHER_57T_SUPPORT Fld(1,1,AC_MSKB0)//[1:1]
#define RX_3A7C_HDCP_P1 (IO_HDCP_P1_BASE + 0xA7C)
    #define RX_3A7C_HDCP_P1_REG_HDCP_DBG_TST Fld(8,8,AC_FULLB1)//[15:8]
#define RX_3B30_HDCP_P1 (IO_HDCP_P1_BASE + 0xB30)
    #define RX_3B30_HDCP_P1_REG_DEBUG_BUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B34_HDCP_P1 (IO_HDCP_P1_BASE + 0xB34)
    #define RX_3B34_HDCP_P1_REG_DEBUG_BUS_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_3B34_HDCP_P1_REG_DEBUG_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define RX_3B38_HDCP_P1 (IO_HDCP_P1_BASE + 0xB38)
    #define RX_3B38_HDCP_P1_REG_HDCP22_HW_CONTROL Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B3C_HDCP_P1 (IO_HDCP_P1_BASE + 0xB3C)
    #define RX_3B3C_HDCP_P1_REG_HDCP22_AUTH_STATUS Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_3B3C_HDCP_P1_REG_HDCP22_KEYFIFO_EVER_OVERFLOW Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_3B3C_HDCP_P1_REG_ST_EVER_AVMUTE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_3B3C_HDCP_P1_REG_ST_EVER_ENC_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_3B3C_HDCP_P1_REG_ST_EVER_ENC_DIS Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_3B3C_HDCP_P1_REG_ST_EVER_CLR_FRAMECTR Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_3B3C_HDCP_P1_REG_ST_EVER_UPD_INPUTCTR Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_3B3C_HDCP_P1_REG_STREAM_ID Fld(3,7,AC_MSKW10)//[9:7]
    #define RX_3B3C_HDCP_P1_REG_ST_EVER_HD22_KEYFIFO_UF Fld(1,10,AC_MSKB1)//[10:10]
#define RX_3B40_HDCP_P1 (IO_HDCP_P1_BASE + 0xB40)
    #define RX_3B40_HDCP_P1_REG_INPUT_CNT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B44_HDCP_P1 (IO_HDCP_P1_BASE + 0xB44)
    #define RX_3B44_HDCP_P1_REG_INPUT_CNT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B48_HDCP_P1 (IO_HDCP_P1_BASE + 0xB48)
    #define RX_3B48_HDCP_P1_REG_INPUT_CNT_2 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B4C_HDCP_P1 (IO_HDCP_P1_BASE + 0xB4C)
    #define RX_3B4C_HDCP_P1_REG_INPUT_CNT_3 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B50_HDCP_P1 (IO_HDCP_P1_BASE + 0xB50)
    #define RX_3B50_HDCP_P1_REG_STREAM_CNT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B54_HDCP_P1 (IO_HDCP_P1_BASE + 0xB54)
    #define RX_3B54_HDCP_P1_REG_STREAM_CNT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B58_HDCP_P1 (IO_HDCP_P1_BASE + 0xB58)
    #define RX_3B58_HDCP_P1_REG_DIS_UPD_FRAMECNT_BY_CPPKT Fld(1,0,AC_MSKB0)//[0:0]
#define RX_3B68_HDCP_P1 (IO_HDCP_P1_BASE + 0xB68)
    #define RX_3B68_HDCP_P1_REG_MESSAGE_LENGTH_CNT_UPDATE_SEL Fld(2,0,AC_MSKB0)//[1:0]
    #define RX_3B68_HDCP_P1_REG_MESSAGE_LENGTH_MASK_CTRL Fld(2,2,AC_MSKB0)//[3:2]
    #define RX_3B68_HDCP_P1_REG_MESSAGE_LENGTH_UPDATE_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_3B68_HDCP_P1_REG_MESSAGE_LENGTH_UPDATE_PULSE_QUEUE Fld(1,15,AC_MSKB1)//[15:15]
#define RX_3B6C_HDCP_P1 (IO_HDCP_P1_BASE + 0xB6C)
    #define RX_3B6C_HDCP_P1_REG_MESSAGE_LENGTH_TIME_OUT_VAL Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B80_HDCP_P1 (IO_HDCP_P1_BASE + 0xB80)
    #define RX_3B80_HDCP_P1_REG_WCMD_LENGTH Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_3B80_HDCP_P1_REG_SRAM_SD_EN_MSG_FIFO Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3B80_HDCP_P1_REG_RST_REQ Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_3B80_HDCP_P1_REG_RST_SM Fld(1,15,AC_MSKB1)//[15:15]
#define RX_3B84_HDCP_P1 (IO_HDCP_P1_BASE + 0xB84)
    #define RX_3B84_HDCP_P1_REG_RCMD_LENGTH Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_3B84_HDCP_P1_REG_MSG_FIFO_BIST_FAIL Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3B84_HDCP_P1_REG_DIS_IIC Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_3B84_HDCP_P1_REG_DIS_XIU Fld(1,15,AC_MSKB1)//[15:15]
#define RX_3B88_HDCP_P1 (IO_HDCP_P1_BASE + 0xB88)
    #define RX_3B88_HDCP_P1_REG_HDCP_V22_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_3B88_HDCP_P1_REG_HDCP_V22_OV_VALUE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_3B88_HDCP_P1_REG_ADVANCE_CIPHER_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_3B88_HDCP_P1_REG_ADVANCE_CIPHER_OV_VALUE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_3B88_HDCP_P1_REG_MESSAGE_BURST_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_3B88_HDCP_P1_REG_MESSAGE_READ_ABORT_REAUTH Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_3B88_HDCP_P1_REG_HDCP_V22_CLR Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_3B88_HDCP_P1_REG_HDCP_V22_READY Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_3B88_HDCP_P1_REG_MESSAGE_ID Fld(8,8,AC_FULLB1)//[15:8]
#define RX_3B8C_HDCP_P1 (IO_HDCP_P1_BASE + 0xB8C)
    #define RX_3B8C_HDCP_P1_REG_MESSAGE_LENGTH Fld(10,0,AC_MSKW10)//[9:0]
#define RX_3B90_HDCP_P1 (IO_HDCP_P1_BASE + 0xB90)
    #define RX_3B90_HDCP_P1_REG_MESSAGE_LENGTH_RECEIVE Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_3B90_HDCP_P1_REG_REAUTH_SET Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_3B90_HDCP_P1_REG_MESSAGE_LENGTH_CLR_BY_AKE_INT Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3B90_HDCP_P1_REG_MESSAGE_READ_AUTO_CLR_READY_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_3B90_HDCP_P1_REG_MESSAGE_LENGTH_UPDATE Fld(1,15,AC_MSKB1)//[15:15]
#define RX_3B94_HDCP_P1 (IO_HDCP_P1_BASE + 0xB94)
    #define RX_3B94_HDCP_P1_REG_BCH_ERROR_CNT_THR Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_3B94_HDCP_P1_REG_BCH_ERROR_CNT_CLR Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_3B94_HDCP_P1_REG_LINK_INTEGRITY_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_3B94_HDCP_P1_REG_REAUTH_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_3B94_HDCP_P1_REG_REAUTH_OV_VALUE Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_3B94_HDCP_P1_REG_REAUTH_CLR Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_3B94_HDCP_P1_REG_NO_INPUT_REAUTH Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3B94_HDCP_P1_REG_KSV_FIFO_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_3B94_HDCP_P1_REG_CROSS_ADR_READ_EN Fld(1,15,AC_MSKB1)//[15:15]
#define RX_3B98_HDCP_P1 (IO_HDCP_P1_BASE + 0xB98)
    #define RX_3B98_HDCP_P1_REG_HDCP_V22_INTERRUPT_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3B9C_HDCP_P1 (IO_HDCP_P1_BASE + 0xB9C)
    #define RX_3B9C_HDCP_P1_REG_HDCP_V22_INTERRUPT_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3BA0_HDCP_P1 (IO_HDCP_P1_BASE + 0xBA0)
    #define RX_3BA0_HDCP_P1_REG_IIC2MEM_RADDR_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_3BA0_HDCP_P1_REG_IIC2MEM_RADDR Fld(10,0,AC_MSKW10)//[9:0]
#define RX_3BEC_HDCP_P1 (IO_HDCP_P1_BASE + 0xBEC)
    #define RX_3BEC_HDCP_P1_REG_8P_HDMI_MODE_TIMEOUT_TH Fld(4,0,AC_MSKB0)//[3:0]
    #define RX_3BEC_HDCP_P1_REG_HDCP_V22_ENABLE Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_3BEC_HDCP_P1_REG_PKT_EVENT_SRC Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_3BEC_HDCP_P1_REG_HDCP22_NO_INPUT_RST_EN Fld(1,15,AC_MSKB1)//[15:15]
#define RX_3BF0_HDCP_P1 (IO_HDCP_P1_BASE + 0xBF0)
    #define RX_3BF0_HDCP_P1_REG_8P_DE_PERIOD Fld(14,0,AC_MSKW10)//[13:0]
    #define RX_3BF0_HDCP_P1_REG_8P_DE_CHANGE Fld(1,14,AC_MSKB1)//[14:14]
#define RX_3BF4_HDCP_P1 (IO_HDCP_P1_BASE + 0xBF4)
    #define RX_3BF4_HDCP_P1_REG_HDCP_8P_HW_CONTROL Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3BF8_HDCP_P1 (IO_HDCP_P1_BASE + 0xBF8)
    #define RX_3BF8_HDCP_P1_REG_8P_DEBUG_BUS_0 Fld(16,0,AC_FULLW10)//[15:0]
#define RX_3BFC_HDCP_P1 (IO_HDCP_P1_BASE + 0xBFC)
    #define RX_3BFC_HDCP_P1_REG_8P_DEBUG_BUS_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_3BFC_HDCP_P1_REG_8P_DEBUG_SEL Fld(8,8,AC_FULLB1)//[15:8]



/********************************Relate HDMI2.1 HDMI2P1_MAC_BASE**************************************/
#define HDMI2P1_MAC_BASE (IO_VIRT+0x00600000)


#define RX_1900_GP_TOP (HDMI2P1_MAC_BASE + 0x1900)
    #define RX_1900_GP_TOP_REG_XIU_ACK_DIS Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_1900_GP_TOP_REG_HDCP_DATA_TRIG Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_1900_GP_TOP_REG_LOAD_ADDR_TRIG Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_1900_GP_TOP_REG_HDCP_SRAM_ACCESS Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_1900_GP_TOP_REG_ENWRITE_HDCP Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_1900_GP_TOP_REG_EN_SRAM_RD Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_1900_GP_TOP_REG_XIU2HDCPKEY_EN Fld(1,0,AC_MSKB0)//[0:0]
#define RX_20EC_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20EC)
    #define RX_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_RESERVED_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_20EC_DTOP_P0_REG_HDCP_IRQ_LEVEL_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_20EC_DTOP_P0_REG_DVICK_SLOW180_CHG_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_20EC_DTOP_P0_REG_DVI_DE_CHG_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_20EC_DTOP_P0_REG_H21_DE_CHG_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_20EC_DTOP_P0_REG_H21_HDMI_MODE_CHG_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_20EC_DTOP_P0_REG_HDMI_MODE_CHG_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_20EC_DTOP_P0_REG_DVICK_LOSE_CHG_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_20EC_DTOP_P0_REG_ADCDVI_IRQ_STATUS_RESERVED Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_20EC_DTOP_P0_REG_HDCP_IRQ_LEVEL Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_20EC_DTOP_P0_REG_DVICK_SLOW180_CHG Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_20EC_DTOP_P0_REG_DVI_DE_CHG Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_20EC_DTOP_P0_REG_H21_DE_CHG Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_20EC_DTOP_P0_REG_H21_HDMI_MODE_CHG Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_20EC_DTOP_P0_REG_HDMI_MODE_CHG Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_20EC_DTOP_P0_REG_DVICK_LOSE_CHG Fld(1,0,AC_MSKB0)//[0:0]
#define RX_20F0_DTOP_P0 (HDMI2P1_MAC_BASE + 0x20F0)
    #define RX_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_7 Fld(1,15,AC_MSKB1)//[15:15]
    #define RX_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_6 Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_5 Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_4 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_3 Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_2 Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_20F0_DTOP_P0_REG_ADCDVI_IRQ_CLR_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_20F0_DTOP_P0_REG_ADCDVI_IRQ_FORCE Fld(8,0,AC_FULLB0)//[7:0]



#endif

