/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


/*****************************************************************************
 *
 * Filename:
 * ---------
 *   $Workfile: hw_tnr.h $
 *
 * Project:
 * --------
 *   MT5886
 *
 * Description:
 * ------------
 *   LCPROC register definition
 *
 * Author:
 * -------
 *   Weibin Chen
 *
 * Last changed:
 * -------------
 * $Author: weibin.chen $
 *
 * $Modtime: 08/19/16 1:22p $
 *
 * $Revision: #1 $
****************************************************************************/
#ifndef _HW_TNR_H_
#define _HW_TNR_H_

#include "hw_vdoin.h"

#define IO_TNR_BASE (IO_VIRT_SRE + 0x44000)

#define TNR_DS_MAIN_00 (IO_TNR_BASE + 0x150)
    #define TNR_DS_MAIN_00_PRE_DSCALE_H_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_MAIN_00_PRE_DSCALER_V_1 Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_MAIN_01 (IO_TNR_BASE + 0x154)
    #define TNR_DS_MAIN_01_PRE_DSCALE_H_INIT_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_MAIN_01_PRE_DSCALE_V_INIT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_MAIN_02 (IO_TNR_BASE + 0x158)
    #define TNR_DS_MAIN_02_PRE_DSCALE_H_INIT_RIGHT_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_MAIN_02_PRE_DSCALE_V_INIT_RIGHT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_MAIN_03 (IO_TNR_BASE + 0x15C)
    #define TNR_DS_MAIN_03_PREDS_MAIN_OUT_H Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_MAIN_03_PREDS_MAIN_OUT_V Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_MAIN_04 (IO_TNR_BASE + 0x160)
    #define TNR_DS_MAIN_04_PREDS_MAIN_IN_H Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_MAIN_04_PREDS_MAIN_IN_V Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_MAIN_05 (IO_TNR_BASE + 0x164)
    #define TNR_DS_MAIN_05_TNR_DS_ATPG_CT Fld(1,31,AC_MSKB3)//[31:31]
    #define TNR_DS_MAIN_05_TNR_DS_ATPG_OB Fld(1,30,AC_MSKB3)//[30:30]
    #define TNR_DS_MAIN_05_MAIN_SET_RES_CLEAR_O Fld(1,27,AC_MSKB3)//[27:27]
    #define TNR_DS_MAIN_05_MAIN_SET_RES_CLEAR_I Fld(1,26,AC_MSKB3)//[26:26]
    #define TNR_DS_MAIN_05_MAIN_SET_RES_FINISH_O Fld(1,25,AC_MSKB3)//[25:25]
    #define TNR_DS_MAIN_05_MAIN_SET_RES_FINISH_I Fld(1,24,AC_MSKB3)//[24:24]
    #define TNR_DS_MAIN_05_MAIN_SETRES_ACT_LINE Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_MAIN_05_MAIN_SEL_HVCNT Fld(1,15,AC_MSKB1)//[15:15]
    #define TNR_DS_MAIN_05_MAIN_CLR_HVCNT Fld(1,14,AC_MSKB1)//[14:14]
    #define TNR_DS_MAIN_05_MAIN_VCEN_ACT_AT_SYNC Fld(1,13,AC_MSKB1)//[13:13]
    #define TNR_DS_MAIN_05_MAIN_HCEN_ACT_AT_SYNC Fld(1,12,AC_MSKB1)//[12:12]
    #define TNR_DS_MAIN_05_PREDS_3DTV_MODE_1 Fld(4,8,AC_MSKB1)//[11:8]
    #define TNR_DS_MAIN_05_PREDS_LR_PAIR_CTRL Fld(2,6,AC_MSKB0)//[7:6]
    #define TNR_DS_MAIN_05_PREDS_3DTV_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define TNR_DS_MAIN_05_PREDS_MAIN_SETRES Fld(1,4,AC_MSKB0)//[4:4]
    #define TNR_DS_MAIN_05_PREDS_M_INV_VSYNC Fld(1,3,AC_MSKB0)//[3:3]
    #define TNR_DS_MAIN_05_PREDS_MAIN_SETRES_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define TNR_DS_MAIN_05_PRE_DSCALE_H_BYPASS_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define TNR_DS_MAIN_05_PRE_DSCALE_V_BYPASS_1 Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_DS_MAIN_06 (IO_TNR_BASE + 0x168)
    #define TNR_DS_MAIN_06_MAIN_H_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_MAIN_06_MAIN_H_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_MAIN_07 (IO_TNR_BASE + 0x16C)
    #define TNR_DS_MAIN_07_MAIN_V_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_MAIN_07_MAIN_V_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_MAIN_08 (IO_TNR_BASE + 0x170)
    #define TNR_DS_MAIN_08_PRE_DSCALE_V_INIT_BTM_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_MAIN_08_PRE_DSCALE_V_INIT_RIGHT_BTM_1 Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_MAIN_09 (IO_TNR_BASE + 0x174)
    #define TNR_DS_MAIN_09_PREDS_3D_FIELD_EN_1 Fld(1,31,AC_MSKB3)//[31:31]
    #define TNR_DS_MAIN_09_PREDS_3D_FIELD_INV_1 Fld(1,30,AC_MSKB3)//[30:30]
    #define TNR_DS_MAIN_09_PREDS_RESERVE_0 Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_DS_MAIN_0A (IO_TNR_BASE + 0x178)
    #define TNR_DS_MAIN_0A_PREDS_H_PHASE_INIT_SIGN_1 Fld(1,31,AC_MSKB3)//[31:31]
    #define TNR_DS_MAIN_0A_PREDS_H_PHASE_INIT_INTG_1 Fld(3,28,AC_MSKB3)//[30:28]
    #define TNR_DS_MAIN_0A_PREDS_H_PHASE_INIT_FRAC_1 Fld(20,8,AC_MSKDW)//[27:8]
    #define TNR_DS_MAIN_0A_PREDS_FIR_COEF_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define TNR_DS_MAIN_0B (IO_TNR_BASE + 0x17C)
    #define TNR_DS_MAIN_0B_PREDS_H_PHASE_DELTA_INTG_1 Fld(3,28,AC_MSKB3)//[30:28]
    #define TNR_DS_MAIN_0B_PREDS_H_PHASE_DELTA_FRAC_1 Fld(20,8,AC_MSKDW)//[27:8]
    #define TNR_DS_MAIN_0B_PREDS_FIR_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define TNR_DS_MAIN_0B_PREDS_FIR_DLY_SEL Fld(4,3,AC_MSKB0)//[6:3]
    #define TNR_DS_MAIN_0B_PREDS_FIR_INPUT_DLY_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define TNR_DS_MAIN_0B_PREDS_CEN_OUT_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_DS_FIL_00 (IO_TNR_BASE + 0x800)
    #define TNR_DS_FIL_00_H_FILTER_BAND0_COEF0 Fld(10,20,AC_MSKW32)//[29:20]
    #define TNR_DS_FIL_00_H_FILTER_BAND0_COEF1 Fld(10,10,AC_MSKW21)//[19:10]
    #define TNR_DS_FIL_00_H_FILTER_BAND0_COEF2 Fld(10,0,AC_MSKW10)//[9:0]
#define TNR_DS_FIL_01 (IO_TNR_BASE + 0x804)
    #define TNR_DS_FIL_01_H_FILTER_BAND0_COEF3 Fld(10,20,AC_MSKW32)//[29:20]
    #define TNR_DS_FIL_01_H_FILTER_BAND0_COEF4 Fld(10,10,AC_MSKW21)//[19:10]
    #define TNR_DS_FIL_01_H_FILTER_BAND0_COEF5 Fld(10,0,AC_MSKW10)//[9:0]
#define TNR_DS_FIL_02 (IO_TNR_BASE + 0x808)
    #define TNR_DS_FIL_02_H_FILTER_BAND0_COEF6 Fld(10,20,AC_MSKW32)//[29:20]
    #define TNR_DS_FIL_02_H_FILTER_BAND0_COEF7 Fld(10,10,AC_MSKW21)//[19:10]
    #define TNR_DS_FIL_02_H_FILTER_BAND0_COEF8 Fld(10,0,AC_MSKW10)//[9:0]
#define TNR_DS_FIL_03 (IO_TNR_BASE + 0x80C)
    #define TNR_DS_FIL_03_H_FILTER_BAND0_COEF9 Fld(10,20,AC_MSKW32)//[29:20]
    #define TNR_DS_FIL_03_H_FILTER_BAND0_COEF10 Fld(10,10,AC_MSKW21)//[19:10]
    #define TNR_DS_FIL_03_H_FILTER_BAND0_COEF11 Fld(10,0,AC_MSKW10)//[9:0]
#define TNR_DS_FIL_04 (IO_TNR_BASE + 0x810)
    #define TNR_DS_FIL_04_H_FILTER_BAND0_COEF12 Fld(10,20,AC_MSKW32)//[29:20]
    #define TNR_DS_FIL_04_H_FILTER_BAND0_COEF13 Fld(10,10,AC_MSKW21)//[19:10]
    #define TNR_DS_FIL_04_H_FILTER_BAND0_COEF14 Fld(10,0,AC_MSKW10)//[9:0]
#define TNR_DS_FIL_05 (IO_TNR_BASE + 0x814)
    #define TNR_DS_FIL_05_H_FILTER_BAND0_COEF15 Fld(10,20,AC_MSKW32)//[29:20]
    #define TNR_DS_FIL_05_H_FILTER_BAND0_COEF16 Fld(10,10,AC_MSKW21)//[19:10]
    #define TNR_DS_FIL_05_H_FILTER_BAND0_COEF17 Fld(10,0,AC_MSKW10)//[9:0]
#define TNR_DS_FIL_06 (IO_TNR_BASE + 0x81C)
    #define TNR_DS_FIL_06_H_FILTER_BAND0_COEF18 Fld(10,20,AC_MSKW32)//[29:20]
    #define TNR_DS_FIL_06_H_FILTER_BAND0_COEF19 Fld(10,10,AC_MSKW21)//[19:10]
    #define TNR_DS_FIL_06_H_FILTER_BAND0_COEF20 Fld(10,0,AC_MSKW10)//[9:0]
#define TNR_DS_FIL_07 (IO_TNR_BASE + 0x820)
    #define TNR_DS_FIL_07_H_FILTER_BAND1_COEF0 Fld(8,24,AC_FULLB3)//[31:24]
    #define TNR_DS_FIL_07_H_FILTER_BAND1_COEF1 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_07_H_FILTER_BAND1_COEF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_07_H_FILTER_BAND1_COEF3 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_08 (IO_TNR_BASE + 0x824)
    #define TNR_DS_FIL_08_H_FILTER_BAND1_COEF4 Fld(8,24,AC_FULLB3)//[31:24]
    #define TNR_DS_FIL_08_H_FILTER_BAND1_COEF5 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_08_H_FILTER_BAND1_COEF6 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_08_H_FILTER_BAND1_COEF7 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_09 (IO_TNR_BASE + 0x82C)
    #define TNR_DS_FIL_09_H_FILTER_BAND1_COEF8 Fld(8,24,AC_FULLB3)//[31:24]
    #define TNR_DS_FIL_09_H_FILTER_BAND1_COEF9 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_09_H_FILTER_BAND1_COEF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_09_H_FILTER_BAND1_COEF11 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_0A (IO_TNR_BASE + 0x830)
    #define TNR_DS_FIL_0A_H_FILTER_BAND1_COEF12 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_0A_H_FILTER_BAND1_COEF13 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_0A_H_FILTER_BAND1_COEF14 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_0B (IO_TNR_BASE + 0x834)
    #define TNR_DS_FIL_0B_H_FILTER_BAND2_COEF0 Fld(8,24,AC_FULLB3)//[31:24]
    #define TNR_DS_FIL_0B_H_FILTER_BAND2_COEF1 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_0B_H_FILTER_BAND2_COEF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_0B_H_FILTER_BAND2_COEF3 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_0C (IO_TNR_BASE + 0x83C)
    #define TNR_DS_FIL_0C_H_FILTER_BAND2_COEF4 Fld(8,24,AC_FULLB3)//[31:24]
    #define TNR_DS_FIL_0C_H_FILTER_BAND2_COEF5 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_0C_H_FILTER_BAND2_COEF6 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_0C_H_FILTER_BAND2_COEF7 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_0D (IO_TNR_BASE + 0x840)
    #define TNR_DS_FIL_0D_H_FILTER_BAND2_COEF8 Fld(8,24,AC_FULLB3)//[31:24]
    #define TNR_DS_FIL_0D_H_FILTER_BAND2_COEF9 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_0D_H_FILTER_BAND2_COEF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_0D_H_FILTER_BAND2_COEF11 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_0E (IO_TNR_BASE + 0x844)
    #define TNR_DS_FIL_0E_H_FILTER_BAND2_COEF12 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_0E_H_FILTER_BAND2_COEF13 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_0E_H_FILTER_BAND2_COEF14 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_0F (IO_TNR_BASE + 0x84C)
    #define TNR_DS_FIL_0F_H_FILTER_BAND3_COEF0 Fld(8,24,AC_FULLB3)//[31:24]
    #define TNR_DS_FIL_0F_H_FILTER_BAND3_COEF1 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_0F_H_FILTER_BAND3_COEF2 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_0F_H_FILTER_BAND3_COEF3 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_10 (IO_TNR_BASE + 0x850)
    #define TNR_DS_FIL_10_H_FILTER_BAND3_COEF4 Fld(8,24,AC_FULLB3)//[31:24]
    #define TNR_DS_FIL_10_H_FILTER_BAND3_COEF5 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_10_H_FILTER_BAND3_COEF6 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_10_H_FILTER_BAND3_COEF7 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_11 (IO_TNR_BASE + 0x854)
    #define TNR_DS_FIL_11_H_FILTER_BAND3_COEF8 Fld(8,24,AC_FULLB3)//[31:24]
    #define TNR_DS_FIL_11_H_FILTER_BAND3_COEF9 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_11_H_FILTER_BAND3_COEF10 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_11_H_FILTER_BAND3_COEF11 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_12 (IO_TNR_BASE + 0x85C)
    #define TNR_DS_FIL_12_H_FILTER_BAND3_COEF12 Fld(8,16,AC_FULLB2)//[23:16]
    #define TNR_DS_FIL_12_H_FILTER_BAND3_COEF13 Fld(8,8,AC_FULLB1)//[15:8]
    #define TNR_DS_FIL_12_H_FILTER_BAND3_COEF14 Fld(8,0,AC_FULLB0)//[7:0]
#define TNR_DS_FIL_13 (IO_TNR_BASE + 0x860)
    #define TNR_DS_FIL_13_H_FILTER_WIDTH Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_FIL_13_H_FILTER_HEIGHT Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_FIL_14 (IO_TNR_BASE + 0x864)
    #define TNR_DS_FIL_14_H_FILTER_H_START Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_FIL_14_H_FILTER_V_START Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_FIL_15 (IO_TNR_BASE + 0x86C)
    #define TNR_DS_FIL_15_H_FILTER_H_SIZE Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_DS_FIL_15_H_FILTER_V_SIZE Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_DS_FIL_16 (IO_TNR_BASE + 0x870)
    #define TNR_DS_FIL_16_H_FILTER_SWITCH_0 Fld(1,31,AC_MSKB3)//[31:31]
    #define TNR_DS_FIL_16_H_FILTER_SWITCH_1 Fld(1,30,AC_MSKB3)//[30:30]
    #define TNR_DS_FIL_16_H_FILTER_SWITCH_2 Fld(1,29,AC_MSKB3)//[29:29]
    #define TNR_DS_FIL_16_H_FILTER_SWITCH_3 Fld(1,28,AC_MSKB3)//[28:28]
    #define TNR_DS_FIL_16_BITSHIFT_A0 Fld(3,25,AC_MSKB3)//[27:25]
    #define TNR_DS_FIL_16_BITSHIFT_B0 Fld(3,22,AC_MSKW32)//[24:22]
    #define TNR_DS_FIL_16_BITSHIFT_A1 Fld(3,19,AC_MSKB2)//[21:19]
    #define TNR_DS_FIL_16_BITSHIFT_B1 Fld(3,16,AC_MSKB2)//[18:16]
    #define TNR_DS_FIL_16_BITSHIFT_A2 Fld(3,13,AC_MSKB1)//[15:13]
    #define TNR_DS_FIL_16_BITSHIFT_B2 Fld(3,10,AC_MSKB1)//[12:10]
    #define TNR_DS_FIL_16_BITSHIFT_A3 Fld(3,7,AC_MSKW10)//[9:7]
    #define TNR_DS_FIL_16_BITSHIFT_B3 Fld(3,4,AC_MSKB0)//[6:4]
    #define TNR_DS_FIL_16_H_FILTER_OUTPUT_MSB Fld(1,3,AC_MSKB0)//[3:3]
#define TNR_DS_FIL_17 (IO_TNR_BASE + 0x874)
    #define TNR_DS_FIL_17_A0_HIST_0 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_18 (IO_TNR_BASE + 0x878)
    #define TNR_DS_FIL_18_A0_HIST_1 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_19 (IO_TNR_BASE + 0x87C)
    #define TNR_DS_FIL_19_A0_HIST_2 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_1A (IO_TNR_BASE + 0x880)
    #define TNR_DS_FIL_1A_A0_HIST_3 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_1B (IO_TNR_BASE + 0x884)
    #define TNR_DS_FIL_1B_A0_HIST_4 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_1C (IO_TNR_BASE + 0x888)
    #define TNR_DS_FIL_1C_A0_HIST_5 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_1D (IO_TNR_BASE + 0x88C)
    #define TNR_DS_FIL_1D_A0_HIST_6 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_1E (IO_TNR_BASE + 0x890)
    #define TNR_DS_FIL_1E_A0_HIST_7 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_1F (IO_TNR_BASE + 0x894)
    #define TNR_DS_FIL_1F_A0_HIST_8 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_20 (IO_TNR_BASE + 0x898)
    #define TNR_DS_FIL_20_A0_HIST_9 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_21 (IO_TNR_BASE + 0x89C)
    #define TNR_DS_FIL_21_A0_HIST_10 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_22 (IO_TNR_BASE + 0x8A0)
    #define TNR_DS_FIL_22_A0_HIST_11 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_23 (IO_TNR_BASE + 0x8A4)
    #define TNR_DS_FIL_23_A0_HIST_12 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_24 (IO_TNR_BASE + 0x8A8)
    #define TNR_DS_FIL_24_A0_HIST_13 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_25 (IO_TNR_BASE + 0x8AC)
    #define TNR_DS_FIL_25_A0_HIST_14 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_26 (IO_TNR_BASE + 0x8B0)
    #define TNR_DS_FIL_26_A0_HIST_15 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_27 (IO_TNR_BASE + 0x8B4)
    #define TNR_DS_FIL_27_B0_HIST_0 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_28 (IO_TNR_BASE + 0x8B8)
    #define TNR_DS_FIL_28_B0_HIST_1 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_29 (IO_TNR_BASE + 0x8BC)
    #define TNR_DS_FIL_29_B0_HIST_2 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_2A (IO_TNR_BASE + 0x8C0)
    #define TNR_DS_FIL_2A_B0_HIST_3 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_2B (IO_TNR_BASE + 0x8C4)
    #define TNR_DS_FIL_2B_B0_HIST_4 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_2C (IO_TNR_BASE + 0x8C8)
    #define TNR_DS_FIL_2C_B0_HIST_5 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_2D (IO_TNR_BASE + 0x8CC)
    #define TNR_DS_FIL_2D_B0_HIST_6 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_2E (IO_TNR_BASE + 0x8D0)
    #define TNR_DS_FIL_2E_B0_HIST_7 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_2F (IO_TNR_BASE + 0x8D4)
    #define TNR_DS_FIL_2F_B0_HIST_8 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_30 (IO_TNR_BASE + 0x8D8)
    #define TNR_DS_FIL_30_B0_HIST_9 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_31 (IO_TNR_BASE + 0x8DC)
    #define TNR_DS_FIL_31_B0_HIST_10 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_32 (IO_TNR_BASE + 0x8E0)
    #define TNR_DS_FIL_32_B0_HIST_11 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_33 (IO_TNR_BASE + 0x8E4)
    #define TNR_DS_FIL_33_B0_HIST_12 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_34 (IO_TNR_BASE + 0x8E8)
    #define TNR_DS_FIL_34_B0_HIST_13 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_35 (IO_TNR_BASE + 0x8EC)
    #define TNR_DS_FIL_35_B0_HIST_14 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_36 (IO_TNR_BASE + 0x8F0)
    #define TNR_DS_FIL_36_B0_HIST_15 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_37 (IO_TNR_BASE + 0x8F4)
    #define TNR_DS_FIL_37_A1_HIST_0 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_38 (IO_TNR_BASE + 0x8F8)
    #define TNR_DS_FIL_38_A1_HIST_1 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_39 (IO_TNR_BASE + 0x8FC)
    #define TNR_DS_FIL_39_A1_HIST_2 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_3A (IO_TNR_BASE + 0x900)
    #define TNR_DS_FIL_3A_A1_HIST_3 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_3B (IO_TNR_BASE + 0x904)
    #define TNR_DS_FIL_3B_A1_HIST_4 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_3C (IO_TNR_BASE + 0x908)
    #define TNR_DS_FIL_3C_A1_HIST_5 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_3D (IO_TNR_BASE + 0x90C)
    #define TNR_DS_FIL_3D_A1_HIST_6 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_3E (IO_TNR_BASE + 0x910)
    #define TNR_DS_FIL_3E_A1_HIST_7 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_3F (IO_TNR_BASE + 0x914)
    #define TNR_DS_FIL_3F_A1_HIST_8 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_40 (IO_TNR_BASE + 0x918)
    #define TNR_DS_FIL_40_A1_HIST_9 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_41 (IO_TNR_BASE + 0x91C)
    #define TNR_DS_FIL_41_A1_HIST_10 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_42 (IO_TNR_BASE + 0x920)
    #define TNR_DS_FIL_42_A1_HIST_11 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_43 (IO_TNR_BASE + 0x924)
    #define TNR_DS_FIL_43_A1_HIST_12 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_44 (IO_TNR_BASE + 0x928)
    #define TNR_DS_FIL_44_A1_HIST_13 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_45 (IO_TNR_BASE + 0x92C)
    #define TNR_DS_FIL_45_A1_HIST_14 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_46 (IO_TNR_BASE + 0x930)
    #define TNR_DS_FIL_46_A1_HIST_15 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_47 (IO_TNR_BASE + 0x934)
    #define TNR_DS_FIL_47_B1_HIST_0 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_48 (IO_TNR_BASE + 0x938)
    #define TNR_DS_FIL_48_B1_HIST_1 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_49 (IO_TNR_BASE + 0x93C)
    #define TNR_DS_FIL_49_B1_HIST_2 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_4A (IO_TNR_BASE + 0x940)
    #define TNR_DS_FIL_4A_B1_HIST_3 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_4B (IO_TNR_BASE + 0x944)
    #define TNR_DS_FIL_4B_B1_HIST_4 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_4C (IO_TNR_BASE + 0x948)
    #define TNR_DS_FIL_4C_B1_HIST_5 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_4D (IO_TNR_BASE + 0x94C)
    #define TNR_DS_FIL_4D_B1_HIST_6 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_4E (IO_TNR_BASE + 0x950)
    #define TNR_DS_FIL_4E_B1_HIST_7 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_4F (IO_TNR_BASE + 0x954)
    #define TNR_DS_FIL_4F_B1_HIST_8 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_50 (IO_TNR_BASE + 0x958)
    #define TNR_DS_FIL_50_B1_HIST_9 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_51 (IO_TNR_BASE + 0x95C)
    #define TNR_DS_FIL_51_B1_HIST_10 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_52 (IO_TNR_BASE + 0x960)
    #define TNR_DS_FIL_52_B1_HIST_11 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_53 (IO_TNR_BASE + 0x964)
    #define TNR_DS_FIL_53_B1_HIST_12 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_54 (IO_TNR_BASE + 0x968)
    #define TNR_DS_FIL_54_B1_HIST_13 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_55 (IO_TNR_BASE + 0x96C)
    #define TNR_DS_FIL_55_B1_HIST_14 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_56 (IO_TNR_BASE + 0x970)
    #define TNR_DS_FIL_56_B1_HIST_15 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_57 (IO_TNR_BASE + 0x974)
    #define TNR_DS_FIL_57_A2_HIST_0 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_58 (IO_TNR_BASE + 0x978)
    #define TNR_DS_FIL_58_A2_HIST_1 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_59 (IO_TNR_BASE + 0x97C)
    #define TNR_DS_FIL_59_A2_HIST_2 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_5A (IO_TNR_BASE + 0x980)
    #define TNR_DS_FIL_5A_A2_HIST_3 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_5B (IO_TNR_BASE + 0x984)
    #define TNR_DS_FIL_5B_A2_HIST_4 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_5C (IO_TNR_BASE + 0x988)
    #define TNR_DS_FIL_5C_A2_HIST_5 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_5D (IO_TNR_BASE + 0x98C)
    #define TNR_DS_FIL_5D_A2_HIST_6 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_5E (IO_TNR_BASE + 0x990)
    #define TNR_DS_FIL_5E_A2_HIST_7 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_5F (IO_TNR_BASE + 0x994)
    #define TNR_DS_FIL_5F_A2_HIST_8 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_60 (IO_TNR_BASE + 0x998)
    #define TNR_DS_FIL_60_A2_HIST_9 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_61 (IO_TNR_BASE + 0x99C)
    #define TNR_DS_FIL_61_A2_HIST_10 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_62 (IO_TNR_BASE + 0x9A0)
    #define TNR_DS_FIL_62_A2_HIST_11 Fld(24,0,AC_MSKDW)//[23:0]
    
    //Page TNR_2
#define TNR_DS_FIL_63 (IO_TNR_BASE + 0x9A4)
    #define TNR_DS_FIL_63_A2_HIST_12 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_64 (IO_TNR_BASE + 0x9A8)
    #define TNR_DS_FIL_64_A2_HIST_13 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_65 (IO_TNR_BASE + 0x9AC)
    #define TNR_DS_FIL_65_A2_HIST_14 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_66 (IO_TNR_BASE + 0x9B0)
    #define TNR_DS_FIL_66_A2_HIST_15 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_67 (IO_TNR_BASE + 0x9B4)
    #define TNR_DS_FIL_67_B2_HIST_0 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_68 (IO_TNR_BASE + 0x9B8)
    #define TNR_DS_FIL_68_B2_HIST_1 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_69 (IO_TNR_BASE + 0x9BC)
    #define TNR_DS_FIL_69_B2_HIST_2 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_6A (IO_TNR_BASE + 0x9C0)
    #define TNR_DS_FIL_6A_B2_HIST_3 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_6B (IO_TNR_BASE + 0x9C4)
    #define TNR_DS_FIL_6B_B2_HIST_4 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_6C (IO_TNR_BASE + 0x9C8)
    #define TNR_DS_FIL_6C_B2_HIST_5 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_6D (IO_TNR_BASE + 0x9CC)
    #define TNR_DS_FIL_6D_B2_HIST_6 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_6E (IO_TNR_BASE + 0x9D0)
    #define TNR_DS_FIL_6E_B2_HIST_7 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_6F (IO_TNR_BASE + 0x9D4)
    #define TNR_DS_FIL_6F_B2_HIST_8 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_70 (IO_TNR_BASE + 0x9D8)
    #define TNR_DS_FIL_70_B2_HIST_9 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_71 (IO_TNR_BASE + 0x9DC)
    #define TNR_DS_FIL_71_B2_HIST_10 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_72 (IO_TNR_BASE + 0x9E0)
    #define TNR_DS_FIL_72_B2_HIST_11 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_73 (IO_TNR_BASE + 0x9E4)
    #define TNR_DS_FIL_73_B2_HIST_12 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_74 (IO_TNR_BASE + 0x9E8)
    #define TNR_DS_FIL_74_B2_HIST_13 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_75 (IO_TNR_BASE + 0x9EC)
    #define TNR_DS_FIL_75_B2_HIST_14 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_76 (IO_TNR_BASE + 0x9F0)
    #define TNR_DS_FIL_76_B2_HIST_15 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_77 (IO_TNR_BASE + 0x9F4)
    #define TNR_DS_FIL_77_A3_HIST_0 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_78 (IO_TNR_BASE + 0x9F8)
    #define TNR_DS_FIL_78_A3_HIST_1 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_79 (IO_TNR_BASE + 0x9FC)
    #define TNR_DS_FIL_79_A3_HIST_2 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_7A (IO_TNR_BASE + 0xA00)
    #define TNR_DS_FIL_7A_A3_HIST_3 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_7B (IO_TNR_BASE + 0xA04)
    #define TNR_DS_FIL_7B_A3_HIST_4 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_7C (IO_TNR_BASE + 0xA08)
    #define TNR_DS_FIL_7C_A3_HIST_5 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_7D (IO_TNR_BASE + 0xA0C)
    #define TNR_DS_FIL_7D_A3_HIST_6 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_7E (IO_TNR_BASE + 0xA10)
    #define TNR_DS_FIL_7E_A3_HIST_7 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_7F (IO_TNR_BASE + 0xA14)
    #define TNR_DS_FIL_7F_A3_HIST_8 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_80 (IO_TNR_BASE + 0xA18)
    #define TNR_DS_FIL_80_A3_HIST_9 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_81 (IO_TNR_BASE + 0xA1C)
    #define TNR_DS_FIL_81_A3_HIST_10 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_82 (IO_TNR_BASE + 0xA20)
    #define TNR_DS_FIL_82_A3_HIST_11 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_83 (IO_TNR_BASE + 0xA24)
    #define TNR_DS_FIL_83_A3_HIST_12 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_84 (IO_TNR_BASE + 0xA28)
    #define TNR_DS_FIL_84_A3_HIST_13 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_85 (IO_TNR_BASE + 0xA2C)
    #define TNR_DS_FIL_85_A3_HIST_14 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_86 (IO_TNR_BASE + 0xA30)
    #define TNR_DS_FIL_86_A3_HIST_15 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_87 (IO_TNR_BASE + 0xA34)
    #define TNR_DS_FIL_87_B3_HIST_0 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_88 (IO_TNR_BASE + 0xA38)
    #define TNR_DS_FIL_88_B3_HIST_1 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_89 (IO_TNR_BASE + 0xA3C)
    #define TNR_DS_FIL_89_B3_HIST_2 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_8A (IO_TNR_BASE + 0xA40)
    #define TNR_DS_FIL_8A_B3_HIST_3 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_8B (IO_TNR_BASE + 0xA44)
    #define TNR_DS_FIL_8B_B3_HIST_4 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_8C (IO_TNR_BASE + 0xA48)
    #define TNR_DS_FIL_8C_B3_HIST_5 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_8D (IO_TNR_BASE + 0xA4C)
    #define TNR_DS_FIL_8D_B3_HIST_6 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_8E (IO_TNR_BASE + 0xA50)
    #define TNR_DS_FIL_8E_B3_HIST_7 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_8F (IO_TNR_BASE + 0xA54)
    #define TNR_DS_FIL_8F_B3_HIST_8 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_90 (IO_TNR_BASE + 0xA58)
    #define TNR_DS_FIL_90_B3_HIST_9 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_91 (IO_TNR_BASE + 0xA5C)
    #define TNR_DS_FIL_91_B3_HIST_10 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_92 (IO_TNR_BASE + 0xA60)
    #define TNR_DS_FIL_92_B3_HIST_11 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_93 (IO_TNR_BASE + 0xA64)
    #define TNR_DS_FIL_93_B3_HIST_12 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_94 (IO_TNR_BASE + 0xA68)
    #define TNR_DS_FIL_94_B3_HIST_13 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_95 (IO_TNR_BASE + 0xA6C)
    #define TNR_DS_FIL_95_B3_HIST_14 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_96 (IO_TNR_BASE + 0xA70)
    #define TNR_DS_FIL_96_B3_HIST_15 Fld(24,0,AC_MSKDW)//[23:0]
#define TNR_DS_FIL_97 (IO_TNR_BASE + 0xA74)
    #define TNR_DS_FIL_97_H_FILTER_BAND0_DIV Fld(4,28,AC_MSKB3)//[31:28]
    #define TNR_DS_FIL_97_H_FILTER_BAND1_DIV Fld(4,24,AC_MSKB3)//[27:24]
    #define TNR_DS_FIL_97_H_FILTER_BAND2_DIV Fld(4,20,AC_MSKB2)//[23:20]
    #define TNR_DS_FIL_97_H_FILTER_BAND3_DIV Fld(4,16,AC_MSKB2)//[19:16]
    #define TNR_DS_FIL_97_H_FILTER_VSYNC_INV Fld(1,15,AC_MSKB1)//[15:15]
    #define TNR_DS_FIL_97_H_FILTER_X0_CNT_SEL Fld(1,14,AC_MSKB1)//[14:14]
#define TNR_RE_GEN_MAIN_00 (IO_TNR_BASE + 0x1B0)
    #define TNR_RE_GEN_MAIN_00_TNR_RE_GEN_ATPG_OB Fld(1,31,AC_MSKB3)//[31:31]
    #define TNR_RE_GEN_MAIN_00_TNR_RE_GEN_ATPG_CT Fld(1,30,AC_MSKB3)//[30:30]
    #define TNR_RE_GEN_MAIN_00_RG_M_SET_RES_FINISHED_O Fld(1,29,AC_MSKB3)//[29:29]
    #define TNR_RE_GEN_MAIN_00_RG_M_SET_RES_FINISHED_I Fld(1,28,AC_MSKB3)//[28:28]
    #define TNR_RE_GEN_MAIN_00_RG_M_SET_RES_CLEAR_O Fld(1,27,AC_MSKB3)//[27:27]
    #define TNR_RE_GEN_MAIN_00_RG_M_SET_RES_CLEAR_I Fld(1,26,AC_MSKB3)//[26:26]
    #define TNR_RE_GEN_MAIN_00_RG_M_SET_RES_ACTIVE Fld(1,25,AC_MSKB3)//[25:25]
    #define TNR_RE_GEN_MAIN_00_RG_M_SET_RES_MODE Fld(2,16,AC_MSKB2)//[17:16]
    #define TNR_RE_GEN_MAIN_00_RG_M_IN_FORMAT Fld(4,12,AC_MSKB1)//[15:12]
    #define TNR_RE_GEN_MAIN_00_RG_M_BYPASS_SET_RES_DB Fld(1,11,AC_MSKB1)//[11:11]
    #define TNR_RE_GEN_MAIN_00_RG_M_IN_DISP_R_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define TNR_RE_GEN_MAIN_00_RG_M_LR_PAIR_CTRL Fld(2,8,AC_MSKB1)//[9:8]
    #define TNR_RE_GEN_MAIN_00_RG_M_SET_RES_IN_TRIG_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define TNR_RE_GEN_MAIN_00_RG_M_EVEN_ONLY Fld(1,4,AC_MSKB0)//[4:4]
    #define TNR_RE_GEN_MAIN_00_RG_M_ODD_ONLY Fld(1,3,AC_MSKB0)//[3:3]
    #define TNR_RE_GEN_MAIN_00_RG_M_CLIP_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define TNR_RE_GEN_MAIN_00_RG_M_REGEN_ENABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define TNR_RE_GEN_MAIN_00_RG_M_REGEN_BYPASS Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_RE_GEN_MAIN_01 (IO_TNR_BASE + 0x1B4)
    #define TNR_RE_GEN_MAIN_01_RG_M_IN_ACTIVE_HEIGHT Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_RE_GEN_MAIN_01_RG_M_IN_ACTIVE_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_RE_GEN_MAIN_02 (IO_TNR_BASE + 0x1B8)
    #define TNR_RE_GEN_MAIN_02_RG_M_OUT_ACTIVE_HEIGHT Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_RE_GEN_MAIN_02_RG_M_OUT_ACTIVE_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_RE_GEN_MAIN_03 (IO_TNR_BASE + 0x1BC)
    #define TNR_RE_GEN_MAIN_03_RG_M_V_START_L Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_RE_GEN_MAIN_03_RG_M_H_START_L Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_RE_GEN_MAIN_04 (IO_TNR_BASE + 0x1C0)
    #define TNR_RE_GEN_MAIN_04_RG_M_V_START_R Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_RE_GEN_MAIN_04_RG_M_H_START_R Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_RE_GEN_MAIN_05 (IO_TNR_BASE + 0x1C4)
    #define TNR_RE_GEN_MAIN_05_RG_M_IN_HEIGHT_MEASURE Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_RE_GEN_MAIN_05_RG_M_IN_WIDTH_MEASURE Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_RE_GEN_MAIN_06 (IO_TNR_BASE + 0x1C8)
    #define TNR_RE_GEN_MAIN_06_RG_M_OUT_HEIGHT_MEASURE Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_RE_GEN_MAIN_06_RG_M_OUT_WIDTH_MEASURE Fld(16,0,AC_FULLW10)//[15:0]

#define TNR_REG00 (IO_TNR_BASE + 0x500)
    #define TNR_REG00_TNR_TOP_ATPG_OB Fld(1,1,AC_MSKB0)//[1:1]
    #define TNR_REG00_TNR_TOP_ATPG_CT Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_REG01 (IO_TNR_BASE + 0x504)
    #define TNR_REG01_TNR_INPTG_YPAT1 Fld(4,26,AC_MSKB3)//[29:26]
    #define TNR_REG01_TNR_INPTG_LEFT_SIDE Fld(1,25,AC_MSKB3)//[25:25]
    #define TNR_REG01_TNR_INPTG_PAT_DUTY_CYCLE Fld(5,20,AC_MSKW32)//[24:20]
    #define TNR_REG01_TNR_INPTG_ANGLE_SEL Fld(3,17,AC_MSKB2)//[19:17]
    #define TNR_REG01_TNR_INPTG_FREQ_SEL Fld(3,14,AC_MSKW21)//[16:14]
    #define TNR_REG01_TNR_INPTG_HOR_LINE_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define TNR_REG01_TNR_INPTG_COLOR_MODE Fld(2,11,AC_MSKB1)//[12:11]
    #define TNR_REG01_TNR_INPTG_PAT_MODE Fld(2,9,AC_MSKB1)//[10:9]
    #define TNR_REG01_TNR_INPTG_FREERUN_SPEED Fld(4,5,AC_MSKW10)//[8:5]
    #define TNR_REG01_TNR_INPTG_FREERUN_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define TNR_REG01_TNR_INPTG_BND_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define TNR_REG01_TNR_INPTG_3D_MODE Fld(2,1,AC_MSKB0)//[2:1]
    #define TNR_REG01_TNR_INPTG_3D_INV Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_REG02 (IO_TNR_BASE + 0x508)
    #define TNR_REG02_TNR_INPTG_BND_H Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_REG02_TNR_INPTG_BND_W Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_REG03 (IO_TNR_BASE + 0x51C)
    #define TNR_REG03_TNR_INPTG_ENABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define TNR_REG03_TNR_INPTG_YPAT2 Fld(4,0,AC_MSKB0)//[3:0]
#define TNR_REG04 (IO_TNR_BASE + 0x520)
    #define TNR_REG04_TNR_STA_HACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_REG04_TNR_STA_HTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_REG05 (IO_TNR_BASE + 0x524)
    #define TNR_REG05_TNR_STA_VACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define TNR_REG05_TNR_STA_VTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define TNR_REG08 (IO_TNR_BASE + 0x530)
    #define TNR_REG08_TNR_INV_MEASURE_H Fld(1,6,AC_MSKB0)//[6:6]
    #define TNR_REG08_TNR_INV_MEASURE_V Fld(1,5,AC_MSKB0)//[5:5]
    #define TNR_REG08_TNR_CLR_OUTPUT_MEASURE Fld(1,4,AC_MSKB0)//[4:4]
    #define TNR_REG08_TNR_OUTPUT_MEASURE_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define TNR_REG08_TNR_CLR_INPUT_MEASURE Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_REG09 (IO_TNR_BASE + 0x534)
    #define TNR_REG09_TNR_IN_CRC_CLIP_V_START Fld(12,18,AC_MSKW32)//[29:18]
    #define TNR_REG09_TNR_IN_CRC_CLIP_H_START Fld(13,5,AC_MSKDW)//[17:5]
    #define TNR_REG09_TNR_IN_CRC_CHECK_SUM_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define TNR_REG09_TNR_IN_CRC_BOT_R_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define TNR_REG09_TNR_IN_CRC_TOP_R_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define TNR_REG09_TNR_IN_CRC_BOT_L_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define TNR_REG09_TNR_IN_CRC_TOP_L_EN Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_REG0A (IO_TNR_BASE + 0x538)
    #define TNR_REG0A_TNR_IN_CRC_CLIP_V_END Fld(12,13,AC_MSKDW)//[24:13]
    #define TNR_REG0A_TNR_IN_CRC_CLIP_H_END Fld(13,0,AC_MSKW10)//[12:0]
#define TNR_REG0B (IO_TNR_BASE + 0x53C)
    #define TNR_REG0B_TNR_IN_CRC_V_IN_MASK Fld(10,20,AC_MSKW32)//[29:20]
    #define TNR_REG0B_TNR_IN_CRC_C_IN_MASK Fld(10,10,AC_MSKW21)//[19:10]
    #define TNR_REG0B_TNR_IN_CRC_Y_IN_MASK Fld(10,0,AC_MSKW10)//[9:0]
#define TNR_REG0C (IO_TNR_BASE + 0x540)
    #define TNR_REG0C_TNR_IN_STA_CRC_OUT_H Fld(32,0,AC_FULLDW)//[31:0]
#define TNR_REG0D (IO_TNR_BASE + 0x544)
    #define TNR_REG0D_TNR_IN_STA_CRC_OUT_V Fld(32,0,AC_FULLDW)//[31:0]
#define TNR_REG0E (IO_TNR_BASE + 0x548)
    #define TNR_REG0E_TNR_OUT_CRC_CLIP_V_START Fld(12,18,AC_MSKW32)//[29:18]
    #define TNR_REG0E_TNR_OUT_CRC_CLIP_H_START Fld(13,5,AC_MSKDW)//[17:5]
    #define TNR_REG0E_TNR_OUT_CRC_CHECK_SUM_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define TNR_REG0E_TNR_OUT_CRC_BOT_R_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define TNR_REG0E_TNR_OUT_CRC_TOP_R_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define TNR_REG0E_TNR_OUT_CRC_BOT_L_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define TNR_REG0E_TNR_OUT_CRC_TOP_L_EN Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_REG0F (IO_TNR_BASE + 0x54C)
    #define TNR_REG0F_TNR_OUT_CRC_CLIP_V_END Fld(12,13,AC_MSKDW)//[24:13]
    #define TNR_REG0F_TNR_OUT_CRC_CLIP_H_END Fld(13,0,AC_MSKW10)//[12:0]
#define TNR_REG10 (IO_TNR_BASE + 0x550)
    #define TNR_REG10_TNR_OUT_CRC_V_IN_MASK Fld(10,20,AC_MSKW32)//[29:20]
    #define TNR_REG10_TNR_OUT_CRC_C_IN_MASK Fld(10,10,AC_MSKW21)//[19:10]
    #define TNR_REG10_TNR_OUT_CRC_Y_IN_MASK Fld(10,0,AC_MSKW10)//[9:0]
#define TNR_REG11 (IO_TNR_BASE + 0x554)
    #define TNR_REG11_TNR_OUT_STA_CRC_OUT_H Fld(32,0,AC_FULLDW)//[31:0]
#define TNR_REG12 (IO_TNR_BASE + 0x558)
    #define TNR_REG12_TNR_OUT_STA_CRC_OUT_V Fld(32,0,AC_FULLDW)//[31:0]
#define TNR_REG13 (IO_TNR_BASE + 0x55C)
    #define TNR_REG13_TNR_420TO422_REPEAT_MODE Fld(1,24,AC_MSKB3)//[24:24]
    #define TNR_REG13_TNR_420TO422_DBUF_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define TNR_REG13_TNR_420TO422_SAMPLE_MODE Fld(1,22,AC_MSKB2)//[22:22]
    #define TNR_REG13_TNR_420TO422_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define TNR_REG13_TNR_PREV_OUT Fld(1,20,AC_MSKB2)//[20:20]
    #define TNR_REG13_TNR_I2P_SIZE_SEL Fld(1,19,AC_MSKB2)//[19:19]
    #define TNR_REG13_TNR_SET_RES_SEL Fld(2,17,AC_MSKB2)//[18:17]
    #define TNR_REG13_TNR_START_LINE Fld(13,4,AC_MSKDW)//[16:4]
    #define TNR_REG13_BYPASS_DIV2_REGEN_TNR Fld(1,1,AC_MSKB0)//[1:1]
    #define TNR_REG13_TNR_YUV2YC_EN Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_REG14 (IO_TNR_BASE + 0x560)
    #define TNR_REG14_RSVD0 Fld(32,0,AC_FULLDW)//[31:0]
#define TNR_REG15 (IO_TNR_BASE + 0x564)
    #define TNR_REG15_RSVD1 Fld(32,0,AC_FULLDW)//[31:0]
#define TNR_REG16 (IO_TNR_BASE + 0x568)
    #define TNR_REG16_TNR_OUT_PIX_TOTAL Fld(32,0,AC_FULLDW)//[31:0]
#define TNR_REG17 (IO_TNR_BASE + 0x56C)
    #define TNR_REG17_TNR_R_IN_PIX_TOTAL Fld(32,0,AC_FULLDW)//[31:0]
#define TNR_REG18 (IO_TNR_BASE + 0x570)
    #define TNR_REG18_NR3D_CUR_DONE Fld(1,26,AC_MSKB3)//[26:26]
    #define TNR_REG18_NR3D_CUR_LINE_CNT Fld(13,13,AC_MSKDW)//[25:13]
    #define TNR_REG18_NR3D_CUR_PXL_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define TNR_REG19 (IO_TNR_BASE + 0x574)
    #define TNR_REG19_NR3D_RDMA_DONE Fld(1,26,AC_MSKB3)//[26:26]
    #define TNR_REG19_NR3D_RDMA_LINE_CNT Fld(13,13,AC_MSKDW)//[25:13]
    #define TNR_REG19_NR3D_RDMA_PXL_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define TNR_REG20 (IO_TNR_BASE + 0x590)
    #define TNR_REG20_NR3D_WDMA_DONE Fld(1,26,AC_MSKB3)//[26:26]
    #define TNR_REG20_NR3D_WDMA_LINE_CNT Fld(13,13,AC_MSKDW)//[25:13]
    #define TNR_REG20_NR3D_WDMA_PXL_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define TNR_REG21 (IO_TNR_BASE + 0x594)
    #define TNR_REG21_SW_RST Fld(3,0,AC_MSKB0)//[2:0]
#define TNR_YCBCR2YC_MAIN_00 (IO_TNR_BASE + 0x1F0)
    #define TNR_YCBCR2YC_MAIN_00_TNR_YCBCR2YC_ATPG_CT Fld(1,9,AC_MSKB1)//[9:9]
    #define TNR_YCBCR2YC_MAIN_00_TNR_YCBCR2YC_ATPG_OB Fld(1,8,AC_MSKB1)//[8:8]
    #define TNR_YCBCR2YC_MAIN_00_C_MAIN_LEFT_PADDING Fld(1,7,AC_MSKB0)//[7:7]
    #define TNR_YCBCR2YC_MAIN_00_C_MAIN_MIRROR_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define TNR_YCBCR2YC_MAIN_00_C_MAIN_EVEN_EXTEND Fld(1,5,AC_MSKB0)//[5:5]
    #define TNR_YCBCR2YC_MAIN_00_C_MAIN_NOSYNC_BLOCK Fld(1,4,AC_MSKB0)//[4:4]
    #define TNR_YCBCR2YC_MAIN_00_C_MAIN_KEEP_LAST_DATA Fld(1,3,AC_MSKB0)//[3:3]
    #define TNR_YCBCR2YC_MAIN_00_C_MAIN_HSYNC_BLACK Fld(1,2,AC_MSKB0)//[2:2]
    #define TNR_YCBCR2YC_MAIN_00_C_MAIN_FILTER_ON Fld(1,1,AC_MSKB0)//[1:1]
    #define TNR_YCBCR2YC_MAIN_00_C_MAIN_ENA Fld(1,0,AC_MSKB0)//[0:0]
#define TNR_YCBCR2YC_WDMA_00 (IO_TNR_BASE + 0x1F4)
    #define TNR_YCBCR2YC_WDMA_00_TNR_YCBCR2YC_WDMA_ATPG_CT Fld(1,9,AC_MSKB1)//[9:9]
    #define TNR_YCBCR2YC_WDMA_00_TNR_YCBCR2YC_WDMA_ATPG_OB Fld(1,8,AC_MSKB1)//[8:8]
    #define TNR_YCBCR2YC_WDMA_00_C_WDMA_LEFT_PADDING Fld(1,7,AC_MSKB0)//[7:7]
    #define TNR_YCBCR2YC_WDMA_00_C_WDMA_MIRROR_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define TNR_YCBCR2YC_WDMA_00_C_WDMA_EVEN_EXTEND Fld(1,5,AC_MSKB0)//[5:5]
    #define TNR_YCBCR2YC_WDMA_00_C_WDMA_NOSYNC_BLOCK Fld(1,4,AC_MSKB0)//[4:4]
    #define TNR_YCBCR2YC_WDMA_00_C_WDMA_KEEP_LAST_DATA Fld(1,3,AC_MSKB0)//[3:3]
    #define TNR_YCBCR2YC_WDMA_00_C_WDMA_HSYNC_BLACK Fld(1,2,AC_MSKB0)//[2:2]
    #define TNR_YCBCR2YC_WDMA_00_C_WDMA_FILTER_ON Fld(1,1,AC_MSKB0)//[1:1]
    #define TNR_YCBCR2YC_WDMA_00_C_WDMA_ENA Fld(1,0,AC_MSKB0)//[0:0]

#define NR3D_ENG_CON (IO_TNR_BASE + 0x200)
    #define NR3D_ENG_CON_USR_TILE_LOSS_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define NR3D_ENG_CON_STAT_SOF_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define NR3D_ENG_CON_EOT_SEQ_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define NR3D_ENG_CON_NR3D_SKIP_MODE Fld(1,13,AC_MSKB1)//[13:13]
    #define NR3D_ENG_CON_NR3D_UV_SIGNED Fld(1,12,AC_MSKB1)//[12:12]
    #define NR3D_ENG_CON_IN_RND_MODE Fld(2,5,AC_MSKB0)//[6:5]
    #define NR3D_ENG_CON_R2C_LBIT_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define NR3D_ENG_CON_NR3D_RESET Fld(1,3,AC_MSKB0)//[3:3]
    #define NR3D_ENG_CON_NR3D_DCM_DIS Fld(1,2,AC_MSKB0)//[2:2]
    #define NR3D_ENG_CON_NR3D_LBIT_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define NR3D_ENG_CON_YCLNR_EN Fld(1,0,AC_MSKB0)//[0:0]
#define NR3D_SIZ (IO_TNR_BASE + 0x204)
    #define NR3D_SIZ_NR3D_HT Fld(13,16,AC_MSKW32)//[28:16]
    #define NR3D_SIZ_NR3D_WD Fld(13,0,AC_MSKW10)//[12:0]
#define NR3D_TILE_XY (IO_TNR_BASE + 0x208)
    #define NR3D_TILE_XY_NR3D_TILE_Y Fld(13,16,AC_MSKW32)//[28:16]
    #define NR3D_TILE_XY_NR3D_TILE_X Fld(13,0,AC_MSKW10)//[12:0]
#define NR3D_ON_CON (IO_TNR_BASE + 0x20C)
    #define NR3D_ON_CON_SL2_OFF Fld(1,20,AC_MSKB2)//[20:20]
    #define NR3D_ON_CON_NR3D_TILE_EDGE Fld(4,8,AC_MSKB1)//[11:8]
    #define NR3D_ON_CON_ON_EN Fld(1,4,AC_MSKB0)//[4:4]
#define NR3D_ON_OFF (IO_TNR_BASE + 0x210)
    #define NR3D_ON_OFF_NR3D_ON_OFST_Y Fld(13,16,AC_MSKW32)//[28:16]
    #define NR3D_ON_OFF_NR3D_ON_OFST_X Fld(13,0,AC_MSKW10)//[12:0]
#define NR3D_ON_SIZ (IO_TNR_BASE + 0x214)
    #define NR3D_ON_SIZ_NR3D_ON_HT Fld(13,16,AC_MSKW32)//[28:16]
    #define NR3D_ON_SIZ_NR3D_ON_WD Fld(13,0,AC_MSKW10)//[12:0]
#define NR3D_TNR_ENABLE (IO_TNR_BASE + 0x218)
    #define NR3D_TNR_ENABLE_TNR_Y_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define NR3D_TNR_ENABLE_TNR_C_EN Fld(1,30,AC_MSKB3)//[30:30]
#define NR3D_FLT_CONFIG (IO_TNR_BASE + 0x21C)
    #define NR3D_FLT_CONFIG_BLEND_RATIO_BLKY Fld(5,27,AC_MSKB3)//[31:27]
    #define NR3D_FLT_CONFIG_BLEND_RATIO_DE Fld(5,22,AC_MSKW32)//[26:22]
    #define NR3D_FLT_CONFIG_BLEND_RATIO_TXTR Fld(5,17,AC_MSKB2)//[21:17]
    #define NR3D_FLT_CONFIG_BLEND_RATIO_MV Fld(5,12,AC_MSKW21)//[16:12]
    #define NR3D_FLT_CONFIG_FLT_STR_MAX Fld(6,6,AC_MSKW10)//[11:6]
    #define NR3D_FLT_CONFIG_EN_CYCR Fld(1,5,AC_MSKB0)//[5:5]
    #define NR3D_FLT_CONFIG_EN_CCR Fld(1,4,AC_MSKB0)//[4:4]
#define NR3D_FB_INFO1 (IO_TNR_BASE + 0x220)
    #define NR3D_FB_INFO1_Q_NL Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_FB_INFO1_Q_SP Fld(6,20,AC_MSKW32)//[25:20]
    
    //Page TNR_3
#define NR3D_THR_1 (IO_TNR_BASE + 0x224)
    #define NR3D_THR_1_BDI_THR Fld(4,26,AC_MSKB3)//[29:26]
    #define NR3D_THR_1_MV_PEN_W Fld(4,22,AC_MSKW32)//[25:22]
    #define NR3D_THR_1_MV_PEN_THR Fld(6,16,AC_MSKB2)//[21:16]
    #define NR3D_THR_1_SMALL_SAD_THR Fld(6,10,AC_MSKB1)//[15:10]
#define NR3D_CURVE_1 (IO_TNR_BASE + 0x228)
    #define NR3D_CURVE_1_Q_BLKY_Y0 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_1_Q_BLKY_Y1 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_1_Q_BLKY_Y2 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_1_Q_BLKY_Y3 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_1_Q_BLKY_Y4 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_2 (IO_TNR_BASE + 0x22C)
    #define NR3D_CURVE_2_Q_BLKY_Y5 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_2_Q_BLKY_Y6 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_2_Q_BLKY_Y7 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_2_Q_BLKC_Y0 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_2_Q_BLKC_Y1 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_3 (IO_TNR_BASE + 0x230)
    #define NR3D_CURVE_3_Q_BLKC_Y2 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_3_Q_BLKC_Y3 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_3_Q_BLKC_Y4 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_3_Q_BLKC_Y5 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_3_Q_BLKC_Y6 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_4 (IO_TNR_BASE + 0x234)
    #define NR3D_CURVE_4_Q_BLKC_Y7 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_4_Q_DETXTR_LVL_Y0 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_4_Q_DETXTR_LVL_Y1 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_4_Q_DETXTR_LVL_Y2 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_4_Q_DETXTR_LVL_Y3 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_5 (IO_TNR_BASE + 0x238)
    #define NR3D_CURVE_5_Q_DETXTR_LVL_Y4 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_5_Q_DETXTR_LVL_Y5 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_5_Q_DETXTR_LVL_Y6 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_5_Q_DETXTR_LVL_Y7 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_5_Q_DE1_BASE_Y0 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_6 (IO_TNR_BASE + 0x23C)
    #define NR3D_CURVE_6_Q_DE1_BASE_Y1 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_6_Q_DE1_BASE_Y2 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_6_Q_DE1_BASE_Y3 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_6_Q_DE1_BASE_Y4 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_6_Q_DE1_BASE_Y5 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_7 (IO_TNR_BASE + 0x240)
    #define NR3D_CURVE_7_Q_DE1_BASE_Y6 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_7_Q_DE1_BASE_Y7 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_7_Q_DE2TXTR_BASE_Y0 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_7_Q_DE2TXTR_BASE_Y1 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_7_Q_DE2TXTR_BASE_Y2 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_8 (IO_TNR_BASE + 0x244)
    #define NR3D_CURVE_8_Q_DE2TXTR_BASE_Y3 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_8_Q_DE2TXTR_BASE_Y4 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_8_Q_DE2TXTR_BASE_Y5 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_8_Q_DE2TXTR_BASE_Y6 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_8_Q_DE2TXTR_BASE_Y7 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_9 (IO_TNR_BASE + 0x248)
    #define NR3D_CURVE_9_Q_MV_Y0 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_9_Q_MV_Y1 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_9_Q_MV_Y2 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_9_Q_MV_Y3 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_9_Q_MV_Y4 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_10 (IO_TNR_BASE + 0x24C)
    #define NR3D_CURVE_10_Q_MV_Y5 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_10_Q_MV_Y6 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_10_Q_MV_Y7 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_10_Q_WVAR_Y0 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_10_Q_WVAR_Y1 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_11 (IO_TNR_BASE + 0x250)
    #define NR3D_CURVE_11_Q_WVAR_Y2 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_11_Q_WVAR_Y3 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_11_Q_WVAR_Y4 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_11_Q_WVAR_Y5 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_11_Q_WVAR_Y6 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_12 (IO_TNR_BASE + 0x254)
    #define NR3D_CURVE_12_Q_WVAR_Y7 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_12_Q_WSM_Y0 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_12_Q_WSM_Y1 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_12_Q_WSM_Y2 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_12_Q_WSM_Y3 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_13 (IO_TNR_BASE + 0x258)
    #define NR3D_CURVE_13_Q_WSM_Y4 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_13_Q_WSM_Y5 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_13_Q_WSM_Y6 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_13_Q_WSM_Y7 Fld(6,8,AC_MSKB1)//[13:8]
#define NR3D_CURVE_14 (IO_TNR_BASE + 0x25C)
    #define NR3D_CURVE_14_Q_SDL_Y0 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_14_Q_SDL_Y1 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_14_Q_SDL_Y2 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_14_Q_SDL_Y3 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_CURVE_14_Q_SDL_Y4 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_CURVE_15 (IO_TNR_BASE + 0x260)
    #define NR3D_CURVE_15_Q_SDL_Y5 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_CURVE_15_Q_SDL_Y6 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_CURVE_15_Q_SDL_Y7 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_CURVE_15_Q_SDL_Y8 Fld(6,8,AC_MSKB1)//[13:8]
#define NR3D_R2C_1 (IO_TNR_BASE + 0x264)
    #define NR3D_R2C_1_R2C_VAL1 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_R2C_1_R2C_VAL2 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_R2C_1_R2C_VAL3 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_R2C_1_R2C_VAL4 Fld(6,2,AC_MSKB0)//[7:2]
    #define NR3D_R2C_1_R2CENC Fld(2,0,AC_MSKB0)//[1:0]
#define NR3D_R2C_2 (IO_TNR_BASE + 0x268)
    #define NR3D_R2C_2_R2C_TXTR_THR1 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_R2C_2_R2C_TXTR_THR2 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_R2C_2_R2C_TXTR_THR3 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_R2C_2_R2C_TXTR_THR4 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_R2C_2_R2C_TXTR_THROFF Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_R2C_3 (IO_TNR_BASE + 0x26C)
    #define NR3D_R2C_3_R2CF_CNT1 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_R2C_3_R2CF_CNT2 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_R2C_3_R2CF_CNT3 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_R2C_3_R2CF_CNT4 Fld(6,8,AC_MSKB1)//[13:8]
#define NR3D_DBG_6 (IO_TNR_BASE + 0x270)
    #define NR3D_DBG_6_FORCE_FLT_STR Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_DBG_6_INK_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define NR3D_DBG_6_INK_Y_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define NR3D_DBG_6_INK_SEL Fld(5,19,AC_MSKB2)//[23:19]
    #define NR3D_DBG_6_INK_LEVEL_DISP Fld(16,3,AC_MSKDW)//[18:3]
    #define NR3D_DBG_6_FORCE_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define NR3D_DBG_6_ONE_FRAME_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define NR3D_DBG_15 (IO_TNR_BASE + 0x274)
    #define NR3D_DBG_15_OSD_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define NR3D_DBG_15_OSD_SEL Fld(3,28,AC_MSKB3)//[30:28]
    #define NR3D_DBG_15_OSD_TARGH Fld(13,15,AC_MSKDW)//[27:15]
    #define NR3D_DBG_15_OSD_TARGV Fld(13,2,AC_MSKW10)//[14:2]
#define NR3D_DBG_16 (IO_TNR_BASE + 0x278)
    #define NR3D_DBG_16_OSD_DISPH Fld(13,19,AC_MSKW32)//[31:19]
    #define NR3D_DBG_16_OSD_DISPV Fld(13,6,AC_MSKDW)//[18:6]
    #define NR3D_DBG_16_OSD_DISP_SCALE Fld(2,4,AC_MSKB0)//[5:4]
    #define NR3D_DBG_16_OSD_Y_EN Fld(1,3,AC_MSKB0)//[3:3]
#define NR3D_DEMO_1 (IO_TNR_BASE + 0x27C)
    #define NR3D_DEMO_1_DEMO_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define NR3D_DEMO_1_DEMO_SEL Fld(1,30,AC_MSKB3)//[30:30]
    #define NR3D_DEMO_1_DEMO_TOP Fld(13,17,AC_MSKW32)//[29:17]
    #define NR3D_DEMO_1_DEMO_BOT Fld(13,4,AC_MSKDW)//[16:4]
#define NR3D_DEMO_2 (IO_TNR_BASE + 0x280)
    #define NR3D_DEMO_2_DEMO_LEFT Fld(13,19,AC_MSKW32)//[31:19]
    #define NR3D_DEMO_2_DEMO_RIGHT Fld(13,6,AC_MSKDW)//[18:6]
#define NR3D_ATPG (IO_TNR_BASE + 0x284)
    #define NR3D_ATPG_NR3D_ATPG_CT Fld(1,1,AC_MSKB0)//[1:1]
    #define NR3D_ATPG_NR3D_ATPG_OB Fld(1,0,AC_MSKB0)//[0:0]
#define NR3D_DMY_0 (IO_TNR_BASE + 0x288)
    #define NR3D_DMY_0_TNR_DUMMY0 Fld(32,0,AC_FULLDW)//[31:0]
#define NR3D_DBG_17 (IO_TNR_BASE + 0x28C)
    #define NR3D_DBG_17_OSD_INFO_C Fld(16,16,AC_FULLW32)//[31:16]
    #define NR3D_DBG_17_OSD_INFO_Y Fld(16,0,AC_FULLW10)//[15:0]
#define NR3D_INTERR (IO_TNR_BASE + 0x2BC)
    #define NR3D_INTERR_INT_RDMA_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define NR3D_INTERR_INT_OF_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define NR3D_INTERR_INT_IF3_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define NR3D_INTERR_INT_IF2_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define NR3D_INTERR_INT_IF1_EN Fld(1,0,AC_MSKB0)//[0:0]
#define NR3D_FB_INFO2 (IO_TNR_BASE + 0x2C4)
    #define NR3D_FB_INFO2_Q_NL_SUM Fld(32,0,AC_FULLDW)//[31:0]
#define NR3D_FB_INFO3 (IO_TNR_BASE + 0x2C8)
    #define NR3D_FB_INFO3_Q_SP_SUM Fld(32,0,AC_FULLDW)//[31:0]
#define NR3D_FB_INFO4 (IO_TNR_BASE + 0x2CC)
    #define NR3D_FB_INFO4_Q_STILL_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define NR3D_DBFISH (IO_TNR_BASE + 0x2D0)
    #define NR3D_DBFISH_DBUF_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define NR3D_DBFISH_REG_PROTECT Fld(1,30,AC_MSKB3)//[30:30]
    #define NR3D_DBFISH_READ_WORKING Fld(1,29,AC_MSKB3)//[29:29]
#define NR3D_DBG_9 (IO_TNR_BASE + 0x2D4)
    #define NR3D_DBG_9_INK_COLOR_Y0 Fld(4,28,AC_MSKB3)//[31:28]
    #define NR3D_DBG_9_INK_COLOR_Y1 Fld(4,24,AC_MSKB3)//[27:24]
    #define NR3D_DBG_9_INK_COLOR_Y2 Fld(4,20,AC_MSKB2)//[23:20]
    #define NR3D_DBG_9_INK_COLOR_Y3 Fld(4,16,AC_MSKB2)//[19:16]
    #define NR3D_DBG_9_INK_COLOR_Y4 Fld(4,12,AC_MSKB1)//[15:12]
    #define NR3D_DBG_9_INK_COLOR_Y5 Fld(4,8,AC_MSKB1)//[11:8]
    #define NR3D_DBG_9_INK_COLOR_Y6 Fld(4,4,AC_MSKB0)//[7:4]
    #define NR3D_DBG_9_INK_COLOR_Y7 Fld(4,0,AC_MSKB0)//[3:0]
#define NR3D_DBG_10 (IO_TNR_BASE + 0x2D8)
    #define NR3D_DBG_10_INK_COLOR_Y8 Fld(4,28,AC_MSKB3)//[31:28]
    #define NR3D_DBG_10_INK_COLOR_Y9 Fld(4,24,AC_MSKB3)//[27:24]
    #define NR3D_DBG_10_INK_COLOR_Y10 Fld(4,20,AC_MSKB2)//[23:20]
    #define NR3D_DBG_10_INK_COLOR_Y11 Fld(4,16,AC_MSKB2)//[19:16]
    #define NR3D_DBG_10_INK_COLOR_Y12 Fld(4,12,AC_MSKB1)//[15:12]
    #define NR3D_DBG_10_INK_COLOR_Y13 Fld(4,8,AC_MSKB1)//[11:8]
    #define NR3D_DBG_10_INK_COLOR_Y14 Fld(4,4,AC_MSKB0)//[7:4]
    #define NR3D_DBG_10_INK_COLOR_Y15 Fld(4,0,AC_MSKB0)//[3:0]
#define NR3D_DBG_11 (IO_TNR_BASE + 0x2DC)
    #define NR3D_DBG_11_INK_COLOR_C0 Fld(4,28,AC_MSKB3)//[31:28]
    #define NR3D_DBG_11_INK_COLOR_C1 Fld(4,24,AC_MSKB3)//[27:24]
    #define NR3D_DBG_11_INK_COLOR_C2 Fld(4,20,AC_MSKB2)//[23:20]
    #define NR3D_DBG_11_INK_COLOR_C3 Fld(4,16,AC_MSKB2)//[19:16]
    #define NR3D_DBG_11_INK_COLOR_C4 Fld(4,12,AC_MSKB1)//[15:12]
    #define NR3D_DBG_11_INK_COLOR_C5 Fld(4,8,AC_MSKB1)//[11:8]
    #define NR3D_DBG_11_INK_COLOR_C6 Fld(4,4,AC_MSKB0)//[7:4]
    #define NR3D_DBG_11_INK_COLOR_C7 Fld(4,0,AC_MSKB0)//[3:0]
#define NR3D_DBG_12 (IO_TNR_BASE + 0x2E0)
    #define NR3D_DBG_12_INK_COLOR_C8 Fld(4,28,AC_MSKB3)//[31:28]
    #define NR3D_DBG_12_INK_COLOR_C9 Fld(4,24,AC_MSKB3)//[27:24]
    #define NR3D_DBG_12_INK_COLOR_C10 Fld(4,20,AC_MSKB2)//[23:20]
    #define NR3D_DBG_12_INK_COLOR_C11 Fld(4,16,AC_MSKB2)//[19:16]
    #define NR3D_DBG_12_INK_COLOR_C12 Fld(4,12,AC_MSKB1)//[15:12]
    #define NR3D_DBG_12_INK_COLOR_C13 Fld(4,8,AC_MSKB1)//[11:8]
    #define NR3D_DBG_12_INK_COLOR_C14 Fld(4,4,AC_MSKB0)//[7:4]
    #define NR3D_DBG_12_INK_COLOR_C15 Fld(4,0,AC_MSKB0)//[3:0]
#define NR3D_DBG_7 (IO_TNR_BASE + 0x2EC)
    #define NR3D_DBG_7_OSD_COLOR_BG_Y Fld(4,28,AC_MSKB3)//[31:28]
    #define NR3D_DBG_7_OSD_COLOR_BG_C Fld(4,24,AC_MSKB3)//[27:24]
    #define NR3D_DBG_7_OSD_COLOR_FG0_Y Fld(4,16,AC_MSKB2)//[19:16]
    #define NR3D_DBG_7_OSD_COLOR_FG0_C Fld(4,12,AC_MSKB1)//[15:12]
    #define NR3D_DBG_7_OSD_COLOR_FG1_Y Fld(4,4,AC_MSKB0)//[7:4]
    #define NR3D_DBG_7_OSD_COLOR_FG1_C Fld(4,0,AC_MSKB0)//[3:0]
#define NR3D_DMY_1 (IO_TNR_BASE + 0x304)
    #define NR3D_DMY_1_TNR_DUMMY1 Fld(32,0,AC_FULLDW)//[31:0]
#define NR3D_DMY_2 (IO_TNR_BASE + 0x308)
    #define NR3D_DMY_2_TNR_DUMMY2 Fld(32,0,AC_FULLDW)//[31:0]
#define NR3D_SAVE_INFO1 (IO_TNR_BASE + 0x320)
    #define NR3D_SAVE_INFO1_HIST_TOP Fld(13,19,AC_MSKW32)//[31:19]
    #define NR3D_SAVE_INFO1_HIST_BOT Fld(13,6,AC_MSKDW)//[18:6]
#define NR3D_SAVE_INFO2 (IO_TNR_BASE + 0x324)
    #define NR3D_SAVE_INFO2_HIST_LEFT Fld(13,19,AC_MSKW32)//[31:19]
    #define NR3D_SAVE_INFO2_HIST_RIGHT Fld(13,6,AC_MSKDW)//[18:6]
#define NR3D_SNR_CURVE_1 (IO_TNR_BASE + 0x3CC)
    #define NR3D_SNR_CURVE_1_Q_SNR_TPRE_Y0 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_SNR_CURVE_1_Q_SNR_TPRE_Y1 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_SNR_CURVE_1_Q_SNR_TPRE_Y2 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_SNR_CURVE_1_Q_SNR_TPRE_Y3 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_SNR_CURVE_1_Q_SNR_TPRE_Y4 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_SNR_CURVE_2 (IO_TNR_BASE + 0x3D0)
    #define NR3D_SNR_CURVE_2_Q_SNR_TPRE_Y5 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_SNR_CURVE_2_Q_SNR_TPRE_Y6 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_SNR_CURVE_2_Q_SNR_TPRE_Y7 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_SNR_CURVE_2_Q_SNR_TPRE_Y8 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_SNR_CURVE_2_Q_SNR_TXTR_Y0 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_SNR_CURVE_3 (IO_TNR_BASE + 0x3D4)
    #define NR3D_SNR_CURVE_3_Q_SNR_TXTR_Y1 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_SNR_CURVE_3_Q_SNR_TXTR_Y2 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_SNR_CURVE_3_Q_SNR_TXTR_Y3 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_SNR_CURVE_3_Q_SNR_TXTR_Y4 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_SNR_CURVE_3_Q_SNR_TXTR_Y5 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_SNR_CURVE_4 (IO_TNR_BASE + 0x3D8)
    #define NR3D_SNR_CURVE_4_Q_SNR_TXTR_Y6 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_SNR_CURVE_4_Q_SNR_TXTR_Y7 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_SNR_CURVE_4_Q_SNR_LUMA_Y0 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_SNR_CURVE_4_Q_SNR_LUMA_Y1 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_SNR_CURVE_4_Q_SNR_LUMA_Y2 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_SNR_CURVE_5 (IO_TNR_BASE + 0x3DC)
    #define NR3D_SNR_CURVE_5_Q_SNR_LUMA_Y3 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_SNR_CURVE_5_Q_SNR_LUMA_Y4 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_SNR_CURVE_5_Q_SNR_LUMA_Y5 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_SNR_CURVE_5_Q_SNR_LUMA_Y6 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_SNR_CURVE_5_Q_SNR_LUMA_Y7 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_SNR_CURVE_6 (IO_TNR_BASE + 0x3E0)
    #define NR3D_SNR_CURVE_6_Q_SNR_LUMA_Y8 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_SNR_CURVE_6_Q_SNR_TPST_Y0 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_SNR_CURVE_6_Q_SNR_TPST_Y1 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_SNR_CURVE_6_Q_SNR_TPST_Y2 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_SNR_CURVE_6_Q_SNR_TPST_Y3 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_SNR_CURVE_7 (IO_TNR_BASE + 0x3E4)
    #define NR3D_SNR_CURVE_7_Q_SNR_TPST_Y4 Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_SNR_CURVE_7_Q_SNR_TPST_Y5 Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_SNR_CURVE_7_Q_SNR_TPST_Y6 Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_SNR_CURVE_7_Q_SNR_TPST_Y7 Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_SNR_CURVE_7_Q_SNR_TPST_Y8 Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_SNR_CONTROL_1 (IO_TNR_BASE + 0x3FC)
    #define NR3D_SNR_CONTROL_1_SNR_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define NR3D_SNR_CONTROL_1_SNR_PRE2D_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define NR3D_SNR_CONTROL_1_SNR_POST2D_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define NR3D_SNR_CONTROL_1_SNR_TPRE_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define NR3D_SNR_CONTROL_1_SNR_TXTR_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define NR3D_SNR_CONTROL_1_SNR_LUMA_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define NR3D_SNR_CONTROL_1_SNR_BLEND_MAXMIN Fld(1,17,AC_MSKB2)//[17:17]
#define NR3D_SNR_THR_2 (IO_TNR_BASE + 0x40C)
    #define NR3D_SNR_THR_2_BLKVAR_TOLERANCE Fld(8,24,AC_FULLB3)//[31:24]
    #define NR3D_SNR_THR_2_CENTVAR_TOLERANCE Fld(8,16,AC_FULLB2)//[23:16]
    #define NR3D_SNR_THR_2_TOLERANCE_CLIP Fld(6,10,AC_MSKB1)//[15:10]
#define NR3D_SNR_THR_3 (IO_TNR_BASE + 0x410)
    #define NR3D_SNR_THR_3_SAD_INVWEI Fld(6,10,AC_MSKB1)//[15:10]
    #define NR3D_SNR_THR_3_CENT_CAND_WEI Fld(6,4,AC_MSKW10)//[9:4]
#define NR3D_SNR_THR_4 (IO_TNR_BASE + 0x414)
    #define NR3D_SNR_THR_4_HFRR_HF_RATIO Fld(6,26,AC_MSKB3)//[31:26]
    #define NR3D_SNR_THR_4_HFRR_MF_RATIO Fld(6,20,AC_MSKW32)//[25:20]
    #define NR3D_SNR_THR_4_ADD_CURR_RATIO Fld(6,14,AC_MSKW21)//[19:14]
    #define NR3D_SNR_THR_4_HFRR_POST2D_HF_RATIO Fld(6,8,AC_MSKB1)//[13:8]
    #define NR3D_SNR_THR_4_HFRR_POST2D_MF_RATIO Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_IN1_CNT (IO_TNR_BASE + 0x418)
    #define NR3D_IN1_CNT_IN1_LINE_CNT Fld(13,16,AC_MSKW32)//[28:16]
    #define NR3D_IN1_CNT_IN1_PXL_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define NR3D_IN2_CNT (IO_TNR_BASE + 0x41C)
    #define NR3D_IN2_CNT_IN2_LINE_CNT Fld(13,16,AC_MSKW32)//[28:16]
    #define NR3D_IN2_CNT_IN2_PXL_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define NR3D_IN3_CNT (IO_TNR_BASE + 0x420)
    #define NR3D_IN3_CNT_IN3_LINE_CNT Fld(13,16,AC_MSKW32)//[28:16]
    #define NR3D_IN3_CNT_IN3_PXL_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define NR3D_OUT_CNT (IO_TNR_BASE + 0x424)
    #define NR3D_OUT_CNT_OUT_LINE_CNT Fld(13,16,AC_MSKW32)//[28:16]
    #define NR3D_OUT_CNT_OUT_PXL_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define NR3D_STATUS (IO_TNR_BASE + 0x428)
    #define NR3D_STATUS_RDMA_UNF Fld(1,4,AC_MSKB0)//[4:4]
    #define NR3D_STATUS_OF_END Fld(1,3,AC_MSKB0)//[3:3]
    #define NR3D_STATUS_IF3_END Fld(1,2,AC_MSKB0)//[2:2]
    #define NR3D_STATUS_IF2_END Fld(1,1,AC_MSKB0)//[1:1]
    #define NR3D_STATUS_IF1_END Fld(1,0,AC_MSKB0)//[0:0]
#define NR3D_TILE_LOSS (IO_TNR_BASE + 0x42C)
    #define NR3D_TILE_LOSS_USR_TILE_LOSS_V Fld(13,16,AC_MSKW32)//[28:16]
    #define NR3D_TILE_LOSS_USR_TILE_LOSS_H Fld(13,0,AC_MSKW10)//[12:0]
#define NR3D_MCVP_STAT1 (IO_TNR_BASE + 0x430)
    #define NR3D_MCVP_STAT1_IF_HD_H_HI_NORMALIZ Fld(4,28,AC_MSKB3)//[31:28]
    #define NR3D_MCVP_STAT1_IF_HD_H_MI_NORMALIZ Fld(4,24,AC_MSKB3)//[27:24]
    #define NR3D_MCVP_STAT1_IF_HD_H_DEAD_ZONE Fld(8,16,AC_FULLB2)//[23:16]
    #define NR3D_MCVP_STAT1_IF_HD_H_M_DEAD_ZONE Fld(8,8,AC_FULLB1)//[15:8]
    #define NR3D_MCVP_STAT1_IF_HD_F_DEAD_ZONE Fld(6,2,AC_MSKB0)//[7:2]
#define NR3D_MCVP_STAT2 (IO_TNR_BASE + 0x434)
    #define NR3D_MCVP_STAT2_IF_HD_HOR_HI_F_SUM Fld(8,24,AC_FULLB3)//[31:24]
    #define NR3D_MCVP_STAT2_IF_HD_HOR_MID_F_SUM Fld(8,16,AC_FULLB2)//[23:16]
    #define NR3D_MCVP_STAT2_IF_HD_FIELD_HI_F_SUM Fld(8,8,AC_FULLB1)//[15:8]
#define NR3D_MCVP_STAT3 (IO_TNR_BASE + 0x438)
    #define NR3D_MCVP_STAT3_IF_HD_FIELD_HI_F_DBL Fld(1,13,AC_MSKB1)//[13:13]
    #define NR3D_MCVP_STAT3_IF_HD_V_HI_NORMALIZ Fld(4,9,AC_MSKB1)//[12:9]
#define NR3D_MCVP_STAT4 (IO_TNR_BASE + 0x43C)
    #define NR3D_MCVP_STAT4_C_FD_QUAN_VALUE1 Fld(8,24,AC_FULLB3)//[31:24]
    #define NR3D_MCVP_STAT4_C_FD_QUAN_VALUE2 Fld(8,16,AC_FULLB2)//[23:16]
    #define NR3D_MCVP_STAT4_C_FD_QUAN_VALUE3 Fld(8,8,AC_FULLB1)//[15:8]
    #define NR3D_MCVP_STAT4_C_FD_QUAN_VALUE4 Fld(8,0,AC_FULLB0)//[7:0]
    
    //Page TNR_4
#define NR3D_MCVP_STAT5 (IO_TNR_BASE + 0x440)
    #define NR3D_MCVP_STAT5_C_FD_QUAN_VALUE5 Fld(8,24,AC_FULLB3)//[31:24]
    #define NR3D_MCVP_STAT5_C_FD_QUAN_VALUE6 Fld(8,16,AC_FULLB2)//[23:16]
    #define NR3D_MCVP_STAT5_C_FD_QUAN_TH1 Fld(8,8,AC_FULLB1)//[15:8]
    #define NR3D_MCVP_STAT5_C_FD_QUAN_TH2 Fld(8,0,AC_FULLB0)//[7:0]
#define NR3D_MCVP_STAT6 (IO_TNR_BASE + 0x444)
    #define NR3D_MCVP_STAT6_C_FD_QUAN_TH3 Fld(8,24,AC_FULLB3)//[31:24]
    #define NR3D_MCVP_STAT6_C_FD_QUAN_TH4 Fld(8,16,AC_FULLB2)//[23:16]
    #define NR3D_MCVP_STAT6_C_FD_QUAN_TH5 Fld(8,8,AC_FULLB1)//[15:8]
    #define NR3D_MCVP_STAT6_C_FD_MOV_PXL_TH2 Fld(4,4,AC_MSKB0)//[7:4]
    #define NR3D_MCVP_STAT6_C_FD_MOV_PXL_TH1 Fld(4,0,AC_MSKB0)//[3:0]
#define NR3D_MCVP_STAT7 (IO_TNR_BASE + 0x448)
    #define NR3D_MCVP_STAT7_C_FD_MOV_MAX_THR Fld(16,16,AC_FULLW32)//[31:16]
    #define NR3D_MCVP_STAT7_C_FD_PRV_FRM_SMALL Fld(1,15,AC_MSKB1)//[15:15]
#define NR3D_MCVP_STAT8 (IO_TNR_BASE + 0x44C)
    #define NR3D_MCVP_STAT8_STA_MOV_FRM_SUM Fld(32,0,AC_FULLDW)//[31:0]
#define NR3D_MCVP_STAT9 (IO_TNR_BASE + 0x450)
    #define NR3D_MCVP_STAT9_STA_MOV_FRM_SUM_FIX Fld(32,0,AC_FULLDW)//[31:0]
#define NR3D_HFR (IO_TNR_BASE + 0x454)
    #define NR3D_HFR_HFR_DENOMINATOR Fld(4,8,AC_MSKB1)//[11:8]
    #define NR3D_HFR_HFR_NUMERATOR Fld(4,4,AC_MSKB0)//[7:4]
    #define NR3D_HFR_HFR_BIT10 Fld(1,2,AC_MSKB0)//[2:2]
    #define NR3D_HFR_HFR_SWITCH Fld(1,1,AC_MSKB0)//[1:1]
    #define NR3D_HFR_HFR_EN Fld(1,0,AC_MSKB0)//[0:0]


#endif
