/*----------------------------------------------------------------------------*
 * No Warranty                                                                *
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 * acknowledge that Company may, either presently and/or in the future,       *
 * instruct MTK to assist it in the development and the implementation, in    *
 * accordance with Company's designs, of certain softwares relating to        *
 * Company's product(s) (the "Services").  Except as may be otherwise agreed  *
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 * given by MTK with respect to the Services provided, and the Services are   *
 * provided on an "AS IS" basis.  Company further acknowledges that the       *
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 * shall prevail in the event of a conflict in the terms in any agreements    *
 * entered into between the parties.                                          *
 *---------------------------------------------------------------------------*/
/******************************************************************************
* [File]			msdc_host_hw.h
* [Version]			v1.0
* [Revision Date]	2011-05-04
* [Author]			Shunli Wang, shunli.wang@mediatek.inc, 82896, 2011-05-04
* [Description]
*	MSDC Driver Header File
* [Copyright]
*	Copyright (C) 2011 MediaTek Incorporation. All Rights Reserved.
******************************************************************************/

#ifndef _MSDC_HOST_HW_H_
#define _MSDC_HOST_HW_H_

#include "x_hal_5381.h"

extern  int ch;
/* support CommandQueue, MSDC AES, MultiHost*/
#if defined(CC_MT5893) || defined(CC_MT5895)
#define MSDC_AES_SUPPORT    1
#define MSDC_MTH_SUPPORT    0
#define MSDC_USE_FIFO_EDGE  1
#ifdef CC_UBOOT
#define MSDC_SUPPORT_CQ     0
#else
#define MSDC_SUPPORT_CQ     0//RPMB not support it
#endif
//only for test
#define MSDC_CQ_MULTI_TASK  0

#else
#define MSDC_AES_SUPPORT    0
#define MSDC_MTH_SUPPORT    0
#define MSDC_USE_FIFO_EDGE  0
#define MSDC_SUPPORT_CQ     0
#define MSDC_CQ_MULTI_TASK  0
#endif
//---------------------------------------------------------------------------
// Configurations
//---------------------------------------------------------------------------
#define MSDC_BASE_ADDR                 (unsigned int) (IO_VIRT + 0x12000)
#define MSDC_VECTOR                    (unsigned int) (28)


//---------------------------------------------------------------------------
// MSDC Register definitions
//---------------------------------------------------------------------------
#define MSDC_CH_NUM                    (unsigned int) (2)
#if defined(CC_MT5883) || defined(CC_MT5865)
	#define MSDC_CH_OFFSET             (unsigned int) (0x00000000)
#else
	#define MSDC_CH_OFFSET             (unsigned int) (0x0005B000)
#endif

#define MSDC_CFG                       (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x00)
#define MSDC_IOCON                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x04)
#define MSDC_PS                        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x08)
#define MSDC_INT                       (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x0C)
#define MSDC_INTEN                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x10)
#define MSDC_FIFOCS                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x14)
#define MSDC_TXDATA                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x18)
#define MSDC_RXDATA                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x1C)
#define SDC_CFG                        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x30)
#define SDC_CMD                        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x34)
#define SDC_ARG                        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x38)
#define SDC_STS                        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x3C)
#define SDC_RESP0                      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x40)
#define SDC_RESP1                      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x44)
#define SDC_RESP2                      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x48)
#define SDC_RESP3                      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x4C)
#define SDC_BLK_NUM                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x50)
#define SDC_VOL_CHG                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x54) /* new add for 5885/5883/5891/5886 */
#define SDC_CSTS                       (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x58)
#define SDC_CSTS_EN                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x5C)
#define SDC_DATCRC_STS                 (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x60)
#define SDC_CMD_STS                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x64) /* new add for 5885 */
#define EMMC_CFG0                      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x70)
#define EMMC_CFG1                      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x74)
#define EMMC_STS                       (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x78)
#define EMMC_IOCON                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x7C)
#define ACMD_RESP                      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x80)
#define ACMD19_TRG                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x84)
#define ACMD19_STS                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x88)
#define DMA_SA_HIGH4BIT                (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x8C) /* new add for 5885/5891/5886 */
#define DMA_SA                         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x90)
#define DMA_CA                         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x94)
#define DMA_CTRL                       (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x98)
#define DMA_CFG                        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x9C)
#define DBG_SEL                        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA0)
#define DBG_OUT                        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA4)
#define DMA_LENGTH                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA8) /* new add for 5399/5890/5882/5883/5891/5886 */
#define PATCH_BIT0                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xB0) /* new add for 5399/5890/5882/5883/5891/5886 */
#define PATCH_BIT1                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xB4) /* new add for 5399/5890/5882/5883/5891/5886 */
#define PATCH_BIT2                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xB8)
#define DAT0_TUNE_CRC                  (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xC0)
#define DAT1_TUNE_CRC                  (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xC4)
#define DAT2_TUNE_CRC                  (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xC8)
#define DAT3_TUNE_CRC                  (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xCC)
#define CMD_TUNE_CRC                   (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xD0)
#define SDIO_TUNE_WIND                 (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xD4)
#define SD30_PAD_CTL0                  (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xE0)  /* for 5399/5890/5882/5885 */
#define SD30_PAD_CTL1                  (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xE4)  /* for 5399/5890/5882/5885 */
#define SD30_PAD_CTL2                  (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xE8)  /* for 5399/5890/5882/5885 */

#if defined(CC_MT5882) || defined(CC_MT5883) || defined(CC_MT5890) || \
	defined(CC_MT5891) || defined(CC_MT5886) || defined(CC_MT5863) || \
	defined(CC_MT5893) || defined(CC_MT5865) || defined(CC_MT5895)

	#if defined(CC_MT5882)
	#define PAD_TUNE		           ((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xEC) :(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF0))
	#define DAT_RD_DLY0		           ((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF0) :(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF8))
	#define DAT_RD_DLY1		           ((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF4) :(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xFC))
	#define HW_DBG			           ((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF8) :(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x110))
	#define VERSION			           ((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x100):(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x114))
	#define ECO_VER			           ((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x104):(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x118))
	#else
	#define PAD_TUNE                   (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF0)
	#define DAT_RD_DLY0                (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF8)
	#define DAT_RD_DLY1                (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xFC)
	#define HW_DBG                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x110)  /* mt5891 use this */
	#define MSDC_VERSION                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x114)  /* MAIN_VERSION */
	#define ECO_VER                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x118)
	#endif
#else
	#define GPIO_DBG_OUT               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xEB)  /* mt5883 don't use */
	#define PAD_TUNE                   (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xEC)
	#define DAT_RD_DLY0                (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF0)
	#define DAT_RD_DLY1                (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF4)
	#define HW_DBG                     (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF8)
	#define VERSION                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xFC)
	#define ECO_VER                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x104)
#endif

#define PAD_TUNE1                      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF4)
#define DAT_RD_DLY2                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x100)
#define DAT_RD_DLY3                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x104)

/* new register for MT5891 */
#define EMMC50_PAD_CTL0                (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x180)
#define EMMC50_PAD_DS_CTL0             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x184)
#define EMMC50_PAD_DS_TUNE             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x188)
#define EMMC50_PAD_CMD_TUNE            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x18C)
#define EMMC50_PAD_DAT01_TUNE          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x190)
#define EMMC50_PAD_DAT23_TUNE          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x194)
#define EMMC50_PAD_DAT45_TUNE          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x198)
#define EMMC50_PAD_DAT67_TUNE          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x19C)
#define EMMC50_SD                      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x200)
#define EMMC50_CFG0                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x208)
#define EMMC50_CFG1                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x20C)

/*AXI related, husky added*/
#define EMMC50_CFG2                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x21C)
#define EMMC50_CFG3                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x220)
#define EMMC50_CFG4                    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x224)
#if defined(CC_MT5886) || defined(CC_MT5863) ||\
	defined(CC_MT5893) || defined(CC_MT5865) || defined(CC_MT5895)
#define SDC_FIFO_CFG				   (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x228)
#else
#define EMMC50_BLOCK_LENGTH            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x228)
#endif

/*NEW Add from Husky mt5893,mainly for msdc1*/
/*Command Queue--CQ*/
#define EMMC51_MTKCQ_CFG0               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x234)
#define EMMC51_MTKCQ_CFG1               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x238)
#define EMMC51_MTKCQ_CFG2               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x23C)
#define EMMC51_MTKCQ_ERR_ST             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x240)
#define EMMC51_MTKCQ_CMD45_READY        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x244)
#define EMMC51_MTKCQ_TASK_READY_ST      (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x248)
#define EMMC51_MTKCQ_TASK_DONE_ST       (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x24C)
#define EMMC51_MTKCQ_ERR_ST_CLR         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x250)
#define EMMC51_MTKCQ_CMD_DONE_CLR       (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x254)
#define EMMC51_MTKCQ_SW_CTL_CQ          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x258)
#define EMMC51_MTKCQ_CMD44_RESP         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x25C)
#define EMMC51_MTKCQ_CMD45_RESP         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x260)
#define EMMC51_MTKCQ_CMD13_RCA          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x264)
#define EMMC51_CQCB_CFG3      			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x500)
#define EMMC51_CQCB_CMD44      			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x504)
#define EMMC51_CQCB_CMD45      			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x508)
#define EMMC51_CQCB_TIDMAP     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x50C)
#define EMMC51_CQCB_TIDMAPCLR     		(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x510)
#define EMMC51_CQCB_CURCMD     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x514)

/*AES*/
#define MSDC_AES_SEL          				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x280)
#define EMMC52_AES_EN     					(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x600)

#define EMMC52_AES_CFG_GP0   				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x604)
#define EMMC52_AES_IV0_GP0     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x610)
#define EMMC52_AES_IV1_GP0     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x614)
#define EMMC52_AES_IV2_GP0     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x618)
#define EMMC52_AES_IV3_GP0     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x61C)
#define EMMC52_AES_CTR0_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x620)
#define EMMC52_AES_CTR1_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x624)
#define EMMC52_AES_CTR2_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x628)
#define EMMC52_AES_CTR3_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x62C)
#define EMMC52_AES_KEY0_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x630)
#define EMMC52_AES_KEY1_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x634)
#define EMMC52_AES_KEY2_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x638)
#define EMMC52_AES_KEY3_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x63C)
#define EMMC52_AES_KEY4_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x640)
#define EMMC52_AES_KEY5_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x644)
#define EMMC52_AES_KEY6_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x648)
#define EMMC52_AES_KEY7_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x64C)
#define EMMC52_AES_TKEY0_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x650)
#define EMMC52_AES_TKEY1_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x654)
#define EMMC52_AES_TKEY2_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x658)
#define EMMC52_AES_TKEY3_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x65C)
#define EMMC52_AES_TKEY4_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x660)
#define EMMC52_AES_TKEY5_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x664)
#define EMMC52_AES_TKEY6_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x668)
#define EMMC52_AES_TKEY7_GP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x66C)
#define EMMC52_AES_SWST     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x670)
#define EMMC52_AES_IV0_GP1     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x680)
#define EMMC52_AES_IV1_GP1     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x684)
#define EMMC52_AES_IV2_GP1     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x688)
#define EMMC52_AES_IV3_GP1     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x68C)
#define EMMC52_AES_CTR0_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x690)
#define EMMC52_AES_CTR1_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x694)
#define EMMC52_AES_CTR2_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x698)
#define EMMC52_AES_CTR3_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x69C)
#define EMMC52_AES_KEY0_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6A0)
#define EMMC52_AES_KEY1_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6A4)
#define EMMC52_AES_KEY2_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6A8)
#define EMMC52_AES_KEY3_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6AC)
#define EMMC52_AES_KEY4_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6B0)
#define EMMC52_AES_KEY5_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6B4)
#define EMMC52_AES_KEY6_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6B8)
#define EMMC52_AES_KEY7_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6BC)
#define EMMC52_AES_TKEY0_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6C0)
#define EMMC52_AES_TKEY1_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6C4)
#define EMMC52_AES_TKEY2_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6C8)
#define EMMC52_AES_TKEY3_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6CC)
#define EMMC52_AES_TKEY4_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6D0)
#define EMMC52_AES_TKEY5_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6D4)
#define EMMC52_AES_TKEY6_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6D8)
#define EMMC52_AES_TKEY7_GP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x6DC)

/*MUlti-Host*/
#define EMMC52_MTH_CFG     				(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA00)
#define EMMC52_MTH_ST     			    (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA04)
#define EMMC52_MTH_PARMAP0     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA08)
#define EMMC52_MTH_PARMAP1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA0C)
#define EMMC52_MTH_PARMAP2     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA10)
#define EMMC52_MTH_PARMAP3     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA14)
#define EMMC52_MTH_TK_CTRL0     		(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA18)
#define EMMC52_MTH_TK_CTRL1     		(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA1C)
#define EMMC52_MTH_TK_CTRL2     		(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA20)
#define EMMC52_MTH_TK_CTRL3     		(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA24)
#define EMMC52_MTH_IT_SET1     			(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA28)
/* -----------------------------------------------------------------------------------------
 * Register bit define
 * ----------------------------------------------------------------------------------------*/

/* MSDC_CFG */
#if defined(CC_MT5891) || defined(CC_MT5886) ||\
	defined(CC_MT5863) || defined(CC_MT5893) ||\
    defined(CC_MT5865) || defined(CC_MT5895)
	#define MSDC_CFG_CK_MODE_SHFIT 	   (20)
#elif defined(CC_MT5882)
	#define MSDC_CFG_CK_MODE_SHFIT     ((IS_IC_5882())? (16) : (20))
#else
	#define MSDC_CFG_CK_MODE_SHFIT	   (16)
#endif
#define MSDC_CFG_SD                    ((0x01U) << 0)
#define MSDC_CFG_CK_EN                 ((0x01U) << 1)
#define MSDC_CFG_RST                   ((0x01U) << 2)
#define MSDC_CFG_PIO_MODE              ((0x01U) << 3)
#define MSDC_CFG_BUS_VOL_START         ((0x01U) << 5)
#define MSDC_CFG_BUS_VOL_PASS          ((0x01U) << 6)
#define MSDC_CFG_CARD_CK_STABLE        ((0x01U) << 7)
#define MSDC_CFG_CK_DIV_SHIFT          (8)
#define MSDC_CFG_CK_MODE_DIVIDER       ((0x00U) << MSDC_CFG_CK_MODE_SHFIT)
#define MSDC_CFG_CK_MODE_DIRECT        ((0x01U) << MSDC_CFG_CK_MODE_SHFIT)
#define MSDC_CFG_CK_MODE_DDR           ((0x02U) << MSDC_CFG_CK_MODE_SHFIT)
#define MSDC_CFG_CK_MODE_HS400         ((0x03U) << MSDC_CFG_CK_MODE_SHFIT)
#define MSDC_CFG_HS400_CK_MODE_SHIFT   (22)
#define MSDC_CFG_HS400_CK_MODE         ((0x01U) << MSDC_CFG_HS400_CK_MODE_SHIFT) /*emmc only */
#define MSDC_CFG_START_BIT_SHIFT       (23)
#define MSDC_CFG_START_BIT             ((0x03U) << MSDC_CFG_START_BIT_SHIFT) /* emmc only */
#define MSDC_CFG_SCLK_STOP_SEL_SHIFT   (25)
#define MSDC_CFG_SCLK_STOP_SEL         ((0x01U) << MSDC_CFG_SCLK_STOP_SEL_SHIFT)
#define MSDC_CFG_BW_SEL			       ((0x01U) << 29)

/* MSDC_IOCON */
#define MSDC_IOCON_R_SMPL_SHIFT        (1)
#define MSDC_IOCON_R_SMPL              ((0x01U) << MSDC_IOCON_R_SMPL_SHIFT)
#define MSDC_IOCON_D_SMPL_SHIFT        (2)
#define MSDC_IOCON_D_SMPL              ((0x01U) << MSDC_IOCON_D_SMPL_SHIFT)
#define MSDC_IOCON_D_DLYLINE_SEL_SHIFT (3)
#define MSDC_IOCON_D_DLYLINE_SEL       ((0x01U) << MSDC_IOCON_D_DLYLINE_SEL_SHIFT)
#define MSDC_IOCON_R_D_SMPL_SEL_SHIFT  (5)
#define MSDC_IOCON_R_D_SMPL_SEL        ((0x01U) << MSDC_IOCON_R_D_SMPL_SEL_SHIFT)
#define MSDC_IOCON_W_D_SMPL_SHIFT      (8)
#define MSDC_IOCON_W_D_SMPL_SEL        ((0x01U) << MSDC_IOCON_W_D_SMPL_SHIFT)
#define MSDC_IOCON_W_D_SMPL_SEL_SHIFT  (9)
#define MSDC_IOCON_W_D_SMPL_SEL_SEL    ((0x01U) << MSDC_IOCON_W_D_SMPL_SEL_SHIFT)
#define MSDC_IOCON_W_D0SPL_SHIFT       (10)
#define MSDC_IOCON_W_D0SPL             ((0x01U) << MSDC_IOCON_W_D0SPL_SHIFT)
#define MSDC_IOCON_R_D0_SMPL_SHIFT     (16)
#define MSDC_IOCON_R_D0_SMPL           ((0x01U) << MSDC_IOCON_R_D0_SMPL_SHIFT)
#define MSDC_IOCON_DAT_RD_DLY0_SHIFT   (24)
#define MSDC_IOCON_DAT_RD_DLY0		   ((0x1FU) << MSDC_IOCON_DAT_RD_DLY0_SHIFT)
#define MSDC_IOCON_RISC_SIZE_MASK      ((0x03U) << MSDC_IOCON_DAT_RD_DLY0_SHIFT)
#define MSDC_IOCON_RISC_SIZE_BYTE      ((0x00U) << MSDC_IOCON_DAT_RD_DLY0_SHIFT)
#define MSDC_IOCON_RISC_SIZE_WORD      ((0x01U) << MSDC_IOCON_DAT_RD_DLY0_SHIFT)
#define MSDC_IOCON_RISC_SIZE_DWRD      ((0x02U) << MSDC_IOCON_DAT_RD_DLY0_SHIFT)

/* MSDC_PS mask*/
#define MSDC_PS_DAT0				   ((0x01U)  << 16)	/* R  */

/* MSDC_INT */
#define INT_MMC_IRQ                    ((0x01U) << 0)
#define INT_MSDC_CDSC                  ((0x01U) << 1)
#define INT_SD_AUTOCMD_RDY             ((0x01U) << 3)
#define INT_SD_AUTOCMD_TO              ((0x01U) << 4)
#define INT_SD_AUTOCMD_RESP_CRCERR     ((0x01U) << 5)
#define INT_DMA_Q_EMPTY                ((0x01U) << 6)
#define INT_SD_SDIOIRQ                 ((0x01U) << 7)
#define INT_SD_CMDRDY                  ((0x01U) << 8)
#define INT_SD_CMDTO                   ((0x01U) << 9)
#define INT_SD_RESP_CRCERR             ((0x01U) << 10)
#define INT_SD_CSTA                    ((0x01U) << 11)
#define INT_SD_XFER_COMPLETE           ((0x01U) << 12)
#define INT_DMA_XFER_DONE              ((0x01U) << 13)
#define INT_SD_DATTO                   ((0x01U) << 14)
#define INT_SD_DATA_CRCERR             ((0x01U) << 15)
#define INT_AUTOCMD19_DONE             ((0x01U) << 16)
#define INT_BD_CS_ERR                  ((0x01U) << 17)
#define INT_GPD_CS_CRCERR              ((0x01U) << 18)
#define INT_DMA_PROTECT                ((0x01U) << 19)
#define INT_GEAR_OUT_BOUND             ((0x01U) << 20)  /* new add from mt5891 sd only */
#define INT_AUTOCMD53_DONE             ((0x01U) << 21)  /* new add from mt5891 sd only */
#define INT_AUTOCMD53_FAIL             ((0x01U) << 22)  /* new add from mt5891 sd only */
#define INT_AXI_RESP_ERR               ((0x01U) << 23)  /* new add from mt5891 sd only */
#define INT_MS_RDY                     ((0x01U) << 24)
#define INT_MS_SIF                     ((0x01U) << 25)
#define INT_MS_TOER                    ((0x01U) << 26)
#define INT_MS_CRCERR                  ((0x01U) << 27)
#define INT_MS_CED                     ((0x01U) << 28)
#define INT_MS_ERR                     ((0x01U) << 29)
#define INT_MS_BREQ                    ((0x01U) << 30)
#define INT_CMDNK                      ((0x01U) << 31)
#define INT_MTH_TK_GET0                ((0x01U) << 24)
#define INT_MTH_TK_GET1                ((0x01U) << 25)
#define INT_MTH_TK_GET2                ((0x01U) << 26)
#define INT_MTH_TK_GET3                ((0x01U) << 27)

/* SDC_CFG */
#define SDC_CFG_BW_SHIFT               (16)
#define SDC_CFG_BW_MASK                ((0x03U) << 16)
#define SDC_CFG_SDIO                   ((0x01U) << 19)
#define SDC_CFG_INTAT_BLK_GAP          ((0x01U) << 21)
#define SDC_CFG_DTOC_SHIFT             (24)

/* SDC_STS */
#define SDC_STS_SDCBUSY                ((0x01U) << 0)
#define SDC_STS_CMDBUSY                ((0x01U) << 1)
#define SDC_CMD_WR_BUSY                ((0x01U) << 16)  /* new add from mt5891/mt5882 */

/* SDC_CMD */
#define SDC_CMD_BREAK                  ((0x01U) << 6)
#define SDC_CMD_ACMD53_EN              ((0x01U) << 31)  /* sd only */

/* SDC_DCRC_STS mask */
#define SDC_DCRC_STS_NEG               ((0xffU) << 8)  /* RO */
#define SDC_DCRC_STS_POS               ((0xffU) << 0)  /* RO */

/*SDC_CMD_STS*/
/*new add from mt5882*/
#define SDC_CMD_STS_RSP_CRC			   ((0x7FU) << 0)  /* RU */
#define SDC_CMD_STS_RSP_INDEX		   ((0x3FU) << 7)  /* RU */
#define SDC_CMD_STS_RSP_ENDBIT		   ((0x1U) << 13)  /* RU */
#define SDC_CMD_STS_INDEX_CHECK		   ((0x1U) << 14)  /* RW */
#define SDC_CMD_STS_ENDBIT_CHECK	   ((0x1U) << 15)  /* RW */
#define SDC_CMD_STS_RX_ENHANCE_EN 	   ((0x1U) << 20)  /* RW */

/* MSDC_FIFOCS */
#define MSDC_FIFOCS_FIFOCLR            ((0x1U) << 31)
#define MSDC_FIFO_LEN                  (128)
#define MSDC_FIFOCS_TXFIFOCNT_SHIFT    (16)
#define MSDC_FIFOCS_TXFIFOCNT_MASK     (0x00FF0000)
#define MSDC_FIFOCS_RXFIFOCNT_SHIFT    (0)
#define MSDC_FIFOCS_RXFIFOCNT_MASK     (0x000000FF)

/* SDC_DATCRC_STS */
#define SDC_DATCRC_STS_POS             ((0xFFU) << 0)
#define SDC_DATCRC_STS_NEG             ((0x0FU) << 8)

/* DMA_CTRL */
#define DMA_CTRL_BST_SHIFT             (12)
#define DMA_CTRL_XFER_SIZE_SHIFT       (16)
#define DMA_CTRL_BST_8                 ((0x3U) << DMA_CTRL_BST_SHIFT)
#define DMA_CTRL_BST_16                ((0x4U) << DMA_CTRL_BST_SHIFT)
#define DMA_CTRL_BST_32                ((0x5U) << DMA_CTRL_BST_SHIFT)
#define DMA_CTRL_BST_64                ((0x6U) << DMA_CTRL_BST_SHIFT)
#define DMA_CTRL_START                 ((0x01U) << 0)
#define DMA_CTRL_STOP                  ((0x01U) << 1)
#define DMA_CTRL_RESUME                ((0x01U) << 2)
#define DMA_CTRL_AHB_READYM            ((0x01U) << 3)
#define DMA_CTRL_DESC_MODE             ((0x01U) << 8)
#define DMA_CTRL_ALIGN                 ((0x01U) << 9)
#define DMA_CTRL_LAST_BUF              ((0x01U) << 10)
#define DMA_CTRL_SPLIT_1K              ((0x01U) << 11)

/* DMA_CFG */
#define DMA_CFG_DMA_STATUS             ((0x01U) << 0)
#define DMA_CFG_CHKSUM                 ((0x01U) << 1)
#define DMA_CFG_LOCK_DISABLE           ((0x01U) << 2)  /* emmc only */
#define DMA_CFG_BD_CS_ERR              ((0x01U) << 4)
#define DMA_CFG_GPD_CS_ERR             ((0x01U) << 5)
#define DMA_CFG_OUTBOUND_STOP_DMA      ((0x01U) << 17)  /* sd only */

/* PAD_TUNE0 */
#define PAD_DAT_WR_RXDLY_SHIFT         (0)
#define PAD_DAT_WR_RXDLY               ((0x1FU) << PAD_DAT_WR_RXDLY_SHIFT)
#define DELAY_EN_SHIFT				   (7)
#define DELAY_EN					   ((0x1U) << DELAY_EN_SHIFT)
#define PAD_DAT_RD_RXDLY_SHIFT         (8)
#define PAD_DAT_RD_RXDLY               ((0x1FU) << PAD_DAT_RD_RXDLY_SHIFT)
#define PAD_DAT_RD_RXDLY_SEL_SHIFT	   (13)
#define PAD_DAT_RD_RXDLY_SEL		   ((0x1U) << PAD_DAT_RD_RXDLY_SEL_SHIFT)
#define PAD_RXDLY_SEL_SHIFT			   (15)
#define PAD_RXDLY_SEL				   ((0x1U) << PAD_RXDLY_SEL_SHIFT)
#define PAD_CMD_RXDLY_SHIFT            (16)
#define PAD_CMD_RXDLY                  ((0x1FU) << PAD_CMD_RXDLY_SHIFT)
#define PAD_CMD_RD_RX_DLY_SEL_SHIFT    (21)
#define PAD_CMD_RD_RX_DLY_SEL          ((0x1U) << PAD_CMD_RD_RX_DLY_SEL_SHIFT)
#define PAD_CMD_RESP_RXDLY_SHIFT       (22)
#define PAD_CMD_RESP_RXDLY             ((0x1FU) << PAD_CMD_RESP_RXDLY_SHIFT)
#define PAD_DAT_RDDLY0_D0_SHIFT        (24)
#define PAD_DAT_RDDLY0_D0              ((0x1FU) << MSDC_DAT_RDDLY0_D0_SHIFT)
#define PAD_CLK_TXDLY_SHIFT        	   (27)
#define PAD_CLK_TXDLY              	   ((0x1FU) << PAD_CLK_TXDLY_SHIFT)

/* PAD_TUNE1 */
#define PAD_TUNE1_DAT_RD_RXDLY2_SHIFT  (8)
#define PAD_TUNE1_DATRRDLY2            (0x1F <<  8)     /* RW */
#define PAD_TUNE1_DAT_RD_RXDLY2		   ((0x1FU) << MSDC_PAD_TUNE1_DAT_RD_RXDLY2_SHIFT)
#define PAD_TUNE1_DAT_RD_RXDLY2_SEL_SHIFT  (13)
#define PAD_TUNE1_DATRRDLY2SEL         (0x1  << 13)     /* RW */
#define PAD_TUNE1_DAT_RD_RXDLY2_SEL	   ((0x1U) << MSDC_PAD_TUNE1_DAT_RD_RXDLY2_SEL_SHIFT)
#define PAD_TUNE1_CMD_RXDLY2_SHIFT	   (16)
#define PAD_TUNE1_CMDRDLY2             (0x1F << 16)     /* RW */
#define PAD_TUNE1_CMD_RXDLY2		   ((0x1FU) << MSDC_PAD_TUNE1_CMD_RXDLY2_SHIFT)
#define PAD_TUNE1_CMD_RD_RX_DLY2_SHIFT (21)
#define PAD_TUNE1_CMDRRDLY2SEL         (0x1  << 21)     /* RW */
#define PAD_TUNE1_CMD_RD_RX_DLY2_SE	   ((0x1U) << MSDC_PAD_TUNE1_CMD_RD_RX_DLY2_SHIFT)

/* EMMC50_PAD_DS_TUNE mask */
#define MSDC_EMMC50_PAD_DS_TUNE_DLYSEL (0x1 << 0)
#define MSDC_EMMC50_PAD_DS_TUNE_DLY2SEL (0x1 << 1)
#define MSDC_EMMC50_PAD_DS_TUNE_DLY1   (0x1f << 2)
#define MSDC_EMMC50_PAD_DS_TUNE_DLY2   (0x1f << 7)
#define MSDC_EMMC50_PAD_DS_TUNE_DLY3   (0x1F << 12)

/* EMMC50_PAD_CMD_TUNE mask */
#define MSDC_EMMC50_PAD_CMD_TUNE_DLY3SEL (0x1 << 0)
#define MSDC_EMMC50_PAD_CMD_TUNE_RXDLY3  (0x1f << 1)
#define MSDC_EMMC50_PAD_CMD_TUNE_TXDLY   (0x1f << 6)

/* DAT_RD_DLY 0/1/2/3 mask */
#define MSDC_DAT_RDDLY0_D3_LINE1_SHIFT (0)
#define MSDC_DAT_RDDLY0_D3_LINE1       ((0x1FU) << MSDC_DAT_RDDLY0_D3_LINE1_SHIFT)
#define MSDC_DAT_RDDLY0_D2_LINE1_SHIFT (8)
#define MSDC_DAT_RDDLY0_D2_LINE1       ((0x1FU) << MSDC_DAT_RDDLY0_D2_LINE1_SHIFT)
#define MSDC_DAT_RDDLY0_D1_LINE1_SHIFT (16)
#define MSDC_DAT_RDDLY0_D1_LINE1       ((0x1FU) << MSDC_DAT_RDDLY0_D1_LINE1_SHIFT)
#define MSDC_DAT_RDDLY0_D0_LINE1_SHIFT (24)
#define MSDC_DAT_RDDLY0_D0_LINE1       ((0x1FU) << MSDC_DAT_RDDLY0_D0_LINE1_SHIFT)
#define MSDC_DAT_RDDLY0_D0_SHIFT       (24)
#define MSDC_DAT_RDDLY0_D0             (((unsigned int)0x1F) << MSDC_DAT_RDDLY0_D0_SHIFT)

#define MSDC_DAT_RDDLY1_D7_LINE1_SHIFT (0)
#define MSDC_DAT_RDDLY1_D7_LINE1       ((0x1FU) << MSDC_DAT_RDDLY1_D7_LINE1_SHIFT)
#define MSDC_DAT_RDDLY1_D6_LINE1_SHIFT (8)
#define MSDC_DAT_RDDLY1_D6_LINE1       ((0x1FU) << MSDC_DAT_RDDLY1_D6_LINE1_SHIFT)
#define MSDC_DAT_RDDLY1_D5_LINE1_SHIFT (16)
#define MSDC_DAT_RDDLY1_D5_LINE1       ((0x1FU) << MSDC_DAT_RDDLY1_D5_LINE1_SHIFT)
#define MSDC_DAT_RDDLY1_D4_LINE1_SHIFT (24)
#define MSDC_DAT_RDDLY1_D4_LINE1       ((0x1FU) << MSDC_DAT_RDDLY1_D4_LINE1_SHIFT)

#define MSDC_DAT_RDDLY2_D3_LINE2_SHIFT (0)
#define MSDC_DAT_RDDLY2_D3_LINE2       ((0x1FU) << MSDC_DAT_RDDLY2_D3_LINE2_SHIFT)
#define MSDC_DAT_RDDLY2_D2_LINE2_SHIFT (8)
#define MSDC_DAT_RDDLY2_D2_LINE2       ((0x1FU) << MSDC_DAT_RDDLY2_D2_LINE2_SHIFT)
#define MSDC_DAT_RDDLY2_D1_LINE2_SHIFT (16)
#define MSDC_DAT_RDDLY2_D1_LINE2       ((0x1FU) << MSDC_DAT_RDDLY2_D1_LINE2_SHIFT)
#define MSDC_DAT_RDDLY2_D0_LINE2_SHIFT (24)
#define MSDC_DAT_RDDLY2_D0_LINE2       ((0x1FU) << MSDC_DAT_RDDLY2_D0_LINE2_SHIFT)

#define MSDC_DAT_RDDLY3_D7_LINE2_SHIFT (0)
#define MSDC_DAT_RDDLY3_D7_LINE2       ((0x1FU) << MSDC_DAT_RDDLY3_D7_LINE2_SHIFT)
#define MSDC_DAT_RDDLY3_D6_LINE2_SHIFT (8)
#define MSDC_DAT_RDDLY3_D6_LINE2       ((0x1FU) << MSDC_DAT_RDDLY3_D6_LINE2_SHIFT)
#define MSDC_DAT_RDDLY3_D5_LINE2_SHIFT (16)
#define MSDC_DAT_RDDLY3_D5_LINE2       ((0x1FU) << MSDC_DAT_RDDLY3_D5_LINE2_SHIFT)
#define MSDC_DAT_RDDLY3_D4_LINE2_SHIFT (24)
#define MSDC_DAT_RDDLY3_D4_LINE2       ((0x1FU) << MSDC_DAT_RDDLY3_D4_LINE2_SHIFT)

/* EMMC50_PAD_DAT01_TUNE mask */
#define MSDC_EMMC50_PAD_DAT0_RXDLY3SEL ((0x1U) << 0)
#define MSDC_EMMC50_PAD_DAT0_RXDLY3    ((0x1FU) << 1)
#define MSDC_EMMC50_PAD_DAT0_TXDLY     ((0x1FU) << 6)
#define MSDC_EMMC50_PAD_DAT1_RXDLY3SEL ((0x1U) << 16)
#define MSDC_EMMC50_PAD_DAT1_RXDLY3    ((0x1FU) << 17)
#define MSDC_EMMC50_PAD_DAT1_TXDLY     ((0x1FU) << 22)

/* EMMC50_PAD_DAT23_TUNE mask */
#define MSDC_EMMC50_PAD_DAT2_RXDLY3SEL ((0x1U) << 0)
#define MSDC_EMMC50_PAD_DAT2_RXDLY3    ((0x1FU) << 1)
#define MSDC_EMMC50_PAD_DAT2_TXDLY     ((0x1FU) << 6)
#define MSDC_EMMC50_PAD_DAT3_RXDLY3SEL ((0x1U) << 16)
#define MSDC_EMMC50_PAD_DAT3_RXDLY3    ((0x1FU) << 17)
#define MSDC_EMMC50_PAD_DAT3_TXDLY     ((0x1FU) << 22)

/* EMMC50_PAD_DAT45_TUNE mask */
#define MSDC_EMMC50_PAD_DAT4_RXDLY3SEL ((0x1U) << 0)
#define MSDC_EMMC50_PAD_DAT4_RXDLY3    ((0x1FU) << 1)
#define MSDC_EMMC50_PAD_DAT4_TXDLY     ((0x1FU) << 6)
#define MSDC_EMMC50_PAD_DAT5_RXDLY3SEL ((0x1U) << 16)
#define MSDC_EMMC50_PAD_DAT5_RXDLY3    ((0x1FU) << 17)
#define MSDC_EMMC50_PAD_DAT5_TXDLY     ((0x1FU) << 22)

/* EMMC50_PAD_DAT67_TUNE mask */
#define MSDC_EMMC50_PAD_DAT6_RXDLY3SEL ((0x1U) << 0)
#define MSDC_EMMC50_PAD_DAT6_RXDLY3    ((0x1FU) << 1)
#define MSDC_EMMC50_PAD_DAT6_TXDLY     ((0x1FU) << 6)
#define MSDC_EMMC50_PAD_DAT7_RXDLY3SEL ((0x1U) << 16)
#define MSDC_EMMC50_PAD_DAT7_RXDLY3    ((0x1FU) << 17)
#define MSDC_EMMC50_PAD_DAT7_TXDLY     ((0x1FU) << 22)

/* THE Tuning for emmc5.0 */
#define MSDC_PB0_INT_DAT_LATCH_CK_SEL  ((0x7U) << 7)

/* EMMC_CFG0 */
#define BTSUP                          ((0x01U) << 15)
#define BTWDLY_0x32                    ((0x00U) << 12)
#define BTWDLY_1x32                    ((0x01U) << 12)
#define BTWDLY_2x32                    ((0x02U) << 12)
#define BTWDLY_7x32                    ((0x07U) << 12)
#define BTACHKDIS                      ((0x01U) << 3)
#define BTMOD_0                        ((0x00U) << 2)
#define BTMOD_1                        ((0x01U) << 2)
#define BTSTOP                         ((0x01U) << 1)
#define BTSTART                        ((0x01U) << 0)

/* EMMC_CFG1 */
#define BTATOC_SHIFT                   (20)
#define BTDTOC_SHIFT                   (0)

/* EMMC_STS */
#define BTDRCV                         ((0x01U) << 6)
#define BTARCV                         ((0x01U) << 5)
#define BTSTS                          ((0x01U) << 4)
#define BTATO                          ((0x01U) << 3)
#define BTDTO                          ((0x01U) << 2)
#define BTAERR                         ((0x01U) << 1)
#define BTDERR                         ((0x01U) << 0)

/* PATCH_BIT0 */
#define RD_RAT_SEL_SHIFT		   	   (3)
#define MSDC_BIT0_RD_RAT_SEL		   ((0x1U) <<  RD_RAT_SEL_SHIFT)
#define DESC_UP_SEL_SHIFT			   (6)
#define MSDC_BIT0_DESC_UP_SEL		   ((0x1U) <<  DESC_UP_SEL_SHIFT)
#define INT_DAT_LATCH_CK_SEL_SHIFT     (7)
#define INT_DAT_LATCH_CK_SEL           ((0x7U) << INT_DAT_LATCH_CK_SEL_SHIFT)
#define CKGEN_MSDC_DLY_SEL_SHIFT       (10)
#define CKGEN_MSDC_DLY_SEL             ((0x1FU) << CKGEN_MSDC_DLY_SEL_SHIFT)
#define SDC_CFG_WDOD_SHIFT			   (22)
#define MSDC_BIT0_SDC_CFG_WDOD		   ((0xFU) << SDC_CFG_WDOD_SHIFT)

/* PATCH_BIT1 */
#define WRDAT_CRCS_TA_CNTR_SHIFT       (0)
#define WRDAT_CRCS_TA_CNTR             ((0x7U) << WRDAT_CRCS_TA_CNTR_SHIFT)
#define CMD_RSP_TA_CNTR_SHIFT          (3)
#define CMD_RSP_TA_CNTR                ((0x7U) << CMD_RSP_TA_CNTR_SHIFT)
#define GET_BUSY_MARGIN_SHIFT          (6)
#define MSDC_PB1_GET_BUSY_MARGIN	   ((0x1U) << 6)
#define GET_CRC_MARGIN_SHIFT           (7)
#define MSDC_PB1_GET_CRC_MARGIN		   ((0x1U) << 7)
#define STOP_DLY_SEL_SHIFT             (8)
#define STOP_DLY_SEL	     	       ((0xF) << STOP_DLY_SEL_SHIFT)
#define RESET_DGMA_SHIFT               (15)
#define MSDC_BIT1_RESET_GDMA		   ((0x1U) << 15)
#define ENABLE_SINGLE_BURST_SHIFT      (16)
#define MSDC_BIT1_SINGAL_BURST		   ((0x1U) << 16)
#define FORCE_STOP_GDMA_SHIFT          (17)
#define DCM_DIV_SEL2_SHIFT             (18)
#define DCM_DIV_SEL1_SHIFT             (20)
#define DCM_EN_SHIFT                   (21)
#define MSDC_BIT1_DCM_EN			   ((0x1U) << 21)
#define AXI_WRAP_CKEN_SHIFT            (22)

/* MSDC_PATCH_BIT2 mask */
#define MSDC_BIT2_ENHANCE_WAIT_GPD	   ((0x1U) <<  0)
#define MSDC_BIT2_SUPPORT_64G		   ((0x1U) <<  1)
#define MSDC_BIT2_RESP_WAIT_CNT		   ((0x3U) <<  2)
#define MSDC_BIT2_CFG_RDAT_CNT		   ((0xFU) <<  4)
#define MSDC_BIT2_CFG_RDAT			   ((0x1U) <<  9)
#define MSDC_BIT2_INTC_RESP_SEL		   ((0x1U) << 11)
#define MSDC_BIT2_CFG_RESP_CNT		   ((0x7U) << 12)
#define MSDC_BIT2_CFG_RESP			   ((0x1U) << 15)
#define MSDC_BIT2_RESP_LATCH_ENSEL	   ((0x7U) << 16)
#define MSDC_BIT2_DDR5O_SEL			   ((0x1U) << 19)
#define MSDC_BIT2_POP_EN_CNT		   ((0xFU) << 20)
#define MSDC_BIT2_CFG_CRCSTS_SEL	   ((0x1U) << 24)
#define MSDC_BIT2_CFG_CRCSTS_EDGE	   ((0x1U) << 25)
#define MSDC_BIT2_CFG_CRCSTS_CNT	   ((0x3U) << 26)
#define MSDC_BIT2_CFG_CRCSTS		   ((0x1U) << 28)
#define MSDC_BIT2_CRCSTS_LATCH_SEL	   ((0x7U) << 29)

#define SDC_CFG_WDOD_SHIFT             (22)
#define SDC_CFG_WDOD                   ((0xFU) << SDC_CFG_WDOD_SHIFT)

#define DESC_UP_SEL_SHIFT              (6)
#define DESC_UP_SEL                    ((0x1U) << DESC_UP_SEL_SHIFT)

/* SD ONLY */
#define RD_DAT_SEL_SHIFT               (3)
#define RD_DAT_SEL                     ((0x1U) << RD_DAT_SEL_SHIFT)

#define MASK_ACMD53_CRC_ERR_INTR_SHIFT (4)
#define MASK_ACMD53_CRC_ERR_INTR       ((0x1U) << MASK_ACMD53_CRC_ERR_INTR_SHIFT)

#define ACMD53_FAIL_ONE_SHOT_SHIFT     (5)
#define ACMD53_FAIL_ONE_SHOT           ((0x1U) << ACMD53_FAIL_ONE_SHOT_SHIFT)


/* PATCH_BIT2 */
#define ENHANCE_WAIT_GPD_SHIFT         (0)
#define SUPPORT_64G_SHIFT              (1)
#define RESP_WAIT_CNT_SHIFT            (2)
#define RESP_WAIT_CNT                  ((0x3U) << RESP_WAIT_CNT_SHIFT)
#define CFG_RDAT_CNT_SHIFT             (4)
#define CFG_RDAT_SHIFT                 (9)
#define CFG_RDAT                       ((0x1U) << CFG_RDAT_SHIFT)
#define INTC_RESP_SEL_SHIFT            (11)
#define CFG_RESP_CNT_SHIFT             (12)
#define CFG_RESP_SHIFT                 (15)
#define CFG_RESP                       ((0x1U) << CFG_RESP_SHIFT)
#define RESP_LATCH_CN_SEL_SHIFT        (16)
#define POP_EN_CNT_SHIFT               (20)
#define POP_EN_CNT_SHIFT               ((0xf) << POP_EN_CNT_SHIFT)
#define CFG_CRCSTS_SEL_SHIFT           (24)
#define CFG_CRCSTS_EDGE_SHIFT          (25)
#define CFG_CRCSTS_EDGE                ((0x1U) << CFG_CRCSTS_EDGE_SHIFT)
#define CFG_CRCSTC_CNT_SHIFT           (26)
#define CFG_CRCSTS_SHIFT               (28)
#define CFG_CRCSTS                     ((0x1U) << CFG_CRCSTS_SHIFT)
#define CRCSTS_LATCH_EN_SEL_SHIFT      (29)
#define CRCSTS_LATCH_EN_SEL            ((0x7U) << CRCSTS_LATCH_EN_SEL_SHIFT)

/* EMMC50_SD */
#define SD_DMA_ENABLE                  (1)

/*EMMC50_CFG0*/
#define CRC_STS_EDGE_SHIFT             (3)
#define CRC_STS_EDGE                   ((0x1U) << CRC_STS_EDGE_SHIFT)
#define CRC_STS_SEL_SHIFT              (4)
#define CRC_STS_SEL                    ((0x1U) << CRC_STS_SEL_SHIFT)
#define CFG_CMD_RESP_SEL               (0x1U << 9)
#define PAD_DAT_RX_DLY3_MUX_SEL_SHIFT  (16)
#define PAD_DAT_RX_DLY3_MUX_SEL        ((0x1U) << PAD_DAT_RX_DLY3_MUX_SEL_SHIFT)
#define PAD_DAT_RX_DLY3_SHIFT          (17)
#define PAD_DAT_RX_DLY3                ((0x1FU) << PAD_DAT_RX_DLY3_SHIFT)

/*EMMC50_CFG1*/
#define LATCH_CK_SWITCH_CNT_SHIFT        (8)
#define LATCH_CK_SWITCH_CNT              ((0x7U) << LATCH_CK_SWITCH_CNT_SHIFT)


#define RD_DAT_STOP_SHIFT             	 (11)
#define RD_DAT_STOP                   	 ((0x1U) << RD_DAT_STOP_SHIFT)

#define WAIT_8_CLK_CNT_SHIFT             (12)
#define WAIT_8_CLK_CNT                   ((0xFU) << WAIT_8_CLK_CNT_SHIFT)

#define EMMC50_DEBUG_SEL_SHIFT           (16)
#define EMMC50_DEBUG_SEL                 ((0xFFU) << EMMC50_DEBUG_SEL_SHIFT)

#define PSH_CNT_SHIFT             		 (24)
#define PSH_CNT                   		 ((0x7U) << PSH_CNT_SHIFT)
#define PSH_PS_SEL_SHIFT             	 (27)
#define PSH_PS_SEL                		 ((0x1U) << PSH_PS_SEL_SHIFT)
#define DS_CFG_SHIFT             		 (28)
#define DS_CFG                			 ((0x1U) << DS_CFG_SHIFT)

/*EMMC50_CFG2*/
#define AXI_IOMMU_WR_EMI_SHIFT            (1)
#define AXI_IOMMU_WR_EMI                  ((0x1U) << AXI_IOMMU_WR_EMI_SHIFT)
#define AXI_SHARE_EN_WR_EMI_SHIFT         (2)
#define AXI_SHARE_EN_WR_EMI               ((0x1U) << AXI_SHARE_EN_WR_EMI_SHIFT)

#define AXI_IOMMU_RD_EM_SHIFT  			  (7)
#define AXI_IOMMU_RD_EM        			  ((0x1U) << AXI_IOMMU_RD_EM_SHIFT)

#define AXI_SHARE_EN_RD_EMI_SHIFT         (8)
#define AXI_SHARE_EN_RD_EMI               ((0x1U) << AXI_SHARE_EN_RD_EMI_SHIFT)

#define AXI_BOUND_128B_SHIFT          	  (13)
#define AXI_BOUND_128B                	  ((0x1U) << AXI_BOUND_128B_SHIFT)
#define AXI_BOUND_256B_SHIFT          	  (14)
#define AXI_BOUND_256B                	  ((0x1U) << AXI_BOUND_256B_SHIFT)
#define AXI_BOUND_512B_SHIFT          	  (15)
#define AXI_BOUND_512B                	  ((0x1U) << AXI_BOUND_512B_SHIFT)

#define AXI_BOUND_1K_SHIFT          	  (16)
#define AXI_BOUND_1K                	  ((0x1U) << AXI_BOUND_1K_SHIFT)
#define AXI_BOUND_2K_SHIFT          	  (17)
#define AXI_BOUND_2K                	  ((0x1U) << AXI_BOUND_2K_SHIFT)
#define AXI_BOUND_4K_SHIFT          	  (18)
#define AXI_BOUND_4K                	  ((0x1U) << AXI_BOUND_4K_SHIFT)


#define AXI_RD_OUTSTANDING_NUM_SHIFT    (19)
#define AXI_RD_OUTSTANDING_NUM          ((0x1FU) << AXI_RD_OUTSTANDING_NUM_SHIFT)

#define AXI_SET_LEN_SHIFT          		(24)
#define AXI_SET_LEN                		((0xFU) << AXI_SET_LEN_SHIFT)

#define AXI_RESP_ERR_TYPE_SHIFT         (28)
#define AXI_RESP_ERR_TYPE               ((0x3U) << AXI_RESP_ERR_TYPE_SHIFT)

#define AXI_BUSY_SHIFT          	    (30)
#define AXI_BUSY                		((0x1U) << AXI_BUSY_SHIFT)

/*EMMC50_CFG3*/
#define OUT_STANDING_WR_SHIFT          (0)
#define OUT_STANDING_WR                ((0x1FU) << OUT_STANDING_WR_SHIFT)
#define ULTRA_SET_WR_SHIFT             (5)
#define ULTRA_SET_WR                   ((0x3FU) << ULTRA_SET_WR_SHIFT)
#define PREULTRA_SET_WR_SHIFT          (11)
#define PREULTRA_SET_WR                ((0x3FU) << PREULTRA_SET_WR_SHIFT)
#define ULTRA_SET_RD_SHIFT             (17)
#define ULTRA_SET_RD                   ((0x3FU) << ULTRA_SET_RD_SHIFT)
#define PREULTRA_SET_RD_SHIFT          (23)
#define PREULTRA_SET_RD                ((0x3FU) << PREULTRA_SET_RD_SHIFT)

/*EMMC50_CFG4*/
#define IMPR_ULTRA_SET_WR_SHIFT         (0)
#define IMPR_ULTRA_SET_WR               ((0xFFU) << IMPR_ULTRA_SET_WR_SHIFT)
#define IMPR_ULTRA_SET_RD_SHIFT         (8)
#define IMPR_ULTRA_SET_RD               ((0xFFU) << IMPR_ULTRA_SET_RD_SHIFT)
#define ULTRA_EN_SHIFT             		(16)
#define ULTRA_EN                   		((0x3U) << ULTRA_EN_SHIFT)
#define WRAP_SEL_SHIFT             		(18)
#define WRAP_SEL                   		((0x1FU) << WRAP_SEL_SHIFT)


/*SDC_FIFO_CFG*/
#define EMMC50_BLOCK_LENGTH_SHIFT       (0)
#define EMMC50_BLOCK_LENGTH             ((0x1FFU) << EMMC50_BLOCK_LENGTH_SHIFT)
#define WR_PTR_MARGIN_SHIFT             (16)
#define WR_PTR_MARGIN                   ((0xFFU) << WR_PTR_MARGIN_SHIFT)
#define WR_VALID_SEL_SHIFT              (24)
#define WR_VALID_SEL                    ((0x1U) << WR_VALID_SEL_SHIFT)
#define RD_VALID_SEL_SHIFT              (25)
#define RD_VALID_SEL                    ((0x1U) << RD_VALID_SEL_SHIFT)
#define WR_VALID_SHIFT                  (26)
#define WR_VALID                        ((0x1U) << WR_VALID_SHIFT)

/*CQ normal param*/
#define MTKCQ_TASK_ID_SHIFT            (16)
#define MTKCQ_TASK_ID                  ((0x1FU) << MTKCQ_TASK_ID_SHIFT)


/*EMMC51_MTKCQ_CFG0*/
#define MTKCQ_ACMD13_TH_SHIFT            (0)
#define MTKCQ_ACMD13_TH                  ((0xFFFFU) << MTKCQ_ACMD13_TH_SHIFT)

/*EMMC51_MTKCQ_CFG1*/
#define MTKCQ_ACMD13_IDLE_SHIFT           (0)
#define MTKCQ_ACMD13_IDLE                 ((0xFFFFU) << MTKCQ_ACMD13_IDLE_SHIFT)

/*EMMC51_MTKCQ_CFG2*/
#define MTKCQ_EN_SHIFT             			(0)
#define MTKCQ_EN                   			((0x1U) << MTKCQ_EN_SHIFT)
#define MTKCQ_BUSY_SHIFT             		(1)
#define MTKCQ_BUSY                   		((0x1U) << MTKCQ_BUSY_SHIFT)
#define MTKCQ_CMD13_FLAG_SHIFT             	(4)
#define MTKCQ_CMD13_FLAG                   	((0x1U) << MTKCQ_CMD13_FLAG_SHIFT)
#define MTKCQ_CMD_FREE_W_EN_SHIFT           (5)
#define MTKCQ_CMD_FREE_W_EN                 ((0x1U) << MTKCQ_CMD_FREE_W_EN_SHIFT)

/*EMMC51_MTKCQ_ERR_ST*/
#define MTKCQ_CMD44_RESP_CRCERR_SHIFT       (0)
#define MTKCQ_CMD44_RESP_CRCERR             ((0x1U) << MTKCQ_CMD44_RESP_CRCERR_SHIFT)
#define MTKCQ_CMD44_RESP_TO_SHIFT           (1)
#define MTKCQ_CMD44_RESP_TO                 ((0x1U) << MTKCQ_CMD44_RESP_TO_SHIFT)
#define MTKCQ_CMD45_RESP_CRCERR_SHIFT       (4)
#define MTKCQ_CMD45_RESP_CRCERR             ((0x1U) << MTKCQ_CMD45_RESP_CRCERR_SHIFT)
#define MTKCQ_CMD45_RESP_TO_SHIFT           (5)
#define MTKCQ_CMD45_RESP_TO                 ((0x1U) << MTKCQ_CMD45_RESP_TO_SHIFT)
#define MTKCQ_CMD13_RESP_CRCERR_SHIFT       (8)
#define MTKCQ_CMD13_RESP_CRCERR             ((0x1U) << MTKCQ_CMD13_RESP_CRCERR_SHIFT)
#define MTKCQ_CMD13_RESP_TO_SHIFT       	(9)
#define MTKCQ_CMD13_RESP_TO             	((0x1U) << MTKCQ_CMD13_RESP_TO_SHIFT)


#define MTKCQ_OTHERCMD_RESP_CRCERR_SHIFT      (12)
#define MTKCQ_OTHERCMD_RESP_CRCERR            ((0x1U) << MTKCQ_OTHERCMD_RESP_CRCERR_SHIFT)
#define MTKCQ_OTHERCMD_RESP_TO_SHIFT          (13)
#define MTKCQ_OTHERCMD_RESP_TO                ((0x1U) << MTKCQ_OTHERCMD_RESP_TO_SHIFT)

#define MTKCQ_RESP_ERR_SHIFT                  (16)
#define MTKCQ_RESP_ERR                        ((0x1U) << MTKCQ_RESP_ERR_SHIFT)
#define MTKCQ_R1_RESP_ERR_SHIFT                (17)
#define MTKCQ_R1_RESP_ERR                      ((0x1U) << MTKCQ_R1_RESP_ERR_SHIFT)
#define MTKCQ_EMMC52_R1_RESP_ERR_SHIFT         (18)
#define MTKCQ_EMMC52_R1_RESP_ERR               ((0x1U) << MTKCQ_EMMC52_R1_RESP_ERR_SHIFT)


/*EMMC51_MTKCQ_CMD45_READY*/
#define MTKCQ_CMD45_READY_ST_SHIFT          (0)
#define MTKCQ_CMD45_READY_ST                ((0xFFFFFFFFU) << MTKCQ_CMD45_READY_ST_SHIFT)

/*EMMC51_MTKCQ_TASK_READY_ST*/
#define MTKCQ_TASK_READY_ST_SHIFT           (0)
#define MTKCQ_TASK_READY_ST                 ((0xFFFFFFFFU) << MTKCQ_TASK_READY_ST_SHIFT)

/*EMMC51_MTKCQ_TASK_DONE_ST*/
#define MTKCQ_CMD13_UPDATE_ST_SHIFT          (0)
#define MTKCQ_CMD13_UPDATE_ST                ((0x1U) << MTKCQ_CMD13_UPDATE_ST_SHIFT)
#define MTKCQ_CMD45_DONE_ST_SHIFT            (1)
#define MTKCQ_CMD45_DONE_ST                  ((0x1U) << MTKCQ_CMD45_DONE_ST_SHIFT)
#define MTKCQ_OTHERCMD_DONE_ST_SHIFT         (2)
#define MTKCQ_OTHERCMD_DONE_ST               ((0x1U) << MTKCQ_OTHERCMD_DONE_ST_SHIFT)
#define MTKCQ_CMD_DONE_ST_SHIFT              (3)
#define MTKCQ_CMD_DONE_ST                    ((0x1U) << MTKCQ_CMD_DONE_ST_SHIFT)
#define MTKCQ_CMD13_DONE_ST_SHIFT            (4)
#define MTKCQ_CMD13_DONE_ST                  ((0x1U) << MTKCQ_CMD13_DONE_ST_SHIFT)
#define MTKCQ_SWCMD_MISS_SHIFT             	 (5)
#define MTKCQ_SWCMD_MISS                     ((0x1U) << MTKCQ_SWCMD_MISS_SHIFT)
#define MTKCQ_CMD45_DONE_ST_MASK_SHIFT       (6)
#define MTKCQ_CMD45_DONE_ST_MASK             ((0x1U) << MTKCQ_CMD45_DONE_ST_MASK_SHIFT)
#define MTKCQ_CEMMC52_R1_RESP_ERR_SHIFT      (7)
#define MTKCQ_CEMMC52_R1_RESP_ERR            ((0x1U) << MTKCQ_CEMMC52_R1_RESP_ERR_SHIFT)

/*EMMC51_MTKCQ_ERR_ST_CLR*/
#define MTKCQ_CMD44_RESP_CRCERR_CLR_SHIFT    (0)
#define MTKCQ_CMD44_RESP_CRCERR_CLR          ((0x1U) << MTKCQ_CMD44_RESP_CRCERR_CLR_SHIFT)
#define MTKCQ_CMD44_RESP_TO_CLR_SHIFT        (1)
#define MTKCQ_CMD44_RESP_TO_CLR              ((0x1U) << MTKCQ_CMD44_RESP_TO_CLR_SHIFT)
#define MTKCQ_CMD45_RESP_CRCERR_CLR_SHIFT    (4)
#define MTKCQ_CMD45_RESP_CRCERR_CLR          ((0x1U) << MTKCQ_CMD45_RESP_CRCERR_CLR_SHIFT)
#define MTKCQ_CMD45_RESP_TO_CLR_SHIFT        (5)
#define MTKCQ_CMD45_RESP_TO_CLR              ((0x1U) << MTKCQ_CMD45_RESP_TO_CLR_SHIFT)


#define MTKCQ_CMD13_RESP_CRCERR_CLR_SHIFT        (8)
#define MTKCQ_CMD13_RESP_CRCERR_CLR              ((0x1U) << MTKCQ_CMD13_RESP_CRCERR_CLR_SHIFT)
#define MTKCQ_CMD13_RESP_TO_CLR_SHIFT            (9)
#define MTKCQ_CMD13_RESP_TO_CLR                  ((0x1U) << MTKCQ_CMD13_RESP_TO_CLR_SHIFT)

#define MTKCQ_OTHERCMD_RESP_CRCERR_CLR_SHIFT      (12)
#define MTKCQ_OTHERCMD_RESP_CRCERR_CLR            ((0x1U) << MTKCQ_OTHERCMD_RESP_CRCERR_CLR_SHIFT)
#define MTKCQ_OTHERCMD_RESP_TO_CLR_SHIFT          (13)
#define MTKCQ_OTHERCMD_RESP_TO_CLR                ((0x1U) << MTKCQ_OTHERCMD_RESP_TO_CLR_SHIFT)

#define MTKCQ_R1_RESP_ERR_CLR_SHIFT                (17)
#define MTKCQ_R1_RESP_ERR_CLR                      ((0x1U) << MTKCQ_R1_RESP_ERR_CLR_SHIFT)
#define MTKCQ_EMMC52_R1_RESP_ERR_CLR_SHIFT         (18)
#define MTKCQ_EMMC52_R1_RESP_ERR_CLR               ((0x1U) << MTKCQ_EMMC52_R1_RESP_ERR_CLR_SHIFT)


/*EMMC51_MTKCQ_CMD_DONE_CLR*/
#define MTKCQ_CMD13_UPDATE_ST_CLR_SHIFT           (0)
#define MTKCQ_CMD13_UPDATE_ST_CLR                 ((0x1U) << MTKCQ_CMD13_UPDATE_ST_CLR_SHIFT)
#define MTKCQ_CMD45_DONE_ST_CLR_SHIFT             (1)
#define MTKCQ_CMD45_DONE_ST_CLR                   ((0x1U) << MTKCQ_CMD45_DONE_ST_CLR_SHIFT)
#define MTKCQ_OTHER_CMD_DONE_ST_CLR_SHIFT         (2)
#define MTKCQ_OTHER_CMD_DONE_ST_CLR               ((0x1U) << MTKCQ_OTHER_CMD_DONE_ST_CLR_SHIFT)
#define MTKCQ_CMD13_DONE_ST_CLR_SHIFT             (4)
#define MTKCQ_CMD13_DONE_ST_CLR                   ((0x1U) << MTKCQ_CMD13_DONE_ST_CLR_SHIFT)


/*EMMC51_MTKCQ_SW_CTL_CQ*/
#define MTKCQ_SW_RESTART_SHIFT          (0)
#define MTKCQ_SW_RESTART                ((0x1U) << MTKCQ_SW_RESTART_SHIFT)


#define MTKCQ_GO_IDLE_SHIFT             (4)
#define MTKCQ_GO_IDLE                   ((0x1U) << MTKCQ_GO_IDLE_SHIFT)

#define MTKCQ_GO_ACTIVE_SHIFT           (5)
#define MTKCQ_GO_ACTIVE                 ((0x1U) << MTKCQ_GO_ACTIVE_SHIFT)

/*EMMC51_MTKCQ_CMD44_RESP*/
#define MTKCQ_CMD44_RESP_SHIFT          (0)
#define MTKCQ_CMD44_RESP                ((0xFFFFFFFFU) << MTKCQ_CMD44_RESP_SHIFT)

/*EMMC51_MTKCQ_CMD45_RESP*/
#define MTKCQ_CMD45_RESP_SHIFT          (0)
#define MTKCQ_CMD45_RESP                ((0xFFFFFFFFU) << MTKCQ_CMD45_RESP_SHIFT)


/*EMMC51_MTKCQ_CMD13_RCA*/
#define MTKCQ_ACMD13_RCA_SHIFT          (0)
#define MTKCQ_ACMD13_RCA                ((0xFFFFU) << MTKCQ_ACMD13_RCA_SHIFT)

/*EMMC51_CQCB_CFG3*/
#define MSDC_CQCB_CLR_SHIFT             (0)
#define MSDC_CQCB_CLR                   ((0x1U) << MSDC_CQCB_CLR_SHIFT)

#define MSDC_CQCB_FIFO_FULL_SHIFT       (4)
#define MSDC_CQCB_FIFO_FULL             ((0x1U) << MSDC_CQCB_FIFO_FULL_SHIFT)


/*EMMC51_CQCB_CMD44*/
#define MSDC_CQCB_CMD44_SHIFT           (0)
#define MSDC_CQCB_CMD44                 ((0xFFFFFFFFU) << MSDC_CQCB_CMD44_SHIFT)


/*EMMC51_CQCB_CMD45*/
#define MSDC_CQCB_CMD45_SHIFT           (0)
#define MSDC_CQCB_CMD45                 ((0xFFFFFFFFU) << MSDC_CQCB_CMD45_SHIFT)


/*EMMC51_CQCB_TIDMAP*/
#define MSDC_CQCB_TIDMAP_SHIFT          (0)
#define MSDC_CQCB_TIDMAP                ((0xFFFFFFFFU) << MSDC_CQCB_TIDMAP_SHIFT)

/*EMMC51_CQCB_TIDMAPCLR*/
#define MSDC_CQCB_TIDMAP_CLR_SHIFT       (0)
#define MSDC_CQCB_TIDMAP_CLR             ((0xFFFFFFFFU) << MSDC_CQCB_TIDMAP_CLR_SHIFT)


/*EMMC51_CQCB_CURCMD*/
#define MSDC_CQCB_CURCMD_SHIFT           (0)
#define MSDC_CQCB_CURCMD                 ((0x3FU) << MSDC_CQCB_CURCMD_SHIFT)

/*AES related*/
#define AES_EN_SHIFT           			(0)
#define AES_EN                 			((0x1U) << AES_EN_SHIFT)
#define AES_SWITCH_VALID0_SHIFT         (1)
#define AES_SWITCH_VALID0               ((0x1U) << AES_SWITCH_VALID0_SHIFT)
#define AES_SWITCH_VALID1_SHIFT         (2)
#define AES_SWITCH_VALID1               ((0x1U) << AES_SWITCH_VALID1_SHIFT)
#define AES_CLK_DIV_SEL_SHIFT           (4)
#define AES_CLK_DIV_SEL                 ((0x7U) << AES_CLK_DIV_SEL_SHIFT)


#define AES_ENC_SHIFT           		(0)
#define AES_ENC                 		((0x1U) << AES_ENC_SHIFT)
#define AES_DEC_SHIFT         			(1)
#define AES_DEC               			((0x1U) << AES_DEC_SHIFT)
#define AES_BYPASS_EN_SHIFT         	(2)
#define AES_BYPASS_EN                 	((0x1U) << AES_BYPASS_EN_SHIFT)

#define AES_MODE_SHIFT           		(0)
#define AES_MODE                 		((0x1FU) << AES_MODE_SHIFT)
#define AES_KEYLENGNTH_SHIFT           	(8)
#define AES_KEYLENGNTH                 	((0x3U) << AES_KEYLENGNTH_SHIFT)

/*MTH realted*/
#define MTH_EN_SHIFT           		(0)
#define MTH_EN                 		((0x1U) << MTH_EN_SHIFT)
#define MTH_CLR_SHIFT           	(1)
#define MTH_CLR                 	((0x1U) << MTH_CLR_SHIFT)

#define MTH_TOKEN_SEL_SHIFT           		(0)
#define MTH_TOKEN_SEL                 		((0x1U) << MTH_TOKEN_SEL_SHIFT)
#define MTH_TOKEN_RELEASE_SHIFT           	(1)
#define MTH_TOKEN_RELEASE                 	((0x1U) << MTH_TOKEN_RELEASE_SHIFT)
/* 8bit Mode */
#define SUPPORT_8_BIT				   (1)

/* Host OCR */
#define BUSY_MASK                      ((unsigned int)(0x1<<31))
#define HCS_MASK                       ((unsigned int)(0x1<<30))
#define CCS_MASK                       ((unsigned int)(0x1<<30))
#define XPC_MASK                       ((unsigned int)(0x1<<28))
#define S18R_MASK                      ((unsigned int)(0x1<<24))
#define S18A_MASK                      ((unsigned int)(0x1<<24))
#define OCR_MASK                       ((unsigned int)(0xFF8000))
#define HOST_OCR_ATTRIBUTE             (HCS_MASK | XPC_MASK | S18R_MASK)
#define HOST_OCR_VOLTAGE               (OCR_MASK)
#define HOST_OCR                       (HOST_OCR_ATTRIBUTE | HOST_OCR_VOLTAGE)

/* Response Type */
#define SDC_CMD_RSPTYPE_NO             ((0x00U) << 7)
#define SDC_CMD_RSPTYPE_R1             ((0x01U) << 7)
#define SDC_CMD_RSPTYPE_R2             ((0x02U) << 7)
#define SDC_CMD_RSPTYPE_R3             ((0x03U) << 7)
#define SDC_CMD_RSPTYPE_R4             ((0x04U) << 7)
#define SDC_CMD_RSPTYPE_R5             ((0x01U) << 7)
#define SDC_CMD_RSPTYPE_R6             ((0x01U) << 7)
#define SDC_CMD_RSPTYPE_R7             ((0x01U) << 7)
#define SDC_CMD_RSPTYPE_R1B            ((0x07U) << 7)

/* Data Type */
#define DTYPE_NONE                     ((0x00U) << 11)
#define DTYPE_SINGLE_BLK               ((0x01U) << 11)
#define DTYPE_MULTI_BLK                ((0x02U) << 11)
#define DTYPE_STREAM                   ((0x03U) << 11)
#define SDC_CMD_READ                   ((0x00U) << 13)
#define SDC_CMD_WRITE                  ((0x01U) << 13)
#define SDC_CMD_STOP                   ((0x01U) << 14)
#define SDC_CMD_GO_IRQ                 ((0x01U) << 15)
#define SDC_CMD_LEN_SHIFT              (16)
#define SDC_CMD_AUTO_CMD_NONE          ((0x0U) << 28)
#define SDC_CMD_AUTO_CMD12             ((0x1U) << 28)
#define SDC_CMD_AUTO_CMD23             ((0x2U) << 28)
#define SDC_CMD_AUTO_CMD19             ((0x3U) << 28)
#define SDC_CMD_VOL_SWITCH             ((0x1U) << 30)

/* Transaction Type */
#define NULL_DATA_MODE                 (0)
#define PIO_DATA_MODE                  (1)
#define BASIC_DMA_DATA_MODE            (2)
#define DESC_DMA_DATA_MODE             (3)
#define ENHANCED_DMA_DATA_MODE         (4)

/* DMA Burst */
#define DMA_BST_8                      (3)
#define DMA_BST_16                     (4)
#define DMA_BST_32                     (5)
#define DMA_BST_64                     (6)


/*I/O Settings*/
//emmc
#define EMMC_PAD_PINMUX                   (IO_VIRT + 0xD600)
#define EMMC_PAD_DRIVING_HIGH             (IO_VIRT + 0xD480)
#define EMMC_PAD_DRIVING_LOW_CFG1         (IO_VIRT + 0xD488)
#define EMMC_PAD_DRIVING_LOW_CFG2         (IO_VIRT + 0xD48C)
#define EMMC_PAD_PUPD                     (IO_VIRT + 0xD4B4)
#define EMMC_PAD_R1R0                     (IO_VIRT + 0xD4AC)
#define EMMC_PAD_DS                       (IO_VIRT + 0xD4C4)
#define EMMC_PAD_IES                      (IO_VIRT + 0xD4B0)

//SD
#define SD_PAD_PINMUX                     (IO_VIRT + 0xD604)

//RESET PAD
#define EMMC_RESET_PAD_PU                 (IO_VIRT + 0xD50C)
#define EMMC_RESET_PAD_PD                 (IO_VIRT + 0xD51C)
#define EMMC_RESET_PAD_SMT                (IO_VIRT + 0xD52C)
#define EMMC_RESET_PAD_IES                (IO_VIRT + 0xD53C)



/* DMA Data Structure */
#if 1
#define BASIC_DMA_MAX_LEN       (0xFFFFFFFF & ~511)
#else
//old IC, discard
#define BASIC_DMA_MAX_LEN       (0xFFFF)
#endif
#define GPD_MAX_LEN                    (0xFFFF)
#define BD_MAX_LEN                     (0xFFFF)
#define MAX_BD_NUM                     (1024)
#define MAX_BD_PER_GPD                 (MAX_BD_NUM)
#define MAX_GPD_PER_QUEUE              (MAX_BD_NUM)

struct __msdc_gpd_s__
{
	unsigned int hwo	:1;
	unsigned int bdp	:1;
	unsigned int resv0	:6;
	unsigned int chksum	:8;
	unsigned int intr	:1;
	unsigned int resv1	:15;

	void *pNext;
	void *pBuff;

	unsigned int buffLen:16;
	unsigned int extLen	:8;
	unsigned int resv3	:8;

	// Enhanced DMA fields
	unsigned int arg;
	unsigned int blkNum;
	unsigned int cmd;
};
typedef struct __msdc_gpd_s__ msdc_gpd_t;

struct __msdc_bd_s__
{
	unsigned int eol	:1;
	unsigned int resv0	:7;
	unsigned int chksum	:8;
	unsigned int resv1	:1;
	unsigned int blkPad	:1;
	unsigned int dwPad	:1;			// DWORD is 4 bytes
	unsigned int resv2	:13;

	void *pNext;
	void *pBuff;

	unsigned int buffLen:16;
	unsigned int resv3	:16;
};
typedef struct __msdc_bd_s__ msdc_bd_t;

//AES
#define MSDC_AES_ECB       0x0
#define MSDC_AES_CBC       0x1
#define MSDC_AES_CTR       0x2
#define MSDC_AES_OFB       0x5


#define MSDC_AES_KEYLEN_128bit  0x0
#define MSDC_AES_KEYLEN_192bit  0x1
#define MSDC_AES_KEYLEN_256bit  0x2
#define MSDC_AES_KEYLEN_0bit    0x3
#endif // #ifndef _MSDC_HOST_HW_H_
