/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
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 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
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 * modification, are permitted provided that the following conditions
 * are met:
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 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: brianpc.huang $
 * $Date: 2015/05/29 $
 * $RCSfile: hw_hdtv.h,v $
 * $Revision: #1 $
 *
 *---------------------------------------------------------------------------*/
 
#ifndef _HW_HDTV_H_
#define _HW_HDTV_H_

#include "typedef.h"

//mt5895
#define IO_HDTV_BASE (IO_VIRT_SRE + 0x20000)

#define HDFE_00 (IO_HDTV_BASE+0x0A80)
    #define AD3_OFFSET Fld(9, 20, AC_MSKW32) //28:20
    #define AD2_OFFSET Fld(9, 10, AC_MSKW21) //18:10
    #define AD1_OFFSET Fld(9, 0, AC_MSKW10) //8:0
#define HDFE_01 (IO_HDTV_BASE+0x0A84)
    #define AD1_GAIN Fld(16, 16, AC_FULLW32) //31:16
    #define AD2_GAIN Fld(16, 0, AC_FULLW10) //15:0
#define HDFE_02 (IO_HDTV_BASE+0x0A88)
    #define AD3_GAIN Fld(16, 16, AC_FULLW32) //31:16
    #define ADC_FT_MODE Fld(1, 4, AC_MSKB0) //4
    #define IDX_CHANNEL_EN Fld(4, 0, AC_MSKB0) //3:0
    #define HDFE_03 (IO_HDTV_BASE+0x0A8C)
    #define AD3_GAIN_BIAS Fld(10, 20, AC_MSKW32) //29:20
    #define AD2_GAIN_BIAS Fld(10, 10, AC_MSKW21) //19:10
    #define AD1_GAIN_BIAS Fld(10, 0, AC_MSKW10) //9:0
#define HDFE_04 (IO_HDTV_BASE+0x086C)
    #define filter_cof3_lsb Fld(6, 26, AC_MSKB3) //31:26
    #define filter_cof2 Fld(13, 13, AC_MSKDW) //25:13
    #define filter_cof1 Fld(13, 0, AC_MSKW10) //12:0
#define HDFE_05 (IO_HDTV_BASE+0x0870)
    #define filter_cof5_lsb Fld(12, 20, AC_MSKW32) //31:20
    #define filter_cof4 Fld(13, 7, AC_MSKDW) //19:7
    #define filter_cof3_msb Fld(7, 0, AC_MSKB0) //6:0
#define HDFE_06 (IO_HDTV_BASE+0x0874)
    #define filter_cof8_lsb Fld(5, 27, AC_MSKB3) //31:27
    #define filter_cof7 Fld(13, 14, AC_MSKDW) //26:14
    #define filter_cof6 Fld(13, 1, AC_MSKW10) //13:1
    #define filter_cof5_msb Fld(1, 0, AC_MSKB0) //0
#define HDFE_07 (IO_HDTV_BASE+0x0878)
    #define vga_filter_byps Fld(2, 22, AC_MSKB2) //23:22
    #define filter_cof9 Fld(13, 8, AC_MSKW21) //20:8
    #define filter_cof8_msb Fld(8, 0, AC_FULLB0) //7:0
#define HDFE_0C (IO_HDTV_BASE+0x0938) 
    #define AD1_GAIN_Temp Fld(12, 16, AC_MSKW32) //27:16
    #define AD2_GAIN_Temp Fld(12, 0, AC_MSKW10) //11:0
#define HDFE_0D (IO_HDTV_BASE+0x093C)
    #define AD3_GAIN_Temp Fld(12, 0, AC_MSKW10) //11:0
#define HDTV_00 (IO_HDTV_BASE+0x07D4)
    #define HDTV_ADC_LSB_CLR Fld(1, 31, AC_MSKB3) //31
    #define HDTV_ADC3_CLR Fld(1, 30, AC_MSKB3) //30
    #define HDTV_ADC2_CLR Fld(1, 29, AC_MSKB3) //29
    #define HDTV_ADC1_CLR Fld(1, 28, AC_MSKB3) //28
    #define ADC_FROM_DVI Fld(1, 27, AC_MSKB3) //27
    #define HDTV_ADC3_MID Fld(1, 26, AC_MSKB3) //26
    #define HDTV_ADC2_MID Fld(1, 25, AC_MSKB3) //25
    #define HDTV_ADC1_MID Fld(1, 24, AC_MSKB3) //24
    #define HDTV_SP0_F Fld(1, 23, AC_MSKB2) //23
    #define HDTV_BLANK_ON Fld(1, 22, AC_MSKB2) //22
    #define ADC1_DELAY_1T Fld(1, 21, AC_MSKB2) //21
    #define ADC2_DELAY_1T Fld(1, 20, AC_MSKB2) //20
    #define ADC3_DELAY_1T Fld(1, 19, AC_MSKB2) //19
    #define HDTV_FIELD_ALIGN Fld(1, 18, AC_MSKB2) //18
    #define HDTV_AVMASK_HEDGE Fld(1, 17, AC_MSKB2) //17
    #define HDTV_AVMASK_SEL Fld(1, 16, AC_MSKB2) //16
    #define HDTV_AVMASK_EN Fld(1, 15, AC_MSKB1) //15
    #define HDTV_FLD_SEL Fld(1, 14, AC_MSKB1) //14
    #define HDTV_RGB Fld(1, 13, AC_MSKB1) //13
    #define HDTV_CEN_SEL Fld(1, 12, AC_MSKB1) //12
    #define HDTV_LCLAMP_EN Fld(1, 11, AC_MSKB1) //11
    #define HDTV_LCLAMP_ZERO Fld(1, 10, AC_MSKB1) //10
    #define HDTV_BLK_CALI_MIN Fld(3, 7, AC_MSKW10) //9:7
    #define HDTV_RAW_DATA_OUT Fld(1, 6, AC_MSKB0) //6
    #define HDTV_BLK_STA_SEL Fld(1, 5, AC_MSKB0) //5
    #define HDTV_BLK_CALI_PERIOD Fld(3, 2, AC_MSKB0) //4:2
    #define HDTV_BLK_CALI_LCNT Fld(2, 0, AC_MSKB0) //1:0
#define HDTV_01 (IO_HDTV_BASE+0x07D8)
    #define HDTV_BLK_CALI_START Fld(7, 25, AC_MSKB3) //31:25
    #define HDTV_AV_START Fld(13, 12, AC_MSKDW) //24:12
    #define HDTV_AV_WIDTH Fld(12, 0, AC_MSKW10) //11:0
#define HDTV_02 (IO_HDTV_BASE+0x07DC)
    #define HDTV_BLK_CALI_ADJ_ON Fld(1, 31, AC_MSKB3) //31
    #define HDTV_BLK_CALI_Y_TAR Fld(7, 24, AC_MSKB3) //30:24
    #define HDTV_BLK_CALI_EN Fld(1, 23, AC_MSKB2) //23
    #define HDTV_BLK_CALI_PB_TAR Fld(7, 16, AC_MSKB2) //22:16
    #define HDTV_BLK_CALI_FREEZE Fld(1, 15, AC_MSKB1) //15
    #define HDTV_BLK_CALI_PR_TAR Fld(7, 8, AC_MSKB1) //14:8
    #define HDTV_BLK_CALI_FCNT Fld(2, 6, AC_MSKB0) //7:6
    #define HDTV_BLK_CALI_THRES Fld(6, 0, AC_MSKB0) //5:0
#define HDTV_03 (IO_HDTV_BASE+0x07E0)
    #define HDTV_V_RELATCH_SEL Fld(1, 31, AC_MSKB3) //31
    #define HDTV_V_RELATCH_POS Fld(1, 30, AC_MSKB3) //30
    #define HDTV_HLOCK_NEG_LATCH Fld(1, 29, AC_MSKB3) //29
    #define HDTV_EN Fld(1, 28, AC_MSKB3) //28
    #define ADC_LSB_EN Fld(4, 24, AC_MSKB3) //27:24
    #define HDTV_BLANK_AVG Fld(2, 22, AC_MSKB2) //23:22
    #define HDTV_RAW_VSYNC_SEL1 Fld(1, 21, AC_MSKB2) //21
    #define HDTV_RAW_VSYNC_SEL0 Fld(1, 20, AC_MSKB2) //20
    #define HDTV_HEDGE_SEL Fld(1, 19, AC_MSKB2) //19
        #define HDTV_RISING_EDGE	0	
        #define HDTV_FALLING_EDGE	1  
    #define HDTV_DATA_SEL Fld(3, 16, AC_MSKB2) //18:16
    #define HDTV_H_SEL Fld(2, 14, AC_MSKB1) //15:14
    #define HDTV_V_SEL Fld(2, 12, AC_MSKB1) //13:12
    #define HDTV_BLANK_CLEAR Fld(1, 11, AC_MSKB1) //11
    #define HDTV_BLANK_HOLD Fld(1, 10, AC_MSKB1) //10
    #define HDTV_BLAK_SET Fld(2,10,AC_MSKB1) //11:10
        #define AS_BLANK_RESET 0x02
        #define AS_BLANK_HOLD 0x01
        #define AS_BLANK_ALWAYS 0x00  
    #define HDTV_BLANK_START Fld(10, 0, AC_MSKW10) //9:0
#define HDTV_04 (IO_HDTV_BASE+0x07E4)
    #define HDTV_AGC Fld(6, 24, AC_MSKB3) //29:24
    #define HDTV_CLAMP_START Fld(12, 12, AC_MSKW21) //23:12
    #define HDTV_CLAMP_END Fld(12, 0, AC_MSKW10) //11:0
#define HDTV_05 (IO_HDTV_BASE+0x07EC)
    #define HDTV_YOFFSET Fld(6, 26, AC_MSKB3) //31:26
    #define BIW_AD_SEL Fld(2, 24, AC_MSKB3) //25:24
    #define BIW_END Fld(12, 12, AC_MSKW21) //23:12
    #define BIW_START Fld(11, 1, AC_MSKW10) //11:1
    #define HDTV_BLANK_EF_EN Fld(1, 0, AC_MSKB0) //0
#define HDTV_06 (IO_HDTV_BASE+0x07F4)
	#define MHL_FS_FIX_SEL Fld(1,31,AC_MSKB3)//[31:31]
    #define CLAMP_HD_en Fld(1, 12, AC_MSKB1) //12
    #define CLAMP_HD_THRE Fld(12, 0, AC_MSKW10) //11:0
#define HDTV_STA_06 (IO_HDTV_BASE+0x0218)
    #define STA_HDTV_BLANK_PR Fld(10, 20, AC_MSKW32) //29:20
    #define STA_HDTV_BLANK_PB Fld(10, 10, AC_MSKW21) //19:10
    #define STA_HDTV_BLANK_Y Fld(10, 0, AC_MSKW10) //9:0
#define HDTV_STA_07 (IO_HDTV_BASE+0x021C)
    #define STA_HDTV_CPIDX Fld(1, 31, AC_MSKB3) //31
    #define STA_HDTV_ADC3 Fld(10, 20, AC_MSKW32) //29:20
    #define STA_HDTV_ADC2 Fld(10, 10, AC_MSKW21) //19:10
    #define STA_HDTV_ADC1 Fld(10, 0, AC_MSKW10) //9:0
    
#endif //_HW_HDTV_H_ 

