/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


#ifndef CONFIG_DEFAULT_H
#define CONFIG_DEFAULT_H

#include "x_pinmux.h"
//----------------------------------------------------------------------------
// Initial dram settings
//----------------------------------------------------------------------------
#define DEFAULT_DRAM_TYPE                   DDR_LP4_x4
#define DEFAULT_DDR_CLOCK                   (3504000000)
//for MTK turnkey PCB only (in bootp.c)
//#define DEFAULT_DRAM_PCB_CHK                (0)

//#ifndef DRAM_PRIORITY_LIST
// Audio/0 > B2R/5 > NR/PSCAN/4 > Scpip/7 > OSD/3 > Mjc_in/13 > Mjc_out/14 > VLD1/9 > Vdec_mc/8 > CPU/6 > Gfx/11 > Demux/PVR/1 > VBI/3D/TVE/2 >VENC/12 > Test/15 > Unused/10
//#define DRAM_PRIORITY_LIST                  ((UINT8*)"0c9421a387fbd56e")
//#endif

#define RELEASE_ENABLE_WATCHDOG (0)
//----------------------------------------------------------------------------
// FBM setup
//----------------------------------------------------------------------------
#if defined(CC_SUPPORT_DRAM_4GB)
	#define TOTAL_MEM_SIZE                      ( 0x100000000 ) // 8888Gb
#elif defined(CC_SUPPORT_DRAM_3GB)
	#define TOTAL_MEM_SIZE                      ( 0xC0000000 ) // 8844Gb
#elif defined(CC_SUPPORT_DRAM_2GB)
	#define TOTAL_MEM_SIZE                      ( 0x80000000 ) // 4444Gb
#else   //CC_SUPPORT_DRAM_2_5GB
	#define TOTAL_MEM_SIZE                      ( 0xA0000000 ) // 8444Gb
#endif

#define EMI_MEM_OFFSET 0x40000000   // 1GB offset


//#define TOTAL_CHB_MEM_SIZE                  (1024 * 1024 * 1024)
#if 1
#define CC_CONFIG_OSD_CM_SIZE               (4) // 4:argb 8888 ;2:argb 4444
#define CC_CONFIG_OSD_BUF_MODE              (2) // 2:double  buffer ;1:sngle buffer

#ifndef CC_CONFIG_OSD_PLANE1_MAX_W
#define CC_CONFIG_OSD_PLANE1_MAX_W          (0)
#endif
#ifndef CC_CONFIG_OSD_PLANE1_MAX_H
#define CC_CONFIG_OSD_PLANE1_MAX_H          (0)
#endif
#define CC_CONFIG_OSD_PLANE1_MEM_SIZE       (((CC_CONFIG_OSD_PLANE1_MAX_W*     \
                                        CC_CONFIG_OSD_PLANE1_MAX_H*        \
                                        CC_CONFIG_OSD_CM_SIZE*             \
                                        CC_CONFIG_OSD_BUF_MODE)+0x1000)&(0xFFFFF000))

        // osd 3d buffer size
#if (defined(CC_CONFIG_OSD_SBS_PLANE1)||defined(CC_CONFIG_OSD_TB_PLANE1))
#define CC_CONFIG_OSD_3D_PLANE1_MEM_SIZE    (CC_CONFIG_OSD_PLANE1_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE1_MEM_SIZE    (0)
#endif

        // osd decompress  buffer size
#ifdef CONFIG_OSD_PLANE1_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE1_MEM_SIZE   (CC_CONFIG_OSD_PLANE1_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE1_MEM_SIZE   (0)
#endif

#ifndef CC_CONFIG_OSD_PLANE2_MAX_W
#define CC_CONFIG_OSD_PLANE2_MAX_W          (960)
#endif
#ifndef CC_CONFIG_OSD_PLANE2_MAX_H
#define CC_CONFIG_OSD_PLANE2_MAX_H          (540)
#endif
#define CC_CONFIG_OSD_PLANE2_MEM_SIZE       (((CC_CONFIG_OSD_PLANE2_MAX_W*     \
                                            CC_CONFIG_OSD_PLANE2_MAX_H*        \
                                            CC_CONFIG_OSD_CM_SIZE*             \
                                            CC_CONFIG_OSD_BUF_MODE)+0x1000)&(0xFFFFF000))

#if (defined(CC_CONFIG_OSD_SBS_PLANE2)||defined(CC_CONFIG_OSD_TB_PLANE2))
#define CC_CONFIG_OSD_3D_PLANE2_MEM_SIZE    (CC_CONFIG_OSD_PLANE2_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE2_MEM_SIZE    (0)
#endif

#ifndef CONFIG_OSD_PLANE2_COMPRESSION
        //#define  CONFIG_OSD_PLANE2_COMPRESSION
#endif

        // osd decompress  buffer size
#ifdef CONFIG_OSD_PLANE2_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE2_MEM_SIZE   (CC_CONFIG_OSD_PLANE2_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE2_MEM_SIZE   (0)
#endif

#ifndef CC_CONFIG_OSD_PLANE3_MAX_W
#define CC_CONFIG_OSD_PLANE3_MAX_W          (1920)
#endif
#ifndef CC_CONFIG_OSD_PLANE3_MAX_H
#define CC_CONFIG_OSD_PLANE3_MAX_H          (1080)
#endif
#define CC_CONFIG_OSD_PLANE3_MEM_SIZE       (((CC_CONFIG_OSD_PLANE3_MAX_W*     \
                                            CC_CONFIG_OSD_PLANE3_MAX_H*        \
                                            CC_CONFIG_OSD_CM_SIZE*             \
                                            CC_CONFIG_OSD_BUF_MODE)+0x1000)&(0xFFFFF000))

#if (defined(CC_CONFIG_OSD_SBS_PLANE3)||defined(CC_CONFIG_OSD_TB_PLANE3))
#define CC_CONFIG_OSD_3D_PLANE3_MEM_SIZE    (CC_CONFIG_OSD_PLANE3_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE3_MEM_SIZE    (0)
#endif

        // osd decompress  buffer size
#ifndef CONFIG_OSD_PLANE3_COMPRESSION
        // #define  CONFIG_OSD_PLANE3_COMPRESSION
#endif

#ifdef CONFIG_OSD_PLANE3_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE3_MEM_SIZE   (CC_CONFIG_OSD_PLANE3_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE3_MEM_SIZE   (0)
#endif

#ifndef CC_CONFIG_OSD_PLANE4_MAX_W
#define CC_CONFIG_OSD_PLANE4_MAX_W          (0)
#endif
#ifndef CC_CONFIG_OSD_PLANE4_MAX_H
#define CC_CONFIG_OSD_PLANE4_MAX_H          (0)
#endif
#define CC_CONFIG_OSD_PLANE4_MEM_SIZE       (((CC_CONFIG_OSD_PLANE4_MAX_W*     \
                                            CC_CONFIG_OSD_PLANE4_MAX_H*        \
                                            CC_CONFIG_OSD_CM_SIZE*             \
                                            CC_CONFIG_OSD_BUF_MODE)+0x1000)&(0xFFFFF000))

#if (defined(CC_CONFIG_OSD_SBS_PLANE4)||defined(CC_CONFIG_OSD_TB_PLANE4))
#define CC_CONFIG_OSD_3D_PLANE4_MEM_SIZE    (CC_CONFIG_OSD_PLANE4_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE4_MEM_SIZE    (0)
#endif

        // osd decompress  buffer size
#ifdef CONFIG_OSD_PLANE4_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE4_MEM_SIZE   (CC_CONFIG_OSD_PLANE4_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE4_MEM_SIZE   (0)
#endif

#ifndef CC_CONFIG_OSD_PLANE5_MAX_W
#define CC_CONFIG_OSD_PLANE5_MAX_W          (100)
#endif
#ifndef CC_CONFIG_OSD_PLANE5_MAX_H
#define CC_CONFIG_OSD_PLANE5_MAX_H          (100)
#endif

#define CC_CONFIG_OSD_PLANE5_MEM_SIZE       (((CC_CONFIG_OSD_PLANE5_MAX_W*     \
                                    CC_CONFIG_OSD_PLANE5_MAX_H*        \
                                    CC_CONFIG_OSD_CM_SIZE)+0x1000)&(0xFFFFF000))

        // osd 3d buffer size
#if (defined(CC_CONFIG_OSD_SBS_PLANE5)||defined(CC_CONFIG_OSD_TB_PLANE5))
#define CC_CONFIG_OSD_3D_PLANE5_MEM_SIZE    (CC_CONFIG_OSD_PLANE5_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE5_MEM_SIZE    (0)
#endif

        // osd decompress  buffer size
#ifdef CONFIG_OSD_PLANE5_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE5_MEM_SIZE   (CC_CONFIG_OSD_PLANE5_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE5_MEM_SIZE   (0)
#endif

#define CC_CONFIG_OSD_PLANE_BASIC_MEM_SIZE  (CC_CONFIG_OSD_PLANE1_MEM_SIZE+ \
                                        CC_CONFIG_OSD_PLANE2_MEM_SIZE+  \
                                        CC_CONFIG_OSD_PLANE3_MEM_SIZE+  \
                                        CC_CONFIG_OSD_PLANE4_MEM_SIZE+  \
                                        CC_CONFIG_OSD_PLANE5_MEM_SIZE)

#define CC_CONFIG_OSD_3D_PLANE_MEM_SIZE     (CC_CONFIG_OSD_3D_PLANE1_MEM_SIZE+  \
                                            CC_CONFIG_OSD_3D_PLANE2_MEM_SIZE+   \
                                            CC_CONFIG_OSD_3D_PLANE3_MEM_SIZE+   \
                                            CC_CONFIG_OSD_3D_PLANE4_MEM_SIZE+   \
                                            CC_CONFIG_OSD_3D_PLANE5_MEM_SIZE)

#define CC_CONFIG_OSD_DEC_PLANE_MEM_SIZE    (CC_CONFIG_OSD_DEC_PLANE1_MEM_SIZE+ \
                                            CC_CONFIG_OSD_DEC_PLANE2_MEM_SIZE+  \
                                            CC_CONFIG_OSD_DEC_PLANE3_MEM_SIZE+  \
                                            CC_CONFIG_OSD_DEC_PLANE4_MEM_SIZE+  \
                                            CC_CONFIG_OSD_DEC_PLANE5_MEM_SIZE)

#define CC_CONFIG_GFX_TEMP_MEM_SIZE         (CC_CONFIG_OSD_PLANE3_MAX_W*    \
                                            CC_CONFIG_OSD_PLANE3_MAX_H*     \
                                            CC_CONFIG_OSD_CM_SIZE)

#define DFB_SUM_MEM_SIZE                    (CC_CONFIG_OSD_PLANE_BASIC_MEM_SIZE+\
                                            CC_CONFIG_OSD_3D_PLANE_MEM_SIZE+    \
                                            CC_CONFIG_OSD_DEC_PLANE_MEM_SIZE+   \
                                            CC_CONFIG_GFX_TEMP_MEM_SIZE)
#endif

#ifdef CC_GFX_MMU
#define DIRECT_FB_MEM_SIZE                  ((DFB_SUM_MEM_SIZE+4*1024)&(0xFFFFF000))
#else
#define DIRECT_FB_MEM_SIZE                  (76 * 1024 * 1024)
#endif



#define FB_MEM_SIZE                         (20 * 1024 * 1024)


#ifndef FBM_MEM_CFG_SIZE
#define FBM_MEM_CFG_SIZE                    (FBM_MEM_CFG_MT5895_3DTV)
#endif /* FBM_MEM_CFG_SIZE */

#if defined(CC_SVP_SUPPORT) && defined(CC_SUPPORT_4K2K)
    #define VFIFO_MAIN   (35*1024*1024 + 35*1024*1024) // 4k(35M) + 4k(35M)
    #define VFIFO_SUB    0
    #define VFIFO_TOTAL VFIFO_SUB + VFIFO_MAIN
#else
    #define VFIFO_MAIN   (10*1024*1024)
    #define VFIFO_SUB    0
    #define VFIFO_TOTAL  VFIFO_SUB + VFIFO_MAIN
#endif

#if defined(CC_TRUSTZONE_64_SUPPORT)
#define TRUSTZONE_CODE_BASE                 (0x10000)
#define TRUSTZONE_CODE_BASE_BL32            (0x5000)
#define TRUSTZONE_MEM_SIZE                  ((20 * 1024 * 1024) + VFIFO_TOTAL)
#define TRUSTZONE_MEM_SIZE_BL32             (TRUSTZONE_MEM_SIZE-0x30000)

#elif defined(CC_TRUSTZONE_SUPPORT)
#define TRUSTZONE_CODE_BASE                 (0x5000)
#define TRUSTZONE_MEM_SIZE                  (20 * 1024 * 1024) + VFIFO_TOTAL

#else
#define TRUSTZONE_MEM_SIZE                  (0)
#endif
#if defined(CC_TRUSTZONE_IN_CHB)
#define TRUSTZONE_MEM_SIZE_CHA (0)
#else
#define TRUSTZONE_MEM_SIZE_CHA TRUSTZONE_MEM_SIZE
#endif
#ifndef CONFIG_TV_DRV_VFY
#define LINUX_KERNEL_MEM_SIZE               ((TOTAL_MEM_SIZE > (FBM_MEM_CFG_SIZE + DIRECT_FB_MEM_SIZE + FB_MEM_SIZE + TRUSTZONE_MEM_SIZE)) ?\
                                            (TOTAL_MEM_SIZE - FBM_MEM_CFG_SIZE - DIRECT_FB_MEM_SIZE - FB_MEM_SIZE - TRUSTZONE_MEM_SIZE) : (54 * 1024 * 1024))
#else
#define LINUX_MM_VFY_RESERVE_SIZE           (512*1024*1024)
#define LINUX_KERNEL_MEM_SIZE               (TOTAL_MEM_SIZE - LINUX_MM_VFY_RESERVE_SIZE)
#endif

#define DEFAULT_TARGET_COUNTRY              (COUNTRY_EU)

//----------------------------------------------------------------------------
// Default Panel setting
//----------------------------------------------------------------------------
#ifndef DEFAULT_PANEL_SELECT
#define DEFAULT_PANEL_SELECT                (PANEL_DEFAULT)
#endif
#define BACKLIGHT_GPIO                      (OPCTRL(4))
#define BACKLIGHT_ON_VAL                    (0)
#define PANELPOWER_GPIO                     (OPCTRL(9))
#define PANELPOWER_ON_VAL                   (1)

// disable spread spectrum for vga output
#define SPREAD_SPECTRUM_PERMILLAGE          (0)

// pwm backlight adjustment setting
#define PANEL_BACKLIGHT_PWM_PORT            (1)

//3D Enable & LR GPIO
//#define EXT_3D_ENABLE_PORT                  (GPIO(54))
//#define EXT_3D_LR_PIN                       (PIN_GPIO53)
//#define EXT_3D_LR_PIN_FUNC                    (1)

// VB1 lockn & htpdn
#define PANEL_VB1_LOCKN_PIN          (PIN_GPIO50)
#define PANEL_VB1_LOCKN_PIN_FUNC     (2)
#define PANEL_VB1_HTPDN_PIN          (PIN_GPIO49)
#define PANEL_VB1_HTPDN_PIN_FUNC     (2)
#define PANEL_VB1_OSD_LOCKN_PIN      (PIN_GPIO54)
#define PANEL_VB1_OSD_LOCKN_PIN_FUNC (2)
#define PANEL_VB1_OSD_HTPDN_PIN      (PIN_GPIO53)
#define PANEL_VB1_OSD_HTPDN_PIN_FUNC (5)

#define PDWNC_POLARITY                      (0)

//----------------------------------------------------------------------------
// Suspend power control GPIO Number, it must be PDWNC GPIO
//----------------------------------------------------------------------------
#define  SUSPEND_GPIO_NUMBER   	(203) //DDR power control.
#define  SUSPEND_GPIO_POL   	(0) //0:active low,1:active high.


//----------------------------------------------------------------------------
// Loader logo
//----------------------------------------------------------------------------
#ifdef CC_LOADER_LOGO_SUPPORT
#define LOADER_LOGO_NUMBER                  (1)
#define LOADER_LOGO_H_FILE                  "mediatek/MediaTek_600x100x5.h"
#endif

//----------------------------------------------------------------------------
// Audio Customization
//----------------------------------------------------------------------------
#define AUDIO_INCLUDE_FILE                  "mediatek/Husky_aud.h"
#define AUDIO_Mute_Gpio_Num                 (OPCTRL(11))
#define AUDIO_Amp_Gpio_Num                  (OPCTRL(5))
#define AUDIO_HP_PLUG_IN_GPIO               (OPCTRL(6))
#define AUDIO_MUTE_GPIO_POLARITY            AUD_MUTE_GPIO_LOW_ENALBE
#define AUDIO_AMP_GPIO_POLARITY             AUD_AMP_GPIO_LOW_ENALBE
#define AUDIO_HP_PLUG_IN_POLARITY           (AUD_GPIO_LOW_ENALBE)
#define AUDIO_INPUT_MUX_SEL_TABLE           (&_rMustangAudInputMuxTable)
#define AUDIO_APROC_ENABLE                  (TRUE)

//----------------------------------------------------------------------------
// Other GPIO customization
//#define DEFAULT_TUNER_RFAGC_SWITCH_GPIO     (88)//d120203_Haibo:OPWM2 is for RFAGC switch
//----------------------------------------------------------------------------
#define FLAG_EXT_STATUS                     (0)

#if defined (CC_TUNER_DB10) || defined (CC_DUAL_TUNER_SUPPORT)
#define DEFAULT_DEMOD_RESET_GPIO            (GPIO(85)) // ???????????????)	 #define DEFAULT_DEMOD_I2C_BUS_ID				 6
#define DEFAULT_TUNER_I2C_BUS_ID  3
#define DEFAULT_DEMOD_I2C_BUS_ID  3

#else
#define DEFAULT_DEMOD_RESET_GPIO            (GPIO(85)) // ???????????????)	 #define DEFAULT_DEMOD_I2C_BUS_ID				 6
#define DEFAULT_TUNER_I2C_BUS_ID  3
#define DEFAULT_DEMOD_I2C_BUS_ID  3
#endif

//----------------------------------------------------------------------------
// EEPROM customization
//----------------------------------------------------------------------------
#define SYSTEM_EEPROM_SIZE                  (4096)
#define SYSTEM_EEPROM_WP_GPIO               (OPCTRL(7)) // OPCTRL9.
#define SYSTEM_EEPROM_WP_ENABLE_POLARITY    (1)
//#define EDID_EEPROM_WP_GPIO               (GPIO(4))   // GPIO14.
//#define EDID_EEPROM_WP_ENABLE_POLARITY    (1)

//----------------------------------------------------------------------------
// European CI (Common Interface) customization
//----------------------------------------------------------------------------
//#define CI_EXTERNAL_IC_INT_GPIO             (GPIO(84))  // Set:Interrupt Mode, UnSet:Polling Mode
#define CI_5V_OC_GPIO                       (GPIO(46))  // GPIO46
#define CI_5V_POWERON_GPIO                  (GPIO(44))
#define CI_5V_POWERON_POLARITY              (1)
#define CI_5V_OC_POLARITY                   (0)
#define CI_EXTERNAL_IC_DRIVING_CURRENT      (2)         // 2mA
#define CI_SYSTEM_CLOCK                     (72)        // 72 MHz
#define CI_TS_CLOCK                         (108)       // 108 MHz
#define CI_SPI_CLOCK                        (27)        // 72 MHz
//----------------------------------------------------------------------------
// USB Customization
//----------------------------------------------------------------------------
// "USBx_PORT_USING_LOADER & USBx_PORT_USING" related define is only for USB2.0 port
// 1. Loader, USB port using define (1)=used (0)=not used
#define USB0_PORT_USING_LOADER              (1)
#define USB1_PORT_USING_LOADER              (1)
#define USB2_PORT_USING_LOADER              (0)
#define USB3_PORT_USING_LOADER              (0)

// 2. Nuclues/Linux/Android System USB port using define (1)=used (0)=not used
#define USB0_PORT_USING                     (1)
#define USB1_PORT_USING                     (1)
#define USB2_PORT_USING                     (0)
#define USB3_PORT_USING                     (0)

// 3. USB +5V power switch Vbus GPIO control, if vbus not control by GPIO, mark off it.
#define USB0_VBUS_GPIO                      GPIO(42)    // GPIO42.
#define USB0_VBUS_GPIO_POLARITY		        (1)
#define USB1_VBUS_GPIO                      GPIO(43)    // GPIO43
#define USB1_VBUS_GPIO_POLARITY		        (1)
#define USB2_VBUS_GPIO                      GPIO(48)    // GPIO48
#define USB2_VBUS_GPIO_POLARITY		        (1)
#define USB3_VBUS_GPIO                      OPCTRL(10)  // OPCTRL10.
#define USB3_VBUS_GPIO_POLARITY		        (1)

// 4. USB power switch overcurrent GPIO control, if have not ic to control by GPIO, mark off it.
#define USB0_OC_GPIO                        ADIN(4)     // ADIN 4.
#define USB0_OC_GPIO_POLARITY		        (0)
#define USB1_OC_GPIO                        ADIN(4)     // ADIN 4.
#define USB1_OC_GPIO_POLARITY		        (0)
#define USB2_OC_GPIO                        ADIN(5)     // ADIN 5.
#define USB2_OC_GPIO_POLARITY		        (0)
#define USB3_OC_GPIO                        ADIN(5)     // ADIN 5.
#define USB3_OC_GPIO_POLARITY		        (0)

// 5. Detect USB upgrade time, default is 0, but some device maybe can't detect when upgrade.
// If possible, set it to (300)ms when in customer's module.
#define USB_LOADER_WAIT_TIME                (1000)

//#define USB_DISABLE_SUSPEND_MODE /* Disable USB suspend, share 240 Mhz with H.264.*/

//----------------------------------------------------------------------------
// sdcard gpio define
//----------------------------------------------------------------------------
#define MSDC_DETECT_GPIO  GPIO(262)
#define MSDC_VOLTAGE_GPIO GPIO(176)
//----------------------------------------------------------------------------
// Button Customization
//----------------------------------------------------------------------------
#define FLAG_BUTTON_SUPPORT                 (0)

#ifndef T8032UP_INCLUDE_FILE
#define T8032UP_INCLUDE_FILE                "mediatek/mtk_t8032fw.h"
#define T8032UP_OFFSET                      au1T8032FW
#define T8032UP_SIZE                        T8032FW_SIZE
#endif

//----------------------------------------------------------------------------
// MTK IR only setting
//----------------------------------------------------------------------------
#define IR_INCLUDE_FILE                     "mediatek/mtk_ir.h"

#ifndef NPTV_SOURCE_TABLE
#define NPTV_SOURCE_TABLE                   "mediatek/source_table.c"
#endif

//----------------------------------------------------------------------------
// default HDMI GPIO control
//----------------------------------------------------------------------------
#ifndef HDMI_GPIO_CONF
#define HDMI_GPIO_CONF                      "mediatek/hdmi_conf.c"
#endif

/*
 * default VGA table
*/
#ifndef VGA_INCLUDE_FILE
#define VGA_INCLUDE_FILE                    "mediatek/mtk_vga.h"
#endif

//----------------------------------------------------------------------------
// Tcon Customization
//----------------------------------------------------------------------------
// support LVDS and MLVDS both
#define PANEL_DISPLAY_TYPE_ALLOWED_MASK ((1<<PANEL_DISPLAY_TYPE_LVDS) | (1 << PANEL_DISPLAY_TYPE_MLVDS) | (1 << PANEL_DISPLAY_TYPE_EPI) | (1 << PANEL_DISPLAY_TYPE_VB1))

#ifndef TCON_CUST_FILE
#define TCON_CUST_FILE                      "mediatek/Husky_tcon_cust.c"
#endif
#define SUPPORT_LOCK_FROM_SRVAD

//----------------------------------------------------------------------------
// SCART out configuration
//----------------------------------------------------------------------------
#ifndef TVE_INCLUDE_FILE
#define TVE_INCLUDE_FILE                    "mediatek/mtk_tve.c"
#endif

//----------------------------------------------------------------------------
// DMX configuration
//----------------------------------------------------------------------------
#ifndef DMX_INCLUDE_FILE
#define DMX_INCLUDE_FILE                    "mediatek/mtk_dmx.h"
#endif

//----------------------------------------------------------------------------
// Loader configuration
//----------------------------------------------------------------------------
#ifdef CC_USE_256MB_NAND
#define MAX_UPGRADE_IMAGE_FILE_SIZE         (256*1024*1024)     /* 256 MB */
#else
#define MAX_UPGRADE_IMAGE_FILE_SIZE         (512*1024*1024)     /* 512 MB */
#endif

#if defined(LINUX_TURNKEY_SOLUTION) || defined(__KERNEL__)
//----------------------------------------------------------------------------
// Flash Partition configuration
//----------------------------------------------------------------------------
    #ifdef CC_USE_256MB_NAND
        #define NAND_FLASH_TOTAL_SIZE       (256*1024*1024)
    #else
        #define NAND_FLASH_TOTAL_SIZE       (512*1024*1024)
    #endif

    #define PART_RESERV_SIZE                (256*1024)
    #define PART_SDM_BAD_SECTOR_SIZE        (5*1024*1024)

    #ifdef CC_FAST_INIT
        #define FAST_INIT_SUSP_SIZE         (60*1024*1024)
    #else
        #define FAST_INIT_SUSP_SIZE         (PART_RESERV_SIZE)
    #endif

    #define PART_LOADER_SIZE                (2*1024*1024)
    #define PART_UBOOT_ENV_SIZE             (2*1024*1024)
    #define PART_KERNEL_SIZE                (6*1024*1024)

    #ifdef CC_DISABLE_BASIC_PART
        #ifndef CC_MSDC_ENABLE
            #define PART_ROOTFS_SIZE        (35*1024*1024)
        #else
            #ifdef CC_ROOTFS_RW
                #define PART_ROOTFS_SIZE        ((UINT32)200*1024*1024)
            #else
                #define PART_ROOTFS_SIZE        ((UINT32)75*1024*1024)
            #endif
        #endif
        #define PART_BASIC_SIZE             (PART_RESERV_SIZE)
    #else
        #ifndef CC_MSDC_ENABLE
        #define PART_ROOTFS_SIZE            (15*1024*1024)
        #else
            #define PART_ROOTFS_SIZE        (75*1024*1024)
        #endif
        #define PART_BASIC_SIZE             (34*1024*1024)
    #endif

    #define PART_PERM_SIZE                  (16*1024*1024)
    #define PART_CHANNEL_SIZE               (256*1024)
    #define PART_PQ_SIZE                    (256*1024)
    #define PART_AQ_SIZE                    (256*1024)
    #define PART_CAPTURE_LOGO_SIZE          (1*1024*1024)

    #ifdef CI_PLUS_SUPPORT
        #define PART_CI_SIZE                (0x0040000)
    #else
        #define PART_CI_SIZE                (PART_RESERV_SIZE)
    #endif

    #ifdef DEFAULT_DB_SUPPORT
        #define PART_DEFAULT_DB_SIZE        (0x0040000)
    #else
        #define PART_DEFAULT_DB_SIZE        (PART_RESERV_SIZE)
    #endif

    #ifdef ADSP_BIN_SUPPORT
        #define PART_ADSP_SIZE              (3*1024*1024) /* audio dsp size */
    #else
        #define PART_ADSP_SIZE              (PART_RESERV_SIZE)
    #endif

	#ifdef CC_SUPPORT_DOLBY_VISION
		#define PART_DOLBY_PQ_SIZE                   ((UINT64)1024*1024)
	#else
		#define PART_DOLBY_PQ_SIZE					 (PART_RESERV_SIZE)
	#endif    

    #define BDM_NON_3RD_SIZE  \
                            (PART_LOADER_SIZE + PART_UBOOT_ENV_SIZE + \
                             PART_RESERV_SIZE + PART_RESERV_SIZE + \
                             PART_KERNEL_SIZE + PART_KERNEL_SIZE + \
                             PART_ROOTFS_SIZE + PART_ROOTFS_SIZE + \
                             PART_BASIC_SIZE + \
                             PART_PERM_SIZE + \
                             FAST_INIT_SUSP_SIZE)

    #define SDM_TOTAL_SIZE \
                           (PART_CHANNEL_SIZE + PART_CHANNEL_SIZE + \
                            PART_PQ_SIZE + PART_AQ_SIZE + \
                            PART_CI_SIZE + \
                            PART_DEFAULT_DB_SIZE + \
                            PART_ADSP_SIZE + \
                            PART_DOLBY_PQ_SIZE + \
                            PART_SDM_BAD_SECTOR_SIZE)

    #ifdef CC_3RD_RO
        #ifndef CC_MSDC_ENABLE
        #define PART_3RD_RO_SIZE            (0x8700000)                 /* 135MB */
    #else
            #define PART_3RD_RO_SIZE        (0xC000000)                 /* 192MB */
        #endif
    #else
        #define PART_3RD_RO_SIZE            (PART_RESERV_SIZE)
    #endif

    #ifndef CC_MSDC_ENABLE
    #define PART_3RD_RW_SIZE                (NAND_FLASH_TOTAL_SIZE - BDM_NON_3RD_SIZE - SDM_TOTAL_SIZE - PART_3RD_RO_SIZE)
    #else
	    #define PART_3RD_RW_SIZE            (0xC000000)      /* 192MB */
	#endif

    #define NAND_PART_SIZE_0                (PART_LOADER_SIZE)              /* loader image              */
    #define NAND_PART_SIZE_1                (PART_UBOOT_ENV_SIZE)           /* nand_1 - uboot env        */
    #define NAND_PART_SIZE_2                (PART_RESERV_SIZE)              /* nand_2 - reserved         */
    #define NAND_PART_SIZE_3                (PART_RESERV_SIZE)              /* nand_3 - reserved         */
    #define NAND_PART_SIZE_4                (PART_KERNEL_SIZE)              /* nand_4 - kernel A         */
    #define NAND_PART_SIZE_5                (PART_KERNEL_SIZE)              /* nand_5 - kernel B         */
    #define NAND_PART_SIZE_6                (PART_ROOTFS_SIZE)              /* nand_6 - rootfs A         */
    #define NAND_PART_SIZE_7                (PART_ROOTFS_SIZE)              /* nand_7 - rootfs B         */
    #define NAND_PART_SIZE_8                (PART_BASIC_SIZE)               /* nand_8 - basic            */
    #define NAND_PART_SIZE_9                (PART_PERM_SIZE)                /* nand_9 - perm             */
    #define NAND_PART_SIZE_10               (PART_3RD_RO_SIZE)              /* nand_10 - 3rd ro          */
    #define NAND_PART_SIZE_11               (PART_3RD_RW_SIZE)              /* nand_11 - 3rd_rw          */
    #define NAND_PART_SIZE_12               (FAST_INIT_SUSP_SIZE)           /* nand_12 - reserved        */
    #define NAND_PART_SIZE_13               (PART_CHANNEL_SIZE)             /* nand_13 - channel list A  */
    #define NAND_PART_SIZE_14               (PART_CHANNEL_SIZE)             /* nand_14 - channel list B  */
    #define NAND_PART_SIZE_15               (PART_PQ_SIZE)                  /* nand_15 - Flash PQ         */
    #define NAND_PART_SIZE_16               (PART_AQ_SIZE)                  /* nand_16 - Flash AQ         */
    #define NAND_PART_SIZE_17               (PART_CI_SIZE)                  /* nand_17 - ci               */
    #define NAND_PART_SIZE_18               (PART_DEFAULT_DB_SIZE)          /* nand_18 - DVBS default db */
    #define NAND_PART_SIZE_19               (PART_ADSP_SIZE)                /* nand_19 - audio dsp        */
    #define NAND_PART_SIZE_20				        (PART_DOLBY_PQ_SIZE)            /* nand_20 - dolby            */

	#ifdef CC_SUPPORT_DOLBY_VISION
		#define NAND_PART_NAME_20				"dolby"
		#define FLASH_DOLBY_VISION_PARTITION	(20)
	#endif

    #define NAND_FLASH_STATIC_LAST_PART_ID  (12)

    #define NAND_FLASH_STATIC_PART_SIZE \
            ((NAND_PART_SIZE_0) + \
            (NAND_PART_SIZE_1) + (NAND_PART_SIZE_2) + (NAND_PART_SIZE_3) + \
            (NAND_PART_SIZE_4) + (NAND_PART_SIZE_5) + (NAND_PART_SIZE_6) + \
            (NAND_PART_SIZE_7) + (NAND_PART_SIZE_8) + (NAND_PART_SIZE_9) + \
            (NAND_PART_SIZE_10) + (NAND_PART_SIZE_11) + (NAND_PART_SIZE_12))

    #if defined(DEFAULT_DB_SUPPORT)
        #define NAND_PART_NAME_18           "dvbsDB"
    #endif

    #ifdef ADSP_BIN_SUPPORT
        #define NAND_PART_NAME_19           "adsp"
        #define FLASH_ADSP_BIN_PARTITION    (19)
    #endif
    
    #define NAND_PART_NAME_20				        "dolby"
    
    
#endif //defined(LINUX_TURNKEY_SOLUTION) || defined(__KERNEL__)

#if defined(LINUX_TURNKEY_SOLUTION) || defined(__KERNEL__)
#ifdef CC_FBM_MAPPING_ONE_BY_ONE
#ifndef FBM_BOOT_MMAP_INCLUDE_FILE
#define FBM_BOOT_MMAP_INCLUDE_FILE           "mediatek/mtk_fbm_mmap.h"
#endif
#endif
#endif

/*
 * default quality table
*/
#ifndef QTYTBL_INCLUDE_FILE
//#define QTYTBL_INCLUDE_FILE               "mediatek/QTY_DEFAULT/mtk_QtyTbl.h"
#endif


#ifdef SUPPORT_FLASH_PQ
#ifdef LINUX_TURNKEY_SOLUTION
#define FLASH_PQ_BASE_PARTITION             (15)
#endif
#endif // #if SUPPORT_FLASH_PQ

#ifdef SUPPORT_FLASH_AQ
#ifdef LINUX_TURNKEY_SOLUTION
#define FLASH_AQ_BASE_PARTITION             (16)
#endif
#endif // #if SUPPORT_FLASH_AQ

/*
 * default color parameter
*/
#ifndef COLOR_PARAM_INCLUDE_FILE
//#define COLOR_PARAM_INCLUDE_FILE          "mediatek/PANEL_DEFAULT/color_param.h"
#endif

/*
 * dynamic backlight parameter
*/

/*
 * OD setting
*/

#define SUPPORT_OD                          (0)

//for PMIC
#ifdef CC_CUSTOM_PMIC_I2C_SUPPORT
#ifndef SIF_ENABLE_PDWNC_MASTER1
#define SIF_ENABLE_PDWNC_MASTER1      (1)
#endif
#define PMIC_VCPU_DEVICE_ADDR    (0xc8)
#define PMIC_VCPU_DATA_ADDR      (0x05)
#define PMIC_VCPU_MODE_ADDR      (0x06)
#define PMIC_VCPU_MODE_MASK      (0x10)
#define PMIC_VCPU_MODE_PWM_EN    (1)
#define PMIC_VCPU_VMIN           (700) //unit: mV
#define PMIC_VCPU_VMAX           (1500)//unit: mV
#define PMIC_VCPU_VSTEP          (1000)//unit: 10uV
#define PMIC_VCPU_CHANNEL_ID     (4)
#define PMIC_VGPU_DEVICE_ADDR    (0xc8)
#define PMIC_VGPU_DATA_ADDR      (0x04)
#define PMIC_VGPU_MODE_ADDR      (0x06)
#define PMIC_VGPU_MODE_MASK      (0x10)
#define PMIC_VGPU_MODE_PWM_EN    (1)
#define PMIC_VGPU_VMIN           (700) //unit: mV
#define PMIC_VGPU_VMAX           (1500)//unit: mV
#define PMIC_VGPU_VSTEP          (1000)//unit: 10uV
#define PMIC_VGPU_CHANNEL_ID     (4)
#endif

// for CPU temperature settings
#define THERMAL_REBOOT_TEMP     113000  // 113 degree-C
#define THERMAL_TRIGGER_HOT     107000  // 107 degree-C
#define THERMAL_TRIGGER_HOT2NOR  90000  //  90 degree-C
#define THERMAL_TRIGGER_COLD2NOR 85000  //  85 degree-C
#define THERMAL_TRIGGER_COLD     70000  //  70 degree-C

#define THERMAL_CPUFREQ_HOT          (1200000)
#define THERMAL_CPUFREQ_NOR          (1596000)
#define THERMAL_CPUFREQ_COLD         (1800000)

#else /* CONFIG_DEFAULT_H */
#error "Cannot include multi-config files"
#endif /* CONFIG_DEFAULT_H */

