/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _HW_HDMI2P1_SCDC_H_
#define _HW_HDMI2P1_SCDC_H_

#define HDMI21_SCDC_BASE 0x10184000
#define IO_HDMI21_SCDC_BASE (IO_VIRT + HDMI21_SCDC_BASE)

//Page HDMI21_SCDC
#define RX_4D00_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD00)
    #define RX_4D00_HD21_SCDC_P2_REG_DDC_SCDC_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D00_HD21_SCDC_P2_REG_DDC_FILTER_ON Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D00_HD21_SCDC_P2_REG_FILTER_MSB Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D00_HD21_SCDC_P2_REG_CHK_START Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D00_HD21_SCDC_P2_REG_SLEW_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define RX_4D00_HD21_SCDC_P2_REG_MFSR_WRITABLE Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D00_HD21_SCDC_P2_REG_DDC_BUSY Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D00_HD21_SCDC_P2_REG_SCDC_ADDRESS Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4D04_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD04)
    #define RX_4D04_HD21_SCDC_P2_REG_INT_ID0 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4D04_HD21_SCDC_P2_REG_INT_ID1 Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4D08_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD08)
    #define RX_4D08_HD21_SCDC_P2_REG_CPU_ADR_REG Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_4D08_HD21_SCDC_P2_REG_LOAD_ADR_P Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D08_HD21_SCDC_P2_REG_ENWRITE_SCDC Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4D08_HD21_SCDC_P2_REG_SCDC_SRAM_ACCESS Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4D08_HD21_SCDC_P2_REG_EN_SRAM_RD Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4D0C_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD0C)
    #define RX_4D0C_HD21_SCDC_P2_REG_CPU_WDATA_REG Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4D0C_HD21_SCDC_P2_REG_SCDC_DATA_WR_P Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D0C_HD21_SCDC_P2_REG_CPU_WR_BUSY_SCDC Fld(1,9,AC_MSKB1)//[9:9]
#define RX_4D10_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD10)
    #define RX_4D10_HD21_SCDC_P2_REG_SCDC_DATA_PORT_RD Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4D10_HD21_SCDC_P2_REG_SCDC_DATA_RD_P Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D10_HD21_SCDC_P2_REG_CPU_RD_BUSY_SCDC Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D10_HD21_SCDC_P2_REG_SCRAMBLE_STATUS_UPDATE_MODE Fld(1,10,AC_MSKB1)//[10:10]
#define RX_4D14_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD14)
    #define RX_4D14_HD21_SCDC_P2_REG_SCRAMBLING_STATUS_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D14_HD21_SCDC_P2_REG_SCRAMBLING_ONLY Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D14_HD21_SCDC_P2_REG_SCRAMBLING_OV_VALUE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D14_HD21_SCDC_P2_REG_SCRAMBLING_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D14_HD21_SCDC_P2_REG_TMDS_CLK_RATIO_OV_VALUE Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D14_HD21_SCDC_P2_REG_TMDS_CLK_RATIO_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D14_HD21_SCDC_P2_REG_READ_REQUEST_RETRY_PERIOD Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4D18_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD18)
    #define RX_4D18_HD21_SCDC_P2_REG_READ_REQUEST_TIMEOUT Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4D18_HD21_SCDC_P2_REG_READ_REQUEST_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D18_HD21_SCDC_P2_REG_READ_REQUEST_OV_VALUE Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D18_HD21_SCDC_P2_REG_READ_REQUEST_TRIG Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D18_HD21_SCDC_P2_REG_READ_REQUEST_RETRY_EN Fld(1,12,AC_MSKB1)//[12:12]
#define RX_4D1C_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD1C)
    #define RX_4D1C_HD21_SCDC_P2_REG_STATUS_UPDATE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D1C_HD21_SCDC_P2_REG_CED_UPDATE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D1C_HD21_SCDC_P2_REG_RR_TEST Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D1C_HD21_SCDC_P2_REG_C0H_7 Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D1C_HD21_SCDC_P2_REG_CLK_STRETCH_HIT Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D1C_HD21_SCDC_P2_REG_HPD_5V_DB_INT Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D1C_HD21_SCDC_P2_REG_SCDC_INT_START_0 Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D1C_HD21_SCDC_P2_REG_SCDC_INT_START_1 Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D1C_HD21_SCDC_P2_REG_STATUS_UPDATE_CLR Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D1C_HD21_SCDC_P2_REG_CED_UPDATE_CLR Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D1C_HD21_SCDC_P2_REG_RR_TEST_CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D1C_HD21_SCDC_P2_REG_C0H_7_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D1C_HD21_SCDC_P2_REG_CLK_STRETCH_HIT_CLR Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D1C_HD21_SCDC_P2_REG_HPD_5V_DB_INT_CLR Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4D1C_HD21_SCDC_P2_REG_SCDC_INT_START_0_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4D1C_HD21_SCDC_P2_REG_SCDC_INT_START_1_CLR Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4D20_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD20)
    #define RX_4D20_HD21_SCDC_P2_REG_STATUS_UPDATE_FORCE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D20_HD21_SCDC_P2_REG_CED_UPDATE_FORCE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D20_HD21_SCDC_P2_REG_RR_TEST_FORCE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D20_HD21_SCDC_P2_REG_C0H_7_FORCE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D20_HD21_SCDC_P2_REG_CLK_STRETCH_HIT_FORCE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D20_HD21_SCDC_P2_REG_HPD_5V_DB_INT_FORCE Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D20_HD21_SCDC_P2_REG_SCDC_INT_START_0_FORCE Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D20_HD21_SCDC_P2_REG_SCDC_INT_START_1_FORCE Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D20_HD21_SCDC_P2_REG_STATUS_UPDATE_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D20_HD21_SCDC_P2_REG_CED_UPDATE_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D20_HD21_SCDC_P2_REG_RR_TEST_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D20_HD21_SCDC_P2_REG_C0H_7_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D20_HD21_SCDC_P2_REG_CLK_STRETCH_HIT_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D20_HD21_SCDC_P2_REG_HPD_5V_DB_INT_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4D20_HD21_SCDC_P2_REG_SCDC_INT_START_0_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4D20_HD21_SCDC_P2_REG_SCDC_INT_START_1_MASK Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4D24_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD24)
    #define RX_4D24_HD21_SCDC_P2_REG_FAST_READ_ADDRESS Fld(8,0,AC_FULLB0)//[7:0]
#define RX_4D28_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD28)
    #define RX_4D28_HD21_SCDC_P2_REG_CLK_STRETCH_ADDRESS Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4D28_HD21_SCDC_P2_REG_CLK_STRETCH_DATA Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4D2C_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD2C)
    #define RX_4D2C_HD21_SCDC_P2_REG_CLK_STRETCH_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D2C_HD21_SCDC_P2_REG_STRETCH_AUTO_RELEASE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D2C_HD21_SCDC_P2_REG_CLK_STRETCH_CNT Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4D30_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD30)
    #define RX_4D30_HD21_SCDC_P2_REG_SCDC_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D30_HD21_SCDC_P2_REG_HPD_RESET Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_RESET_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_RESET_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_RESET_I Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_RESET_OEN Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_RESET_C Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_LOW_DB Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_HIGH_DB Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_LOW_INT Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_HIGH_INT Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D30_HD21_SCDC_P2_REG_TX_5V_02H_DIS Fld(1,11,AC_MSKB1)//[11:11]
#define RX_4D34_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD34)
    #define RX_4D34_HD21_SCDC_P2_REG_CED_RSED_UPDATE_MODE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D34_HD21_SCDC_P2_REG_ERROR_CNT_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D34_HD21_SCDC_P2_REG_ERROR_CNT_OV_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D34_HD21_SCDC_P2_REG_SCDC_ADR_OUT_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D34_HD21_SCDC_P2_REG_SCDC_READ_INT_SEL1 Fld(2,6,AC_MSKB0)//[7:6]
    #define RX_4D34_HD21_SCDC_P2_REG_SCDC_READ_INT_SEL2 Fld(2,8,AC_MSKB1)//[9:8]
    #define RX_4D34_HD21_SCDC_P2_REG_SCDC_READ_INT_SEL3 Fld(2,10,AC_MSKB1)//[11:10]
    #define RX_4D34_HD21_SCDC_P2_REG_SCDC_READ_INT_SEL4 Fld(2,12,AC_MSKB1)//[13:12]
    #define RX_4D34_HD21_SCDC_P2_REG_SCDC_READ_INT_SEL5 Fld(2,14,AC_MSKB1)//[15:14]
#define RX_4D38_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD38)
    #define RX_4D38_HD21_SCDC_P2_REG_SCDC_READ_OFFSET1 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4D38_HD21_SCDC_P2_REG_SCDC_READ_OFFSET2 Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4D3C_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD3C)
    #define RX_4D3C_HD21_SCDC_P2_REG_SCDC_READ_OFFSET3 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4D3C_HD21_SCDC_P2_REG_SCDC_READ_OFFSET4 Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4D40_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD40)
    #define RX_4D40_HD21_SCDC_P2_REG_TIMER_1US Fld(8,0,AC_FULLB0)//[7:0]
#define RX_4D44_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD44)
    #define RX_4D44_HD21_SCDC_P2_REG_1S_UPDATE_CNT_PERIOD Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_4D44_HD21_SCDC_P2_REG_SCDC_RSED_UPDATE_PULSE_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D44_HD21_SCDC_P2_REG_SCDC_CED_UPDATE_PULSE_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4D44_HD21_SCDC_P2_REG_CED_UPDATE_CNT_PERIOD_OVE Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4D44_HD21_SCDC_P2_REG_RSED_UPDATE_CNT_PERIOD_OVE Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4D48_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD48)
    #define RX_4D48_HD21_SCDC_P2_REG_BUS_FREE_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define RX_4D4C_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD4C)
    #define RX_4D4C_HD21_SCDC_P2_REG_TMDS_CFG_ACCESS Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D4C_HD21_SCDC_P2_REG_FLT_UPDATE_FINAL Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D4C_HD21_SCDC_P2_REG_RSED_UPDATE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D4C_HD21_SCDC_P2_REG_FLT_NO_RETRAIN Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D4C_HD21_SCDC_P2_REG_SOURCE_TEST_UPDATE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D4C_HD21_SCDC_P2_REG_FRL_RATE_CHG Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D4C_HD21_SCDC_P2_REG_SCDC_IRQ_STATUS_EXT_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D4C_HD21_SCDC_P2_REG_FFE_LEVELS_CHG Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D4C_HD21_SCDC_P2_REG_TMDS_CFG_ACCESS_CLR Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D4C_HD21_SCDC_P2_REG_FLT_UPDATE_FINAL_CLR Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D4C_HD21_SCDC_P2_REG_RSED_UPDATE_CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D4C_HD21_SCDC_P2_REG_FLT_NO_RETRAIN_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D4C_HD21_SCDC_P2_REG_SOURCE_TEST_UPDATE_CLR Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D4C_HD21_SCDC_P2_REG_FRL_RATE_CHG_CLR Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4D4C_HD21_SCDC_P2_REG_SCDC_IRQ_STATUS_EXT_6_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4D4C_HD21_SCDC_P2_REG_FFE_LEVELS_CHG_CLR Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4D50_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD50)
    #define RX_4D50_HD21_SCDC_P2_REG_TMDS_CFG_ACCESS_FORCE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D50_HD21_SCDC_P2_REG_FLT_UPDATE_FINAL_FORCE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D50_HD21_SCDC_P2_REG_RSED_UPDATE_FORCE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D50_HD21_SCDC_P2_REG_FLT_NO_RETRAIN_FORCE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D50_HD21_SCDC_P2_REG_SOURCE_TEST_UPDATE_FORCE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D50_HD21_SCDC_P2_REG_FRL_RATE_CHG_FORCE Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D50_HD21_SCDC_P2_REG_SCDC_IRQ_STATUS_EXT_6_FORCE Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D50_HD21_SCDC_P2_REG_FFE_LEVELS_CHG_FORCE Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D50_HD21_SCDC_P2_REG_TMDS_CFG_ACCESS_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D50_HD21_SCDC_P2_REG_FLT_UPDATE_FINAL_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D50_HD21_SCDC_P2_REG_RSED_UPDATE_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D50_HD21_SCDC_P2_REG_FLT_NO_RETRAIN_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D50_HD21_SCDC_P2_REG_SOURCE_TEST_UPDATE_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D50_HD21_SCDC_P2_REG_FRL_RATE_CHG_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4D50_HD21_SCDC_P2_REG_SCDC_IRQ_STATUS_EXT_6_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4D50_HD21_SCDC_P2_REG_FFE_LEVELS_CHG_MASK Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4D58_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD58)
    #define RX_4D58_HD21_SCDC_P2_REG_SCDC_ADR_OUT Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4D58_HD21_SCDC_P2_REG_CH0_ERROR_CNT_VLD Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D58_HD21_SCDC_P2_REG_CH1_ERROR_CNT_VLD Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D58_HD21_SCDC_P2_REG_CH2_ERROR_CNT_VLD Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D58_HD21_SCDC_P2_REG_CH3_ERROR_CNT_VLD Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D58_HD21_SCDC_P2_REG_RS_ERROR_CNT_VLD Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D58_HD21_SCDC_P2_REG_SCDC_FLT_NO_RETRAIN Fld(1,13,AC_MSKB1)//[13:13]
#define RX_4D74_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD74)
    #define RX_4D74_HD21_SCDC_P2_REG_10H_OV_LOCK_STATUS Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D74_HD21_SCDC_P2_REG_10H_OV_CED_UPDATE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D74_HD21_SCDC_P2_REG_10H_OV_RR_TEST Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D74_HD21_SCDC_P2_REG_10H_OV_SOURCE_TEST_UPDATE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D74_HD21_SCDC_P2_REG_10H_OV_FRL_START_ECO Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D74_HD21_SCDC_P2_REG_10H_OV_FLT_UPDATE_FINAL Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D74_HD21_SCDC_P2_REG_10H_OV_RSED_UPDATE_P Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D74_HD21_SCDC_P2_REG_10H_OV_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D74_HD21_SCDC_P2_REG_11H_OV_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D74_HD21_SCDC_P2_REG_11H_OV_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D74_HD21_SCDC_P2_REG_11H_OV_2 Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D74_HD21_SCDC_P2_REG_11H_OV_3 Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D74_HD21_SCDC_P2_REG_11H_OV_4 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D74_HD21_SCDC_P2_REG_11H_OV_5 Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4D74_HD21_SCDC_P2_REG_11H_OV_6 Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4D74_HD21_SCDC_P2_REG_11H_OV_7 Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4D78_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD78)
    #define RX_4D78_HD21_SCDC_P2_REG_40H_OV_CLOCK_DETECTED Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D78_HD21_SCDC_P2_REG_40H_OV_CH0_LN0_LOCKED Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D78_HD21_SCDC_P2_REG_40H_OV_CH1_LN1_LOCKED Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D78_HD21_SCDC_P2_REG_40H_OV_CH2_LN2_LOCKED Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D78_HD21_SCDC_P2_REG_40H_OV_CH3_LN3_LOCKED Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D78_HD21_SCDC_P2_REG_40H_OV_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D78_HD21_SCDC_P2_REG_40H_OV_FLT_READY Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D78_HD21_SCDC_P2_REG_40H_OV_DSC_DECODERFAIL Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D78_HD21_SCDC_P2_REG_41H_OV_LN0_LTP_REQ_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D78_HD21_SCDC_P2_REG_41H_OV_LN0_LTP_REQ_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D78_HD21_SCDC_P2_REG_41H_OV_LN0_LTP_REQ_2 Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D78_HD21_SCDC_P2_REG_41H_OV_LN0_LTP_REQ_3 Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D78_HD21_SCDC_P2_REG_41H_OV_LN1_LTP_REQ_0 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D78_HD21_SCDC_P2_REG_41H_OV_LN1_LTP_REQ_1 Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4D78_HD21_SCDC_P2_REG_41H_OV_LN1_LTP_REQ_2 Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4D78_HD21_SCDC_P2_REG_41H_OV_LN1_LTP_REQ_3 Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4D7C_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD7C)
    #define RX_4D7C_HD21_SCDC_P2_REG_42H_OV_LN2_LTP_REQ_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D7C_HD21_SCDC_P2_REG_42H_OV_LN2_LTP_REQ_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D7C_HD21_SCDC_P2_REG_42H_OV_LN2_LTP_REQ_2 Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D7C_HD21_SCDC_P2_REG_42H_OV_LN2_LTP_REQ_3 Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D7C_HD21_SCDC_P2_REG_42H_OV_LN3_LTP_REQ_0 Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D7C_HD21_SCDC_P2_REG_42H_OV_5_LN3_LTP_REQ_1 Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D7C_HD21_SCDC_P2_REG_42H_OV_6_LN3_LTP_REQ_2 Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D7C_HD21_SCDC_P2_REG_42H_OV_7_LN3_LTP_REQ_3 Fld(1,7,AC_MSKB0)//[7:7]
#define RX_4D80_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD80)
    #define RX_4D80_HD21_SCDC_P2_REG_FRL_RATE_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D80_HD21_SCDC_P2_REG_FFE_LEVELS_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D80_HD21_SCDC_P2_REG_RSC_CNT_OV Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D80_HD21_SCDC_P2_REG_DIS_FLT_UPDATE_TIMER Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D80_HD21_SCDC_P2_REG_DIS_FLT_UPDATE_DIFF Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D80_HD21_SCDC_P2_REG_RR_VLD_RANGE_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D80_HD21_SCDC_P2_REG_RR_TRIG_SEL Fld(1,13,AC_MSKB1)//[13:13]
#define RX_4D84_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD84)
    #define RX_4D84_HD21_SCDC_P2_REG_FRL_RATE_OV_VALUE Fld(4,0,AC_MSKB0)//[3:0]
    #define RX_4D84_HD21_SCDC_P2_REG_FFE_LEVELS_OV_VALUE Fld(4,4,AC_MSKB0)//[7:4]
#define RX_4D8C_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xD8C)
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_STATUS_UPDATE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_CED_UPDATE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_RR_TEST Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_SOURCE_TEST_UPDATE_RISING Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_DSC_FRL_MAX Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_FLT_UPDATE Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_RSED_UPDATE Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_10 Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_11 Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_12 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_13 Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_14 Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4D8C_HD21_SCDC_P2_REG_RR_TRIG_MASK_15 Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4DA0_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xDA0)
    #define RX_4DA0_HD21_SCDC_P2_REG_SCDC_IRQ_NA Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4DA0_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L0 Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4DA0_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L1 Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4DA0_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L2 Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4DA0_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L3 Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4DA0_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_RS Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4DA0_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_RESERVED Fld(2,6,AC_MSKB0)//[7:6]
#define RX_4DA4_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xDA4)
    #define RX_4DA4_HD21_SCDC_P2_REG_SCDC_IRQ_NA_FCE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4DA4_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L0_FCE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4DA4_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L1_FCE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4DA4_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L2_FCE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4DA4_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L3_FCE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4DA4_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_RS_FCE Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4DA4_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_RESERVED_FCE Fld(2,6,AC_MSKB0)//[7:6]
#define RX_4DA8_HD21_SCDC_P2 (IO_HDMI21_SCDC_BASE + 0xDA8)
    #define RX_4DA8_HD21_SCDC_P2_REG_SCDC_IRQ_NA_MSK Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4DA8_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L0_MSK Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4DA8_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L1_MSK Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4DA8_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L2_MSK Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4DA8_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_L3_MSK Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4DA8_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_RS_MSK Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4DA8_HD21_SCDC_P2_REG_SCDC_IRQ_CED_RD_RESERVED_MSK Fld(2,6,AC_MSKB0)//[7:6]
#define RX_4F00_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF00)
    #define RX_4F00_HD21_SCDC_P3_REG_DDC_SCDC_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F00_HD21_SCDC_P3_REG_DDC_FILTER_ON Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F00_HD21_SCDC_P3_REG_FILTER_MSB Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F00_HD21_SCDC_P3_REG_CHK_START Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F00_HD21_SCDC_P3_REG_SLEW_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define RX_4F00_HD21_SCDC_P3_REG_MFSR_WRITABLE Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F00_HD21_SCDC_P3_REG_DDC_BUSY Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F00_HD21_SCDC_P3_REG_SCDC_ADDRESS Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4F04_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF04)
    #define RX_4F04_HD21_SCDC_P3_REG_INT_ID0 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4F04_HD21_SCDC_P3_REG_INT_ID1 Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4F08_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF08)
    #define RX_4F08_HD21_SCDC_P3_REG_CPU_ADR_REG Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_4F08_HD21_SCDC_P3_REG_LOAD_ADR_P Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F08_HD21_SCDC_P3_REG_ENWRITE_SCDC Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4F08_HD21_SCDC_P3_REG_SCDC_SRAM_ACCESS Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4F08_HD21_SCDC_P3_REG_EN_SRAM_RD Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4F0C_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF0C)
    #define RX_4F0C_HD21_SCDC_P3_REG_CPU_WDATA_REG Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4F0C_HD21_SCDC_P3_REG_SCDC_DATA_WR_P Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F0C_HD21_SCDC_P3_REG_CPU_WR_BUSY_SCDC Fld(1,9,AC_MSKB1)//[9:9]
#define RX_4F10_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF10)
    #define RX_4F10_HD21_SCDC_P3_REG_SCDC_DATA_PORT_RD Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4F10_HD21_SCDC_P3_REG_SCDC_DATA_RD_P Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F10_HD21_SCDC_P3_REG_CPU_RD_BUSY_SCDC Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F10_HD21_SCDC_P3_REG_SCRAMBLE_STATUS_UPDATE_MODE Fld(1,10,AC_MSKB1)//[10:10]
#define RX_4F14_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF14)
    #define RX_4F14_HD21_SCDC_P3_REG_SCRAMBLING_STATUS_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F14_HD21_SCDC_P3_REG_SCRAMBLING_ONLY Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F14_HD21_SCDC_P3_REG_SCRAMBLING_OV_VALUE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F14_HD21_SCDC_P3_REG_SCRAMBLING_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F14_HD21_SCDC_P3_REG_TMDS_CLK_RATIO_OV_VALUE Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F14_HD21_SCDC_P3_REG_TMDS_CLK_RATIO_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F14_HD21_SCDC_P3_REG_READ_REQUEST_RETRY_PERIOD Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4F18_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF18)
    #define RX_4F18_HD21_SCDC_P3_REG_READ_REQUEST_TIMEOUT Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4F18_HD21_SCDC_P3_REG_READ_REQUEST_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F18_HD21_SCDC_P3_REG_READ_REQUEST_OV_VALUE Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F18_HD21_SCDC_P3_REG_READ_REQUEST_TRIG Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F18_HD21_SCDC_P3_REG_READ_REQUEST_RETRY_EN Fld(1,12,AC_MSKB1)//[12:12]
#define RX_4F1C_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF1C)
    #define RX_4F1C_HD21_SCDC_P3_REG_STATUS_UPDATE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F1C_HD21_SCDC_P3_REG_CED_UPDATE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F1C_HD21_SCDC_P3_REG_RR_TEST Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F1C_HD21_SCDC_P3_REG_C0H_7 Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F1C_HD21_SCDC_P3_REG_CLK_STRETCH_HIT Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F1C_HD21_SCDC_P3_REG_HPD_5V_DB_INT Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F1C_HD21_SCDC_P3_REG_SCDC_INT_START_0 Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F1C_HD21_SCDC_P3_REG_SCDC_INT_START_1 Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F1C_HD21_SCDC_P3_REG_STATUS_UPDATE_CLR Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F1C_HD21_SCDC_P3_REG_CED_UPDATE_CLR Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F1C_HD21_SCDC_P3_REG_RR_TEST_CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F1C_HD21_SCDC_P3_REG_C0H_7_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F1C_HD21_SCDC_P3_REG_CLK_STRETCH_HIT_CLR Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F1C_HD21_SCDC_P3_REG_HPD_5V_DB_INT_CLR Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4F1C_HD21_SCDC_P3_REG_SCDC_INT_START_0_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4F1C_HD21_SCDC_P3_REG_SCDC_INT_START_1_CLR Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4F20_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF20)
    #define RX_4F20_HD21_SCDC_P3_REG_STATUS_UPDATE_FORCE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F20_HD21_SCDC_P3_REG_CED_UPDATE_FORCE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F20_HD21_SCDC_P3_REG_RR_TEST_FORCE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F20_HD21_SCDC_P3_REG_C0H_7_FORCE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F20_HD21_SCDC_P3_REG_CLK_STRETCH_HIT_FORCE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F20_HD21_SCDC_P3_REG_HPD_5V_DB_INT_FORCE Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F20_HD21_SCDC_P3_REG_SCDC_INT_START_0_FORCE Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F20_HD21_SCDC_P3_REG_SCDC_INT_START_1_FORCE Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F20_HD21_SCDC_P3_REG_STATUS_UPDATE_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F20_HD21_SCDC_P3_REG_CED_UPDATE_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F20_HD21_SCDC_P3_REG_RR_TEST_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F20_HD21_SCDC_P3_REG_C0H_7_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F20_HD21_SCDC_P3_REG_CLK_STRETCH_HIT_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F20_HD21_SCDC_P3_REG_HPD_5V_DB_INT_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4F20_HD21_SCDC_P3_REG_SCDC_INT_START_0_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4F20_HD21_SCDC_P3_REG_SCDC_INT_START_1_MASK Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4F24_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF24)
    #define RX_4F24_HD21_SCDC_P3_REG_FAST_READ_ADDRESS Fld(8,0,AC_FULLB0)//[7:0]
#define RX_4F28_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF28)
    #define RX_4F28_HD21_SCDC_P3_REG_CLK_STRETCH_ADDRESS Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4F28_HD21_SCDC_P3_REG_CLK_STRETCH_DATA Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4F2C_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF2C)
    #define RX_4F2C_HD21_SCDC_P3_REG_CLK_STRETCH_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F2C_HD21_SCDC_P3_REG_STRETCH_AUTO_RELEASE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F2C_HD21_SCDC_P3_REG_CLK_STRETCH_CNT Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4F30_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF30)
    #define RX_4F30_HD21_SCDC_P3_REG_SCDC_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F30_HD21_SCDC_P3_REG_HPD_RESET Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_RESET_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_RESET_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_RESET_I Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_RESET_OEN Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_RESET_C Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_LOW_DB Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_HIGH_DB Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_LOW_INT Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_HIGH_INT Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F30_HD21_SCDC_P3_REG_TX_5V_02H_DIS Fld(1,11,AC_MSKB1)//[11:11]

//Page HDMI21_SCDC_2
#define RX_4F34_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF34)
    #define RX_4F34_HD21_SCDC_P3_REG_CED_RSED_UPDATE_MODE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F34_HD21_SCDC_P3_REG_ERROR_CNT_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F34_HD21_SCDC_P3_REG_ERROR_CNT_OV_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F34_HD21_SCDC_P3_REG_SCDC_ADR_OUT_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F34_HD21_SCDC_P3_REG_SCDC_READ_INT_SEL1 Fld(2,6,AC_MSKB0)//[7:6]
    #define RX_4F34_HD21_SCDC_P3_REG_SCDC_READ_INT_SEL2 Fld(2,8,AC_MSKB1)//[9:8]
    #define RX_4F34_HD21_SCDC_P3_REG_SCDC_READ_INT_SEL3 Fld(2,10,AC_MSKB1)//[11:10]
    #define RX_4F34_HD21_SCDC_P3_REG_SCDC_READ_INT_SEL4 Fld(2,12,AC_MSKB1)//[13:12]
    #define RX_4F34_HD21_SCDC_P3_REG_SCDC_READ_INT_SEL5 Fld(2,14,AC_MSKB1)//[15:14]
#define RX_4F38_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF38)
    #define RX_4F38_HD21_SCDC_P3_REG_SCDC_READ_OFFSET1 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4F38_HD21_SCDC_P3_REG_SCDC_READ_OFFSET2 Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4F3C_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF3C)
    #define RX_4F3C_HD21_SCDC_P3_REG_SCDC_READ_OFFSET3 Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4F3C_HD21_SCDC_P3_REG_SCDC_READ_OFFSET4 Fld(8,8,AC_FULLB1)//[15:8]
#define RX_4F40_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF40)
    #define RX_4F40_HD21_SCDC_P3_REG_TIMER_1US Fld(8,0,AC_FULLB0)//[7:0]
#define RX_4F44_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF44)
    #define RX_4F44_HD21_SCDC_P3_REG_1S_UPDATE_CNT_PERIOD Fld(10,0,AC_MSKW10)//[9:0]
    #define RX_4F44_HD21_SCDC_P3_REG_SCDC_RSED_UPDATE_PULSE_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F44_HD21_SCDC_P3_REG_SCDC_CED_UPDATE_PULSE_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4F44_HD21_SCDC_P3_REG_CED_UPDATE_CNT_PERIOD_OVE Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4F44_HD21_SCDC_P3_REG_RSED_UPDATE_CNT_PERIOD_OVE Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4F48_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF48)
    #define RX_4F48_HD21_SCDC_P3_REG_BUS_FREE_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define RX_4F4C_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF4C)
    #define RX_4F4C_HD21_SCDC_P3_REG_TMDS_CFG_ACCESS Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F4C_HD21_SCDC_P3_REG_FLT_UPDATE_FINAL Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F4C_HD21_SCDC_P3_REG_RSED_UPDATE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F4C_HD21_SCDC_P3_REG_FLT_NO_RETRAIN Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F4C_HD21_SCDC_P3_REG_SOURCE_TEST_UPDATE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F4C_HD21_SCDC_P3_REG_FRL_RATE_CHG Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F4C_HD21_SCDC_P3_REG_SCDC_IRQ_STATUS_EXT_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F4C_HD21_SCDC_P3_REG_FFE_LEVELS_CHG Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F4C_HD21_SCDC_P3_REG_TMDS_CFG_ACCESS_CLR Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F4C_HD21_SCDC_P3_REG_FLT_UPDATE_FINAL_CLR Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F4C_HD21_SCDC_P3_REG_RSED_UPDATE_CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F4C_HD21_SCDC_P3_REG_FLT_NO_RETRAIN_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F4C_HD21_SCDC_P3_REG_SOURCE_TEST_UPDATE_CLR Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F4C_HD21_SCDC_P3_REG_FRL_RATE_CHG_CLR Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4F4C_HD21_SCDC_P3_REG_SCDC_IRQ_STATUS_EXT_6_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4F4C_HD21_SCDC_P3_REG_FFE_LEVELS_CHG_CLR Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4F50_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF50)
    #define RX_4F50_HD21_SCDC_P3_REG_TMDS_CFG_ACCESS_FORCE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F50_HD21_SCDC_P3_REG_FLT_UPDATE_FINAL_FORCE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F50_HD21_SCDC_P3_REG_RSED_UPDATE_FORCE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F50_HD21_SCDC_P3_REG_FLT_NO_RETRAIN_FORCE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F50_HD21_SCDC_P3_REG_SOURCE_TEST_UPDATE_FORCE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F50_HD21_SCDC_P3_REG_FRL_RATE_CHG_FORCE Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F50_HD21_SCDC_P3_REG_SCDC_IRQ_STATUS_EXT_6_FORCE Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F50_HD21_SCDC_P3_REG_FFE_LEVELS_CHG_FORCE Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F50_HD21_SCDC_P3_REG_TMDS_CFG_ACCESS_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F50_HD21_SCDC_P3_REG_FLT_UPDATE_FINAL_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F50_HD21_SCDC_P3_REG_RSED_UPDATE_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F50_HD21_SCDC_P3_REG_FLT_NO_RETRAIN_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F50_HD21_SCDC_P3_REG_SOURCE_TEST_UPDATE_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F50_HD21_SCDC_P3_REG_FRL_RATE_CHG_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4F50_HD21_SCDC_P3_REG_SCDC_IRQ_STATUS_EXT_6_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4F50_HD21_SCDC_P3_REG_FFE_LEVELS_CHG_MASK Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4F58_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF58)
    #define RX_4F58_HD21_SCDC_P3_REG_SCDC_ADR_OUT Fld(8,0,AC_FULLB0)//[7:0]
    #define RX_4F58_HD21_SCDC_P3_REG_CH0_ERROR_CNT_VLD Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F58_HD21_SCDC_P3_REG_CH1_ERROR_CNT_VLD Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F58_HD21_SCDC_P3_REG_CH2_ERROR_CNT_VLD Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F58_HD21_SCDC_P3_REG_CH3_ERROR_CNT_VLD Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F58_HD21_SCDC_P3_REG_RS_ERROR_CNT_VLD Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F58_HD21_SCDC_P3_REG_SCDC_FLT_NO_RETRAIN Fld(1,13,AC_MSKB1)//[13:13]
#define RX_4F74_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF74)
    #define RX_4F74_HD21_SCDC_P3_REG_10H_OV_LOCK_STATUS Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F74_HD21_SCDC_P3_REG_10H_OV_CED_UPDATE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F74_HD21_SCDC_P3_REG_10H_OV_RR_TEST Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F74_HD21_SCDC_P3_REG_10H_OV_SOURCE_TEST_UPDATE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F74_HD21_SCDC_P3_REG_10H_OV_FRL_START_ECO Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F74_HD21_SCDC_P3_REG_10H_OV_FLT_UPDATE_FINAL Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F74_HD21_SCDC_P3_REG_10H_OV_RSED_UPDATE_P Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F74_HD21_SCDC_P3_REG_10H_OV_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F74_HD21_SCDC_P3_REG_11H_OV_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F74_HD21_SCDC_P3_REG_11H_OV_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F74_HD21_SCDC_P3_REG_11H_OV_2 Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F74_HD21_SCDC_P3_REG_11H_OV_3 Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F74_HD21_SCDC_P3_REG_11H_OV_4 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F74_HD21_SCDC_P3_REG_11H_OV_5 Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4F74_HD21_SCDC_P3_REG_11H_OV_6 Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4F74_HD21_SCDC_P3_REG_11H_OV_7 Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4F78_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF78)
    #define RX_4F78_HD21_SCDC_P3_REG_40H_OV_CLOCK_DETECTED Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F78_HD21_SCDC_P3_REG_40H_OV_CH0_LN0_LOCKED Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F78_HD21_SCDC_P3_REG_40H_OV_CH1_LN1_LOCKED Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F78_HD21_SCDC_P3_REG_40H_OV_CH2_LN2_LOCKED Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F78_HD21_SCDC_P3_REG_40H_OV_CH3_LN3_LOCKED Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F78_HD21_SCDC_P3_REG_40H_OV_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F78_HD21_SCDC_P3_REG_40H_OV_FLT_READY Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F78_HD21_SCDC_P3_REG_40H_OV_DSC_DECODERFAIL Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F78_HD21_SCDC_P3_REG_41H_OV_LN0_LTP_REQ_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F78_HD21_SCDC_P3_REG_41H_OV_LN0_LTP_REQ_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F78_HD21_SCDC_P3_REG_41H_OV_LN0_LTP_REQ_2 Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F78_HD21_SCDC_P3_REG_41H_OV_LN0_LTP_REQ_3 Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F78_HD21_SCDC_P3_REG_41H_OV_LN1_LTP_REQ_0 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F78_HD21_SCDC_P3_REG_41H_OV_LN1_LTP_REQ_1 Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4F78_HD21_SCDC_P3_REG_41H_OV_LN1_LTP_REQ_2 Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4F78_HD21_SCDC_P3_REG_41H_OV_LN1_LTP_REQ_3 Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4F7C_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF7C)
    #define RX_4F7C_HD21_SCDC_P3_REG_42H_OV_LN2_LTP_REQ_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F7C_HD21_SCDC_P3_REG_42H_OV_LN2_LTP_REQ_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F7C_HD21_SCDC_P3_REG_42H_OV_LN2_LTP_REQ_2 Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F7C_HD21_SCDC_P3_REG_42H_OV_LN2_LTP_REQ_3 Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F7C_HD21_SCDC_P3_REG_42H_OV_LN3_LTP_REQ_0 Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F7C_HD21_SCDC_P3_REG_42H_OV_5_LN3_LTP_REQ_1 Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F7C_HD21_SCDC_P3_REG_42H_OV_6_LN3_LTP_REQ_2 Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F7C_HD21_SCDC_P3_REG_42H_OV_7_LN3_LTP_REQ_3 Fld(1,7,AC_MSKB0)//[7:7]
#define RX_4F80_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF80)
    #define RX_4F80_HD21_SCDC_P3_REG_FRL_RATE_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F80_HD21_SCDC_P3_REG_FFE_LEVELS_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F80_HD21_SCDC_P3_REG_RSC_CNT_OV Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F80_HD21_SCDC_P3_REG_DIS_FLT_UPDATE_TIMER Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F80_HD21_SCDC_P3_REG_DIS_FLT_UPDATE_DIFF Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F80_HD21_SCDC_P3_REG_RR_VLD_RANGE_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F80_HD21_SCDC_P3_REG_RR_TRIG_SEL Fld(1,13,AC_MSKB1)//[13:13]
#define RX_4F84_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF84)
    #define RX_4F84_HD21_SCDC_P3_REG_FRL_RATE_OV_VALUE Fld(4,0,AC_MSKB0)//[3:0]
    #define RX_4F84_HD21_SCDC_P3_REG_FFE_LEVELS_OV_VALUE Fld(4,4,AC_MSKB0)//[7:4]
#define RX_4F8C_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xF8C)
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_STATUS_UPDATE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_CED_UPDATE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_RR_TEST Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_SOURCE_TEST_UPDATE_RISING Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_DSC_FRL_MAX Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_FLT_UPDATE Fld(1,8,AC_MSKB1)//[8:8]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_RSED_UPDATE Fld(1,9,AC_MSKB1)//[9:9]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_10 Fld(1,10,AC_MSKB1)//[10:10]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_11 Fld(1,11,AC_MSKB1)//[11:11]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_12 Fld(1,12,AC_MSKB1)//[12:12]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_13 Fld(1,13,AC_MSKB1)//[13:13]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_14 Fld(1,14,AC_MSKB1)//[14:14]
    #define RX_4F8C_HD21_SCDC_P3_REG_RR_TRIG_MASK_15 Fld(1,15,AC_MSKB1)//[15:15]
#define RX_4FA0_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xFA0)
    #define RX_4FA0_HD21_SCDC_P3_REG_SCDC_IRQ_NA Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4FA0_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L0 Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4FA0_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L1 Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4FA0_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L2 Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4FA0_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L3 Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4FA0_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_RS Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4FA0_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_RESERVED Fld(2,6,AC_MSKB0)//[7:6]
#define RX_4FA4_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xFA4)
    #define RX_4FA4_HD21_SCDC_P3_REG_SCDC_IRQ_NA_FCE Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4FA4_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L0_FCE Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4FA4_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L1_FCE Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4FA4_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L2_FCE Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4FA4_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L3_FCE Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4FA4_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_RS_FCE Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4FA4_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_RESERVED_FCE Fld(2,6,AC_MSKB0)//[7:6]
#define RX_4FA8_HD21_SCDC_P3 (IO_HDMI21_SCDC_BASE + 0xFA8)
    #define RX_4FA8_HD21_SCDC_P3_REG_SCDC_IRQ_NA_MSK Fld(1,0,AC_MSKB0)//[0:0]
    #define RX_4FA8_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L0_MSK Fld(1,1,AC_MSKB0)//[1:1]
    #define RX_4FA8_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L1_MSK Fld(1,2,AC_MSKB0)//[2:2]
    #define RX_4FA8_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L2_MSK Fld(1,3,AC_MSKB0)//[3:3]
    #define RX_4FA8_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_L3_MSK Fld(1,4,AC_MSKB0)//[4:4]
    #define RX_4FA8_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_RS_MSK Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_4FA8_HD21_SCDC_P3_REG_SCDC_IRQ_CED_RD_RESERVED_MSK Fld(2,6,AC_MSKB0)//[7:6]

#endif //#ifndef _HW_HDMI2P1_SCDC_H_

