/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef __X_CM4_REG_H__
#define __X_CM4_REG_H__

#include "x_hal_reg.h"

#ifndef BIT
#define BIT(x) (1 << x)
#endif

/*
 * This should be synced with
 * cm4/cm4_base/peripheral_library/hal/mt5895/inc/mt_reg.h
 */

/* Reserve 32K for preloader */
#define CMSYS_RESREVE_SIZE               IO_VIRT_PDWNC_RESERVED
#define CMSYS_SRAM_SIZE                  0x40000
#define CMSYS_ENTRY_LEN                  0x6
#define CMSYS_SRAM_TOTAL_SIZE            (CMSYS_SRAM_SIZE * CMSYS_ENTRY_LEN - CMSYS_RESREVE_SIZE)
/* header size is a largest acceptable value */
#define CMSYS_BIN_HEADER_SIZE            0x100
#define CMSYS_BIN_SIZE                   (CMSYS_SRAM_TOTAL_SIZE + CMSYS_BIN_HEADER_SIZE)
#define CMSYS_SRAM0_BASE                 (IO_VIRT_PDWNC_SRAM)
#define CMSYS_SRAM1_BASE                 (IO_VIRT_PDWNC_SRAM + 0x40000)
#define CMSYS_SRAM2_BASE                 (IO_VIRT_PDWNC_SRAM + 0x80000)
#define CMSYS_SRAM3_BASE                 (IO_VIRT_PDWNC_SRAM + 0xc0000)
#define CMSYS_SRAM4_BASE                 (IO_VIRT_PDWNC_SRAM + 0x100000)
#define CMSYS_SRAM5_BASE                 (IO_VIRT_PDWNC_SRAM + 0x140000)

#define CMSYS_SRAM_POISION               (0xdeadbeef)

#define CMSYS_LOAD_ADDR                  (CMSYS_SRAM0_BASE)

#define CMSYS_REG_RESET_CTL              (0x0 + CM4_CONFIG_BASE)
#define CMSYS_BIT_RESET_CPU_RST_SW       BIT(0)
#define CMSYS_BIT_RESET_BUS_RST_SW       BIT(1)
#define CMSYS_BIT_RESET_HBUS_RST_SW      BIT(2)
#define CMSYS_BIT_RESET_CPU_RST          BIT(4)
#define CMSYS_BIT_RESET_BUS_RST          BIT(5)
#define CMSYS_BIT_RESET_HBUS_RST         BIT(6)
#define CMSYS_BIT_RESET_CPU_WDT_RSTEN    BIT(8)
#define CMSYS_BIT_RESET_BUS_WDT_RSTEN    BIT(9)
#define CMSYS_BIT_RESET_HBUS_WDT_RSTEN   BIT(10)
#define CMSYS_BIT_RESET_CM4_SLP          BIT(12)
#define CMSYS_BIT_RESET_CM4_SLPDP        BIT(13)

#define CMSYS_REG_CLOCK_CTL              (0x8 + CM4_CONFIG_BASE)
#define CMSYS_REG_DEBUG_CTL              (0xc + CM4_CONFIG_BASE)
#define CMSYS_BIT_DEBUG_DBGEN            BIT(0)
#define CMSYS_BIT_DEBUG_IRQEN            BIT(4)
#define CMSYS_BIT_DEBUG_IRQSEL           BIT(5)


#define CMSYS_REG_EVENT_CTL              (0x10 + CM4_CONFIG_BASE)
#define CMSYS_BIT_EVENT_CM2SPM_EVENT     BIT(0)
#define CMSYS_BIT_EVENT_CM2AP_IRQ        BIT(1)
#define CMSYS_BIT_EVENT_SWIRQ0           BIT(2)
#define CMSYS_BIT_EVENT_SWIRQ1           BIT(4)
#define CMSYS_BIT_EVENT_SWIRQ2           BIT(5)
#define CMSYS_BIT_EVENT_NMIIRQ           BIT(6)


#define CMSYS_REG_IRQ_CTL                (0x14 + CM4_CONFIG_BASE)
#define CMSYS_BIT_IRQ_CM2SPM_EVT_CLR     BIT(0)
#define CMSYS_BIT_IRQ_CM2AP_IRQ_CLR      BIT(1)
#define CMSYS_BIT_IRQ_SWIRQ0_CLR         BIT(2)
#define CMSYS_BIT_IRQ_SWIRQ1_CLR         BIT(4)
#define CMSYS_BIT_IRQ_SWIRQ2_CLR         BIT(5)
#define CMSYS_BIT_IRQ_NMIIRQ_CLR         BIT(6)


#define CMSYS_REG_POL0_CTL               (0x18 + CM4_CONFIG_BASE)
#define CMSYS_REG_POL1_CTL               (0x1c + CM4_CONFIG_BASE)
#define CMSYS_REG_POL2_CTL               (0x20 + CM4_CONFIG_BASE)
#define CMSYS_REG_POL3_CTL               (0x24 + CM4_CONFIG_BASE)
#define CMSYS_REG_POL4_CTL               (0x28 + CM4_CONFIG_BASE)
#define CMSYS_REG_POL5_CTL               (0x2c + CM4_CONFIG_BASE)
#define CMSYS_REG_POL6_CTL               (0x30 + CM4_CONFIG_BASE)
#define CMSYS_REG_POL7_CTL               (0x34 + CM4_CONFIG_BASE)

#define CMSYS_REG_SEMA0                  (0x38 + CM4_CONFIG_BASE)
#define CMSYS_REG_SEMA1                  (0x3c + CM4_CONFIG_BASE)

#define CMSYS_REG_SYSTICK_CTL            (0x40 + CM4_CONFIG_BASE)
#define CMSYS_REG_CONFIG                 (0x44 + CM4_CONFIG_BASE)

#define CMSYS_REG_GPR0                   (0x48 + CM4_CONFIG_BASE)
#define CMSYS_REG_GPR1                   (0x4c + CM4_CONFIG_BASE)

#define CMSYS_REG_WDT_CTL                (0x50 + CM4_CONFIG_BASE)
#define CMSYS_BITS_WDT_SET               BITS(0, 19)
#define CMSYS_BIT_WDT_EN                 BIT(20)
#define CMSYS_BIT_WDT_RESTART            BIT(21)
#define CMSYS_BIT_WDT_FLAG               BIT(22)
#define CMSYS_BIT_WDT_SYSRSTREQ_EN       BIT(24)
#define CMSYS_BIT_WDT_LOCKUP             BIT(25)
#define CMSYS_BIT_WDT_SYSRSTREQ          BIT(26)
#define CMSYS_BIT_WDT_SYSRST_CLR         BIT(27)

#define CMSYS_REG_TIMER_CTL              (0x54 + CM4_CONFIG_BASE)
#define CMSYS_REG_TIMER_SET              (0x58 + CM4_CONFIG_BASE)
#define CMSYS_REG_TIMER_COUNT            (0x5c + CM4_CONFIG_BASE)
#define CMSYS_VAL_TIMER_COUNT_MAX        0xffffffff

#define CMSYS_BIT_TIMER_TMEN             BIT(0)
#define CMSYS_BIT_TIMER_TMRLD            BIT(1)
#define CMSYS_BIT_TIMER_TMIRQEN          BIT(4)
#define CMSYS_BIT_TIMER_TMIRQ            BIT(5)
#define CMSYS_BIT_TIMER_TMIRQCLR         BIT(8)
#define CMSYS_VAL_TIMER_RSTVAL           0xffffffff


#define CMSYS_REG_SHARE0                 (0x60 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE1                 (0x64 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE2                 (0x68 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE3                 (0x6c + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE4                 (0x70 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE5                 (0x74 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE6                 (0x78 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE7                 (0x7c + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE9                 (0x84 + CM4_CONFIG_BASE)// for vq version transfer
#define CMSYS_REG_SHARE11                (0x8c + CM4_CONFIG_BASE)
/* 10 is uesd at cm4 init time, don't use this */
#define CMSYS_REG_SHARE10                (0x88 + CM4_CONFIG_BASE)
/* 8, 12 ~ 15 are used by irq arg, DO NOT touch them */
#define CMSYS_REG_SHARE8                 (0x80 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE12                (0x90 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE13                (0x94 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE14                (0x98 + CM4_CONFIG_BASE)
#define CMSYS_REG_SHARE15                (0x9c + CM4_CONFIG_BASE)

#define CMSYS_REG_MBIST                  (0xa0 + CM4_CONFIG_BASE)
#define CMSYS_REG_VAD_CTL                (0xd0 + CM4_CONFIG_BASE)

#define CMSYS_REG_VERSION                CMSYS_REG_SHARE10

#define CMSYS_REG_PWR_CTL                (0x4494 + CM4_CONFIG_BASE)
#define CMSYS_BIT_PWR_ON                 BIT(0)
#define CMSYS_BIT_PWR_ON_S               BIT(1)
#define CMSYS_BIT_PWR_ISO_EN             BIT(2)
#define CMSYS_BIT_PWR_ACK                BIT(3)
#define CMSYS_BIT_PWR_ACK_S              BIT(4)

#define CMSYS_REG_CLK_CTL                (0x402c + CM4_CONFIG_BASE)
#define CMSYS_REG_SRAM_PD1               (0x4940 + CM4_CONFIG_BASE)
#define CMSYS_REG_SRAM_PD2               (0x4944 + CM4_CONFIG_BASE)
#define CMSYS_REG_PWR_RST                (0x4018 + CM4_CONFIG_BASE)

#define APDMA_REG_EN                     (IO_VIRT + 0x7084)
#define APDMA_REG_SRC_ADDR               (IO_VIRT + 0x709c)
#define APDMA_REG_DST_ADDR               (IO_VIRT + 0x70a0)
#define APDMA_REG_LEN                    (IO_VIRT + 0x70a4)
#define APDMA_REG_INT_EN                 (IO_VIRT + 0x7088)
#define APDMA_REG_INT_FLAG               (IO_VIRT + 0x7080)

#define CMSYS_CMSYS2AP_INT_STA           19
#define CMSYS_EVENT_STA                  10

#endif
