/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


/*****************************************************************************
 *
 * Filename:
 * ---------
 *   $Workfile: ether_priv.h $
 *
 * Project:
 * --------
 *
 *
 * Description:
 * ------------
 *   Ethernet private structure header file
 *
 * Author:
 * -------
 *   HsHuang
 *
 * Last changed:
 * -------------
 * $Author:
 *
 * $Modtime:
 *
 * $Revision:
****************************************************************************/

#ifndef _ETHER_PRIV_H_
#define _ETHER_PRIV_H_

/****************************************************************************
** Config definitions
****************************************************************************/
#define CONFIG_ETHER_TX_INT_MODE    0   /* wait event from irq service for transmission */
#define CONFIG_ETHER_CRC_NORMAL     1   /* apply normal poly parameter for CRC calculation */
#define CONFIG_ETHER_DRV_RW_MAC     0   /* r/w MAC address in flash at driver layer */
#define CONFIG_ETHER_USE_OS_NATIVE  0   /* apply OS native APIs */
#define CONFIG_ETHER_TX_NO_COPY     1   /* no packet copy for tx */
#define CONFIG_ETHER_HW_CHKSUM      0   /* apply hw to calculate checksum,need to set HW_CHKSUM_ON_THE_FLY 1 in chksum.h*/
#define CONFIG_ETHER_USE_SAM_INSTEAD_EV  0   /* use sam insteand of event*/
#define ENABLE_REALTIME_THROUGHPUT_COUNT 0
#define SLT_TEST_ETHERNET_EN  0     
//*********************************************************************
// MAC RX Descriptors
//*********************************************************************
#define OWNED_BY_DMA	0
#define OWNED_BY_CPU	1

typedef union MacRxDescControl
{
        UINT32 u4Val;
        struct
        {
	    UINT32   u2BufSize      		: 16;   	// Buffer size
	    UINT32   fgL4ChecksumErr   		: 1;    	// TCP/UDP checksum error 
	    UINT32   fgIPChecksumErr   		: 1;    	// IP checksum error 
	    UINT32   u1ProtocolSel   		: 2;    	// Protocol select IP/TCP/UPD checksum select
	    UINT32   fgVlanPacket        	: 1;    	// indicate VLAN tag packet  
	    UINT32   fgMyMacAddr  			: 1;   		// Receive packet match My MAC addr.
	    UINT32   fgHitHash       		: 1;    	// Receive packet hit hash table
	    UINT32   fgRsvMultiAddr   		: 1;    	// Receive packet is reserved multicast addr.
	    UINT32   fgCrcErr          		: 1;   		// Receive packet is CRC error
	    UINT32   fgOversizeErr       	: 1;    	// Receive packet is oversize error.  
	    UINT32   u1Reserved       		: 2;    	// Reserved
	    UINT32   fgLastSeg          	: 1;   		// Rx - Last segment of the frame 
	    UINT32   fgFirstSeg           	: 1;    	// Rx - First segment of the frame  
	    UINT32   fgEndOfRing            : 1;    	// End of descriptors ring   
	    UINT32   fgOwn           		: 1;    	// Descriptor is owned by CPU engine   
        }Bits;
} MAC_RX_DESC_CTRL_T, *PMAC_RX_DESC_CTRL_T;

typedef struct MacRxDescVLAN
{
    UINT32   u2VlanID     		: 12;   	// VLAN tag ID
    UINT32   fgCFI    			: 1;   		// VLAN tag CFI  
    UINT32   u1Priority        	: 3;    	// VLAN tag priority
    UINT32   u2EPID       		: 16;    	// VLAN tag EPID
} MAC_RX_DESC_VLAN_T, *PMAC_RX_DESC_VLAN_T;

typedef struct MacRxDescriptor
{
//#ifdef CC_MT5399
#if defined(CC_MT5890) || defined(CC_MT5891)
    MAC_RX_DESC_CTRL_T  	rRxCtrl;   
    UINT32   u4BufAddr;     
#else
    UINT32   u4BufAddr; 
    MAC_RX_DESC_CTRL_T  	rRxCtrl;   
#endif    
    MAC_RX_DESC_VLAN_T   rRxVlan;                 
    UINT32   u4Reserved;                     
} MAC_RX_DESC_T, *PMAC_RX_DESC_T;

//*********************************************************************
// MAC TX Descriptors
//*********************************************************************
typedef union MacTxDescControl
{
        UINT32 u4Val;
        struct
        {
	    UINT32   u2BufSize      		: 16;   	// Buffer size
	    UINT32   u1Reserved    			: 6;   		// Reserved   
	    UINT32   fgVTG        			: 1;    	// Tx packet is VLAN tagged
	    UINT32   fgTCO       			: 1;    	// TCP checksum generation offload
	    UINT32   fgUCO         			: 1;    	// UDP checksum generation offload   
	    UINT32   fgICO         			: 1;   		// IP checksum generation offload
	    UINT32   fgINSV         		: 1;    	// insert VLAN tag
	    UINT32   fgTxIntOn       		: 1;    	// interrupt enable after sending out packet
	    UINT32   fgLastSeg          	: 1;   		// Tx - Last segment of the frame 
	    UINT32   fgFirstSeg           	: 1;    	// Tx - First segment of the frame  
	    UINT32   fgEndOfRing            : 1;    	// End of descriptors ring   
	    UINT32   fgOwn           		: 1;    	// Descriptor is owned by CPU engine   
        }Bits;
} MAC_TX_DESC_CTRL_T, *PMAC_TX_DESC_CTRL_T;

typedef struct MacTxDescVLAN
{
    UINT32   u2VlanID     		: 12;   	// VLAN tag ID
    UINT32   fgCFI    			: 1;   		// VLAN tag CFI  
    UINT32   u1Priority        	: 3;    	// VLAN tag priority
    UINT32   u2EPID       		: 16;    	// VLAN tag EPID
} MAC_TX_DESC_VLAN_T, *PMAC_TX_DESC_VLAN_T;

typedef struct MacTxDescriptor
{
//#ifdef CC_MT5399
#if defined(CC_MT5890) || defined(CC_MT5891)
    MAC_TX_DESC_CTRL_T 	rTxCtrl;    
    UINT32   u4BufAddr;  
#else	
    UINT32   u4BufAddr;  
    MAC_TX_DESC_CTRL_T 	rTxCtrl;    
#endif    
    MAC_TX_DESC_VLAN_T   rTxVlan;               
    UINT32   u4Reserved;           
} MAC_TX_DESC_T, *PMAC_TX_DESC_T;


/* Ethernet rx packet list structure */
typedef struct _ETHER_RX_LIST_T_
{
    UINT8                       *pucPktBuf;
    struct _ETHER_RX_LIST_T_    *prNext;
} ETHER_RX_LIST_T;

/* Ethernet tx packet list structure */
typedef struct _ETHER_TX_LIST_T_
{
    PKT_BUFF_T                  *prPktBuf;
    struct _ETHER_TX_LIST_T_    *prNext;
} ETHER_TX_LIST_T;


//*********************************************************************
// MAC TX/RX statistics 
//*********************************************************************
typedef struct MacTxRxStat
{
    UINT64 u8RxFrame;                  // number of received frame
    UINT64 u8RxOctet;                  // number of received octet
    UINT64 u8RxPreOctet;               // number of previous received octet
    UINT32 u4RxThroughput;			   // Rx current thourghput(octec/sec)(u8RxOctet - u8RxPreOctet)
    UINT32 u4RxFrameSrv;               // number of received frame can be serviced each time
    UINT32 u4RxOctetSrv;               // number of received octet can be serviced each time
    UINT32 u4RxDrop;                   // Dropped packets
    UINT32 u4RxErr;                    // Total RX error count
    UINT32 u4RxCrcErr;                 // CRC error count 
    UINT32 u4RxLateColErr;             // Late collision error count 
    UINT32 u4RxLenErr;                 // Length error count
    UINT32 u4RxOverErr;                // Overflow error count
    UINT32 u4RxDribErr;                // Dribbled error count

    UINT32 u4TxFrame;                  // number of transmitted frame
    UINT32 u4TxOctet;                  // number of transmitted octet
    UINT32 u4TxFrameSrv;               // number of tx frame can be serviced each time
    UINT32 u4TxOctetSrv;               // number of tx octet can be serviced each time
    UINT32 u4TxErr;                    // Total TX error count
    UINT32 u4TxColCnt;                 // Collision count
    UINT32 u4TxCarErr;                 // No and lost carrier error count
    UINT32 u4TxExcessDefer;            // Excessive deferral of over 24288 bit time
    UINT32 u4TxExcessColErr;           // Tx excessive collision error count
    UINT32 u4TxLateColErr;             // Tx late collision error count
} MAC_STAT_T, *PMAC_STAT_T;


//*********************************************************************
// MAC MII status  
//*********************************************************************
typedef struct MacMiiStatus
{
    UINT32   fgFullDup           : 1;    // Fill duplex or half duplex
    UINT32   fgSpeed1000         : 1;    // 1000Mbit speed or not, reserved
    UINT32   fgSpeed100          : 1;    // 100 or 10 Mbit speed
    UINT32   fgLinkUp            : 1;    // Link ip or link off
    UINT32   fgLpNwAble          : 1;    // Link partner support auto-negotiation
} MAC_MII_T, *PMAC_MII_T;


typedef struct MacAddr
{
    MAC_ADDRESS_T   rMacAddr;            // MAC address
    BOOL            fgValidInFlash;      // MAC in flash is valid or not
} MAC_ADDR_T;


typedef struct EthBitRate
{
    UINT32      u4RxBitRate;        /* Ethernet driver rx bit rate */
    UINT32      u4PrevRxOctet;      /* Previous number of bytes received */
    UINT32      u4TxBitRate;        /* Ethernet driver tx bit rate */
    UINT32      u4PrevTxOctet;      /* Previous number of bytes transmitted */
    HAL_TIME_T  rTime_Start;
    HAL_TIME_T  rTime_End;
    HAL_TIME_T  rTime_Delta;
} ETH_BIT_RATE_T;


//*********************************************************************
// Ethernet MAC Struct
//*********************************************************************
typedef struct MacStruct
{
    /* tx related parameters */
    UINT32 u4TxIdx;                 /* TX descriptors index */
    UINT32 u4TxCompIdx;             /* Index of tx descriptor that is sent completed */
    UINT32 *pu4TxDescBuf;           /* TX descriptors buffer address */
    UINT32 *pu4TxPktList;           /* TX packet list memory address */
    LIST_HEAD_T rTxPktList;         /* TX descriptor list */
    //HANDLE_T        hTxListSema;  /* TX list semaphore handler */
    PMAC_TX_DESC_T  prTxDesc;       /* TX descriptor struct */
	
    /* rx related parameters */
    UINT32 u4RxIdx;                 /* RX descriptors index */
    UINT32 u4RxDescNoBufIdx;        /* Index of rx descriptor without packet buffer */
    UINT32 u4RxNoBufCnt;            /* no RX buffer count */
    UINT32 u4RxPktHdrSize;          /* RX packet buffer header size */
    UINT32 *pu4RxDescBuf;           /* RX descriptors buffer address */
    UINT32 *pu4RxPktBuf;            /* RX packet buffer address */
    LIST_HEAD_T rRxPktList;         /* RX packet buffer list */
    HANDLE_T        hRxListSema;    /* RX list semaphore handler */
    PMAC_RX_DESC_T  prRxDesc;       /* RX descriptors struct */
    	
    /* others */
    UINT32 u4PhyAddr;               /* PHY device address on MII interface */
    UINT32 u4IrqStatus;             /* Interrupt status */
    UINT32 u4McListNum;             /* multicast list number, max. is 15 */
    UINT32 u4DevStatus;             /* MAC device status */
    HANDLE_T       hDevStatusSema;  /* MAC device status semaphore handler */
    ETH_BIT_RATE_T rEthBitRate;     /* record current tx/rx bit rate */ 
    MAC_MII_T      rMii;            /* MII status */ 
    MAC_STAT_T     rStat;           /* TX/RX process statistics */
    EV_GRP_EVENT_T u8TaskEvt;
} ETHER_ADAPTER_T, *PETHER_ADAPTER_T;

#endif // _ETHER_PRIV_H_
