/******************************************************************************
 *
 * 2017 (c) Lattice Semiconductor Corporation
 * 
 * This program is free software; you can redistribute it and/or
 * modify it only under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation, and not any later version.
 * 
 * This program is distributed "AS IS" WITHOUT ANY WARRANTY of any kind,
 * whether express or implied, including without limitation the implied warranty
 * of MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE or NON-INFRINGEMENT.
 * See the GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 * 
 * You may contact Lattice Semiconductor Corporation at 
 * 111 SW 5th Ave, Suite 700, Portland, OR 97204.
 *
 *****************************************************************************/
/******************************************************************************
! @file     sii9438_drv.h
! @brief    Defines Internal macros, structures and functions
******************************************************************************/
#ifndef _SII9438_DRV_H_
#define _SII9438_DRV_H_

#include "sii_datatypes.h"
#include "sii9438_api.h"

#define REG_TOP__INT_NUM			3
#define REG_INTR_TOP_1				0
#define REG_INTR_TOP_2				1
#define REG_INTR_TOP_3				2

#define REG_TX__INT_NUM				7

#define REG_INTR_0				0
#define REG_INTR_1				1
#define REG_INTR_2				2
#define REG_INTR_3				3
#define REG_INTR_4				4
#define REG_INTR_5				5
#define REG_INTR_6				6
#define REG_INTR_7				7
#define REG_INTR_8				8

#define BIT__GPIO_NUM_0				0x01
#define BIT__GPIO_NUM_1				0x02
#define BIT__GPIO_NUM_2				0x04
#define BIT__GPIO_NUM_3				0x08
#define BIT__GPIO_NUM_4				0x10
#define BIT__GPIO_NUM_5				0x20

#define SII_CAPS_DS_BLOCK_SIZE			128

enum sii9438_freq_zone {
	SII_FREQ_ZONE_1X,
	SII_FREQ_ZONE_2X,
	SII_FREQ_ZONE_4X,
	SII_FREQ_ZONE_8X,
};

uint32_t sii9438_hal_initialize(uint32_t dev_id,
				const struct sii9438_config *p_config);

uint32_t sii9438_hal_gpio_query(uint32_t dev_id, uint16_t *p_gpio_pin_mask);

uint32_t sii9438_hal_gpio_output_set(uint32_t dev_id,
		uint16_t *p_gpio_pin_mask);

uint32_t sii9438_hal_gpio_config(uint32_t dev_id, uint16_t *gpio_pin_io_config);

uint32_t sii9438_hal_gpio_output_set(uint32_t dev_id,
		uint16_t *p_gpio_pin_mask);

uint32_t sii9438_hal_gpio_config(uint32_t dev_id, uint16_t *gpio_pin_io_config);

uint32_t sii9438_hal_chip_reset(uint32_t dev_id);
uint32_t sii9438_hal_caps_ds_get(uint32_t dev_id, uint8_t *p_caps_ds);
bool_t sii9438_hal_earc_hpd_query(uint32_t dev_id, bool_t *hpd);
bool_t sii9438_hal_rx_stat_chng_query(uint32_t dev_id,
						bool_t *b_hb_stat_chng);
bool_t sii9438_hal_rx_cap_chng_query(uint32_t dev_id,
						bool_t *re_read_caps_ds);
uint32_t sii_hal_channel_status_update(uint32_t dev_id,
				 uint8_t *p_ch_stat,
				 uint16_t size);
void sii9438_hal_hpd_set(uint32_t dev_id, bool_t en);
uint32_t sii9438_hal_gpio_output_update(uint32_t dev_id,
		uint16_t *p_gpio_pin_mask, bool_t b_set);
uint32_t sii9438_hal_top_int_get(uint32_t dev_id,
				uint8_t *p_top_int);
uint32_t sii9438_hal_enable_all_int(uint32_t dev_id,
				bool_t en);
uint32_t sii9438_hal_top_int_status_get(uint32_t dev_id,
				uint8_t *p_int_top_regs,
				uint16_t num_regs);
uint32_t sii9438_hal_earc_block_int_get(uint32_t dev_id,
				 uint8_t *p_int);
uint32_t sii9438_hal_gpio_event_mask_set(uint32_t dev_id,
		uint8_t *gpio_pin_event_mask);
uint32_t sii9438_hal_earc_int_status_get(uint32_t dev_id,
				uint8_t *p_int_regs,
				uint16_t num_regs);
uint32_t sii9438_hal_i2s_clk_status_get(uint32_t dev_id,
				bool_t *i2s_clock_status);
uint32_t sii9438_hal_earc_conn_status_get(uint32_t dev_id,
					bool_t *p_earc_stat);
uint32_t sii9438_hal_caps_ds_read_status_get(uint32_t dev_id,
					uint8_t *p_caps_ds_stat);
uint32_t sii9438_hal_sw_access_status_get(uint32_t dev_id,
					uint8_t *p_stat);
uint32_t sii9438_hal_reset_aud_fifo(uint32_t dev_id);
uint32_t sii_hal_audio_mode_set(uint32_t dev_id,
			enum  sii9438_insertion_mode ins_mode);
uint32_t sii9438_hal_aud_mute_set(uint32_t dev_id,
				 bool_t en);
uint32_t sii_hal_freq_zone_set(uint32_t dev_id,
			enum  sii9438_freq_zone ins_mode);
uint32_t sii9438_hal_intr_enable(uint32_t dev_id, bool_t b_on);
uint32_t sii9438_hal_reset_ddc_no_ack(uint32_t dev_id);
uint32_t sii9438_hal_arc_mode_set(uint32_t dev_id,
				enum sii_arc_mode arc_mode);
uint32_t sii9438_hal_spdif_channel_status_query(uint32_t dev_id,
		struct sii_channel_status *p_channel_status);
uint32_t sii9438_hal_tx_own_aksv_get(uint32_t dev_id, uint8_t *p_tx_aksv,
					uint16_t size);
uint32_t sii9438_hal_virtual_hdmi_hpd_enable_set(uint32_t dev_id,
		bool_t b_enable);
uint32_t sii9438_hal_stat_chng_conf_enable_set(uint32_t dev_id,
		bool_t b_enable);
uint32_t sii9438_hal_cap_chng_conf_enable_set(uint32_t dev_id,
		bool_t b_enable);
uint32_t sii9438_hal_virtual_hdmi_hpd_set(uint32_t dev_id,
		bool_t b_hdmi_hpd_val);
uint32_t sii9438_hal_stat_chng_conf_set(uint32_t dev_id,
		bool_t b_enable);
uint32_t sii9438_hal_cap_chng_conf_set(uint32_t dev_id,
		bool_t b_set);
uint32_t sii9438_hal_hpd_out_set(uint32_t dev_id, bool_t b_hpd_out_val);
uint32_t sii9438_hal_tx_audio_in_reset(uint32_t dev_id, bool_t en);
uint32_t sii9438_hal_tx_spdif_ch_status_intr_enable(uint32_t dev_id,
		bool_t en);
uint32_t sii9438_hal_tx_phy_fifo_reset_set(uint32_t dev_id,
				bool_t b_reset);
uint32_t sii9438_hal_timer_value_set(uint32_t dev_id, uint16_t time_value_ms);
uint32_t sii9438_hal_timer_value_get(uint32_t dev_id, uint16_t *time_value_ms);
uint32_t sii9438_hal_chip_version_query(uint32_t dev_id,
					uint8_t *p_chip_version);
uint32_t sii_hal_bsync_count_set(uint32_t dev_id, uint8_t bsync_count);

uint32_t sii9438_hal_idle2_enable(uint32_t dev_id, bool_t b_en);
uint32_t sii9438_hal_sm_state_get(uint32_t dev_id, uint8_t *p_state_val);
uint32_t sii9438_hal_sm_state_set(uint32_t dev_id, uint8_t state_val);
uint32_t sii9438_hal_sm_state_override_enable(uint32_t dev_id, bool_t b_en);
uint32_t sii9438_hal_arc_init_term(uint32_t dev_id, bool_t b_init_is);
uint32_t sii9438_hal_sm_states_intr_enable(uint32_t dev_id, bool_t b_en);
uint32_t sii9438_hal_erx_latency_query(uint32_t dev_id,
					uint8_t *erx_latency);
uint32_t sii9438_hal_erx_latency_req_set(uint32_t dev_id,
					uint8_t erx_latency_req);

uint32_t sii9438_hal_ecc_mask_init(uint32_t dev_id);
uint32_t sii9438_hal_ecc_enable(uint32_t dev_id, bool_t b_en);
uint32_t sii9438_hal_ecc_status(uint32_t dev_id, bool_t *p_b_on);
uint32_t sii9438_hal_ecc_err_cnt_get(uint32_t dev_id, uint16_t *p_err_cnt);
uint32_t sii9438_hal_ecc_err_cnt_clear(uint32_t dev_id);
uint32_t sii9438_hal_ecc_err_fixed_cnt_get(uint32_t dev_id,
		uint16_t *p_err_fixed_cnt);
uint32_t sii9438_hal_ecc_err_fixed_cnt_clear(uint32_t dev_id);
uint32_t sii9438_hal_tx_hw_mute_out_status_query(uint32_t dev_id,
						bool_t *hw_mute_out_status);
uint32_t sii9438_hal_tx_mute_excep_det_int_clr(uint32_t dev_id);
uint32_t sii9438_hal_mute_excep_det_intr_enable(uint32_t dev_id, bool_t en);
uint32_t sii9438_hal_is_spdif_cs_ch_intr_en(uint32_t dev_id, bool_t *is_en);
uint32_t sii9438_hal_tx_pll_enable(uint32_t dev_id, bool_t pll_enable);
uint32_t sii9438_hal_norm_phase_set(uint32_t dev_id,
					bool_t norm_phase_en);
uint32_t sii9438_hal_tx_earc_mode_set(uint32_t dev_id, bool_t b_earc_mode);
uint32_t sii9438_hal_vbit_set(uint32_t dev_id,
				enum sii9438_vbit vbit_value,
				bool_t b_spdif_in);
uint32_t sii9438_hal_mclk_div_set(uint32_t dev_id,
		enum sii9438_mclk_div mclk_div);
uint32_t sii9438_hal_tx_out_clk_en(uint32_t dev_id, bool_t b_en);
uint32_t sii9438_hal_tx_timeout_set(uint32_t dev_id, uint16_t timeout_val);

uint32_t sii9438_hal_hb_intr_mask_en(uint32_t dev_id, bool_t en);
uint32_t sii9438_hal_hb_intr_clear(uint32_t dev_id);
#endif /* _SII9438_DRV_H_ */
