/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
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 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
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 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
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 *    notice, this list of conditions and the following disclaimer in
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 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: xiaojun.zhu $
 * $Date: 2015/08/08 $
 * $RCSfile: hal_io.c,v $
 * $Revision: #3 $
 *
 *---------------------------------------------------------------------------*/

/** @file hal_io.c
 *  hal_1176.c provides functions of register access
 */


#include "x_hal_io.h"
#include "x_assert.h"

#if defined(CC_MT5890)||defined(CC_MT5891)||defined(CC_MT5886)
#include "x_hal_5381.h"
#include "hw_mlvds.h"
#include "hw_vbyone.h"
#include "hw_tg.h"
#endif

#if (defined(CC_MTK_LOADER) || defined(CC_MTK_PRELOADER))
    #undef x_crit_start
    #undef x_crit_end
    #define x_crit_start() 0
    #define x_crit_end(x) UNUSED(x)
    #define CRIT_STATE_T UINT8
#else
    #include "x_os.h"
#endif

#ifdef CC_MTK_HOTBOOT_START
void raise(void)
{
    return;
}
#endif

UINT16 u2IO32Read2B(UPTR reg32)
{
    UPTR addr ;
#if defined(CONFIG_64BIT) || defined (__USERDRV__)
    UPTR uptrOffset = __HAL_READ_OFFSET(reg32);
#else
    UPTR uptrOffset = 0;
#endif

    addr = (reg32 + uptrOffset)&~3 ;

    switch(reg32&3)
    {
        case 0:
        case 2:
            return (*(volatile UINT16 *)(reg32 + uptrOffset));
        case 1:
            return  ((*(volatile UINT32 *)(addr))>>8)&0xffff;
        default:
            ASSERT((reg32&3)<3);
            return  ((*(volatile UINT32 *)(addr))>>24)&0xff;
    }
}

#if defined(FORCE_IO32_1BMSK_FUNCTION) || defined(CC_MTK_LOADER) || defined(CC_UBOOT) || !defined(__KERNEL__)
void vIO32Write1BMsk(UPTR reg32, UINT32 val8, UINT8 msk8)
{
    CRIT_STATE_T csState;
    UINT32 u4Val, u4Msk;
    UINT8 bByte;
#if defined(CONFIG_64BIT) || defined (__USERDRV__)
    UPTR uptrOffset = __HAL_READ_OFFSET(reg32);
#else
    UPTR uptrOffset = 0;
#endif

    bByte = reg32&3;
    reg32 &= ~3;
    val8 &= msk8;
    u4Msk = ~(UINT32)(msk8<<((UINT32)bByte<<3));

    csState = x_crit_start();
	{
    u4Val = (*(volatile UINT32 *)(reg32 + uptrOffset));
    u4Val = ((u4Val & u4Msk) | ((UINT32)val8 << (bByte<<3)));
	}	
    (*(volatile UINT32 *)(reg32 + uptrOffset)=(u4Val));
    x_crit_end(csState);

}
#endif

void vIO32Write2BMsk(UPTR reg32, UINT32 val16, UINT16 msk16)
{
    CRIT_STATE_T csState;
    UINT32 u4Val, u4Msk;
    UINT8 bByte;
#if defined(CONFIG_64BIT) || defined (__USERDRV__)
    UPTR uptrOffset = __HAL_READ_OFFSET(reg32);
#else
    UPTR uptrOffset = 0;
#endif

    bByte = reg32&3;
    ASSERT(bByte<3);

    reg32 &= ~3;
    val16 &= msk16;
    u4Msk = ~(UINT32)(msk16<<((UINT32)bByte<<3));

    csState = x_crit_start();

    u4Val = (*(volatile UINT32 *)(reg32 + uptrOffset));
    u4Val = ((u4Val & u4Msk) | ((UINT32)val16 << (bByte<<3)));
    (*(volatile UINT32 *)(reg32 + uptrOffset)=(u4Val));
    x_crit_end(csState);

}

void vIO32Write4BMsk(UPTR reg32, UINT32 val32, UINT32 msk32)
{
    CRIT_STATE_T csState;
#if defined(CONFIG_64BIT) || defined (__USERDRV__)
    UPTR uptrOffset = __HAL_READ_OFFSET(reg32);
#else
    UPTR uptrOffset = 0;
#endif

    ASSERT((reg32&3)==0);
    val32 &=msk32;

    csState = x_crit_start();
	{
    (*(volatile UINT32 *)(reg32 + uptrOffset)=((*(volatile UINT32 *)(reg32 + uptrOffset))&~msk32)|val32);
	}
    x_crit_end(csState);
}
void vIO32Write4BMsk_All(UPTR reg32, UINT32 val32, UINT32 msk32)
{
    UINT8 ii;
    UPTR reg32_index;
    CRIT_STATE_T csState;
#if defined(CONFIG_64BIT) || defined (__USERDRV__)
    UPTR uptrOffset = __HAL_READ_OFFSET(reg32);
#else
    UPTR uptrOffset = 0;
#endif

    ASSERT((reg32&3)==0);
    val32 &=msk32;

    csState = x_crit_start();
	{
   	 for(ii=0; ii< 4; ii++) 
    {
	reg32_index=((8 << 12)*ii+ (reg32)); 
    (*(volatile UINT32 *)(reg32_index + uptrOffset)=((*(volatile UINT32 *)(reg32_index + uptrOffset))&~msk32)|val32);
    }
	}
    x_crit_end(csState);
}

void vIO32Write4B_All(UPTR reg32, UINT32 val32)
{
    UINT8 ii;
    UPTR reg32_index;
   	 for(ii=0; ii< 4; ii++) 
    {
	reg32_index=((8 << 12)*ii+ (reg32)); 
	//CHIP_DisplayString("reg32_index=");
	//CHIP_DisplayHex(reg32_index);
	//CHIP_DisplayString("   val32  ");
	//CHIP_DisplayHex(val32);
	//CHIP_DisplayString(".\n");
	(*(volatile UINT32 *)(reg32_index)=(val32));
    }

}

