/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author$
 * $Date  $
 * $RCSfile: cec_drv_if.h,v $
 * $Revision$
 *
 *---------------------------------------------------------------------------*/

#ifndef CEC_DRV_IF
#define CEC_DRV_IF

//---------------------------------------------------------------------------
// Include files
//---------------------------------------------------------------------------
#include "x_lint.h"

LINT_EXT_HEADER_BEGIN

#include "hw_vdoin.h"
#include "cec_hw_if.h"
#include "cec_if.h"

#include "hw_ckgen.h"
#include "api_eep.h"
#include "eepdef.h"
#include "eeprom_if.h"
#include "drvcust_if.h"
#include "pdwnc_if.h"

#include "x_os.h"
#include "x_printf.h"
#include "x_assert.h"
#include "x_pinmux.h"
#include "x_pdwnc.h"
#include "x_bim.h"
#include "x_timer.h"

/// define CEC module debug log function.
#define DEFINE_IS_LOG      CEC_IsLog
#include "x_debug.h"

LINT_EXT_HEADER_END
//---------------------------------------------------------------------------
// Configurations
//---------------------------------------------------------------------------

#ifdef CC_DRIVER_PROGRAM
#define CTS_TEST
#else
#define NOTIFY_CECMW
#endif

//---------------------------------------------------------------------------
// Constant definitions
//---------------------------------------------------------------------------
#define RETX_MAX_CNT 2

#define CEC_LOG_BROADCAST CEC_LOG_UNREGISTERED

#define CEC_SUCCESS (0)

#define CEC_ERROR (1)

#define CEC_ACK 0
#define CEC_NACK 1
#define CEC_BUSY 2
//---------------------------------------------------------------------------
// Type definitions
//---------------------------------------------------------------------------
typedef enum
{
    CEC_LOG_TV                = 0,
    CEC_LOG_RECORDING_DEVICE1 = 1,
    CEC_LOG_RECORDING_DEVICE2 = 2,
    CEC_LOG_TUNER1            = 3,
    CEC_LOG_PLAYBACK_DEVICE1  = 4,
    CEC_LOG_AUDIO_SYSTEM      = 5,
    CEC_LOG_TUNER2            = 6,
    CEC_LOG_TUNER3            = 7,
    CEC_LOG_PLAYBACK_DEVICE2  = 8,
    CEC_LOG_RECORDING_DEVICE3 = 9,
    CEC_LOG_TUNER4            = 10,
    CEC_LOG_PLAYBACK_DEVICE3  = 11,
    CEC_LOG_RESERVED1         = 12,
    CEC_LOG_RESERVED2         = 13,
    CEC_LOG_FREE_USE          = 14,
    CEC_LOG_UNREGISTERED      = 15
} CEC_LOGICAL_ADDR;

typedef enum
{
    OPCODE_FEATURE_ABORT = 0x00,                // 4
    OPCODE_IMAGE_VIEW_ON = 0x04,                // 2
    OPCODE_TUNER_STEP_INCREMENT = 0x05,            // 2
    OPCODE_TUNER_STEP_DECREMENT = 0x06,            // 2
    OPCODE_TUNER_DEVICE_STATUS = 0x07,            // 7 or 10
    OPCODE_GIVE_TUNER_DEVICE_STATUS = 0x08,            // 3
    OPCODE_RECORD_ON = 0x09,                // 3~10
    OPCODE_RECORD_STATUS = 0x0A,                // 3
    OPCODE_RECORD_OFF = 0x0B,                // 2
    OPCODE_TEXT_VIEW_ON = 0x0D,                // 2
    OPCODE_RECORD_TV_SCREEN = 0x0F,                // 2
    OPCODE_GIVE_DECK_STATUS = 0x1A,                // 3
    OPCODE_DECK_STATUS = 0x1B,                // 3
    OPCODE_SET_MENU_LANGUAGE = 0x32,            // 5
    OPCODE_CLEAR_ANALOGUE_TIMER = 0x33,            // 13
    OPCODE_SET_ANALOGUE_TIMER = 0x34,            // 13
    OPCODE_TIMER_STATUS = 0x35,                // 3 or 5
    OPCODE_STANDBY = 0x36,                    // 2
    OPCODE_PLAY = 0x41,                    // 3
    OPCODE_DECK_CONTROL = 0x42,                // 3
    OPCODE_TIMER_CLEARED_STATUS = 0x43,            // 3
    OPCODE_USER_CONTROL_PRESSED = 0x44,            // 3
    OPCODE_USER_CONTROL_RELEASED = 0x45,            // 2
    OPCODE_GIVE_OSD_NAME = 0x46,                // 2
    OPCODE_SET_OSD_NAME = 0x47,                // 3~16
    OPCODE_SET_OSD_STRING = 0x64,                // 4~16
    OPCODE_SET_TIMER_PROGRAM_TITLE = 0x67,            // 3~16
    OPCODE_SYSTEM_AUDIO_MODE_REQUEST = 0x70,        // 4
    OPCODE_GIVE_AUDIO_STATUS = 0x71,            // 2
    OPCODE_SET_SYSTEM_AUDIO_MODE = 0x72,            // 3
    OPCODE_REPORT_AUDIO_STATUS = 0x7A,            // 3
    OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS = 0x7D,        // 2
    OPCODE_SYSTEM_AUDIO_MODE_STATUS = 0x7E,            // 3
    OPCODE_ROUTING_CHANGE = 0x80,                // 6
    OPCODE_ROUTING_INFORMATION = 0x81,            // 4
    OPCODE_ACTIVE_SOURCE = 0x82,                // 4
    OPCODE_GIVE_PHYSICAL_ADDRESS = 0x83,            // 2
    OPCODE_REPORT_PHYSICAL_ADDRESS = 0x84,            // 5
    OPCODE_REQUEST_ACTIVE_SOURCE = 0x85,            // 2
    OPCODE_SET_STREAM_PATH = 0x86,                // 4
    OPCODE_DEVICE_VENDOR_ID = 0x87,                // 5
    OPCODE_VENDOR_COMMAND = 0x89,                // <= 16
    OPCODE_VENDOR_REMOTE_BUTTON_DOWN = 0x8A,        // <= 16
    OPCODE_VENDOR_REMOTE_BUTTON_UP = 0x8B,            // 2
    OPCODE_GIVE_DEVICE_VENDOR_ID = 0x8C,            // 2
    OPCODE_MENU_REQUEST = 0x8D,                // 3
    OPCODE_MENU_STATUS = 0x8E,                // 3
    OPCODE_GIVE_DEVICE_POWER_STATUS = 0x8F,            // 2
    OPCODE_REPORT_POWER_STATUS = 0x90,            // 3
    OPCODE_GET_MENU_LANGUAGE = 0x91,            // 2
    OPCODE_SELECT_ANALOGUE_SERVICE = 0x92,            // 6
    OPCODE_SELECT_DIGITAL_SERVICE = 0x93,            // 9
    OPCODE_SET_DIGITAL_TIMER = 0x97,            // 16
    OPCODE_CLEAR_DIGITAL_TIMER = 0x99,            // 16
    OPCODE_SET_AUDIO_RATE = 0x9A,                // 3
    OPCODE_INACTIVE_SOURCE = 0x9D,                // 4
    OPCODE_CEC_VERSION = 0x9E,                // 3
    OPCODE_GET_CEC_VERSION = 0x9F,                // 2
    OPCODE_VENDOR_COMMAND_WITH_ID = 0xA0,            // <= 16
    OPCODE_CLEAR_EXTERNAL_TIMER = 0xA1,            // 10 ~ 11
    OPCODE_SET_EXTERNAL_TIMER = 0xA2,            // 10 ~ 11
    OPCODE_DEVICE_CHECK_ATMOS = 0xA3,
    OPCODE_GIVE_FEATURE       = 0xa5, /* ---> */
    OPCODE_REPORT_FEATURE     = 0xa6, /* ---> */
    OPCODE_ARC_INIT = 0xC0,                                      // 2
    OPCODE_ARC_REPORT_INIT = 0xC1,                      // 2
    OPCODE_ARC_REPORT_TERMINATE = 0xC2,          // 2
    OPCODE_ARC_REQUEST_INIT = 0xC3,                   // 2
    OPCODE_ARC_REQUEST_TERMINATE = 0xC4,       // 2
    OPCODE_ARC_TERMINATE = 0xC5,                        // 2
#ifdef SYS_MHL_SUPPORT
    OPCODE_MHL_CONTENT_ON = 0xE0,                // 4
    OPCODE_MHL_CONTENT_OFF = 0xE1,                // 4
    OPCODE_MHL_SCRATCHPAD_DATA = 0xE3,                // 4
#endif
    OPCODE_CDC_MESSAGE = 0xF8,
    OPCODE_ABORT = 0xFF,                    // 2
    OPCODE_NONE = 0xFFF
} CEC_OPCODE;

typedef enum
{
    STATE_TX_SEND_FRAME = 0x0001,
    STATE_TX_WAIT_DATA_TAKEN = 0x0002,  /*Tx with data, not ping frame.*/
    STATE_TX_RESEND = 0x0004,
    STATE_TX_NOACK = 0x0008,
    STATE_TX_SEND_FRAME_OK = 0x0010,
    STATE_TX_BUSY = 0x0020,

    STATE_RX_GET_NEW_HEADER = 0x0100,
    STATE_RX_WAIT_COMPLETE = 0x0200
} CEC_SW_STATE;

typedef enum {
    HDMI_CONNECT_PORT_INIT = 0,
    HDMI_CONNECT_PORT_1,
    HDMI_CONNECT_PORT_2,
    HDMI_CONNECT_PORT_3,
    HDMI_CONNECT_PORT_4,
    HDMI_CONNECT_PORT_MAX
}HDMI_CONNECT_PORT_NUM;

//---------------------------------------------------------------------------
// Macro definitions
//---------------------------------------------------------------------------
/* RX_EVENT */
#define IS_INT_DATA_RDY() (IO32ReadFldAlign(RX_EVENT, DATA_RDY))
#define IS_INT_HEADER_RDY() (IO32ReadFldAlign(RX_EVENT, HEADER_RDY))
#define IS_INT_OV() (IO32ReadFldAlign(RX_EVENT, OV))
#define IS_INT_BR_SB_RDY() (IO32ReadFldAlign(RX_EVENT, BR_SB_RDY))
#define IS_INT_SB_RDY() (IO32ReadFldAlign(RX_EVENT, SB_RDY))
#define IS_INT_BR_RDY() (IO32ReadFldAlign(RX_EVENT, BR_RDY))
#define ENABLE_INT_DATA_RDY(onoff) ((void)vIO32WriteFldAlign(RX_EVENT, onoff, I_EN_DATA))
#define ENABLE_INT_HEADER_RDY(onoff) ((void)vIO32WriteFldAlign(RX_EVENT, onoff, I_EN_HEADER))
#define ENABLE_INT_OV(onoff) ((void)vIO32WriteFldAlign(RX_EVENT, onoff, I_EN_OV))
#define ENABLE_INT_PULSE(onoff) ((void)vIO32WriteFldAlign(RX_EVENT, onoff, I_EN_PULSE))
#define ENABLE_INT_BR_SB_RDY(onoff) ((void)vIO32WriteFldAlign(RX_EVENT, onoff, I_EN_BR_SB))
#define ENABLE_INT_SB_RDY(onoff) ((void)vIO32WriteFldAlign(RX_EVENT, onoff, I_EN_SB))
#define ENABLE_INT_BR_RDY(onoff) ((void)vIO32WriteFldAlign(RX_EVENT, onoff, I_EN_BR))
#define CLR_INT_DATA_RDY() ((void)vIO32WriteFldAlign(RX_EVENT, 0, DATA_RDY))
#define CLR_INT_HEADER_RDY() ((void)vIO32WriteFldAlign(RX_EVENT, 0, HEADER_RDY))
#define CLR_INT_OV() ((void)vIO32WriteFldAlign(RX_EVENT, 0, OV))
#define NOTIFY_RX_HW_DATA_TAKEN() ((void)vIO32WriteFldAlign(RX_EVENT, 0, BR_RDY))
#define RX_EVENT_STATUS() (u4IO32Read4B(RX_EVENT))

/* TX_EVENT */
#define IS_INT_UN() (IO32ReadFldAlign(TX_EVENT, UN))
#define IS_INT_FAIL() (IO32ReadFldAlign(TX_EVENT, FAIL))
#define IS_INT_LOW() (IO32ReadFldAlign(TX_EVENT, LOW))
#define IS_TX_FINISH() (IO32ReadFldAlign(TX_EVENT, TX_D_FINISH))
#define IS_INT_RB_RDY() (IO32ReadFldAlign(TX_EVENT, RB_RDY))
#define IS_INT_HEADER_ACK() (IO32ReadFldAlign(TX_FAIL, HEADER_ACK))
#define ENABLE_INT_DATA_FIN(onoff) ((void)vIO32WriteFldAlign(TX_EVENT, onoff, TX_DATA_FIN_E))
#define ENABLE_INT_UN(onoff) ((void)vIO32WriteFldAlign(TX_EVENT, onoff, I_EN_UN))
#define ENABLE_INT_FAIL(onoff) ((void)vIO32WriteFldAlign(TX_EVENT, onoff, I_EN_FAIL))
#define ENABLE_INT_LOW(onoff) ((void)vIO32WriteFldAlign(TX_EVENT, onoff, I_EN_LOW))
#define ENABLE_INT_BS(onoff) ((void)vIO32WriteFldAlign(TX_EVENT, onoff, I_EN_BS))
#define ENABLE_INT_RB(onoff) ((void)vIO32WriteFldAlign(TX_EVENT, onoff, I_EN_RB))
#define CLR_INT_UN() ((void)vIO32WriteFldAlign(TX_EVENT, 0, UN))
#define CLR_INT_LOW() ((void)vIO32WriteFldAlign(TX_EVENT, 0, LOW))
#define CLR_TX_FINISH() ((void)vIO32WriteFldAlign(TX_EVENT, 0, TX_D_FINISH))
#define TRIGGER_TX_HW() ((void)vIO32WriteFldAlign(TX_EVENT, 1, RB_RDY))
#define IS_TX_DATA_TAKEN() (!(IS_INT_RB_RDY()))
#define IS_INT_RB_ENABLE() (IO32ReadFldAlign(TX_EVENT, I_EN_RB))
#define IS_INT_FAIL_ENABLE() (IO32ReadFldAlign(TX_EVENT, I_EN_FAIL))
#define TX_EVENT_STATUS() (u4IO32Read4B(TX_EVENT))

#define DISABLE_ALL_TX_INT() \
{ \
    ENABLE_INT_FAIL(0); \
    ENABLE_INT_RB(0); \
    ENABLE_INT_LOW(0); \
    ENABLE_INT_UN(0); \
    ENABLE_INT_BS(0); \
}

/* RX FSM status */
#define IS_RX_FSM_IDLE() (IO32ReadFldAlign(RX_STATUS, RX_FSM) == 0x01)
#define IS_RX_FSM_START() (IO32ReadFldAlign(RX_STATUS, RX_FSM) == 0x02)
#define IS_RX_FSM_MODE() (IO32ReadFldAlign(RX_STATUS, RX_FSM) == 0x04)
#define IS_RX_FSM_MODE3_HEADER() (IO32ReadFldAlign(RX_STATUS, RX_FSM) == 0x08)
#define IS_RX_FSM_MODE3_DATA() (IO32ReadFldAlign(RX_STATUS, RX_FSM) == 0x10)
#define IS_RX_FSM_ERROR_S() (IO32ReadFldAlign(RX_STATUS, RX_FSM) == 0x20)
#define IS_RX_FSM_ERROR_D() (IO32ReadFldAlign(RX_STATUS, RX_FSM) == 0x40)
#define RX_FSM_STATUS() (IO32ReadFldAlign(RX_STATUS, RX_FSM))

/* TX FSM status */
#define IS_TX_FSM_IDLE() (IO32ReadFldAlign(TX_STATUS, TX_FSM) == 0x01)
#define IS_TX_FSM_INIT() (IO32ReadFldAlign(TX_STATUS, TX_FSM) == 0x02)
#define IS_TX_FSM_EOM() (IO32ReadFldAlign(TX_STATUS, TX_FSM) == 0x04)
#define IS_TX_FSM_RETRASMIT() (IO32ReadFldAlign(TX_STATUS, TX_FSM) == 0x08)
#define IS_TX_FSM_FAIL() (IO32ReadFldAlign(TX_STATUS, TX_FSM) == 0x10)
#define IS_TX_FSM_START() (IO32ReadFldAlign(TX_STATUS, TX_FSM) == 0x20)
#define IS_TX_FSM_MODE() (IO32ReadFldAlign(TX_STATUS, TX_FSM) == 0x40)
#define IS_TX_FSM_MODE3_HEADER() (IO32ReadFldAlign(TX_STATUS, TX_FSM) == 0x80)
#define IS_TX_FSM_MODE3_DATA() (IO32ReadFldAlign(TX_STATUS, TX_FSM) == 0x100)
#define TX_FSM_STATUS() (IO32ReadFldAlign(TX_STATUS, TX_FSM))

#define ENABLE_TX_EN() ((void)vIO32WriteFldAlign(TR_CONFIG, 1, TX_EN))
#define DISABLE_TX_EN() ((void)vIO32WriteFldAlign(TR_CONFIG, 0, TX_EN))
#define ENABLE_RX_EN() ((void)vIO32WriteFldAlign(TR_CONFIG, 1, RX_EN))
#define DISABLE_RX_EN() ((void)vIO32WriteFldAlign(TR_CONFIG, 0, RX_EN))

#define SET_HW_TX_LEN(num) ((void)vIO32WriteFldAlign(TX_HD_NEXT, num, WTX_M3_DATA_MASK))
#define FILL_SRC_FIELD(addr) ((void)vIO32WriteFldAlign(TX_HD_NEXT, addr, WTX_SRC))
#define FILL_DST_FIELD(addr) ((void)vIO32WriteFldAlign(TX_HD_NEXT, addr, WTX_DST))
#define MARK_H_EOM(onoff) ((void)vIO32WriteFldAlign(TX_HD_NEXT, onoff, WTX_H_EOM))
#define MARK_D_EOM(onoff) ((void)vIO32WriteFldAlign(TX_HD_NEXT, onoff, WTX_D_EOM))
#define FILL_TX_DATA(data) ((void)vIO32WriteFldAlign(TX_DATA_NEXT, data, WTX_DATA))

#define GET_HW_RX_LEN() (IO32ReadFldAlign(RX_HEADER, RXED_M3_DATA_MASK))
#define GET_SRC_FIELD() (IO32ReadFldAlign(RX_HEADER, RXED_SRC))
#define GET_DST_FIELD() (IO32ReadFldAlign(RX_HEADER, RXED_DST))
#define GET_SRC_FIELD_RECEIVING() (IO32ReadFldAlign(RX_HD_NEXT, RXING_SRC))
#define GET_DST_FIELD_RECEIVING() (IO32ReadFldAlign(RX_HD_NEXT, RXING_DST))
#define IS_RX_H_EOM() (IO32ReadFldAlign(RX_HEADER, RXED_H_EOM))
#define IS_RX_D_EOM() (IO32ReadFldAlign(RX_HEADER, RXED_D_EOM))

#define GET_HW_RX_DATA() (IO32ReadFldAlign(RX_DATA, RXED_DATA))

#define FLOW_CONTROL_ACK(onoff) \
    ((void)vIO32WriteFldAlign(RX_HD_NEXT, (!(onoff)), RXING_H_ACK)); \
    ((void)vIO32WriteFldAlign(RX_HD_NEXT, (!(onoff)), RXING_D_ACK));

#define GET_FOLLOWER_H_ACK() (IO32ReadFldAlign(TX_HEADER, TXING_H_ACK))
#define GET_FOLLOWER_D_ACK() (IO32ReadFldAlign(TX_HEADER, TXING_D_ACK))

#define TX_FAIL_MAX() (IO32ReadFldAlign(TX_FAIL, RETX_MAX))
#define CLR_TX_FAIL_MAX()  ((void)vIO32WriteFldAlign(TX_FAIL, 0, RETX_MAX))
#define TX_FAIL_RECORD() (u4IO32Read4B(TX_FAIL))

#define GET_DEVICE_LA() (IO32ReadFldAlign(TR_CONFIG, DEVICE_ADDR1))
#define CHECK_RX_EN() (IO32ReadFldAlign(TR_CONFIG, RX_EN))
#define SET_TV_LA(value) ((void)vIO32WriteFldAlign(TR_CONFIG, value, DEVICE_ADDR1))

#define RX_FAIL_RECORD() (u4IO32Read4B(RX_FAIL))
#define CLR_RX_ERROR_ONCE() ((void)vIO32WriteFldAlign(RX_FAIL, 0, ERR_ONCE))

#define RESET_HW_TX() \
    DISABLE_TX_EN(); ENABLE_TX_EN()

#define GET_TX_BIT_COUNTER() (IO32ReadFldAlign(TX_STATUS, TX_BIT_COUNTER))

#define SetCECStatus(arg) { \
    CRIT_STATE_T rCritState; \
    rCritState = x_crit_start(); \
    (_CEC_Status |= ((UINT16)arg)); \
    x_crit_end(rCritState); }

#define ClrCECStatus(arg) { \
    CRIT_STATE_T rCritState; \
    rCritState = x_crit_start(); \
    (_CEC_Status &= (~((UINT16)arg))); \
    x_crit_end(rCritState); }

#define IsCECStatus(arg)     ((_CEC_Status & ((UINT16)arg)) > 0)

#define CLR_CEC_BUSY_STATUS() (_u2CecBusyStatus = 0)
#define CEC_BUSY_STATUS() _u2CecBusyStatus

#define CEC_IS_BUSY() (_u2CecBusyStatus)

#define CEC_RX_IS_BUSY() (_u2CecBusyStatus & CEC_RX_BUSY)

#define SET_CECRX_BUSY()\
     do {\
         _u2CecBusyStatus |= CEC_RX_BUSY;\
         LOG(7, "RX busy ----->>\n");\
        }while(0)

#define CLR_CECRX_BUSY()\
     do {\
         _u2CecBusyStatus &= (~CEC_RX_BUSY);\
         LOG(7, "Clr RX busy <<-----\n");\
        }while(0)

#define CEC_TX_IS_BUSY() (_u2CecBusyStatus & CEC_TX_BUSY)

#define SET_CECTX_BUSY()\
     do {\
         _u2CecBusyStatus |= CEC_TX_BUSY;\
         LOG(7, "TX busy ----->>\n");\
        }while(0)

#define CLR_CECTX_BUSY()\
     do {\
         if (CEC_TX_IS_BUSY())\
         LOG(7, "Clr TX busy <<-----\n");\
         _u2CecBusyStatus &= (~CEC_TX_BUSY);\
        }while(0)

#define CEC_TX_FRAME (TRUE)
#define CEC_RX_FRAME (FALSE)
//---------------------------------------------------------------------------
// Inter-file variable
//---------------------------------------------------------------------------
EXTERN UINT16 _CEC_Status;

//---------------------------------------------------------------------------
// Inter-file functions
//---------------------------------------------------------------------------
EXTERN void CEC_PrintFrame(const CEC_FRAME_DESCRIPTION *pFrame, BOOL fgTxFrame);

//---------------------------------------------------------------------------
// Public functions
//---------------------------------------------------------------------------

#endif /* CEC_DRV_IF */

