/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: jiewen.zhou $
 * $Date  $
 * $RCSfile: drv_pwm.h,v $
 * $Revision: #2 $
 *
 *---------------------------------------------------------------------------*/

#ifndef DRV_PWM_H
#define DRV_PWM_H


//-----------------------------------------------------------------------------
// Include files
//-----------------------------------------------------------------------------

#include "x_typedef.h"
#include "x_bim.h"

//-----------------------------------------------------------------------------
// Constant definitions
//-----------------------------------------------------------------------------
/*#if defined(CC_MT5893)
#define SUPPORT_SCANPWM_HALF_MODE
#endif*/

#ifdef CC_PHP_SUPPORT
#define D_DRV_SCAN_PWM_DUTY_MAX 255 //alvin 20150116
#else
#define D_DRV_SCAN_PWM_DUTY_MAX 1000 //alvin 20150116
#endif
#define SrcPWM0 0
#define SrcPWM1 1
#define SrcPWM2 2
#define SrcPWM3 3
#define SrcPWM4 4
#define SrcPWM5 5
#define SrcPWM6 6
#define SrcPWM7 7
#define SrcPWM8 8

#define MINILVDS_IS_HSYNC 0
#define MINILVDS_IS_VSYNC 1

//OPWM0
#define PAD_PWM0_PWM0 	0	//FUNC2 

//OPWM1
#define PAD_PWM1_PWM1 	0	//FUNC2 (FUNC3 SCANPWM)
#define PAD_PWM1_GPIO48 1	//FUNC1

//OPWM2
#define PAD_PWM2_PWM2 	0	//FUNC2 

#define SCAN_PWM_LATCH_MODE_SETDATA_OFF     0
#define SCAN_PWM_LATCH_MODE_SETDATA         1
#define SCAN_PWM_LATCH_MODE_OFF             0
#define SCAN_PWM_LATCH_MODE_ON              1
#define SCAN_PWM_ALIGN_MODE_ONCE            0
#define SCAN_PWM_ALIGN_MODE_VSYNC           1

#define vDrvSetScan1Phase(u4Val) vIO32WriteFldAlign(PWM_SCAN_29, u4Val, REG_PWM_SCAN1_START_PHASE)
#define vDrvSetScan1Start(u4Val) vIO32WriteFldAlign(PWM_SCAN_00, u4Val, REG_PWM_SCAN1_START)
#define vDrvSetScan1High(u4Val) vIO32WriteFldAlign(PWM_SCAN_01, u4Val, REG_PWM_SCAN1_HIGH)
#define vDrvSetScan1Low(u4Val) vIO32WriteFldAlign(PWM_SCAN_02, u4Val, REG_PWM_SCAN1_LOW)

#define vDrvSetScan2Phase(u4Val) vIO32WriteFldAlign(PWM_SCAN_2A, u4Val, REG_PWM_SCAN2_START_PHASE)
#define vDrvSetScan2Start(u4Val) vIO32WriteFldAlign(PWM_SCAN_03, u4Val, REG_PWM_SCAN2_START)
#define vDrvSetScan2High(u4Val) vIO32WriteFldAlign(PWM_SCAN_04, u4Val, REG_PWM_SCAN2_HIGH)
#define vDrvSetScan2Low(u4Val) vIO32WriteFldAlign(PWM_SCAN_05, u4Val, REG_PWM_SCAN2_LOW)
// MT5396/68 New feature for ECO
#define vDrvSetScan3Phase(u4Val) vIO32WriteFldAlign(PWM_SCAN_2B, u4Val, REG_PWM_SCAN3_START_PHASE)
#define vDrvSetScan3Start(u4Val) vIO32WriteFldAlign(PWM_SCAN_07, u4Val, REG_PWM_SCAN3_START)
#define vDrvSetScan3High(u4Val) vIO32WriteFldAlign(PWM_SCAN_08, u4Val, REG_PWM_SCAN3_HIGH)
#define vDrvSetScan3Low(u4Val) vIO32WriteFldAlign(PWM_SCAN_09, u4Val, REG_PWM_SCAN3_LOW)

#define vDrvSetScan4Phase(u4Val) vIO32WriteFldAlign(PWM_SCAN_2C, u4Val, REG_PWM_SCAN4_START_PHASE)
#define vDrvSetScan4Start(u4Val) vIO32WriteFldAlign(PWM_SCAN_0A, u4Val, REG_PWM_SCAN4_START)
#define vDrvSetScan4High(u4Val) vIO32WriteFldAlign(PWM_SCAN_0B, u4Val, REG_PWM_SCAN4_HIGH)
#define vDrvSetScan4Low(u4Val) vIO32WriteFldAlign(PWM_SCAN_0C, u4Val, REG_PWM_SCAN4_LOW)

#define vDrvSetScan5Phase(u4Val) vIO32WriteFldAlign(PWM_SCAN_2D, u4Val, REG_PWM_SCAN5_START_PHASE)
#define vDrvSetScan5Start(u4Val) vIO32WriteFldAlign(PWM_SCAN_0D, u4Val, REG_PWM_SCAN5_START)
#define vDrvSetScan5High(u4Val) vIO32WriteFldAlign(PWM_SCAN_0E, u4Val, REG_PWM_SCAN5_HIGH)
#define vDrvSetScan5Low(u4Val) vIO32WriteFldAlign(PWM_SCAN_0F, u4Val, REG_PWM_SCAN5_LOW)

// MT5398 new feature
#define vDrvSetScan6Phase(u4Val) vIO32WriteFldAlign(PWM_SCAN_2E, u4Val, REG_PWM_SCAN6_START_PHASE)
#define vDrvSetScan6Start(u4Val) vIO32WriteFldAlign(PWM_SCAN_23, u4Val, REG_PWM_SCAN6_START)
#define vDrvSetScan6High(u4Val) vIO32WriteFldAlign(PWM_SCAN_24, u4Val, REG_PWM_SCAN6_HIGH)
#define vDrvSetScan6Low(u4Val) vIO32WriteFldAlign(PWM_SCAN_25, u4Val, REG_PWM_SCAN6_LOW)

//MT5861 and MT5882 new feature
#define vDrvSetScan7Phase(u4Val) vIO32WriteFldAlign(PWM_SCAN_2F, u4Val, REG_PWM_SCAN7_START_PHASE)
#define vDrvSetScan7Start(u4Val) vIO32WriteFldAlign(PWM_SCAN_30, u4Val, REG_PWM_SCAN7_START)
#define vDrvSetScan7High(u4Val) vIO32WriteFldAlign(PWM_SCAN_31, u4Val, REG_PWM_SCAN7_HIGH)
#define vDrvSetScan7Low(u4Val) vIO32WriteFldAlign(PWM_SCAN_32, u4Val, REG_PWM_SCAN7_LOW)

#define vDrvSetScan8Phase(u4Val) vIO32WriteFldAlign(PWM_SCAN_36, u4Val, REG_PWM_SCAN8_START_PHASE)
#define vDrvSetScan8Start(u4Val) vIO32WriteFldAlign(PWM_SCAN_37, u4Val, REG_PWM_SCAN8_START)
#define vDrvSetScan8High(u4Val) vIO32WriteFldAlign(PWM_SCAN_38, u4Val, REG_PWM_SCAN8_HIGH)
#define vDrvSetScan8Low(u4Val) vIO32WriteFldAlign(PWM_SCAN_39, u4Val, REG_PWM_SCAN8_LOW)

//-----------------------------------------------------------------------------
// Public functions
//-----------------------------------------------------------------------------
extern BOOL _fgScanPWMAuto;
extern UINT8 _u1ScanPWMTestSrc;
extern UINT8 _u1ScanPWMTestChg;
extern UINT32 _u4ScanPWMTesFreq;
extern INT32 _i4ScanPWMTestStart;
extern UINT32 _u4ScanPWMTestTop;
extern UINT32 _u4ScanPWMTestBottom;
extern UINT32 _u4ScanPWMTestHigh;
extern UINT32 _u4ScanPWMTestLow;
#ifdef SUPPORT_SCANPWM_HALF_MODE
extern UINT8 u1ScanPWMHalfModeEn;
#endif


#ifdef CC_S_PLATFORM
extern UINT16 arScanPWMPulseNum[4];
#endif

extern void vDrvSetPWM(UINT32 u4Src, UINT32 u4TimeBase, UINT32 u4DutyON,
                       UINT32 u4DutyAll);
void vDrvSetLock(UINT32 u4Src, UINT32 u4LockON);
UINT8 vDrvGetPWMDutyCycleRatio(void);
void vDrvInitSCANPWM(UINT8 u1Src);
void vDrvInitPWM(UINT8 u1Src);
extern void vDrvSetScanPWMSW(UINT8 u1Src, UINT32 u4Start, UINT32 u4High, UINT32 u4Low);
extern void vDrvSetScanPWM(UINT8 u1Src, UINT32 u4Start, UINT32 u4High, UINT32 u4Low);
extern void vDrvSetScanPWMSW_SETDATA(void);
extern void vDrvSetScanPWMSW_SETDATA_Status(void);
extern UINT8 u1DrvGetScanPWMStruct_Ready(void);
extern void vDrvSetScanPWMSW_StepControl(void);
extern void vDrvSetScanPWMStepControlEn(UINT8 fgEnable);
extern void vDrvSetScanPWMStepControl(UINT8 fgEnable, UINT16 u2Step);
extern void vDrvGetScanPWMStepControlStatus(void);
void vDrvSetScanPWMStartPhase(UINT32 u4Src, UINT32 u4Start_Phase);
void vDrvSetSCANPWMBasic(UINT8 u1PwmPort,UINT32 u4High,UINT32 u4Low);
void vDrvSetSCANPWMPhaseBasic(UINT8 u1PwmPort,UINT32 u4Phase);
BOOL fgTX2CHMode(void);
BOOL fgTX4CHMode(void);
void vDrvSetScanBLOnOff(UINT8 u1OnOff);
#ifdef SUPPORT_SCANPWM_HALF_MODE
extern void vDrvSetScanHalfModeEnable(UINT8 u1OnOff);
extern UINT8 vDrvGetScanHalfModeEnable(void);
extern void vDrvSetScanHalfModeStart(UINT8 u1Start);
#endif
extern void vDrvSetScanPWMStepTarget(UINT32 u4High, UINT32 u4Low);
extern void vDrvSetCrozzUpLimit(UINT16 u2Value);
extern UINT16 u2DrvGetCrozzUpLimit(void);

void vDrvSetScanPWMPolarity(UINT32 u4Src, UINT8 u1blPol);
void vDrvSetScanPWMOnOff(UINT32 u4Src, UINT8 u1OnOff);
void vDrvSetScanPWMHFOnOff(UINT32 u4Src, UINT8 u1OnOff);
void vDrvSetScanPWMHFMode(UINT32 u4Src, UINT8 u1Mode);
BOOL fgIsScanPWMSetDataLatch(void);
void vDrvSetScanPWMLatchMode(UINT8 u1SetDataMode,UINT8 u1Mode, UINT8 u1AlignMode);
void vDrvScanPWMDataFire(void);
void vDrvSetScanPWMOutBL(UINT32 u4Src, UINT8 u1OutBL);
void vDrvSetScanStartModeOnOff(UINT32 u4Src, UINT8 u1OnOff);
void vDrvSetScanBLPolarity(UINT8 u1blPol);
void vDrvSetScanBLOnOff(UINT8 u1OnOff);
void vDrvSetScanBLLatchMode(UINT8 u1Mode);
void vDrvSetScanPWMStartHigh(UINT32 u4Src, UINT8 u1OnOff);
extern void vDrvSetScanFixHighLow(UINT8 channel, UINT8 mode);
extern UINT8 u1DrvGetScanFixHighLow(UINT8 channel);
extern void vDrvScanPWMAutoTest(void);

void vDrvSetISOnOff(UINT8 u1Src, UINT8 u1OnOff);
void vDrvSetISMaskNum(UINT8 u1Src, UINT8 u1MaskNum);
void vDrvSetISInputInverse(UINT8 u1Src, UINT8 u1Enable);
void vDrvSetISDelayOnOff(UINT8 u1Src, UINT8 u1OnOff);
void vDrvSetISDelayNum(UINT8 u1Src, UINT16 u2DelayNum);
void vDrvSetISHoldOnOff(UINT8 u1Src, UINT8 u1OnOff);
void vDrvSetISRelation(UINT8 u1Src, UINT8 u1SyncCnt, UINT8 u1ISSyncCnt);

extern void PWM_pm_str_suspend(void);
extern void PWM_pm_str_resume(void);
extern void vDrvSetScanPWMStructData(UINT8 u1Src, UINT32 u4Start, UINT32 u4High, UINT32 u4Low);


#endif
