/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _HW_HDR_H_
#define _HW_HDR_H_
#define IO_HDR_BASE (IO_VIRT_SRE + 0x45000)
#endif

#ifndef _HW_TECHNICOLOR_HDR_H_
#define _HW_TECHNICOLOR_HDR_H_
#define IO_TECH_HDR_BASE (IO_VIRT_SRE + 0x45000)
#endif

#ifndef _HW_PREDOWN_H_
#define _HW_PREDOWN_H_

#include "x_hal_5381.h"

#define IO_PRE_DS_BASE  (IO_VIRT_SRE + 0x41000)


//Page PREDSMAIN
#define PRE_DS_MAIN_00 (IO_PRE_DS_BASE + 0x150)
    #define PRE_DS_MAIN_00_PRE_DSCALE_H_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_00_PRE_DSCALER_V_1 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_01 (IO_PRE_DS_BASE + 0x154)
    #define PRE_DS_MAIN_01_PRE_DSCALE_H_INIT_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_01_PRE_DSCALE_V_INIT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_02 (IO_PRE_DS_BASE + 0x158)
    #define PRE_DS_MAIN_02_PRE_DSCALE_H_INIT_RIGHT_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_02_PRE_DSCALE_V_INIT_RIGHT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_03 (IO_PRE_DS_BASE + 0x15C)
    #define PRE_DS_MAIN_03_PREDS_MAIN_OUT_H Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_03_PREDS_MAIN_OUT_V Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_04 (IO_PRE_DS_BASE + 0x160)
    #define PRE_DS_MAIN_04_PREDS_MAIN_IN_H Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_04_PREDS_MAIN_IN_V Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_05 (IO_PRE_DS_BASE + 0x164)
    #define PRE_DS_MAIN_05_PREDSMAIN_ATPG_CT Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_MAIN_05_PREDSMAIN_ATPG_OB Fld(1,30,AC_MSKB3)//[30:30]
    #define PRE_DS_MAIN_05_MAIN_SET_RES_CLEAR_O Fld(1,27,AC_MSKB3)//[27:27]
    #define PRE_DS_MAIN_05_MAIN_SET_RES_CLEAR_I Fld(1,26,AC_MSKB3)//[26:26]
    #define PRE_DS_MAIN_05_MAIN_SET_RES_FINISH_O Fld(1,25,AC_MSKB3)//[25:25]
    #define PRE_DS_MAIN_05_MAIN_SET_RES_FINISH_I Fld(1,24,AC_MSKB3)//[24:24]
    #define PRE_DS_MAIN_05_MAIN_SETRES_ACT_LINE Fld(8,16,AC_FULLB2)//[23:16]
    #define PRE_DS_MAIN_05_MAIN_SEL_HVCNT Fld(1,15,AC_MSKB1)//[15:15]
    #define PRE_DS_MAIN_05_MAIN_CLR_HVCNT Fld(1,14,AC_MSKB1)//[14:14]
    #define PRE_DS_MAIN_05_MAIN_VCEN_ACT_AT_SYNC Fld(1,13,AC_MSKB1)//[13:13]
    #define PRE_DS_MAIN_05_MAIN_HCEN_ACT_AT_SYNC Fld(1,12,AC_MSKB1)//[12:12]
    #define PRE_DS_MAIN_05_PREDS_3DTV_MODE_1 Fld(4,8,AC_MSKB1)//[11:8]
    #define PRE_DS_MAIN_05_PREDS_LR_PAIR_CTRL Fld(2,6,AC_MSKB0)//[7:6]
    #define PRE_DS_MAIN_05_PREDS_3DTV_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define PRE_DS_MAIN_05_PREDS_MAIN_SETRES Fld(1,4,AC_MSKB0)//[4:4]
    #define PRE_DS_MAIN_05_PREDS_MAIN_SETRES_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define PRE_DS_MAIN_05_PRE_DSCALE_H_BYPASS_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define PRE_DS_MAIN_05_PRE_DSCALE_V_BYPASS_1 Fld(1,0,AC_MSKB0)//[0:0]
#define PRE_DS_MAIN_06 (IO_PRE_DS_BASE + 0x168)
    #define PRE_DS_MAIN_06_MAIN_H_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_06_MAIN_H_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_07 (IO_PRE_DS_BASE + 0x16C)
    #define PRE_DS_MAIN_07_MAIN_V_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_07_MAIN_V_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_08 (IO_PRE_DS_BASE + 0x170)
    #define PRE_DS_MAIN_08_PRE_DSCALE_V_INIT_BTM_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_08_PRE_DSCALE_V_INIT_RIGHT_BTM_1 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_09 (IO_PRE_DS_BASE + 0x174)
    #define PRE_DS_MAIN_09_PREDS_3D_FIELD_EN_1 Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_MAIN_09_PREDS_3D_FIELD_INV_1 Fld(1,30,AC_MSKB3)//[30:30]
#define PRE_DS_MAIN_0A (IO_PRE_DS_BASE + 0x178)
    #define PRE_DS_MAIN_0A_PREDS_H_PHASE_INIT_SIGN_1 Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_MAIN_0A_PREDS_H_PHASE_INIT_INTG_1 Fld(3,28,AC_MSKB3)//[30:28]
    #define PRE_DS_MAIN_0A_PREDS_H_PHASE_INIT_FRAC_1 Fld(20,8,AC_MSKDW)//[27:8]
#define PRE_DS_MAIN_0B (IO_PRE_DS_BASE + 0x17C)
    #define PRE_DS_MAIN_0B_PREDS_H_PHASE_DELTA_INTG_1 Fld(3,28,AC_MSKB3)//[30:28]
    #define PRE_DS_MAIN_0B_PREDS_H_PHASE_DELTA_FRAC_1 Fld(20,8,AC_MSKDW)//[27:8]
    #define PRE_DS_MAIN_0B_PREDS_FIR_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define PRE_DS_MAIN_0B_PREDS_FIR_DLY_SEL Fld(4,3,AC_MSKB0)//[6:3]
    #define PRE_DS_MAIN_0B_PREDS_FIR_INPUT_DLY_SEL Fld(1,1,AC_MSKB0)//[1:1]


//Page PREDSPIP
#define PRE_DS_PIP_00 (IO_PRE_DS_BASE + 0x350)
    #define PRE_DS_PIP_00_PRE_DSCALE_H_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_00_PRE_DSCALER_V_2 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_01 (IO_PRE_DS_BASE + 0x354)
    #define PRE_DS_PIP_01_PRE_DSCALE_H_INIT_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_01_PRE_DSCALE_V_INIT_2 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_02 (IO_PRE_DS_BASE + 0x358)
    #define PRE_DS_PIP_02_PREDS_PIP_OUT_H Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_02_PREDS_PIP_OUT_V Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_03 (IO_PRE_DS_BASE + 0x35C)
    #define PRE_DS_PIP_03_PREDS_PIP_IN_H Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_03_PREDS_PIP_IN_V Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_04 (IO_PRE_DS_BASE + 0x360)
    #define PRE_DS_PIP_04_PREDSPIP_ATPG_CT Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_PIP_04_PREDSPIP_ATPG_OB Fld(1,30,AC_MSKB3)//[30:30]
    #define PRE_DS_PIP_04_PIP_SET_RES_CLEAR_O Fld(1,27,AC_MSKB3)//[27:27]
    #define PRE_DS_PIP_04_PIP_SET_RES_CLEAR_I Fld(1,26,AC_MSKB3)//[26:26]
    #define PRE_DS_PIP_04_PIP_SET_RES_FINISH_O Fld(1,25,AC_MSKB3)//[25:25]
    #define PRE_DS_PIP_04_PIP_SET_RES_FINISH_I Fld(1,24,AC_MSKB3)//[24:24]
    #define PRE_DS_PIP_04_PIP_SETRES_ACT_LINE Fld(8,16,AC_FULLB2)//[23:16]
    #define PRE_DS_PIP_04_PIP_SEL_HVCNT Fld(1,15,AC_MSKB1)//[15:15]
    #define PRE_DS_PIP_04_PIP_CLR_HVCNT Fld(1,14,AC_MSKB1)//[14:14]
    #define PRE_DS_PIP_04_PIP_VCEN_ACT_AT_SYNC Fld(1,13,AC_MSKB1)//[13:13]
    #define PRE_DS_PIP_04_PIP_HCEN_ACT_AT_SYNC Fld(1,12,AC_MSKB1)//[12:12]
    #define PRE_DS_PIP_04_PREDS_PIP_SETRES Fld(1,4,AC_MSKB0)//[4:4]
    #define PRE_DS_PIP_04_PREDS_PIP_SETRES_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define PRE_DS_PIP_04_PRE_DSCALE_H_BYPASS_2 Fld(1,1,AC_MSKB0)//[1:1]
    #define PRE_DS_PIP_04_PRE_DSCALE_V_BYPASS_2 Fld(1,0,AC_MSKB0)//[0:0]
#define PRE_DS_PIP_06 (IO_PRE_DS_BASE + 0x368)
    #define PRE_DS_PIP_06_PIP_H_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_06_PIP_H_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_07 (IO_PRE_DS_BASE + 0x36C)
    #define PRE_DS_PIP_07_PIP_V_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_07_PIP_V_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_08 (IO_PRE_DS_BASE + 0x370)
    #define PRE_DS_PIP_08_PRE_DSCALE_V_INIT_BTM_2 Fld(16,16,AC_FULLW32)//[31:16]
#define PRE_DS_PIP_09 (IO_PRE_DS_BASE + 0x374)
    #define PRE_DS_PIP_09_PREDS_3D_FIELD_EN_2 Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_PIP_09_PREDS_3D_FIELD_INV_2 Fld(1,30,AC_MSKB3)//[30:30]
    #define PRE_DS_PIP_09_PREDS_PIP_10BIT_BYPASS Fld(1,29,AC_MSKB3)//[29:29]   //gazelle only

#define HDR_TOP (IO_HDR_BASE + 0x900)
    #define HDR_ATPG_OB Fld(1,31,AC_MSKB3)//[31:31]
    #define HDR_ATPG_CT Fld(1,30,AC_MSKB3)//[30:30]
    #define DBUF_READ_WRK Fld(1,15,AC_MSKB1)//[15:15]
    #define DBUF_PROTECT Fld(1,14,AC_MSKB1)//[14:14]
    #define DBUF_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HDR_INK_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define INK_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define DCM_DIS Fld(1,3,AC_MSKB0)//[3:3]
    #define HDR_RESET Fld(1,2,AC_MSKB0)//[2:2]
    #define HDR_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_RELAY (IO_HDR_BASE + 0x904)
    #define REG_RELAY Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_INTERR (IO_HDR_BASE + 0x908)
    #define INT_BOX_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define INT_HIST_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define INT_OF_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define INT_IF_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_INTSTA (IO_HDR_BASE + 0x90C)
    #define INT_BOX_END Fld(1,3,AC_MSKB0)//[3:3]
    #define INT_HIST_END Fld(1,2,AC_MSKB0)//[2:2]
    #define INT_OF_END Fld(1,1,AC_MSKB0)//[1:1]
    #define INT_IF_END Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_ENGSTA (IO_HDR_BASE + 0x910)
    #define STA_CSR_UNF Fld(1,2,AC_MSKB0)//[2:2]
    #define STA_OF_UNF Fld(1,1,AC_MSKB0)//[1:1]
    #define STA_IF_UNF Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_SIZE_0 (IO_HDR_BASE + 0x914)
    #define HDR_IN_VSIZE Fld(13,16,AC_MSKW32)//[28:16]
    #define HDR_IN_HSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_HIST_CTRL_0 (IO_HDR_BASE + 0x920)
    #define HIST_DB_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HIST_BEGIN_Y Fld(13,16,AC_MSKW32)//[28:16]
    #define HIST_BEGIN_X Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_HIST_CTRL_1 (IO_HDR_BASE + 0x924)
    #define HIST_END_Y Fld(13,16,AC_MSKW32)//[28:16]
    #define HIST_END_X Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_DEMO_CTRL_0 (IO_HDR_BASE + 0x928)
    #define DEMO_BEGIN_Y Fld(13,16,AC_MSKW32)//[28:16]
    #define DEMO_BEGIN_X Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_DEMO_CTRL_1 (IO_HDR_BASE + 0x92C)
    #define HDR_DEMO_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define DEMO_SEL Fld(1,30,AC_MSKB3)//[30:30]
    #define DEMO_END_Y Fld(13,16,AC_MSKW32)//[28:16]
    #define DEMO_END_X Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_3X3_COEF_00 (IO_HDR_BASE + 0x930)
    #define GAMUT_ROUND_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define GAMUT_MATRIX_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_3X3_COEF_01 (IO_HDR_BASE + 0x934)
    #define C00 Fld(17,0,AC_MSKDW)//[16:0]
#define HDR_3X3_COEF_02 (IO_HDR_BASE + 0x938)
    #define C01 Fld(17,0,AC_MSKDW)//[16:0]
#define HDR_3X3_COEF_03 (IO_HDR_BASE + 0x93C)
    #define C02 Fld(17,0,AC_MSKDW)//[16:0]
#define HDR_3X3_COEF_04 (IO_HDR_BASE + 0x940)
    #define C10 Fld(17,0,AC_MSKDW)//[16:0]
#define HDR_3X3_COEF_05 (IO_HDR_BASE + 0x944)
    #define C11 Fld(17,0,AC_MSKDW)//[16:0]
#define HDR_3X3_COEF_06 (IO_HDR_BASE + 0x948)
    #define C12 Fld(17,0,AC_MSKDW)//[16:0]
#define HDR_3X3_COEF_07 (IO_HDR_BASE + 0x94C)
    #define C20 Fld(17,0,AC_MSKDW)//[16:0]
#define HDR_3X3_COEF_08 (IO_HDR_BASE + 0x950)
    #define C21 Fld(17,0,AC_MSKDW)//[16:0]
#define HDR_3X3_COEF_09 (IO_HDR_BASE + 0x954)
    #define C22 Fld(17,0,AC_MSKDW)//[16:0]
#define HDR_3X3_COEF_10 (IO_HDR_BASE + 0x958)
    #define PRE_ADD_0 Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_3X3_COEF_11 (IO_HDR_BASE + 0x95C)
    #define PRE_ADD_1 Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_3X3_COEF_12 (IO_HDR_BASE + 0x960)
    #define PRE_ADD_2 Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_3X3_COEF_13 (IO_HDR_BASE + 0x964)
    #define POST_ADD_0 Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_3X3_COEF_14 (IO_HDR_BASE + 0x968)
    #define POST_ADD_1 Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_3X3_COEF_15 (IO_HDR_BASE + 0x96C)
    #define POST_ADD_2 Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_TONE_MAP_P01 (IO_HDR_BASE + 0x970)
    #define REG_P2 Fld(16,16,AC_FULLW32)//[31:16]
    #define REG_P1 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_TONE_MAP_P02 (IO_HDR_BASE + 0x974)
    #define REG_P4 Fld(16,16,AC_FULLW32)//[31:16]
    #define REG_P3 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_TONE_MAP_P03 (IO_HDR_BASE + 0x978)
    #define REG_P6 Fld(16,16,AC_FULLW32)//[31:16]
    #define REG_P5 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_TONE_MAP_P04 (IO_HDR_BASE + 0x97C)
    #define REG_P8 Fld(16,16,AC_FULLW32)//[31:16]
    #define REG_P7 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_TONE_MAP_P05 (IO_HDR_BASE + 0x980)
    #define REG_P10 Fld(16,16,AC_FULLW32)//[31:16]
    #define REG_P9 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_TONE_MAP_P06 (IO_HDR_BASE + 0x984)
    #define REG_P12 Fld(16,16,AC_FULLW32)//[31:16]
    #define REG_P11 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_TONE_MAP_P07 (IO_HDR_BASE + 0x988)
    #define REG_P14 Fld(16,16,AC_FULLW32)//[31:16]
    #define REG_P13 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_TONE_MAP_P08 (IO_HDR_BASE + 0x98C)
    #define REG_P16 Fld(16,16,AC_FULLW32)//[31:16]
    #define REG_P15 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_TONE_MAP_S00 (IO_HDR_BASE + 0x990)
    #define REG_SLOPE0 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S01 (IO_HDR_BASE + 0x994)
    #define REG_SLOPE1 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S02 (IO_HDR_BASE + 0x998)
    #define REG_SLOPE2 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S03 (IO_HDR_BASE + 0x99C)
    #define REG_SLOPE3 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S04 (IO_HDR_BASE + 0x9A0)
    #define REG_SLOPE4 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S05 (IO_HDR_BASE + 0x9A4)
    #define REG_SLOPE5 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S06 (IO_HDR_BASE + 0x9A8)
    #define REG_SLOPE6 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S07 (IO_HDR_BASE + 0x9AC)
    #define REG_SLOPE7 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S08 (IO_HDR_BASE + 0x9B0)
    #define REG_SLOPE8 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S09 (IO_HDR_BASE + 0x9B4)
    #define REG_SLOPE9 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S10 (IO_HDR_BASE + 0x9B8)
    #define REG_SLOPE10 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S11 (IO_HDR_BASE + 0x9BC)
    #define REG_SLOPE11 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S12 (IO_HDR_BASE + 0x9C0)
    #define REG_SLOPE12 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S13 (IO_HDR_BASE + 0x9C4)
    #define REG_SLOPE13 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S14 (IO_HDR_BASE + 0x9C8)
    #define REG_SLOPE14 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_TONE_MAP_S15 (IO_HDR_BASE + 0x9CC)
    #define REG_SLOPE15 Fld(19,0,AC_MSKDW)//[18:0]
#define HDR_B_CHANNEL_NR (IO_HDR_BASE + 0x9D0)
    #define REG_NR_STRENGTH Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_FILTER_NO Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_NR_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_HIST_ADDR (IO_HDR_BASE + 0x9D4)
    #define HIST_PING_PONG_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HIST_MSB_SHIFT_VALID Fld(1,29,AC_MSKB3)//[29:29]
    #define HIST_MSB_SHIFT Fld(5,24,AC_MSKB3)//[28:24]
    #define LAST_NON_ZERO_BIN Fld(6,16,AC_MSKB2)//[21:16]
    #define HIST_READ_FULL Fld(1,13,AC_MSKB1)//[13:13]
    #define HIST_ADDR_AUTO_INC_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HIST_ADDR_AUTO_INC_RW Fld(1,10,AC_MSKB1)//[10:10]
    #define HIST_CLR_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_HIST_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HIST_ADDR Fld(6,0,AC_MSKB0)//[5:0]
#define HDR_HIST_DATA (IO_HDR_BASE + 0x9D8)
    #define HIST_DATA Fld(32,0,AC_FULLDW)//[31:0]
#define HDR_A_LUMINANCE (IO_HDR_BASE + 0x9DC)
    #define LUT_INTEGER_PART_BITS Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_MAXRGB_WEIGHT Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_LUMA_GAIN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_GAIN_TABLE_0 (IO_HDR_BASE + 0x9E0)
    #define GAIN_TABLE_PING_PONG_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define GAIN_TABLE_ODD_WEN Fld(1,15,AC_MSKB1)//[15:15]
    #define GAIN_TABLE_EVEN_WEN Fld(1,14,AC_MSKB1)//[14:14]
    #define GAIN_TABLE_ADDR_AUTO_INC_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define GAIN_TABLE_ADDR_AUTO_INC_RW Fld(1,12,AC_MSKB1)//[12:12]
    #define GAIN_TABLE_UPDATE Fld(1,11,AC_MSKB1)//[11:11]
    #define GAIN_TABLE_ADDR Fld(9,0,AC_MSKW10)//[8:0]
#define HDR_GAIN_TABLE_1 (IO_HDR_BASE + 0x9E4)
    #define GAIN_TABLE_DATA_EVEN Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_GAIN_TABLE_2 (IO_HDR_BASE + 0x9E8)
    #define GAIN_TABLE_DATA_ODD Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_LBOX_DET_1 (IO_HDR_BASE + 0x9F0)
    #define BLACK_Y_LEVEL Fld(8,8,AC_FULLB1)//[15:8]
    #define OUTPUT_OFFSET Fld(4,4,AC_MSKB0)//[7:4]
    #define LBOX_DET_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_LBOX_DET_2 (IO_HDR_BASE + 0x9F4)
    #define RT_SKIP Fld(13,16,AC_MSKW32)//[28:16]
    #define LF_SKIP Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_LBOX_DET_3 (IO_HDR_BASE + 0x9F8)
    #define LBOX_DB_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define DN_SKIP Fld(13,16,AC_MSKW32)//[28:16]
    #define UP_SKIP Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_LBOX_DET_4 (IO_HDR_BASE + 0x9FC)
    #define DNPOS Fld(13,16,AC_MSKW32)//[28:16]
    #define UPPOS Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_CURSOR_CTRL (IO_HDR_BASE + 0xA00)
    #define CURSOR_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define CURSOR_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_CURSOR_POS (IO_HDR_BASE + 0xA04)
    #define CURSOR_TARGV Fld(13,16,AC_MSKW32)//[28:16]
    #define CURSOR_TARGH Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_CURSOR_COLOR (IO_HDR_BASE + 0xA08)
    #define CURSOR_CR Fld(4,8,AC_MSKB1)//[11:8]
    #define CURSOR_CB Fld(4,4,AC_MSKB0)//[7:4]
    #define CURSOR_Y Fld(4,0,AC_MSKB0)//[3:0]
#define HDR_CURSOR_BUF0 (IO_HDR_BASE + 0xA10)
    #define CURSOR_BUFFER0 Fld(32,0,AC_FULLDW)//[31:0]
#define HDR_CURSOR_BUF1 (IO_HDR_BASE + 0xA14)
    #define CURSOR_BUFFER1 Fld(32,0,AC_FULLDW)//[31:0]
#define HDR_CURSOR_BUF2 (IO_HDR_BASE + 0xA18)
    #define CURSOR_BUFFER2 Fld(32,0,AC_FULLDW)//[31:0]
#define HDR_R2Y_00 (IO_HDR_BASE + 0xA1C)
    #define R2Y_C01 Fld(16,16,AC_FULLW32)//[31:16]
    #define R2Y_C00 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_R2Y_01 (IO_HDR_BASE + 0xA20)
    #define R2Y_C10 Fld(16,16,AC_FULLW32)//[31:16]
    #define R2Y_C02 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_R2Y_02 (IO_HDR_BASE + 0xA24)
    #define R2Y_C12 Fld(16,16,AC_FULLW32)//[31:16]
    #define R2Y_C11 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_R2Y_03 (IO_HDR_BASE + 0xA28)
    #define R2Y_C21 Fld(16,16,AC_FULLW32)//[31:16]
    #define R2Y_C20 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_R2Y_04 (IO_HDR_BASE + 0xA2C)
    #define R2Y_C22 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_R2Y_05 (IO_HDR_BASE + 0xA30)
    #define R2Y_PRE_ADD_1 Fld(13,16,AC_MSKW32)//[28:16]
    #define R2Y_PRE_ADD_0 Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_R2Y_06 (IO_HDR_BASE + 0xA34)
    #define R2Y_PRE_ADD_2 Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_R2Y_07 (IO_HDR_BASE + 0xA38)
    #define R2Y_POST_ADD_1 Fld(11,16,AC_MSKW32)//[26:16]
    #define R2Y_POST_ADD_0 Fld(11,0,AC_MSKW10)//[10:0]
#define HDR_R2Y_08 (IO_HDR_BASE + 0xA3C)
    #define R2Y_POST_ADD_2 Fld(11,0,AC_MSKW10)//[10:0]
#define HDR_R2Y_09 (IO_HDR_BASE + 0xA40)
    #define R2Y_OUTPUT_FORMAT Fld(2,2,AC_MSKB0)//[3:2]
    #define R2Y_ROUND_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define R2Y_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_Y2R_00 (IO_HDR_BASE + 0xA44)
    #define Y2R_C01 Fld(16,16,AC_FULLW32)//[31:16]
    #define Y2R_C00 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_Y2R_01 (IO_HDR_BASE + 0xA48)
    #define Y2R_C10 Fld(16,16,AC_FULLW32)//[31:16]
    #define Y2R_C02 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_Y2R_02 (IO_HDR_BASE + 0xA4C)
    #define Y2R_C12 Fld(16,16,AC_FULLW32)//[31:16]
    #define Y2R_C11 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_Y2R_03 (IO_HDR_BASE + 0xA50)
    #define Y2R_C21 Fld(16,16,AC_FULLW32)//[31:16]
    #define Y2R_C20 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_Y2R_04 (IO_HDR_BASE + 0xA54)
    #define Y2R_C22 Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_Y2R_05 (IO_HDR_BASE + 0xA5C)
    #define Y2R_PRE_ADD_1 Fld(11,16,AC_MSKW32)//[26:16]
    #define Y2R_PRE_ADD_0 Fld(11,0,AC_MSKW10)//[10:0]
#define HDR_Y2R_06 (IO_HDR_BASE + 0xA60)
    #define Y2R_PRE_ADD_2 Fld(11,0,AC_MSKW10)//[10:0]
#define HDR_Y2R_07 (IO_HDR_BASE + 0xA64)
    #define Y2R_POST_ADD_1 Fld(13,16,AC_MSKW32)//[28:16]
    #define Y2R_POST_ADD_0 Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_Y2R_08 (IO_HDR_BASE + 0xA68)
    #define Y2R_POST_ADD_2 Fld(13,0,AC_MSKW10)//[12:0]
#define HDR_Y2R_09 (IO_HDR_BASE + 0xA6C)
    #define Y2R_INPUT_FORMAT Fld(3,2,AC_MSKB0)//[4:2]
    #define Y2R_ROUND_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define Y2R_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_Y2R_10 (IO_HDR_BASE + 0xA70)
    #define Y2R_C21_SP Fld(16,16,AC_FULLW32)//[31:16]
    #define Y2R_C02_SP Fld(16,0,AC_FULLW10)//[15:0]
#define HDR_PROG_EOTF_0 (IO_HDR_BASE + 0xA74)
    #define LAST_EOTF_ELEMENTR Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_PROG_EOTF_1 (IO_HDR_BASE + 0xA78)
    #define LAST_EOTF_POSR Fld(11,0,AC_MSKW10)//[10:0]
#define HDR_PROG_EOTF_2 (IO_HDR_BASE + 0xA7C)
    #define LAST_EOTF_ELEMENTG Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_PROG_EOTF_3 (IO_HDR_BASE + 0xA80)
    #define LAST_EOTF_POSG Fld(11,0,AC_MSKW10)//[10:0]
#define HDR_PROG_EOTF_4 (IO_HDR_BASE + 0xA84)
    #define LAST_EOTF_ELEMENTB Fld(23,0,AC_MSKDW)//[22:0]
#define HDR_PROG_EOTF_5 (IO_HDR_BASE + 0xA88)
    #define LAST_EOTF_POSB Fld(11,0,AC_MSKW10)//[10:0]
#define HDR_EOTF_TABLE_0 (IO_HDR_BASE + 0xA8C)
    #define EOTF_TABLE_PING_PONG_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define EOTF_TABLE_SEP_MODE Fld(2,26,AC_MSKB3)//[27:26]
    #define EOTF_TABLE_ODD_WEN Fld(1,15,AC_MSKB1)//[15:15]
    #define EOTF_TABLE_EVEN_WEN Fld(1,14,AC_MSKB1)//[14:14]
    #define EOTF_TABLE_ADDR_AUTO_INC_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define EOTF_TABLE_ADDR_AUTO_INC_RW Fld(1,12,AC_MSKB1)//[12:12]
    #define EOTF_TABLE_UPDATE Fld(1,11,AC_MSKB1)//[11:11]
    #define EOTF_TABLE_ADDR Fld(9,0,AC_MSKW10)//[8:0]
#define HDR_EOTF_TABLE_1 (IO_HDR_BASE + 0xA90)
    #define EOTF_TABLE_DATA_EVEN Fld(22,0,AC_MSKDW)//[21:0]
#define HDR_EOTF_TABLE_2 (IO_HDR_BASE + 0xA94)
    #define EOTF_TABLE_DATA_ODD Fld(22,0,AC_MSKDW)//[21:0]
#define HDR_OETF_TABLE_0 (IO_HDR_BASE + 0xA9C)
    #define OETF_TABLE_PING_PONG_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define OETF_TABLE_SEP_MODE Fld(2,26,AC_MSKB3)//[27:26]
    #define OETF_TABLE_ODD_WEN Fld(1,15,AC_MSKB1)//[15:15]
    #define OETF_TABLE_EVEN_WEN Fld(1,14,AC_MSKB1)//[14:14]
    #define OETF_TABLE_ADDR_AUTO_INC_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define OETF_TABLE_ADDR_AUTO_INC_RW Fld(1,12,AC_MSKB1)//[12:12]
    #define OETF_TABLE_UPDATE Fld(1,11,AC_MSKB1)//[11:11]
    #define OETF_TABLE_ADDR Fld(10,0,AC_MSKW10)//[9:0]
#define HDR_OETF_TABLE_1 (IO_HDR_BASE + 0xAA0)
    #define OETF_TABLE_DATA Fld(32,0,AC_FULLDW)//[31:0]
#define TONE_MAP_TOP (IO_HDR_BASE + 0xAA4)
    #define TONE_MAP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_EOTF_ACCURACY_0 (IO_HDR_BASE + 0xAA8)
    #define EOTF_ACCURACY_CONTROL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_EOTF_ACCURACY_1 (IO_HDR_BASE + 0xAAC)
    #define EOTF_ACCURACY_CONTROL_P2 Fld(10,16,AC_MSKW32)//[25:16]
    #define EOTF_ACCURACY_CONTROL_P1 Fld(10,0,AC_MSKW10)//[9:0]
#define HDR_EOTF_ACCURACY_2 (IO_HDR_BASE + 0xAB0)
    #define EOTF_ACCURACY_CONTROL_P4 Fld(10,16,AC_MSKW32)//[25:16]
    #define EOTF_ACCURACY_CONTROL_P3 Fld(10,0,AC_MSKW10)//[9:0]
#define HDR_L_MIX_0 (IO_HDR_BASE + 0xAB4)
    #define MIN_MIXING_RATIO Fld(4,4,AC_MSKB0)//[7:4]
    #define ADAPTIVE_L_MIX_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HDR_L_MIX_1 (IO_HDR_BASE + 0xAB8)
    #define T1 Fld(10,0,AC_MSKW10)//[9:0]
#define HDR_L_MIX_2 (IO_HDR_BASE + 0xABC)
    #define T2 Fld(10,0,AC_MSKW10)//[9:0]
#define HDR_Y_GAIN_IDX_0 (IO_HDR_BASE + 0xAC0)
    #define Y_G_COEF Fld(11,16,AC_MSKW32)//[26:16]
    #define Y_R_COEF Fld(11,0,AC_MSKW10)//[10:0]
#define HDR_Y_GAIN_IDX_1 (IO_HDR_BASE + 0xAC4)
    #define Y_B_COEF Fld(11,0,AC_MSKW10)//[10:0]
#define HDR_DUMMY0 (IO_HDR_BASE + 0xAC8)
    #define REG_DUMMY0 Fld(32,0,AC_FULLDW)//[31:0]
#define HDR_DUMMY1 (IO_HDR_BASE + 0xACC)
    #define REG_DUMMY1 Fld(32,0,AC_FULLDW)//[31:0]
#define HDR_DUMMY2 (IO_HDR_BASE + 0xAD0)
    #define REG_DUMMY2 Fld(32,0,AC_FULLDW)//[31:0]
#define HDR_HLG_SG (IO_HDR_BASE + 0xAD4)
    #define HLG_BETA Fld(16,0,AC_FULLW10)//[15:0]
    
#define HDR2SDR_NXNR_YC2YUV (IO_HDR_BASE + 0xAF0)
    #define C_YC2YUV_H_BOUND Fld(12,8,AC_MSKW21)//[19:8]
    #define C_YC2YUV_H_BOUND_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define C_YC2YUV_MIRROR_422 Fld(2,2,AC_MSKB0)//[3:2]
    #define C_YC2YUV_UVINV Fld(1,1,AC_MSKB0)//[1:1]
    #define C_YC2YUV_SEL444 Fld(1,0,AC_MSKB0)//[0:0]
#define HDR2SDR_NXNR_YUV2YC (IO_HDR_BASE + 0xAF4)
    #define C_YUV2YC_SEL444 Fld(1,2,AC_MSKB0)//[2:2]
    #define C_YUV2YC_UVINV Fld(1,1,AC_MSKB0)//[1:1]
    #define C_YUV2YC_OPTION Fld(1,0,AC_MSKB0)//[0:0]
#define HDR2SDR_NXNR_CTRL_0 (IO_HDR_BASE + 0xAF8)
    #define YC2YUV_DB_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HDR2SDR_NXNR_DB_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define NXNR_HDR_FIFO_RESET Fld(1,1,AC_MSKB0)//[1:1]
    #define C_HDR2SDR_NXNR_BYPASS_0 Fld(1,0,AC_MSKB0)//[0:0]
#define HDR2SDR_NXNR_ATPG (IO_HDR_BASE + 0xAFC)
    #define HDR2SDR_NXNR_ATPG_OB Fld(1,1,AC_MSKB0)//[1:1]
    #define HDR2SDR_NXNR_ATPG_CT Fld(1,0,AC_MSKB0)//[0:0]

#define HDR_8K_CTRL_0 (IO_HDR_BASE + 0xDE4)
    #define C_HDR_8K_SOF_LENGTH Fld(4,4,AC_MSKB0)//[7:4]
    #define C_HDR_8K_SOF_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HDR2SDR_CTRL_0 (IO_HDR_BASE + 0xDE8)
    #define HDR2SDR_DB_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HDR_8K_FIFO_RESET Fld(1,9,AC_MSKB1)//[9:9]
    #define C_8K_HDR_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define PIP_HDR_FIFO_RESET Fld(1,5,AC_MSKB0)//[5:5]
    #define C_HDR2SDR_PIP_BYPASS Fld(1,4,AC_MSKB0)//[4:4]
    #define MAIN_HDR_FIFO_RESET Fld(1,2,AC_MSKB0)//[2:2]
    #define C_HDR2SDR_MAIN_BYPASS_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define C_HDR2SDR_MAIN_BYPASS_0 Fld(1,0,AC_MSKB0)//[0:0]
#define HDR2SDR_DITHER_00 (IO_HDR_BASE + 0xDEC)
    #define SUB_HDR_REG_FPHASE_BIT Fld(3,29,AC_MSKB3)//[31:29]
    #define SUB_HDR_REG_FPHASE_SEL Fld(2,27,AC_MSKB3)//[28:27]
    #define SUB_HDR_REG_FPHASE_CTRL Fld(2,25,AC_MSKB3)//[26:25]
    #define SUB_HDR_FPHASE Fld(6,19,AC_MSKW32)//[24:19]
    #define SUB_HDR_REG_FPHASE_R Fld(1,18,AC_MSKB2)//[18:18]
    #define SUB_HDR_REG_FPHASE_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define SUB_HDR_REG_SUB_B Fld(2,15,AC_MSKW21)//[16:15]
    #define SUB_HDR_REG_SUB_G Fld(2,13,AC_MSKB1)//[14:13]
    #define SUB_HDR_REG_SUB_R Fld(2,11,AC_MSKB1)//[12:11]
    #define SUB_HDR_REG_SUBPIX_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define SUB_HDR_REG_TABLE_EN Fld(2,8,AC_MSKB1)//[9:8]
    #define SUB_HDR_REG_TWO_CH_LR Fld(1,7,AC_MSKB0)//[7:7]
    #define SUB_HDR_DITHER_LFSR_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define SUB_HDR_RDITHER_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define SUB_HDR_EDITHER_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define SUB_HDR_ROUND_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define SUB_HDR_REG_LEFT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define SUB_HDR_REG_SUBSAMPLE_MODE Fld(2,0,AC_MSKB0)//[1:0]
#define HDR2SDR_DITHER_01 (IO_HDR_BASE + 0xDF0)
    #define SUB_HDR_REG_INK_DATA_G Fld(12,16,AC_MSKW32)//[27:16]
    #define SUB_HDR_REG_INK_DATA_R Fld(12,0,AC_MSKW10)//[11:0]
#define HDR2SDR_DITHER_02 (IO_HDR_BASE + 0xDF4)
    #define SUB_HDR_REG_INK Fld(1,31,AC_MSKB3)//[31:31]
    #define SUB_HDR_LSB_OFF Fld(1,30,AC_MSKB3)//[30:30]
    #define SUB_HDR_DRMOD_B Fld(2,16,AC_MSKB2)//[17:16]
    #define SUB_HDR_DRMOD_G Fld(2,14,AC_MSKB1)//[15:14]
    #define SUB_HDR_DRMOD_R Fld(2,12,AC_MSKB1)//[13:12]
    #define SUB_HDR_REG_INK_DATA_B Fld(12,0,AC_MSKW10)//[11:0]
#define HDR2SDR_DITHER_03 (IO_HDR_BASE + 0xDF8)
    #define SUB_HDR_DITHER_DB_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define SUB_HDR_REG_H_ACTIVE Fld(16,0,AC_FULLW10)//[15:0]
#define HDR2SDR_ATPG (IO_HDR_BASE + 0xDFC)
    #define HDR2SDR_ATPG_OB Fld(1,1,AC_MSKB0)//[1:1]
    #define HDR2SDR_ATPG_CT Fld(1,0,AC_MSKB0)//[0:0]

#endif    
