/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef CEC_HW_IF
#define CEC_HW_IF
#define CEC_IO_BASE (IO_VIRT + 0x20000)
#define TR_CONFIG (CEC_IO_BASE + 0x8500)
 #define TR_CONFIG_0 (CEC_IO_BASE + 0x8500)
 #define TR_CONFIG_1 (CEC_IO_BASE + 0x8501)
 #define TR_CONFIG_2 (CEC_IO_BASE +0x8502)
 #define TR_CONFIG_3 (CEC_IO_BASE +0x8503)
    #define BYPASS Fld(1, 28, AC_MSKB3) //28
    #define DEVICE_ADDR3 Fld(4, 24, AC_MSKB3) //27:24
    #define DEVICE_ADDR2 Fld(4, 20, AC_MSKB2) //23:20
    #define DEVICE_ADDR1 Fld(4, 16, AC_MSKB2) //19:16
    #define TX_EN Fld(1, 12, AC_MSKB1) //12
    #define RX_EN Fld(1, 8, AC_MSKB1) //8
    #define TX_INT_EN1 Fld(1,7,AC_MSKB0)//[7:7]
    #define TX_INT_EN0 Fld(1,6,AC_MSKB0)//[6:6]
    #define RX_INT_EN1 Fld(1,5,AC_MSKB0)//[5:5]
    #define RX_INT_EN0 Fld(1,4,AC_MSKB0)//[4:4]
    #define CEC_ENABLE Fld(1, 0, AC_MSKB0) //0
#define CKGEN (CEC_IO_BASE +0x8504)
 #define CKGEN_0 (CEC_IO_BASE +0x8504)
 #define CKGEN_1 (CEC_IO_BASE +0x8505)
 #define CKGEN_2 (CEC_IO_BASE +0x8506)
 #define CKGEN_3 (CEC_IO_BASE +0x8507)
    #define PDN Fld(1, 16, AC_MSKB2) //16
    #define DIV_SEL Fld(16, 0, AC_FULLW10) //15:0
#define RX_T_START_R (CEC_IO_BASE +0x8508)
 #define RX_T_START_R_0 (CEC_IO_BASE +0x8508)
 #define RX_T_START_R_1 (CEC_IO_BASE +0x8509)
 #define RX_T_START_R_2 (CEC_IO_BASE +0x850a)
 #define RX_T_START_R_3 (CEC_IO_BASE +0x850b)
    #define RX_TIMER_START_R_MAX Fld(11, 16, AC_MSKW32) //26:16
    #define RX_TIMER_START_R_MIN Fld(11, 0, AC_MSKW10) //10:0
#define RX_T_START_F (CEC_IO_BASE +0x850c)
 #define RX_T_START_F_0 (CEC_IO_BASE +0x850c)
 #define RX_T_START_F_1 (CEC_IO_BASE +0x850d)
 #define RX_T_START_F_2 (CEC_IO_BASE +0x850e)
 #define RX_T_START_F_3 (CEC_IO_BASE +0x850f)
    #define RX_TIMER_START_F_MAX Fld(11, 16, AC_MSKW32) //26:16
    #define RX_TIMER_START_F_MIN Fld(11, 0, AC_MSKW10) //10:0
#define RX_T_DATA (CEC_IO_BASE +0x8510)
 #define RX_T_DATA_0 (CEC_IO_BASE +0x8510)
 #define RX_T_DATA_1 (CEC_IO_BASE +0x8511)
 #define RX_T_DATA_2 (CEC_IO_BASE +0x8512)
 #define RX_T_DATA_3 (CEC_IO_BASE +0x8513)
    #define RX_TIMER_DATA_SAMPLE Fld(11, 16, AC_MSKW32) //26:16
    #define RX_TIMER_DATA_F_MIN Fld(11, 0, AC_MSKW10) //10:0
#define RX_T_ACK (CEC_IO_BASE +0x8514)
 #define RX_T_ACK_0 (CEC_IO_BASE +0x8514)
 #define RX_T_ACK_1 (CEC_IO_BASE +0x8515)
 #define RX_T_ACK_2 (CEC_IO_BASE +0x8516)
 #define RX_T_ACK_3 (CEC_IO_BASE +0x8517)
    #define RX_TIMER_ACK_R Fld(11, 0, AC_MSKW10) //10:0
#define RX_T_ERROR (CEC_IO_BASE +0x8518)
 #define RX_T_ERROR_0 (CEC_IO_BASE +0x8518)
 #define RX_T_ERROR_1 (CEC_IO_BASE +0x8519)
 #define RX_T_ERROR_2 (CEC_IO_BASE +0x851a)
 #define RX_T_ERROR_3 (CEC_IO_BASE +0x851b)
    #define RX_TIMER_ERROR_D Fld(11, 16, AC_MSKW32) //26:16
    #define RX_TIMER_ERROR_S Fld(11, 0, AC_MSKW10) //10:0
#define TX_T_START (CEC_IO_BASE +0x851c)
 #define TX_T_START_0 (CEC_IO_BASE +0x851c)
 #define TX_T_START_1 (CEC_IO_BASE +0x851d)
 #define TX_T_START_2 (CEC_IO_BASE +0x851e)
 #define TX_T_START_3 (CEC_IO_BASE +0x851f)
    #define TX_TIMER_START_F Fld(11, 16, AC_MSKW32) //26:16
    #define TX_TIMER_START_R Fld(11, 0, AC_MSKW10) //10:0
#define TX_T_DATA_R (CEC_IO_BASE +0x8520)
 #define TX_T_DATA_R_0 (CEC_IO_BASE +0x8520)
 #define TX_T_DATA_R_1 (CEC_IO_BASE +0x8521)
 #define TX_T_DATA_R_2 (CEC_IO_BASE +0x8522)
 #define TX_T_DATA_R_3 (CEC_IO_BASE +0x8523)
    #define TX_TIMER_BIT1_R Fld(11, 16, AC_MSKW32) //26:16
    #define TX_TIMER_BIT0_R Fld(11, 0, AC_MSKW10) //10:0
#define TX_T_DATA_F (CEC_IO_BASE +0x8524)
 #define TX_T_DATA_F_0 (CEC_IO_BASE +0x8524)
 #define TX_T_DATA_F_1 (CEC_IO_BASE +0x8525)
 #define TX_T_DATA_F_2 (CEC_IO_BASE +0x8526)
 #define TX_T_DATA_F_3 (CEC_IO_BASE +0x8527)
    #define TX_TIMER_DATA_N Fld(11, 16, AC_MSKW32) //26:16
    #define TX_TIMER_DATA_F Fld(11, 0, AC_MSKW10) //10:0
#define TX_ARB (CEC_IO_BASE +0x8528)
 #define TX_ARB_0 (CEC_IO_BASE +0x8528)
 #define TX_ARB_1 (CEC_IO_BASE +0x8529)
 #define TX_ARB_2 (CEC_IO_BASE +0x852a)
 #define TX_ARB_3 (CEC_IO_BASE +0x852b)
    #define TX_INPUT_DELAY Fld(5, 25, AC_MSKB3) //29:25
    #define RX_CHK_DST Fld(1, 24, AC_MSKB3) //24
    #define TX_LEAVE_FAIL Fld(1, 17, AC_MSKB2) //17
    #define TX_NEW_RETRY_CNT Fld(1, 16, AC_MSKB2) //16
    #define MAX_RETRANSMIT Fld(4, 12, AC_MSKB1) //15:12
    #define BCNT_RETRANSMIT Fld(4, 8, AC_MSKB1) //11:8
    #define BCNT_NEW_MSG Fld(4, 4, AC_MSKB0) //7:4
    #define BCNT_NEW_INIT Fld(4, 0, AC_MSKB0) //3:0

 #define RX_HEADER (CEC_IO_BASE +0x852c)
 #define RX_HEADER_0 (CEC_IO_BASE +0x852c)
 #define RX_HEADER_1 (CEC_IO_BASE +0x852d)
 #define RX_HEADER_2 (CEC_IO_BASE +0x852e)
 #define RX_HEADER_3 (CEC_IO_BASE +0x852f)
    #define RXED_M3_DATA_MASK Fld(4, 24, AC_MSKB3) //27:24
    #define RXED_SRC Fld(4, 20, AC_MSKB2) //23:20
    #define RXED_DST Fld(4, 16, AC_MSKB2) //19:16
    #define RXED_H_EOM Fld(1, 15, AC_MSKB1) //15
    #define RXED_D_EOM Fld(1, 13, AC_MSKB1) //13

 #define RX_DATA (CEC_IO_BASE +0x8530)
 #define RX_DATA_0 (CEC_IO_BASE +0x8530)
 #define RX_DATA_1 (CEC_IO_BASE +0x8531)
 #define RX_DATA_2 (CEC_IO_BASE +0x8532)
 #define RX_DATA_3 (CEC_IO_BASE +0x8533)
    #define RXED_DATA Fld(32, 0, AC_FULLDW) //31:0

 #define RX_HD_NEXT (CEC_IO_BASE +0x8534)
 #define RX_HD_NEXT_0 (CEC_IO_BASE +0x8534)
 #define RX_HD_NEXT_1 (CEC_IO_BASE +0x8535)
 #define RX_HD_NEXT_2 (CEC_IO_BASE +0x8536)
 #define RX_HD_NEXT_3 (CEC_IO_BASE +0x8537)
    #define RXING_M3_DATA_MASK Fld(4, 24, AC_MSKB3) //27:24
    #define RXING_SRC Fld(4, 20, AC_MSKB2) //23:20
    #define RXING_DST Fld(4, 16, AC_MSKB2) //19:16
    #define RXING_H_EOM Fld(1, 15, AC_MSKB1) //15
    #define RXING_H_ACK Fld(1, 14, AC_MSKB1) //14
    #define RXING_D_EOM Fld(1, 13, AC_MSKB1) //13
    #define RXING_D_ACK Fld(1, 12, AC_MSKB1) //12

 #define RX_DATA_NEXT (CEC_IO_BASE +0x8538)
 #define RX_DATA_NEXT_0 (CEC_IO_BASE +0x8538)
 #define RX_DATA_NEXT_1 (CEC_IO_BASE +0x8539)
 #define RX_DATA_NEXT_2 (CEC_IO_BASE +0x853a)
 #define RX_DATA_NEXT_3 (CEC_IO_BASE +0x853b)
    #define RXING_DATA Fld(32, 0, AC_FULLDW) //31:0

 #define RX_EVENT (CEC_IO_BASE +0x8540)
 #define RX_EVENT_0 (CEC_IO_BASE +0x8540)
 #define RX_EVENT_1 (CEC_IO_BASE +0x8541)
 #define RX_EVENT_2 (CEC_IO_BASE +0x8542)
 #define RX_EVENT_3 (CEC_IO_BASE +0x8543)
    #define DATA_RDY Fld(1, 23, AC_MSKB2) //23
    #define HEADER_RDY Fld(1, 22, AC_MSKB2) //22
    #define OV Fld(1, 20, AC_MSKB2) //20
    #define BR_SB_RDY Fld(1, 18, AC_MSKB2) //18
    #define SB_RDY Fld(1, 17, AC_MSKB2) //17
    #define BR_RDY Fld(1, 16, AC_MSKB2) //16
    #define I_EN_DATA Fld(1, 7, AC_MSKB0) //7
    #define I_EN_HEADER Fld(1, 6, AC_MSKB0) //6
    #define I_EN_OV Fld(1, 4, AC_MSKB0) //4
    #define I_EN_PULSE Fld(1, 3, AC_MSKB0) //3
    #define I_EN_BR_SB Fld(1, 2, AC_MSKB0) //2
    #define I_EN_SB  Fld(1, 1, AC_MSKB0) //1
    #define I_EN_BR Fld(1, 0, AC_MSKB0) //0

 #define RX_FAIL (CEC_IO_BASE +0x8544)
 #define RX_FAIL_0 (CEC_IO_BASE +0x8544)
 #define RX_FAIL_1 (CEC_IO_BASE +0x8545)
 #define RX_FAIL_2 (CEC_IO_BASE +0x8546)
 #define RX_FAIL_3 (CEC_IO_BASE +0x8547)
    #define ERR_ONCE Fld(1, 4, AC_MSKB0) // 4
    #define ERR_H Fld(1, 0, AC_MSKB0) //0

 #define RX_STATUS (CEC_IO_BASE +0x8548)
 #define RX_STATUS_0 (CEC_IO_BASE +0x8548)
 #define RX_STATUS_1 (CEC_IO_BASE +0x8549)
 #define RX_STATUS_2 (CEC_IO_BASE +0x854a)
 #define RX_STATUS_3 (CEC_IO_BASE +0x854b)
    #define RX_BIT_COUNTER Fld(4, 28, AC_MSKB3) //31:28
    #define RX_TIMER Fld(11, 16, AC_MSKW32) //26:16
    #define RX_FSM Fld(7, 0, AC_MSKB0) //6:0

 #define TX_HD_NEXT (CEC_IO_BASE +0x854c)
 #define TX_HD_NEXT_0 (CEC_IO_BASE +0x854c)
 #define TX_HD_NEXT_1 (CEC_IO_BASE +0x854d)
 #define TX_HD_NEXT_2 (CEC_IO_BASE +0x854e)
 #define TX_HD_NEXT_3 (CEC_IO_BASE +0x854f)
     #define WTX_M3_DATA_MASK Fld(4, 24, AC_MSKB3) //27:24
    #define WTX_SRC Fld(4, 20, AC_MSKB2) //23:20
    #define WTX_DST Fld(4, 16, AC_MSKB2) //19:16
    #define WTX_H_EOM Fld(1, 15, AC_MSKB1) //15
    #define WTX_D_EOM Fld(1, 13, AC_MSKB1) //13

 #define TX_DATA_NEXT (CEC_IO_BASE +0x8550)
 #define TX_DATA_NEXT_0 (CEC_IO_BASE +0x8550)
 #define TX_DATA_NEXT_1 (CEC_IO_BASE +0x8551)
 #define TX_DATA_NEXT_2 (CEC_IO_BASE +0x8552)
 #define TX_DATA_NEXT_3 (CEC_IO_BASE +0x8553)
     #define WTX_DATA Fld(32, 0, AC_FULLDW) //31:0

 #define TX_HEADER (CEC_IO_BASE +0x8554)
 #define TX_HEADER_0 (CEC_IO_BASE +0x8554)
 #define TX_HEADER_1 (CEC_IO_BASE +0x8555)
 #define TX_HEADER_2 (CEC_IO_BASE +0x8556)
 #define TX_HEADER_3 (CEC_IO_BASE +0x8557)
    #define TXING_M3_DATA_SENT Fld(4, 28, AC_MSKB3) //31:28
    #define TXING_M3_DATA_MASK Fld(4, 24, AC_MSKB3) //27:24
    #define TXING_SRC Fld(4, 20, AC_MSKB2) //23:20
    #define TXING_DST Fld(4, 16, AC_MSKB2) //19:16
    #define TXING_H_EOM Fld(1, 15, AC_MSKB1) //15
    #define TXING_H_ACK Fld(1, 14, AC_MSKB1) //14
    #define TXING_D_EOM Fld(1, 13, AC_MSKB1) //13
    #define TXING_D_ACK Fld(1, 12, AC_MSKB1) //12

 #define TX_DATA (CEC_IO_BASE +0x8558)
 #define TX_DATA_0 (CEC_IO_BASE +0x8558)
 #define TX_DATA_1 (CEC_IO_BASE +0x8559)
 #define TX_DATA_2 (CEC_IO_BASE +0x855a)
 #define TX_DATA_3 (CEC_IO_BASE +0x855b)
     #define TXING_DATA Fld(32, 0, AC_FULLDW) //31:0

 #define TX_EVENT (CEC_IO_BASE +0x8560)
 #define TX_EVENT_0 (CEC_IO_BASE +0x8560)
 #define TX_EVENT_1 (CEC_IO_BASE +0x8561)
 #define TX_EVENT_2 (CEC_IO_BASE +0x8562)
 #define TX_EVENT_3 (CEC_IO_BASE +0x8563)
     #define TX_D_FINISH Fld(1, 21, AC_MSKB2) //21
    #define UN Fld(1, 20, AC_MSKB2) //20
    #define FAIL Fld(1, 19, AC_MSKB2) //19
    #define LOW Fld(1, 18, AC_MSKB2) //18
    #define TX_DATA_FINISH Fld(1, 17, AC_MSKB2) //17
    #define RB_RDY Fld(1, 16, AC_MSKB2) //16
    #define TX_DATA_FIN_E Fld(1, 5, AC_MSKB0) //5
    #define I_EN_UN Fld(1, 4, AC_MSKB0) //4
    #define I_EN_FAIL Fld(1, 3, AC_MSKB0) //3
    #define I_EN_LOW Fld(1, 2, AC_MSKB0) //2
    #define I_EN_BS Fld(1, 1, AC_MSKB0) //1
    #define I_EN_RB Fld(1, 0, AC_MSKB0) //0

 #define TX_FAIL (CEC_IO_BASE +0x8564)
 #define TX_FAIL_0 (CEC_IO_BASE +0x8564)
 #define TX_FAIL_1 (CEC_IO_BASE +0x8565)
 #define TX_FAIL_2 (CEC_IO_BASE +0x8566)
 #define TX_FAIL_3 (CEC_IO_BASE +0x8567)
     #define RETX_MAX Fld(1, 28, AC_MSKB3) //28
    #define DATA Fld(1, 24, AC_MSKB3) //24
    #define HEADER_ACK Fld(1, 17, AC_MSKB2) //17
    #define HEADER Fld(1, 16, AC_MSKB2) //16
    #define SOURCE Fld(1, 12, AC_MSKB1) //12
    #define MODE Fld(1, 4, AC_MSKB0)

 #define TX_STATUS (CEC_IO_BASE +0x8568)
 #define TX_STATUS_0 (CEC_IO_BASE +0x8568)
 #define TX_STATUS_1 (CEC_IO_BASE +0x8569)
 #define TX_STATUS_2 (CEC_IO_BASE +0x856a)
 #define TX_STATUS_3 (CEC_IO_BASE +0x856b)
    #define TX_BIT_COUNTER Fld(4, 22, AC_MSKW10) //25:22
    #define TX_TIMER Fld(11, 10, AC_MSKW32) //20:10
    #define TX_FSM Fld(9, 0, AC_MSKW10) //8:0

 #define TR_TEST (CEC_IO_BASE +0x856c)
 #define TR_TEST_0 (CEC_IO_BASE +0x856c)
 #define TR_TEST_1 (CEC_IO_BASE +0x856d)
 #define TR_TEST_2 (CEC_IO_BASE +0x856e)
 #define TR_TEST_3 (CEC_IO_BASE +0x856f)
    #define TX_EOM_EN Fld(1, 15, AC_MSKB1) //15
    #define TR_TEST_BAK_14 Fld(1, 14, AC_MSKB1) //14
    #define RX_RUNNING_SEL Fld(1, 13, AC_MSKB1) //13
    #define TX_NO_WAIT Fld(1, 12, AC_MSKB1) //12:12
    #define TR_TEST_BAK_11_0 Fld(12, 0, AC_MSKW10) //11:0
#endif /* CEC_HW_IF */
