/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
  *
  * $Author: jiewen.zhou $
  * $Date  $
  * $RCSfile: hw_mlvds.h,v $
  * $Revision: #3 $
  *
  *---------------------------------------------------------------------------*/
  
#ifndef _HW_MLVDS_H_
#define _HW_MLVDS_H_

//******************Page PANEL_INTF*******************************************
#define VINTF_B0 (IO_VIRT + 0x02008600)
    #define VINTF_DISPR_BYPASS Fld(1,27,AC_MSKB3)//[27:27]
    #define VINTF_DISPR_ALLIGH_VS Fld(1,26,AC_MSKB3)//[26:26]
    #define VINTF_HV_HOLD Fld(1,23,AC_MSKB2)//[23:23]
    #define VINTF_HV_BYPASS Fld(1,22,AC_MSKB2)//[22:22]
    #define VINTF_PDP_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define VINTF_LINE_BUFFER_BYPASS Fld(1,16,AC_MSKB2)//[16:16]
    #define VINTF_EH_LATCH_HSYNC Fld(1,11,AC_MSKB1)//[11:11]
#define VINTF_B1 (IO_VIRT + 0x02008604)
    #define VINTF_PTGEN_H_ACTIVE Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_PTGEN_H_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_B2 (IO_VIRT + 0x02008608)
    #define VINTF_PTGEN_V_ACTIVE Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_PTGEN_V_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_B3 (IO_VIRT + 0x0200860C)
    #define VINTF_PTGEN_H_START Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_PTGEN_V_START Fld(12,0,AC_MSKW10)//[11:0]
#define VINTF_B4 (IO_VIRT + 0x02008610)
    #define VINTF_PTGEN_H_WIDTH Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_PTGEN_V_WIDTH Fld(12,0,AC_MSKW10)//[11:0]
#define VINTF_B5 (IO_VIRT + 0x02008614)
    #define VINTF_PTGEN_R Fld(10,20,AC_MSKW32)//[29:20]
    #define VINTF_PTGEN_G Fld(10,10,AC_MSKW21)//[19:10]
    #define VINTF_PTGEN_B Fld(10,0,AC_MSKW10)//[9:0]
#define VINTF_B6 (IO_VIRT + 0x02008618)
	#define VINTF_PTGEN_TYPE_BD_DIS Fld(1,31,AC_MSKB3)//[31:31]
	#define VINTF_PTGEN_TYPE Fld(4,24,AC_MSKB3)//[27:24]
    #define VINTF_INTF_PTGEN_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define VINTF_PTGEN_LLRR Fld(1,20,AC_MSKB2)//[20:20]
    #define VINTF_PTGEN_MIRROR Fld(1,19,AC_MSKB2)//[19:19]
    #define VINTF_PTGEN_SEQ Fld(1,18,AC_MSKB2)//[18:18]
    #define VINTF_PTGEN_2CH_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define VINTF_PTGEN_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define VINTF_PTGEN_SET_DATA_GATE_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define VINTF_PTGEN_SET_DATA Fld(1,14,AC_MSKB1)//[14:14]
    #define VINTF_PTGEN_FIX_DISP_R_VAL Fld(1,13,AC_MSKB1)//[13:13]
    #define VINTF_PTGEN_FIX_DISP_R_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define VINTF_PTGEN_COLOR_BAR_TH Fld(12,0,AC_MSKW10)//[11:0]
#define VINTF_B7 (IO_VIRT + 0x0200861C)
    #define VINTF_LBRB_GRAY Fld(12,20,AC_MSKW32)//[31:20]
    #define VINTF_LBRB_MODE Fld(1,17,AC_MSKB2)//[17:17]
    #define VINTF_LBRB_EN Fld(1,16,AC_MSKB2)//[16:16]
#define VINTF_B8 (IO_VIRT + 0x02008620)
    #define VINTF_PTGEN_BD_R Fld(10,20,AC_MSKW32)//[29:20]
    #define VINTF_PTGEN_BD_G Fld(10,10,AC_MSKW21)//[19:10]
    #define VINTF_PTGEN_BD_B Fld(10,0,AC_MSKW10)//[9:0]
#define VINTF_B9 (IO_VIRT + 0x02008624)
    #define VINTF_PTGEN_H_OSD_INDEX_START Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_PTGEN_H_OSD_INDEX_END Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_B10 (IO_VIRT + 0x02008628)
    #define VINTF_PTGEN_V_OSD_INDEX_START Fld(12,16,AC_MSKW32)//[27:16]
    #define VINTF_PTGEN_V_OSD_INDEX_END Fld(12,0,AC_MSKW10)//[11:0]
#define VINTF_B11 (IO_VIRT + 0x0200862C)
	#define VINTF_OSD_ALPHA_REV Fld(2,30,AC_MSKB3)//[31:30]
    #define VINTF_PTGEN_V_OSD_START Fld(12,16,AC_MSKW32)//[27:16]
    #define VINTF_PTGEN_V_OSD_ACTIVE Fld(12,0,AC_MSKW10)//[11:0]
#define VINTF_B12 (IO_VIRT + 0x02008630)
    #define VINTF_PTGEN_OSD_TYPE Fld(8,24,AC_FULLB3)//[31:24]
	#define VINTF_PTGEN_V_RUN Fld(2,10,AC_MSKB1)//[11:10]
	#define VINTF_PTGEN_H_RUN Fld(2,8,AC_MSKB1)//[9:8]
    #define VINTF_CHESS_BOX_H Fld(2, 4, AC_MSKB0) //[5:4]
    #define VINTF_CHESS_BOX_W Fld(3,0,AC_MSKB0)//[2:0]
#define VINTF_B13 (IO_VIRT + 0x02008634)
    #define VINTF_CURSOR_H Fld(12,16,AC_MSKW32)//[27:16]
    #define VINTF_CURSOR_V Fld(12,0,AC_MSKW10)//[11:0]
#define VINTF_B14 (IO_VIRT + 0x02008638)
    #define VINTF_PTGEN_FLICKER_MAP Fld(32,0,AC_FULLDW)//[31:0]  // new for Husky
#define VINTF_P0 (IO_VIRT + 0x02008700)
    #define VINTF_PANEL_IN_SEL Fld(2,30,AC_MSKB3)//[31:30]
    #define VINTF_PANEL_IN_B_SWAP Fld(2,12,AC_MSKB1)//[13:12]
    #define VINTF_PANEL_IN_G_SWAP Fld(2,10,AC_MSKB1)//[11:10]
    #define VINTF_PANEL_IN_R_SWAP Fld(2,8,AC_MSKB1)//[9:8]
    #define VINTF_PANEL_MONI_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define VINTF_DISPR_OUT_P Fld(1,4,AC_MSKB0)//[4:4]
    #define VINTF_DISPR_IN_P Fld(1,3,AC_MSKB0)//[3:3]
    #define VINTF_IF_DE_IN_P Fld(1,2,AC_MSKB0)//[2:2]
    #define VINTF_IF_HSYNC_IN_P Fld(1,1,AC_MSKB0)//[1:1]
    #define VINTF_IF_VSYNC_IN_P Fld(1,0,AC_MSKB0)//[0:0]
#define VINTF_P1 (IO_VIRT + 0x02008704)
    #define VINTF_H_TOTAL_CLR Fld(1,31,AC_MSKB3)//[31:31]
#define VINTF_P2 (IO_VIRT + 0x02008708)
    #define MAX_H_TOTAL Fld(13,16,AC_MSKW32)//[28:16]
    #define MIN_H_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_P3 (IO_VIRT + 0x0200870C)
    #define MAX_H_ACTIVE Fld(12,16,AC_MSKW32)//[27:16]
    #define MIN_H_ACTIVE Fld(12,0,AC_MSKW10)//[11:0]
#define VINTF_P4 (IO_VIRT + 0x02008710)
    #define VINTF_REORDER_BYPASS Fld(1,31,AC_MSKB3)//[31:31]
    #define VINTF_REORDER_FORMAIN_OUT Fld(2,20,AC_MSKB2)//[21:20]
     #define REORDER_FORMAIN_OUT_SEQ 0
      #define REORDER_FORMAIN_OUT_4CH_HALF 1
	  #define REORDER_FORMAIN_OUT_2CH_HALF 2
    #define VINTF_REORDER_MIDDLE_PT Fld(11,0,AC_MSKW10)//[10:0]
#define VINTF_P5 (IO_VIRT + 0x02008714)
    #define TCON_3DBL_PWM Fld(1,4,AC_MSKB0)//[4:4]
    #define TCON_3DLR_PWM Fld(1,3,AC_MSKB0)//[3:3]
    #define TCON_3DR_PWM Fld(1,2,AC_MSKB0)//[2:2]
    #define TCON_3DL_PWM Fld(1,1,AC_MSKB0)//[1:1]
    #define EVEN_ODD_INFO Fld(1,0,AC_MSKB0)//[0:0]
#define VINTF_P6 (IO_VIRT + 0x02008718)
    #define VINTF_2EYE_WIDTH Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_2EYE_H_DLY Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_P7 (IO_VIRT + 0x0200871C)
    #define VINTF_2EYE_PWM_NDLY Fld(1,12,AC_MSKB1)//[12:12]
    #define VINTF_2EYE_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define VINTF_2EYE_OP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define VINTF_2EYE_POL Fld(1,6,AC_MSKB0)//[6:6]
    #define VINTF_2EYE_RST_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define VINTF_2EYE_LRLR Fld(1,2,AC_MSKB0)//[2:2]
    #define VINTF_2EYE_V_DLY Fld(2,0,AC_MSKB0)//[1:0]
#define VINTF_P8 (IO_VIRT + 0x02008720)
    #define VINTF_REYE_WIDTH Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_REYE_H_DLY Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_P9 (IO_VIRT + 0x02008724)
    #define VINTF_REYE_PWM_NDLY Fld(1,12,AC_MSKB1)//[12:12]
    #define VINTF_REYE_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define VINTF_REYE_OP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define VINTF_REYE_POL Fld(1,6,AC_MSKB0)//[6:6]
    #define VINTF_REYE_RST_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define VINTF_REYE_V_POS Fld(1,4,AC_MSKB0)//[4:4]
    #define VINTF_REYE_LRLR Fld(1,2,AC_MSKB0)//[2:2]
    #define VINTF_REYE_V_DLY Fld(2,0,AC_MSKB0)//[1:0]
#define VINTF_P10 (IO_VIRT + 0x02008728)
    #define VINTF_LEYE_WIDTH Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_LEYE_H_DLY Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_P11 (IO_VIRT + 0x0200872C)
    #define VINTF_LEYE_PWM_NDLY Fld(1,12,AC_MSKB1)//[12:12]
    #define VINTF_LEYE_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define VINTF_LEYE_OP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define VINTF_LEYE_POL Fld(1,6,AC_MSKB0)//[6:6]
    #define VINTF_LEYE_RST_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define VINTF_LEYE_V_POS Fld(1,4,AC_MSKB0)//[4:4]
    #define VINTF_LEYE_LRLR Fld(1,2,AC_MSKB0)//[2:2]
    #define VINTF_LEYE_V_DLY Fld(2,0,AC_MSKB0)//[1:0]
#define VINTF_P12 (IO_VIRT + 0x02008730)
    #define VINTF_3DBL_WIDTH Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_3DBL_H_DLY Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_P13 (IO_VIRT + 0x02008734)
    #define VINTF_3DBL_PWM_NDLY Fld(1,12,AC_MSKB1)//[12:12]
    #define VINTF_3DBL_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define VINTF_3DBL_OP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define VINTF_3DBL_POL Fld(1,6,AC_MSKB0)//[6:6]
    #define VINTF_3DBL_RST_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define VINTF_3DBL_LRLR Fld(1,4,AC_MSKB0)//[4:4]
    #define VINTF_3DBL_V_DLY Fld(2,0,AC_MSKB0)//[1:0]
#define VINTF_P14 (IO_VIRT + 0x02008738)
    #define VINTF_CRC_H_END Fld(16,16,AC_FULLW32)//[31:16]
    #define VINTF_CRC_H_START Fld(16,0,AC_FULLW10)//[15:0]
#define VINTF_P15 (IO_VIRT + 0x0200873C)
    #define VINTF_CRC_VCNT Fld(16,16,AC_FULLW32)//[31:16]
    #define VINTF_CRC_ALG_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define VINTF_CRC_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define VINTF_CRC_CH_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define VINTF_CRC_SRC_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define VINTF_CRC_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define VINTF_CRC_START Fld(1,0,AC_MSKB0)//[0:0]
#define VINTF_P16 (IO_VIRT + 0x02008740)
    #define ST_INTF_CRC_OUT_23_0 Fld(30,0,AC_MSKDW)//[29:0]
    #define ST_INTF_CRC_ERR Fld(1,30,AC_MSKB3)//[30:30]
    #define ST_INTF_CRC_RDY Fld(1,31,AC_MSKB3)//[31:31]
#define VINTF_P17 (IO_VIRT + 0x02008744)  // delete ???
    #define VINTF_3D_DISP_SHIFT_VALUE_R Fld(8,16,AC_FULLB2)//[23:16]
    #define VINTF_3D_DISP_SHIFT_VALUE_L Fld(8,8,AC_FULLB1)//[15:8]
    #define VINTF_3D_DISP_SHIFT_CTL Fld(3,4,AC_MSKB0)//[6:4]
    #define VINTF_3D_DISP_SHIFT_FRAME Fld(1,3,AC_MSKB0)//[3:3]
    #define VINTF_3D_DISP_SHIFT_SAME_REG Fld(1,2,AC_MSKB0)//[2:2]
    #define VINTF_3D_DISP_SHIFT_INV Fld(1,1,AC_MSKB0)//[1:1]
    #define VINTF_3D_DISP_SHIFT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define VINTF_P18 (IO_VIRT + 0x02008748)  // delete ???
    #define VINTF_3D_DISP_SHIFT_B Fld(8,16,AC_FULLB2)//[23:16]
    #define VINTF_3D_DISP_SHIFT_G Fld(8,8,AC_FULLB1)//[15:8]
    #define VINTF_3D_DISP_SHIFT_R Fld(8,0,AC_FULLB0)//[7:0]
#define VINTF_P19 (IO_VIRT + 0x0200874C)
	#define VINTF_DIS_MODIFY Fld(1,28,AC_MSKB3)//[28:28]
	#define VINTF_2K2K_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define VINTF_8SEC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define VINTF_4SEC_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define VINTF_DIS_VALIGN Fld(1,21,AC_MSKB2)//[21:21]
    #define VINTF_2SEC_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define VINTF_2SEC_RO Fld(1,19,AC_MSKB2)//[19:19]
    #define VINTF_2SEC_DIS_VSR Fld(1,18,AC_MSKB2)//[18:18]
    #define VINTF_DISP_R_ALLIGN_TYPE Fld(2,16,AC_MSKB2)//[17:16]
    #define VINTF_DISPR_SEL_FOR_DELAY Fld(1, 13, AC_MSKB1) //13
    #define VINTF_DISP_R_H_DLY Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_P20 (IO_VIRT + 0x02008750)  // delete ???
    #define VINTF_IS_DELAY_H Fld(16,16,AC_FULLW32)//[31:16]
    #define VINTF_IS_DIV_H Fld(4,12,AC_MSKB1)//[15:12]
    #define VINTF_IS_MUL_H Fld(4,8,AC_MSKB1)//[11:8]
    #define VINTF_IS_FORCE_DELAY Fld(1,7,AC_MSKB0)//[7:7]
    #define VINTF_IS_SYNC_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define VINTF_IS_USE_SC_SET_DATA Fld(1,5,AC_MSKB0)//[5:5]
    #define VINTF_IS_JIT_FIL_OFF_H Fld(1,4,AC_MSKB0)//[4:4]
    #define VINTF_IS_HOLD_EN_H Fld(1,3,AC_MSKB0)//[3:3]
    #define VINTF_IS_POL_H Fld(1,2,AC_MSKB0)//[2:2]
    #define VINTF_SYNC_TOTAL_PLUS_1_H Fld(1,1,AC_MSKB0)//[1:1]
    #define VINTF_INV_SYNC_START Fld(1,0,AC_MSKB0)//[0:0]
#define VINTF_P21 (IO_VIRT + 0x02008754)
    #define VINTF_IS_LEN_PLUS_1_H Fld(4,24,AC_MSKB3)//[27:24]
    #define VINTF_IS_MASK_LEN_H Fld(8,16,AC_FULLB2)//[23:16]
    #define VINTF_IS_PWM_SYNC_TOTAL_H Fld(16,0,AC_FULLW10)//[15:0]
#define VINTF_P22 (IO_VIRT + 0x02008758)
    #define VINTF_IS_DELAY_V Fld(16,16,AC_FULLW32)//[31:16]
    #define VINTF_IS_DIV_V Fld(4,12,AC_MSKB1)//[15:12]
    #define VINTF_IS_MUL_V Fld(4,8,AC_MSKB1)//[11:8]
    #define VINTF_IS_JIT_FIL_OFF_V Fld(1,4,AC_MSKB0)//[4:4]
    #define VINTF_IS_HOLD_EN_V Fld(1,3,AC_MSKB0)//[3:3]
    #define VINTF_IS_POL_V Fld(1,2,AC_MSKB0)//[2:2]
    #define VINTF_SYNC_TOTAL_PLUS_1_V Fld(1,1,AC_MSKB0)//[1:1]
#define VINTF_P23 (IO_VIRT + 0x0200875C)
    #define VINTF_IS_LEN_PLUS_1_V Fld(4,24,AC_MSKB3)//[27:24]
    #define VINTF_IS_MASK_LEN_V Fld(8,16,AC_FULLB2)//[23:16]
    #define VINTF_IS_PWM_SYNC_TOTAL_V Fld(16,0,AC_FULLW10)//[15:0]
#define VINTF_P24 (IO_VIRT + 0x02008760)
    #define VINTF_SYNCO_POL_V Fld(1, 14, AC_MSKB1) //14
    #define VINTF_PWM_LEN_SEL_V Fld(2,12,AC_MSKB1)//[13:12]
    #define VINTF_SYNCO_POL_H Fld(1,10,AC_MSKB1)//[10:10]
    #define VINTF_PWM_LEN_SEL_H Fld(2,8,AC_MSKB1)//[9:8]
#define VINTF_P25 (IO_VIRT + 0x02008764)
    #define VINTF_3DBL_2_WIDTH Fld(13,16,AC_MSKW32)//[28:16]
    #define VINTF_3DBL_2_H_DLY Fld(13,0,AC_MSKW10)//[12:0]
#define VINTF_P26 (IO_VIRT + 0x02008768)
    #define VINTF_3DBL_2_PWM_NDLY Fld(1,12,AC_MSKB1)//[12:12]
    #define VINTF_3DBL_2_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define VINTF_3DBL_2_OP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define VINTF_3DBL_2_POL Fld(1,6,AC_MSKB0)//[6:6]
    #define VINTF_3DBL_2_RST_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define VINTF_3DBL_2_LRLR Fld(1,4,AC_MSKB0)//[4:4]
    #define VINTF_3DBL_2_V_DLY Fld(2,0,AC_MSKB0)//[1:0]
#define VINTF_P27 (IO_VIRT + 0x0200876C)
    #define VINTF_P27_2SEC_H_TOTAL Fld(12, 16, AC_MSKW32) //27:16
    #define VINTF_P27_2SEC_H_VALID Fld(11,0,AC_MSKW10)//[10:0]
#define VINTF_P28 (IO_VIRT + 0x02008770)
    #define VINTF_P28_2SEC_H_END Fld(12, 16, AC_MSKW32) //27:16
    #define VINTF_P28_2SEC_H_START  Fld(12, 0, AC_MSKW10) //11:0
#define VINTF_P29 (IO_VIRT + 0x02008774)
    #define VINTF_P29_2SEC_V_WIDTH Fld(7,16,AC_MSKB2)//[22:16]
    #define VINTF_P29_2SEC_V_TOTAL  Fld(12, 0, AC_MSKW10) //11:0

//******************Page LVDS*******************************************
#define LVDSB_REG00 (IO_VIRT+0x02008C00)
	#define RG_LVDS_ATPG_CT Fld(1,31,AC_MSKB3)//[31:31]
	#define RG_LVDS_ATPG_OB Fld(1,30,AC_MSKB3)//[30:30]
	#define RG_LVDSTX_MON_SEL Fld(8,22,AC_MSKW32)//[29:22]
	#define RG_DISPR_P Fld(1, 15, AC_MSKB1) //[15:15]  
    #define RG_DE_P Fld(1, 14, AC_MSKB1) //[14:14]
    #define RG_VSYNC_P Fld(1, 13, AC_MSKB1) //[13:13]
    #define RG_HSYNC_P Fld(1, 12, AC_MSKB1) //[12:12]
    #define RG_LVDSTX_2CH_ARCH Fld(1,11,AC_MSKB1)//[11:11]
    #define RG_LVDSTX_ANA_TEST Fld(1,10,AC_MSKB1)//[10:10]
	#define RG_LVDSTX_ANA_FORCE Fld(10,0,AC_MSKW10)//[9:0]
#define LVDSB_REG01 (IO_VIRT+0x02008C04)
	#define RG_IBUF_BYPASS Fld(1,31,AC_MSKB3)//[31:31]
	#define RG_IBUF_SIZE Fld(11,20,AC_MSKW32)//[30:20]
	#define RG_AMST_TR Fld(11,9,AC_MSKW21)//[19:9]
	#define RG_AMST_UF_CLR Fld(1, 8, AC_MSKB1) //[8:8]
	#define RG_AMST_OF_CLR Fld(1, 7, AC_MSKB0) //[7:7]
	#define RG_IBUF_RST_SEL Fld(1, 6, AC_MSKB0) //[6:6]
#define LVDSB_REG02 (IO_VIRT+0x02008C08)
    #define RG_LLV7_SEL Fld(4, 28, AC_MSKB3) //31:28
    #define RG_LLV6_SEL Fld(4, 24, AC_MSKB3) //27:24
    #define RG_LLV5_SEL Fld(4, 20, AC_MSKB2) //23:20
    #define RG_LLV4_SEL Fld(4, 16, AC_MSKB2) //19:16
    #define RG_LLV3_SEL Fld(4, 12, AC_MSKB1) //15:12
    #define RG_LLV2_SEL Fld(4, 8, AC_MSKB1) //11:8
    #define RG_LLV1_SEL Fld(4, 4, AC_MSKB0) //7:4
    #define RG_LLV0_SEL Fld(4, 0, AC_MSKB0) //3:0	
#define LVDSB_REG03 (IO_VIRT+0x02008C0C)
    #define RG_RLV7_SEL Fld(4, 28, AC_MSKB3) //31:28
    #define RG_RLV6_SEL Fld(4, 24, AC_MSKB3) //27:24
    #define RG_RLV5_SEL Fld(4, 20, AC_MSKB2) //23:20
    #define RG_RLV4_SEL Fld(4, 16, AC_MSKB2) //19:16
    #define RG_RLV3_SEL Fld(4, 12, AC_MSKB1) //15:12
    #define RG_RLV2_SEL Fld(4, 8, AC_MSKB1) //11:8
    #define RG_RLV1_SEL Fld(4, 4, AC_MSKB0) //7:4
    #define RG_RLV0_SEL Fld(4, 0, AC_MSKB0) //3:0
#define LVDSB_REG04 (IO_VIRT+0x02008C10)
    #define RG_LLV_CK1_SEL Fld(4, 28, AC_MSKB3) //31:28
    #define RG_LLV_CK0_SEL Fld(4, 24, AC_MSKB3) //27:24
    #define RG_RLV_CK1_SEL Fld(4, 20, AC_MSKB2) //23:20
    #define RG_RLV_CK0_SEL Fld(4, 16, AC_MSKB2) //19:16
    #define RG_LLV9_SEL Fld(4, 12, AC_MSKB1) //15:12
    #define RG_LLV8_SEL Fld(4, 8, AC_MSKB1) //11:8
    #define RG_RLV9_SEL Fld(4, 4, AC_MSKB0) //7:4
    #define RG_RLV8_SEL Fld(4, 0, AC_MSKB0) //3:0
#define LVDSB_REG05 (IO_VIRT+0x02008C14)
	#define RG_TOP_LLV_LINK_INV Fld(1,28,AC_MSKB3)//[28:28]
    #define RG_TOP_LLV_PN Fld(12, 16, AC_MSKW32) //27:16
	    #define RG_LLVCK1_PN_SWAP Fld(1,27,AC_MSKB3)//[27:27]
	    #define RG_LLVCK0_PN_SWAP Fld(1,26,AC_MSKB3)//[26:26]
	    #define RG_LLV9_PN_SWAP Fld(1,25,AC_MSKB3)//[25:25]
	    #define RG_LLV8_PN_SWAP Fld(1,24,AC_MSKB3)//[24:24]
	    #define RG_LLV7_PN_SWAP Fld(1,23,AC_MSKB2)//[23:23]
	    #define RG_LLV6_PN_SWAP Fld(1,22,AC_MSKB2)//[22:22]
	    #define RG_LLV5_PN_SWAP Fld(1,21,AC_MSKB2)//[21:21]
	    #define RG_LLV4_PN_SWAP Fld(1,20,AC_MSKB2)//[20:20]
	    #define RG_LLV3_PN_SWAP Fld(1,19,AC_MSKB2)//[19:19]
	    #define RG_LLV2_PN_SWAP Fld(1,18,AC_MSKB2)//[18:18]
	    #define RG_LLV1_PN_SWAP Fld(1,17,AC_MSKB2)//[17:17]
	    #define RG_LLV0_PN_SWAP Fld(1,16,AC_MSKB2)//[16:16]
    #define RG_TOP_RLV_LINK_INV Fld(1, 12, AC_MSKB1) //[12:12]
    #define RG_TOP_RLV_PN Fld(12, 0, AC_MSKW10) //11:0
	    #define RG_RLVCK1_PN_SWAP Fld(1, 11, AC_MSKB1) //[11:11]
	    #define RG_RLVCK0_PN_SWAP Fld(1, 10, AC_MSKB1) //[10:10]
	    #define RG_RLV9_PN_SWAP Fld(1, 9, AC_MSKB1) //[9:9]
	    #define RG_RLV8_PN_SWAP Fld(1, 8, AC_MSKB1) //[8:8]
	    #define RG_RLV7_PN_SWAP Fld(1, 7, AC_MSKB0) //[7:7]
	    #define RG_RLV6_PN_SWAP Fld(1, 6, AC_MSKB0) //[6:6]
	    #define RG_RLV5_PN_SWAP Fld(1, 5, AC_MSKB0) //[5:5]
	    #define RG_RLV4_PN_SWAP Fld(1, 4, AC_MSKB0) //[4:4]
	    #define RG_RLV3_PN_SWAP Fld(1, 3, AC_MSKB0) //[3:3]
	    #define RG_RLV2_PN_SWAP Fld(1, 2, AC_MSKB0) //[2:2]
	    #define RG_RLV1_PN_SWAP Fld(1, 1, AC_MSKB0) //[1:1]
	    #define RG_RLV0_PN_SWAP Fld(1, 0, AC_MSKB0) //[0:0]
#define LVDSB_REG06 (IO_VIRT + 0x02008C18)
    #define RG_REG_EVEN_ODD Fld(1,31,AC_MSKB3)//[31:31]
    #define RG_CNTLF Fld(1,30,AC_MSKB3)//[30:30]
    #define RG_CNTLE Fld(1,29,AC_MSKB3)//[29:29]
    #define RG_RES Fld(1,28,AC_MSKB3)//[28:28]
    #define RG_DE_SEL Fld(1,27,AC_MSKB3)//[27:27]
    #define RG_VS_SEL Fld(1,26,AC_MSKB3)//[26:26]
    #define RG_HS_SEL Fld(1,25,AC_MSKB3)//[25:25]
    #define RG_RES_FLD Fld(1,24,AC_MSKB3)//[24:24]
    #define RG_RGB_444_MERGE Fld(1,23,AC_MSKB2)//[23:23]
    #define RG_8BIT_DUAL Fld(1,22,AC_MSKB2)//[22:22]
    #define RG_2CH_MERGE Fld(1,21,AC_MSKB2)//[21:21]
    #define RG_MERGE_OSD Fld(1,20,AC_MSKB2)//[20:20]
    #define RG_TEST_TX_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define RG_TEST_TX_EYE Fld(1,17,AC_MSKB2)//[17:17]
    #define RG_TEST_TX_DEN Fld(1,16,AC_MSKB2)//[16:16]
    #define RG_DCBAL_SCAN Fld(1,15,AC_MSKB1)//[15:15]
    #define RG_TMDS_PG_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define RG_4CH Fld(1,13,AC_MSKB1)//[13:13]
    #define RG_DUAL Fld(1,12,AC_MSKB1)//[12:12]
    #define RG_ODD_SW Fld(1,11,AC_MSKB1)//[11:11]
    #define RG_RS_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define RG_CH_SW Fld(2,8,AC_MSKB1)//[9:8]
    #define RG_DE_DELAY_SEL Fld(1, 7, AC_MSKB0) //[7:7]
    #define RG_CLK_DCBAL Fld(1,6,AC_MSKB0)//[6:6]
    #define RG_DCBAL Fld(1,5,AC_MSKB0)//[5:5]
    #define RG_5381_10B_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define RG_12B_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define RG_10B_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define RG_NS_VESA_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define RG_SPECIAL_NS Fld(1,0,AC_MSKB0)//[0:0]
#define LVDSB_REG07 (IO_VIRT + 0x02008C1C)
    #define RG_CLK_CTRL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define RG_CLK_CTRL Fld(7,24,AC_MSKB3)//[30:24]
    #define RG_PD Fld(24,0,AC_MSKDW)//[23:0]
#define LVDSB_REG08 (IO_VIRT + 0x02008C20)
    #define RG_OSD_3D_IN_HS Fld(1,29,AC_MSKB3)//[29:29]
    #define RG_OSD_3D_IN_VS Fld(1,28,AC_MSKB3)//[28:28]
    #define RG_PNSWAP Fld(1,15,AC_MSKB1)//[15:15]
    #define RG_LVDS_INV Fld(1,14,AC_MSKB1)//[14:14]
    #define RG_LVDS_7TO10FIFO_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define RG_DPMODE Fld(1,12,AC_MSKB1)//[12:12]
    #define RG_C_LINE_EXT Fld(1,11,AC_MSKB1)//[11:11]
    #define RG_LPF_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define RG_YUV2YC_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define RG_UVINV Fld(1,8,AC_MSKB1)//[8:8]
    #define RG_D_SW Fld(2,6,AC_MSKB0)//[7:6]
    #define RG_C_SW Fld(2,4,AC_MSKB0)//[5:4]
    #define RG_B_SW Fld(2,2,AC_MSKB0)//[3:2]
    #define RG_A_SW Fld(2,0,AC_MSKB0)//[1:0]
#define LVDSB_REG09 (IO_VIRT + 0x02008C24)
    #define RG_TMDS_SEL Fld(32,0,AC_FULLDW)//[31:0]
#define LVDSB_REG10 (IO_VIRT + 0x02008C28)
    #define RG_CRC_VCNT Fld(16,8,AC_FULLW21)//[23:8]
    #define RG_CRC_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define RG_CRC_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define RG_CRC_START Fld(1,0,AC_MSKB0)//[0:0]
#define LVDSB_REG11 (IO_VIRT + 0x02008C2C)
    #define ST_VGA_CRC_OUT Fld(24,8,AC_MSKDW)//[31:8]
    #define ST_VGA_CRC_ERR Fld(1,1,AC_MSKB0)//[1:1]
    #define ST_VGA_CRC_RDY Fld(1,0,AC_MSKB0)//[0:0]
#define LVDSB_REG12 (IO_VIRT + 0x02008C30)
    #define ST_LVDS_CRC_OUT_23_0 Fld(24,8,AC_MSKDW)//[31:8]
    #define ST_LVDS_CRC_ERR Fld(1,1,AC_MSKB0)//[1:1]    
    #define ST_LVDS_CRC_RDY Fld(1,0,AC_MSKB0)//[0:0]
#define LVDSB_REG13 (IO_VIRT + 0x02008C34)
    #define ST_LVDS_CRC_OUT_41_24 Fld(18,0,AC_MSKDW)//[17:0]   
#define LVDSB_REG14 (IO_VIRT + 0x02008C38)
    #define ST_FIFO_LEFT_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define ST_FIFO_OVER Fld(1, 11, AC_MSKB1) //11
    #define ST_FIFO_UNDER Fld(1, 10, AC_MSKB1) //10
    #define ST_FIFO_FULL Fld(1,9,AC_MSKB1)//[9:9]
    #define ST_FIFO_EMPTY Fld(1,8,AC_MSKB1)//[8:8]
    #define ST_LVDS_DISP_R Fld(1, 0, AC_MSKB0) //0
#define LVDSB_REG15 (IO_VIRT + 0x02008C3C)
    #define RG_TMDS_PG0 Fld(28,4,AC_MSKDW)//[31:4] 
    #define RG_TP_TS10 Fld(1,3,AC_MSKB0)//[3:3] 
    #define RG_TP_JD98 Fld(1,2,AC_MSKB0)//[2:2]
    #define RG_TP_JD10 Fld(1,1,AC_MSKB0)//[1:1]
    #define RG_TP_VS10 Fld(1,0,AC_MSKB0)//[0:0]
#define LVDSB_REG16 (IO_VIRT + 0x02008C40)
    #define RG_TMDS_PG1 Fld(32,0,AC_FULLDW)//[31:0]  
#define LVDSB_REG17 (IO_VIRT + 0x02008C44)
    #define RG_TMDS_PG2 Fld(32,0,AC_FULLDW)//[31:0]  
#define LVDSB_REG18 (IO_VIRT + 0x02008C48)
    #define RG_RES_EVEN_ODD_L Fld(1,31,AC_MSKB3)//[31:31]
    #define RG_CNTLF_L Fld(1,30,AC_MSKB3)//[30:30]
    #define RG_CNTLE_L Fld(1,29,AC_MSKB3)//[29:29]
    #define RG_RES_L Fld(1,28,AC_MSKB3)//[28:28]
    #define RG_DE_SEL_L Fld(1,27,AC_MSKB3)//[27:27]
    #define RG_VS_SEL_L Fld(1,26,AC_MSKB3)//[26:26]
    #define RG_HS_SEL_L Fld(1,25,AC_MSKB3)//[25:25]
    #define RG_RES_FIELD_L Fld(1,24,AC_MSKB3)//[24:24]
    #define RG_TEST_TTL_DAT Fld(8,8,AC_FULLB1)//[15:8]
    #define RG_TEST_LC_DAT Fld(7,0,AC_MSKB0)//[6:0]
#define LVDSB_REG19 (IO_VIRT + 0x02008C4C)
    #define RG_RES2_FLD Fld(1,31,AC_MSKB3)//[31:31]
    #define RG_RES2_FLD_L Fld(1,30,AC_MSKB3)//[30:30]
    #define RG_RES2_FLD_L_4CH Fld(1,29,AC_MSKB3)//[29:29]
    #define RG_RES2_FLD_U_4CH Fld(1,28,AC_MSKB3)//[28:28]
    #define RG_OSD_INDEX_TEST_ENABLE Fld(1,20,AC_MSKB2)//[20:20]
    #define RG_RES_OSD_INDEX Fld(1,19,AC_MSKB2)//[19:19]
    #define RG_RES_OSD_INDEX_L Fld(1,18,AC_MSKB2)//[18:18]
    #define RG_RES_OSD_INDEX_U_4CH Fld(1,17,AC_MSKB2)//[17:17]
    #define RG_RES_OSD_INDEX_L_4CH Fld(1,16,AC_MSKB2)//[16:16]
    #define RG_RES_EVEN_ODD_L_4CH Fld(1,15,AC_MSKB1)//[15:15]
    #define RG_CNTLF_L_4CH Fld(1,14,AC_MSKB1)//[14:14]
    #define RG_CNTLE_L_4CH Fld(1,13,AC_MSKB1)//[13:13]
    #define RG_RES_L_4CH Fld(1,12,AC_MSKB1)//[12:12]
    #define RG_DE_SEL_L_4CH Fld(1,11,AC_MSKB1)//[11:11]
    #define RG_VS_SEL_L_4CH Fld(1,10,AC_MSKB1)//[10:10]
    #define RG_HS_SEL_L_4CH Fld(1,9,AC_MSKB1)//[9:9]
    #define RG_RES_FIELD_L_4CH Fld(1,8,AC_MSKB1)//[8:8]
    #define RG_RES_EVEN_ODD_U_4CH Fld(1,7,AC_MSKB0)//[7:7]
    #define RG_CNTLF_U_4CH Fld(1,6,AC_MSKB0)//[6:6]
    #define RG_CNTLE_U_4CH Fld(1,5,AC_MSKB0)//[5:5]
    #define RG_RES_U_4CH Fld(1,4,AC_MSKB0)//[4:4]
    #define RG_DE_SEL_U_4CH Fld(1,3,AC_MSKB0)//[3:3]
    #define RG_VS_SEL_U_4CH Fld(1,2,AC_MSKB0)//[2:2]
    #define RG_HS_SEL_U_4CH Fld(1,1,AC_MSKB0)//[1:1]
    #define RG_RES_FIELD_U_4CH Fld(1,0,AC_MSKB0)//[0:0]
#define LVDSB_REG20 (IO_VIRT + 0x02008C50)
    #define RG_LVDSRX_FIFO_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define RG_LVDSRX_CRC_SEL Fld(2,21,AC_MSKB2)//[22:21]
    #define RG_LVDSRX_CRC_START Fld(1,20,AC_MSKB2)//[20:20]
    #define RG_LVDSRX_CRC_CLR Fld(1,19,AC_MSKB2)//[19:19]
    #define RG_LVDSRX_CRC_MODE Fld(2,17,AC_MSKB2)//[18:17]
    #define RG_LVDSRX_CRC_ALG_SEL Fld(1,16,AC_MSKB2)//[16:16]
    #define RG_LVDSRX_CRC_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define LVDSB_REG21 (IO_VIRT + 0x02008C54)
    #define RG_LVDSRX_CRC_H_END Fld(16,16,AC_FULLW32)//[31:16]
    #define RG_LVDSRX_CRC_H_START Fld(16,0,AC_FULLW10)//[15:0]
#define LVDSB_REG22 (IO_VIRT + 0x02008C58)
    #define LVDSRX_CRC_DONE Fld(1,31,AC_MSKB3)//[31:31]
    #define LVDSRX_CRC_FAIL Fld(1,30,AC_MSKB3)//[30:30]
    #define LVDSRX_CRC_VALUE Fld(14,16,AC_MSKW32)//[29:16]
	#define LVDSTX_FIFO_WRPTR_ESD Fld(4,12,AC_MSKB1)//[15:12]
	#define LVDSTX_FIFO_RDPTR_ESD Fld(4,8,AC_MSKB1)//[11:8]
    #define LVDSTX_FIFO_WRPTR Fld(4,4,AC_MSKB0)//[7:4]
    #define LVDSTX_FIFO_RDPTR Fld(4,0,AC_MSKB0)//[3:0]
#define LVDSB_REG24 (IO_VIRT + 0x02008C60)
	#define OSD_IN_46_32 Fld(15,0,AC_MSKW10)//[14:0]
#define LVDSB_REG25 (IO_VIRT + 0x02008C64)
    #define OSD_IN_31_0 Fld(32,0,AC_FULLDW)//[31:0]  
#define LVDSB_REG26 (IO_VIRT + 0x02008C68)
	#define RG_OSD_SWITCH_CH Fld(2,30,AC_MSKB3)//[31:30]
		#define RG_OSD_SWITCH_CH1 Fld(1,31,AC_MSKB3)//[31:31]
		#define RG_OSD_SWITCH_CH0 Fld(1,30,AC_MSKB3)//[30:30]
    #define RG_OSD_ENCODE_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define RG_OSD_HSYNC_P Fld(1,28,AC_MSKB3)//[28:28]
    #define RG_OSD_VSYNC_P Fld(1,27,AC_MSKB3)//[27:27]
    #define RG_OSD_DE_P Fld(1,26,AC_MSKB3)//[26:26]
    #define RG_OSD_HS_SEL Fld(1,25,AC_MSKB3)//[25:25]
    #define RG_OSD_VS_SEL Fld(1,24,AC_MSKB3)//[24:24]
    #define RG_OSD_DE_SEL Fld(1,23,AC_MSKB2)//[23:23]
    #define RG_OSD_RES1_SEL Fld(1,22,AC_MSKB2)//[22:22]
    #define RG_OSD_RES2_SEL Fld(1,21,AC_MSKB2)//[21:21]
	#define RG_OSD_RES Fld(1,20,AC_MSKB2)//[20:20]
	#define RG_OSD_CNTLE Fld(1, 19, AC_MSKB2) //19
	#define RG_OSD_CNTLF Fld(1, 18, AC_MSKB2) //18
	#define RG_OSD_RES1 Fld(1, 17, AC_MSKB2) //17
    #define RG_OSD_RES2 Fld(1, 16, AC_MSKB2) //16
    #define RG_OSD_IN_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define RG_OSD_IN_46_32 Fld(15,0,AC_MSKW10)//[14:0]
#define LVDSB_REG27 (IO_VIRT + 0x02008C6C)
    #define RG_OSD_IN_31_0 Fld(32,0,AC_FULLDW)//[31:0] 

#endif
