#ifndef _HW_FD_H_
#define _HW_FD_H_

#define FD_BASE (IO_VIRT_SRE + 0x1C000)

//Page FDVT_A_1
#define DMA_SOFT_RSTSTAT (FD_BASE + 0x200)
    #define DMA_SOFT_RSTSTAT_FDVT_RDB_1_SOFT_RST_STAT Fld(1,19,AC_MSKB2)//[19:19]
    #define DMA_SOFT_RSTSTAT_FDVT_RDB_0_SOFT_RST_STAT Fld(1,18,AC_MSKB2)//[18:18]
    #define DMA_SOFT_RSTSTAT_FDVT_RDA_1_SOFT_RST_STAT Fld(1,17,AC_MSKB2)//[17:17]
    #define DMA_SOFT_RSTSTAT_FDVT_RDA_0_SOFT_RST_STAT Fld(1,16,AC_MSKB2)//[16:16]
    #define DMA_SOFT_RSTSTAT_FDVT_WRB_1_SOFT_RST_STAT Fld(1,3,AC_MSKB0)//[3:3]
    #define DMA_SOFT_RSTSTAT_FDVT_WRB_0_SOFT_RST_STAT Fld(1,2,AC_MSKB0)//[2:2]
    #define DMA_SOFT_RSTSTAT_FDVT_WRA_1_SOFT_RST_STAT Fld(1,1,AC_MSKB0)//[1:1]
    #define DMA_SOFT_RSTSTAT_FDVT_WRA_0_SOFT_RST_STAT Fld(1,0,AC_MSKB0)//[0:0]
#define TDRI_BASE_ADDR (FD_BASE + 0x204)
    #define TDRI_BASE_ADDR_BASE_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define TDRI_OFST_ADDR (FD_BASE + 0x208)
    #define TDRI_OFST_ADDR_OFFSET_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define TDRI_XSIZE (FD_BASE + 0x20C)
    #define TDRI_XSIZE_XSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define VERTICAL_FLIP_EN (FD_BASE + 0x210)
    #define VERTICAL_FLIP_EN_FDVT_RDB_1_V_FLIP_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define VERTICAL_FLIP_EN_FDVT_RDB_0_V_FLIP_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define VERTICAL_FLIP_EN_FDVT_RDA_1_V_FLIP_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define VERTICAL_FLIP_EN_FDVT_RDA_0_V_FLIP_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define VERTICAL_FLIP_EN_FDVT_WRB_1_V_FLIP_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define VERTICAL_FLIP_EN_FDVT_WRB_0_V_FLIP_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define VERTICAL_FLIP_EN_FDVT_WRA_1_V_FLIP_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define VERTICAL_FLIP_EN_FDVT_WRA_0_V_FLIP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DMA_SOFT_RESET (FD_BASE + 0x214)
    #define DMA_SOFT_RESET_SEPARATE_SOFT_RST_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define DMA_SOFT_RESET_FDVT_RDB_1_SOFT_RST Fld(1,19,AC_MSKB2)//[19:19]
    #define DMA_SOFT_RESET_FDVT_RDB_0_SOFT_RST Fld(1,18,AC_MSKB2)//[18:18]
    #define DMA_SOFT_RESET_FDVT_RDA_1_SOFT_RST Fld(1,17,AC_MSKB2)//[17:17]
    #define DMA_SOFT_RESET_FDVT_RDA_0_SOFT_RST Fld(1,16,AC_MSKB2)//[16:16]
    #define DMA_SOFT_RESET_FDVT_WRB_1_SOFT_RST Fld(1,3,AC_MSKB0)//[3:3]
    #define DMA_SOFT_RESET_FDVT_WRB_0_SOFT_RST Fld(1,2,AC_MSKB0)//[2:2]
    #define DMA_SOFT_RESET_FDVT_WRA_1_SOFT_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define DMA_SOFT_RESET_FDVT_WRA_0_SOFT_RST Fld(1,0,AC_MSKB0)//[0:0]
#define LAST_ULTRA_EN (FD_BASE + 0x218)
    #define LAST_ULTRA_EN_FDVT_WRB_1_LAST_ULTRA_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define LAST_ULTRA_EN_FDVT_WRB_0_LAST_ULTRA_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define LAST_ULTRA_EN_FDVT_WRA_1_LAST_ULTRA_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define LAST_ULTRA_EN_FDVT_WRA_0_LAST_ULTRA_EN Fld(1,0,AC_MSKB0)//[0:0]
#define SPECIAL_FUN_EN (FD_BASE + 0x21C)
    #define SPECIAL_FUN_EN_SLOW_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define SPECIAL_FUN_EN_GCLAST_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define SPECIAL_FUN_EN_FIFO_CHANGE_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define SPECIAL_FUN_EN_CONTINUOUS_COM_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define SPECIAL_FUN_EN_MULTI_PLANE_ID_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define SPECIAL_FUN_EN_CONTINUOUS_COM_CON Fld(2,20,AC_MSKB2)//[21:20]
    #define SPECIAL_FUN_EN_SLOW_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRA_0_BASE_ADDR (FD_BASE + 0x230)
    #define FDVT_WRA_0_BASE_ADDR_BASE_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_WRA_0_OFST_ADDR (FD_BASE + 0x238)
    #define FDVT_WRA_0_OFST_ADDR_OFFSET_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_WRA_0_XSIZE (FD_BASE + 0x240)
    #define FDVT_WRA_0_XSIZE_XSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRA_0_YSIZE (FD_BASE + 0x244)
    #define FDVT_WRA_0_YSIZE_YSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRA_0_STRIDE (FD_BASE + 0x248)
    #define FDVT_WRA_0_STRIDE_BUS_SIZE_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_WRA_0_STRIDE_FORMAT_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FDVT_WRA_0_STRIDE_FORMAT Fld(2,20,AC_MSKB2)//[21:20]
    #define FDVT_WRA_0_STRIDE_BUS_SIZE Fld(4,16,AC_MSKB2)//[19:16]
    #define FDVT_WRA_0_STRIDE_STRIDE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRA_0_CON (FD_BASE + 0x24C)
    #define FDVT_WRA_0_CON_MAX_BURST_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define FDVT_WRA_0_CON_FIFO_SIZE Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRA_0_CON2 (FD_BASE + 0x250)
    #define FDVT_WRA_0_CON2_FIFO_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_WRA_0_CON2_FIFO_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRA_0_CON3 (FD_BASE + 0x254)
    #define FDVT_WRA_0_CON3_FIFO_PRE_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_WRA_0_CON3_FIFO_PRE_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRA_0_CROP (FD_BASE + 0x258)
    #define FDVT_WRA_0_CROP_YOFFSET Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_WRA_0_CROP_XOFFSET Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRA_1_BASE_ADDR (FD_BASE + 0x260)
    #define FDVT_WRA_1_BASE_ADDR_BASE_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_WRA_1_OFST_ADDR (FD_BASE + 0x268)
    #define FDVT_WRA_1_OFST_ADDR_OFFSET_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_WRA_1_XSIZE (FD_BASE + 0x270)
    #define FDVT_WRA_1_XSIZE_XSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRA_1_YSIZE (FD_BASE + 0x274)
    #define FDVT_WRA_1_YSIZE_YSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRA_1_STRIDE (FD_BASE + 0x278)
    #define FDVT_WRA_1_STRIDE_BUS_SIZE_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_WRA_1_STRIDE_FORMAT_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FDVT_WRA_1_STRIDE_FORMAT Fld(2,20,AC_MSKB2)//[21:20]
    #define FDVT_WRA_1_STRIDE_BUS_SIZE Fld(4,16,AC_MSKB2)//[19:16]
    #define FDVT_WRA_1_STRIDE_STRIDE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRA_1_CON (FD_BASE + 0x27C)
    #define FDVT_WRA_1_CON_MAX_BURST_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define FDVT_WRA_1_CON_FIFO_SIZE Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRA_1_CON2 (FD_BASE + 0x280)
    #define FDVT_WRA_1_CON2_FIFO_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_WRA_1_CON2_FIFO_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRA_1_CON3 (FD_BASE + 0x284)
    #define FDVT_WRA_1_CON3_FIFO_PRE_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_WRA_1_CON3_FIFO_PRE_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRA_1_CROP (FD_BASE + 0x288)
    #define FDVT_WRA_1_CROP_YOFFSET Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_WRA_1_CROP_XOFFSET Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDA_0_BASE_ADDR (FD_BASE + 0x290)
    #define FDVT_RDA_0_BASE_ADDR_BASE_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_RDA_0_OFST_ADDR (FD_BASE + 0x298)
    #define FDVT_RDA_0_OFST_ADDR_OFFSET_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_RDA_0_XSIZE (FD_BASE + 0x2A0)
    #define FDVT_RDA_0_XSIZE_XSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDA_0_YSIZE (FD_BASE + 0x2A4)
    #define FDVT_RDA_0_YSIZE_YSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDA_0_STRIDE (FD_BASE + 0x2A8)
    #define FDVT_RDA_0_STRIDE_SWAP Fld(2,30,AC_MSKB3)//[31:30]
    #define FDVT_RDA_0_STRIDE_BUS_SIZE_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_RDA_0_STRIDE_FORMAT_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FDVT_RDA_0_STRIDE_FORMAT Fld(2,20,AC_MSKB2)//[21:20]
    #define FDVT_RDA_0_STRIDE_BUS_SIZE Fld(4,16,AC_MSKB2)//[19:16]
    #define FDVT_RDA_0_STRIDE_STRIDE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDA_0_CON (FD_BASE + 0x2AC)
    #define FDVT_RDA_0_CON_MAX_BURST_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define FDVT_RDA_0_CON_FIFO_SIZE Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDA_0_CON2 (FD_BASE + 0x2B0)
    #define FDVT_RDA_0_CON2_FIFO_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RDA_0_CON2_FIFO_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDA_0_CON3 (FD_BASE + 0x2B4)
    #define FDVT_RDA_0_CON3_FIFO_PRE_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RDA_0_CON3_FIFO_PRE_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDA_1_BASE_ADDR (FD_BASE + 0x2C0)
    #define FDVT_RDA_1_BASE_ADDR_BASE_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_RDA_1_OFST_ADDR (FD_BASE + 0x2C8)
    #define FDVT_RDA_1_OFST_ADDR_OFFSET_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_RDA_1_XSIZE (FD_BASE + 0x2D0)
    #define FDVT_RDA_1_XSIZE_XSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDA_1_YSIZE (FD_BASE + 0x2D4)
    #define FDVT_RDA_1_YSIZE_YSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDA_1_STRIDE (FD_BASE + 0x2D8)
    #define FDVT_RDA_1_STRIDE_SWAP Fld(2,30,AC_MSKB3)//[31:30]
    #define FDVT_RDA_1_STRIDE_BUS_SIZE_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_RDA_1_STRIDE_FORMAT_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FDVT_RDA_1_STRIDE_FORMAT Fld(2,20,AC_MSKB2)//[21:20]
    #define FDVT_RDA_1_STRIDE_BUS_SIZE Fld(4,16,AC_MSKB2)//[19:16]
    #define FDVT_RDA_1_STRIDE_STRIDE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDA_1_CON (FD_BASE + 0x2DC)
    #define FDVT_RDA_1_CON_MAX_BURST_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define FDVT_RDA_1_CON_FIFO_SIZE Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDA_1_CON2 (FD_BASE + 0x2E0)
    #define FDVT_RDA_1_CON2_FIFO_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RDA_1_CON2_FIFO_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDA_1_CON3 (FD_BASE + 0x2E4)
    #define FDVT_RDA_1_CON3_FIFO_PRE_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RDA_1_CON3_FIFO_PRE_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRB_0_BASE_ADDR (FD_BASE + 0x2F0)
    #define FDVT_WRB_0_BASE_ADDR_BASE_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_WRB_0_OFST_ADDR (FD_BASE + 0x2F8)
    #define FDVT_WRB_0_OFST_ADDR_OFFSET_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_WRB_0_XSIZE (FD_BASE + 0x300)
    #define FDVT_WRB_0_XSIZE_XSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRB_0_YSIZE (FD_BASE + 0x304)
    #define FDVT_WRB_0_YSIZE_YSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRB_0_STRIDE (FD_BASE + 0x308)
    #define FDVT_WRB_0_STRIDE_BUS_SIZE_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_WRB_0_STRIDE_FORMAT_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FDVT_WRB_0_STRIDE_FORMAT Fld(2,20,AC_MSKB2)//[21:20]
    #define FDVT_WRB_0_STRIDE_BUS_SIZE Fld(4,16,AC_MSKB2)//[19:16]
    #define FDVT_WRB_0_STRIDE_STRIDE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRB_0_CON (FD_BASE + 0x30C)
    #define FDVT_WRB_0_CON_MAX_BURST_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define FDVT_WRB_0_CON_FIFO_SIZE Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRB_0_CON2 (FD_BASE + 0x310)
    #define FDVT_WRB_0_CON2_FIFO_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_WRB_0_CON2_FIFO_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRB_0_CON3 (FD_BASE + 0x314)
    #define FDVT_WRB_0_CON3_FIFO_PRE_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_WRB_0_CON3_FIFO_PRE_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRB_0_CROP (FD_BASE + 0x318)
    #define FDVT_WRB_0_CROP_YOFFSET Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_WRB_0_CROP_XOFFSET Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRB_1_BASE_ADDR (FD_BASE + 0x320)
    #define FDVT_WRB_1_BASE_ADDR_BASE_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_WRB_1_OFST_ADDR (FD_BASE + 0x328)
    #define FDVT_WRB_1_OFST_ADDR_OFFSET_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_WRB_1_XSIZE (FD_BASE + 0x330)
    #define FDVT_WRB_1_XSIZE_XSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRB_1_YSIZE (FD_BASE + 0x334)
    #define FDVT_WRB_1_YSIZE_YSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRB_1_STRIDE (FD_BASE + 0x338)
    #define FDVT_WRB_1_STRIDE_BUS_SIZE_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_WRB_1_STRIDE_FORMAT_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FDVT_WRB_1_STRIDE_FORMAT Fld(2,20,AC_MSKB2)//[21:20]
    #define FDVT_WRB_1_STRIDE_BUS_SIZE Fld(4,16,AC_MSKB2)//[19:16]
    #define FDVT_WRB_1_STRIDE_STRIDE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRB_1_CON (FD_BASE + 0x33C)
    #define FDVT_WRB_1_CON_MAX_BURST_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define FDVT_WRB_1_CON_FIFO_SIZE Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRB_1_CON2 (FD_BASE + 0x340)
    #define FDVT_WRB_1_CON2_FIFO_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_WRB_1_CON2_FIFO_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRB_1_CON3 (FD_BASE + 0x344)
    #define FDVT_WRB_1_CON3_FIFO_PRE_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_WRB_1_CON3_FIFO_PRE_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_WRB_1_CROP (FD_BASE + 0x348)
    #define FDVT_WRB_1_CROP_YOFFSET Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_WRB_1_CROP_XOFFSET Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDB_0_BASE_ADDR (FD_BASE + 0x350)
    #define FDVT_RDB_0_BASE_ADDR_BASE_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_RDB_0_OFST_ADDR (FD_BASE + 0x358)
    #define FDVT_RDB_0_OFST_ADDR_OFFSET_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_RDB_0_XSIZE (FD_BASE + 0x360)
    #define FDVT_RDB_0_XSIZE_XSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDB_0_YSIZE (FD_BASE + 0x364)
    #define FDVT_RDB_0_YSIZE_YSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDB_0_STRIDE (FD_BASE + 0x368)
    #define FDVT_RDB_0_STRIDE_SWAP Fld(2,30,AC_MSKB3)//[31:30]
    #define FDVT_RDB_0_STRIDE_BUS_SIZE_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_RDB_0_STRIDE_FORMAT_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FDVT_RDB_0_STRIDE_FORMAT Fld(2,20,AC_MSKB2)//[21:20]
    #define FDVT_RDB_0_STRIDE_BUS_SIZE Fld(4,16,AC_MSKB2)//[19:16]
    #define FDVT_RDB_0_STRIDE_STRIDE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDB_0_CON (FD_BASE + 0x36C)
    #define FDVT_RDB_0_CON_MAX_BURST_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define FDVT_RDB_0_CON_FIFO_SIZE Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDB_0_CON2 (FD_BASE + 0x370)
    #define FDVT_RDB_0_CON2_FIFO_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RDB_0_CON2_FIFO_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDB_0_CON3 (FD_BASE + 0x374)
    #define FDVT_RDB_0_CON3_FIFO_PRE_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RDB_0_CON3_FIFO_PRE_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDB_1_BASE_ADDR (FD_BASE + 0x380)
    #define FDVT_RDB_1_BASE_ADDR_BASE_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_RDB_1_OFST_ADDR (FD_BASE + 0x388)
    #define FDVT_RDB_1_OFST_ADDR_OFFSET_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_RDB_1_XSIZE (FD_BASE + 0x390)
    #define FDVT_RDB_1_XSIZE_XSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDB_1_YSIZE (FD_BASE + 0x394)
    #define FDVT_RDB_1_YSIZE_YSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDB_1_STRIDE (FD_BASE + 0x398)
    #define FDVT_RDB_1_STRIDE_SWAP Fld(2,30,AC_MSKB3)//[31:30]
    #define FDVT_RDB_1_STRIDE_BUS_SIZE_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_RDB_1_STRIDE_FORMAT_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FDVT_RDB_1_STRIDE_FORMAT Fld(2,20,AC_MSKB2)//[21:20]
    #define FDVT_RDB_1_STRIDE_BUS_SIZE Fld(4,16,AC_MSKB2)//[19:16]
    #define FDVT_RDB_1_STRIDE_STRIDE Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDB_1_CON (FD_BASE + 0x39C)
    #define FDVT_RDB_1_CON_MAX_BURST_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define FDVT_RDB_1_CON_FIFO_SIZE Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDB_1_CON2 (FD_BASE + 0x3A0)
    #define FDVT_RDB_1_CON2_FIFO_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RDB_1_CON2_FIFO_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RDB_1_CON3 (FD_BASE + 0x3A4)
    #define FDVT_RDB_1_CON3_FIFO_PRE_PRI_THRH Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RDB_1_CON3_FIFO_PRE_PRI_THRL Fld(12,0,AC_MSKW10)//[11:0]
#define DMA_ERR_CTRL (FD_BASE + 0x3B0)
    #define DMA_ERR_CTRL_ERR_CLR_MD Fld(1,31,AC_MSKB3)//[31:31]
    #define DMA_ERR_CTRL_FDVT_RDB_1_ERR Fld(1,19,AC_MSKB2)//[19:19]
    #define DMA_ERR_CTRL_FDVT_RDB_0_ERR Fld(1,18,AC_MSKB2)//[18:18]
    #define DMA_ERR_CTRL_FDVT_RDA_1_ERR Fld(1,17,AC_MSKB2)//[17:17]
    #define DMA_ERR_CTRL_FDVT_RDA_0_ERR Fld(1,16,AC_MSKB2)//[16:16]
    #define DMA_ERR_CTRL_FDVT_WRB_1_ERR Fld(1,3,AC_MSKB0)//[3:3]
    #define DMA_ERR_CTRL_FDVT_WRB_0_ERR Fld(1,2,AC_MSKB0)//[2:2]
    #define DMA_ERR_CTRL_FDVT_WRA_1_ERR Fld(1,1,AC_MSKB0)//[1:1]
    #define DMA_ERR_CTRL_FDVT_WRA_0_ERR Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_WRA_0_ERR_STAT (FD_BASE + 0x3B4)
    #define FDVT_WRA_0_ERR_STAT_ERR_EN Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_WRA_0_ERR_STAT_ERR_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRA_1_ERR_STAT (FD_BASE + 0x3B8)
    #define FDVT_WRA_1_ERR_STAT_ERR_EN Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_WRA_1_ERR_STAT_ERR_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRB_0_ERR_STAT (FD_BASE + 0x3BC)
    #define FDVT_WRB_0_ERR_STAT_ERR_EN Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_WRB_0_ERR_STAT_ERR_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_WRB_1_ERR_STAT (FD_BASE + 0x3C0)
    #define FDVT_WRB_1_ERR_STAT_ERR_EN Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_WRB_1_ERR_STAT_ERR_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDA_0_ERR_STAT (FD_BASE + 0x3C4)
    #define FDVT_RDA_0_ERR_STAT_ERR_EN Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_RDA_0_ERR_STAT_ERR_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDA_1_ERR_STAT (FD_BASE + 0x3C8)
    #define FDVT_RDA_1_ERR_STAT_ERR_EN Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_RDA_1_ERR_STAT_ERR_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDB_0_ERR_STAT (FD_BASE + 0x3CC)
    #define FDVT_RDB_0_ERR_STAT_ERR_EN Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_RDB_0_ERR_STAT_ERR_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_RDB_1_ERR_STAT (FD_BASE + 0x3D0)
    #define FDVT_RDB_1_ERR_STAT_ERR_EN Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_RDB_1_ERR_STAT_ERR_STAT Fld(16,0,AC_FULLW10)//[15:0]
#define DMA_DEBUG_ADDR (FD_BASE + 0x3E0)
    #define DMA_DEBUG_ADDR_DEBUG_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define DMA_RSV1 (FD_BASE + 0x3E4)
    #define DMA_RSV1_RSV Fld(32,0,AC_FULLDW)//[31:0]
#define DMA_RSV2 (FD_BASE + 0x3E8)
    #define DMA_RSV2_RSV Fld(32,0,AC_FULLDW)//[31:0]
#define DMA_RSV3 (FD_BASE + 0x3EC)
    #define DMA_RSV3_RSV Fld(32,0,AC_FULLDW)//[31:0]
#define DMA_RSV4 (FD_BASE + 0x3F0)
    #define DMA_RSV4_RSV Fld(32,0,AC_FULLDW)//[31:0]
#define DMA_DEBUG_SEL (FD_BASE + 0x3F4)
    #define DMA_DEBUG_SEL_ARBITER_COM_FULL Fld(1,31,AC_MSKB3)//[31:31]
    #define DMA_DEBUG_SEL_ARBITER_BVALID_FULL Fld(1,30,AC_MSKB3)//[30:30]
    #define DMA_DEBUG_SEL_SUB_MODULE_SEL Fld(8,16,AC_FULLB2)//[23:16]
    #define DMA_DEBUG_SEL_R_W_DMA_TOP_SEL Fld(8,8,AC_FULLB1)//[15:8]
    #define DMA_DEBUG_SEL_DMA_TOP_SEL Fld(8,0,AC_FULLB0)//[7:0]
#define DMA_BW_SELF_TEST (FD_BASE + 0x3F8)
    #define DMA_BW_SELF_TEST_BW_SELF_TEST_EN_FDVT_WRB_1 Fld(1,3,AC_MSKB0)//[3:3]
    #define DMA_BW_SELF_TEST_BW_SELF_TEST_EN_FDVT_WRB_0 Fld(1,2,AC_MSKB0)//[2:2]
    #define DMA_BW_SELF_TEST_BW_SELF_TEST_EN_FDVT_WRA_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define DMA_BW_SELF_TEST_BW_SELF_TEST_EN_FDVT_WRA_0 Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_START (FD_BASE + 0x000)
    #define FDVT_START_DMA_STOP Fld(1,17,AC_MSKB2)//[17:17]
    #define FDVT_START_HARD_RST Fld(1,16,AC_MSKB2)//[16:16]
    #define FDVT_START_START Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_ENABLE (FD_BASE + 0x004)
    #define FDVT_ENABLE_FD_ENABLE Fld(1,8,AC_MSKB1)//[8:8]
    #define FDVT_ENABLE_RS_EABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define FDVT_ENABLE_RGB2YUV_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_RS (FD_BASE + 0x008)
    #define FDVT_RS_SCALING_COEFF Fld(3,8,AC_MSKB1)//[10:8]
    #define FDVT_RS_RS_LOOP_NUM Fld(5,0,AC_MSKB0)//[4:0]
#define FDVT_RSCON_BASE_ADR (FD_BASE + 0x00C)
    #define FDVT_RSCON_BASE_ADR_RS_CONFIG_BASE_ADR Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_YUV2RGB (FD_BASE + 0x010)
    #define FDVT_YUV2RGB_YUV2RGB_DES_FORMAT Fld(3,4,AC_MSKB0)//[6:4]
    #define FDVT_YUV2RGB_YUV2RGB_SRC_FORMAT Fld(3,0,AC_MSKB0)//[2:0]

//Page FDVT_A_2
#define FDVT_FD_PACK_MODE (FD_BASE + 0x014)
    #define FDVT_FD_PACK_MODE_IN_CHANNEL_PACK Fld(2,28,AC_MSKB3)//[29:28]
    #define FDVT_FD_PACK_MODE_KERNEL_OUT_CHANNEL_PACK Fld(2,25,AC_MSKB3)//[26:25]
    #define FDVT_FD_PACK_MODE_KERNEL_CHANNEL_PACK Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_FD_PACK_MODE_OUT_CHANNEL_PACK Fld(2,20,AC_MSKB2)//[21:20]
    #define FDVT_FD_PACK_MODE_INPUT_CHANNEL Fld(8,8,AC_FULLB1)//[15:8]
    #define FDVT_FD_PACK_MODE_OUTPUT_CHANNEL Fld(8,0,AC_FULLB0)//[7:0]
#define FDVT_CONV0 (FD_BASE + 0x018)
    #define FDVT_CONV0_OUTLAYER_PACK7_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define FDVT_CONV0_OUTLAYER_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_CONV0_MAX_POOLING_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define FDVT_CONV0_RELU_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define FDVT_CONV0_INPUT_ROTATE Fld(2,12,AC_MSKB1)//[13:12]
    #define FDVT_CONV0_INPUT_STRIDE Fld(1,8,AC_MSKB1)//[8:8]
    #define FDVT_CONV0_INPUT_KERNEL Fld(1,4,AC_MSKB0)//[4:4]
    #define FDVT_CONV0_CONV_TYPE Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_CONV1 (FD_BASE + 0x01C)
    #define FDVT_CONV1_OUTPUT_TWO_SIZE Fld(1,28,AC_MSKB3)//[28:28]
    #define FDVT_CONV1_OUTLAYER_LOGIT Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_CONV1_CONV_WIDTH_MOD6 Fld(3,20,AC_MSKB2)//[22:20]
    #define FDVT_CONV1_QUANTIZE_ADD_DELTA Fld(1,16,AC_MSKB2)//[16:16]
    #define FDVT_CONV1_QUANTIZE_SHIFT_MODE Fld(6,8,AC_MSKB1)//[13:8]
    #define FDVT_CONV1_BIAS_SHIFT_MODE Fld(6,0,AC_MSKB0)//[5:0]
#define FDVT_CONV_WD_HT (FD_BASE + 0x020)
    #define FDVT_CONV_WD_HT_CONV_IMG_WD Fld(11,16,AC_MSKW32)//[26:16]
    #define FDVT_CONV_WD_HT_CONVT_IMG_HT Fld(11,0,AC_MSKW10)//[10:0]
#define FDVT_SRC_WD_HT (FD_BASE + 0x024)
    #define FDVT_SRC_WD_HT_INPUT_IMG_WD Fld(11,16,AC_MSKW32)//[26:16]
    #define FDVT_SRC_WD_HT_INPUT_IMG_HT Fld(11,0,AC_MSKW10)//[10:0]
#define FDVT_DES_WD_HT (FD_BASE + 0x028)
    #define FDVT_DES_WD_HT_OUTPUT_IMG_WD Fld(11,16,AC_MSKW32)//[26:16]
    #define FDVT_DES_WD_HT_OUTPUT_IMG_HT Fld(11,0,AC_MSKW10)//[10:0]
#define FDVT_YUV2RGBCON_BASE_ADR (FD_BASE + 0x02C)
    #define FDVT_YUV2RGBCON_BASE_ADR_YUV2RGB_CONFIG_BASE_ADR Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_KERNEL (FD_BASE + 0x030)
    #define FDVT_KERNEL_KERNEL_FNUM Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_KERNEL_BIAS_FNUM Fld(8,0,AC_FULLB0)//[7:0]
#define FDVT_IN_SIZE_0 (FD_BASE + 0x034)
    #define FDVT_IN_SIZE_0_IN_YSIZE_0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_IN_SIZE_0_IN_XSIZE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_IN_STRIDE_0 (FD_BASE + 0x038)
    #define FDVT_IN_STRIDE_0_IN_STRIDE_0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_IN_STRIDE_0_IN_BUS_SIZE_0 Fld(4,0,AC_MSKB0)//[3:0]
#define FDVT_IN_SIZE_1 (FD_BASE + 0x03C)
    #define FDVT_IN_SIZE_1_IN_YSIZE_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_IN_SIZE_1_IN_XSIZE_1 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_IN_STRIDE_1 (FD_BASE + 0x040)
    #define FDVT_IN_STRIDE_1_IN_STRIDE_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_IN_STRIDE_1_IN_BUS_SIZE_1 Fld(4,0,AC_MSKB0)//[3:0]
#define FDVT_IN_SIZE_2 (FD_BASE + 0x044)
    #define FDVT_IN_SIZE_2_IN_YSIZE_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_IN_SIZE_2_IN_XSIZE_2 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_IN_STRIDE_2 (FD_BASE + 0x048)
    #define FDVT_IN_STRIDE_2_IN_STRIDE_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_IN_STRIDE_2_IN_BUS_SIZE_2 Fld(4,0,AC_MSKB0)//[3:0]
#define FDVT_IN_SIZE_3 (FD_BASE + 0x04C)
    #define FDVT_IN_SIZE_3_IN_YSIZE_3 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_IN_SIZE_3_IN_XSIZE_3 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_IN_STRIDE_3 (FD_BASE + 0x050)
    #define FDVT_IN_STRIDE_3_IN_STRIDE_3 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_IN_STRIDE_3_IN_BUS_SIZE_3 Fld(4,0,AC_MSKB0)//[3:0]
#define FDVT_OUT_SIZE_0 (FD_BASE + 0x054)
    #define FDVT_OUT_SIZE_0_OUT_YSIZE_0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_OUT_SIZE_0_OUT_XSIZE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_OUT_STRIDE_0 (FD_BASE + 0x058)
    #define FDVT_OUT_STRIDE_0_OUT_STRIDE_0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_OUT_STRIDE_0_OUT_BUS_SIZE_0 Fld(4,0,AC_MSKB0)//[3:0]
#define FDVT_OUT_SIZE_1 (FD_BASE + 0x05C)
    #define FDVT_OUT_SIZE_1_OUT_YSIZE_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_OUT_SIZE_1_OUT_XSIZE_1 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_OUT_STRIDE_1 (FD_BASE + 0x060)
    #define FDVT_OUT_STRIDE_1_OUT_STRIDE_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_OUT_STRIDE_1_OUT_BUS_SIZE_1 Fld(4,0,AC_MSKB0)//[3:0]
#define FDVT_OUT_SIZE_2 (FD_BASE + 0x064)
    #define FDVT_OUT_SIZE_2_OUT_YSIZE_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_OUT_SIZE_2_OUT_XSIZE_2 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_OUT_STRIDE_2 (FD_BASE + 0x068)
    #define FDVT_OUT_STRIDE_2_OUT_STRIDE_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_OUT_STRIDE_2_OUT_BUS_SIZE_2 Fld(4,0,AC_MSKB0)//[3:0]
#define FDVT_OUT_SIZE_3 (FD_BASE + 0x06C)
    #define FDVT_OUT_SIZE_3_OUT_YSIZE_3 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_OUT_SIZE_3_OUT_XSIZE_3 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_OUT_STRIDE_3 (FD_BASE + 0x070)
    #define FDVT_OUT_STRIDE_3_OUT_STRIDE_3 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_OUT_STRIDE_3_OUT_BUS_SIZE_3 Fld(4,0,AC_MSKB0)//[3:0]
#define FDVT_KERNEL_SIZE (FD_BASE + 0x074)
    #define FDVT_KERNEL_SIZE_KERNEL_YSIZE_3 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_KERNEL_SIZE_KERNEL_XSIZE_3 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_KERNEL_STRIDE (FD_BASE + 0x078)
    #define FDVT_KERNEL_STRIDE_KERNEL_STRIDE Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_KERNEL_STRIDE_KERNEL_BUS_SIZE Fld(4,0,AC_MSKB0)//[3:0]
#define FDVT_IN_BASE_ADR_0 (FD_BASE + 0x07C)
    #define FDVT_IN_BASE_ADR_0_IN_FM_BASE_ADR_0 Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_IN_BASE_ADR_1 (FD_BASE + 0x080)
    #define FDVT_IN_BASE_ADR_1_IN_FM_BASE_ADR_1 Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_IN_BASE_ADR_2 (FD_BASE + 0x084)
    #define FDVT_IN_BASE_ADR_2_IN_FM_BASE_ADR_2 Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_IN_BASE_ADR_3 (FD_BASE + 0x088)
    #define FDVT_IN_BASE_ADR_3_IN_FM_BASE_ADR_3 Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_OUT_BASE_ADR_0 (FD_BASE + 0x08C)
    #define FDVT_OUT_BASE_ADR_0_OUT_FM_BASE_ADR_0 Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_OUT_BASE_ADR_1 (FD_BASE + 0x090)
    #define FDVT_OUT_BASE_ADR_1_OUT_FM_BASE_ADR_1 Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_OUT_BASE_ADR_2 (FD_BASE + 0x094)
    #define FDVT_OUT_BASE_ADR_2_OUT_FM_BASE_ADR_2 Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_OUT_BASE_ADR_3 (FD_BASE + 0x098)
    #define FDVT_OUT_BASE_ADR_3_OUT_FM_BASE_ADR_3 Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_KERNEL_BASE_ADR_0 (FD_BASE + 0x09C)
    #define FDVT_KERNEL_BASE_ADR_0_KERNEL_BASE_ADR_ Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_KERNEL_BASE_ADR_1 (FD_BASE + 0x0A0)
    #define FDVT_KERNEL_BASE_ADR_1_KERNEL_BASE_ADR_ Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_FD (FD_BASE + 0x0A4)
    #define FDVT_FD_MAX_FACE_NUM Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_FD_FD_LOOP_NUM Fld(7,0,AC_MSKB0)//[6:0]
#define FDVT_FD_CON_BASE_ADR (FD_BASE + 0x0A8)
    #define FDVT_FD_CON_BASE_ADR_FD_CONFIG_BASE_ADR Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_FD_RLT_BASE_ADR (FD_BASE + 0x0B0)
    #define FDVT_FD_RLT_BASE_ADR_FD_RESULT_BASE_ADR Fld(28,4,AC_MSKDW)//[31:4]
#define FDVT_RPN (FD_BASE + 0x0B4)
    #define FDVT_RPN_RPN_ANCHOR_THRD Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_RPN_RPN_ANCHOR_NUM Fld(3,12,AC_MSKB1)//[14:12]
    #define FDVT_RPN_RPN_ANCHOR_STEP Fld(4,8,AC_MSKB1)//[11:8]
    #define FDVT_RPN_RPN_BLOCK_SIZE Fld(2,4,AC_MSKB0)//[5:4]
    #define FDVT_RPN_RPN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_FD_ANCHOR0_INFO0 (FD_BASE + 0x0B8)
    #define FDVT_FD_ANCHOR0_INFO0_ANCHOR_HEIGHT_0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_FD_ANCHOR0_INFO0_ANCHOR_WIDTH_0 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_FD_ANCHOR1_INFO0 (FD_BASE + 0x0C4)
    #define FDVT_FD_ANCHOR1_INFO0_ANCHOR_HEIGHT_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_FD_ANCHOR1_INFO0_ANCHOR_WIDTH_1 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_FD_ANCHOR2_INFO0 (FD_BASE + 0x0D0)
    #define FDVT_FD_ANCHOR2_INFO0_ANCHOR_HEIGHT_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_FD_ANCHOR2_INFO0_ANCHOR_WIDTH_2 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_FD_ANCHOR3_INFO0 (FD_BASE + 0x0DC)
    #define FDVT_FD_ANCHOR3_INFO0_ANCHOR_HEIGHT_3 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_FD_ANCHOR3_INFO0_ANCHOR_WIDTH_3 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_FD_ANCHOR4_INFO0 (FD_BASE + 0x0E8)
    #define FDVT_FD_ANCHOR4_INFO0_ANCHOR_HEIGHT_4 Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_FD_ANCHOR4_INFO0_ANCHOR_WIDTH_4 Fld(16,0,AC_FULLW10)//[15:0]
#define FDVT_YUV_SRC_WD_HT (FD_BASE + 0x0F4)
    #define FDVT_YUV_SRC_WD_HT_YUV_SRC_IMG_WD Fld(11,16,AC_MSKW32)//[26:16]
    #define FDVT_YUV_SRC_WD_HT_YUV_SRC_IMG_HT Fld(11,0,AC_MSKW10)//[10:0]
#define FDVT_INT_EN (FD_BASE + 0x15C)
    #define FDVT_INT_EN_FD_DONE Fld(1,25,AC_MSKB3)//[25:25]
    #define FDVT_INT_EN_FD_BUSY Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_INT_EN_FF_DONE Fld(1,21,AC_MSKB2)//[21:21]
    #define FDVT_INT_EN_FF_BUSY Fld(1,20,AC_MSKB2)//[20:20]
    #define FDVT_INT_EN_RS_DONE Fld(1,17,AC_MSKB2)//[17:17]
    #define FDVT_INT_EN_RS_BUSY Fld(1,16,AC_MSKB2)//[16:16]
    #define FDVT_INT_EN_INT_RD_CNT Fld(3,8,AC_MSKB1)//[10:8]
    #define FDVT_INT_EN_INT_CLR_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FDVT_INT_EN_INT_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_INT (FD_BASE + 0x168)
    #define FDVT_INT_INT_FDVT Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_DEBUG_INFO_1 (FD_BASE + 0x16C)
    #define FDVT_DEBUG_INFO_1_DCM_SHARE_MEM_ST Fld(1,29,AC_MSKB3)//[29:29]
    #define FDVT_DEBUG_INFO_1_DCM_DMA_ST Fld(1,28,AC_MSKB3)//[28:28]
    #define FDVT_DEBUG_INFO_1_DCM_FD_ST Fld(1,27,AC_MSKB3)//[27:27]
    #define FDVT_DEBUG_INFO_1_DCM_RS_ST Fld(1,26,AC_MSKB3)//[26:26]
    #define FDVT_DEBUG_INFO_1_DCM_YUV2RGB_ST Fld(1,25,AC_MSKB3)//[25:25]
    #define FDVT_DEBUG_INFO_1_DCM_SEQ_ST Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_DEBUG_INFO_1_YUV2RGB_LOOP_CNT Fld(5,16,AC_MSKB2)//[20:16]
    #define FDVT_DEBUG_INFO_1_RS_LOOP_CNT Fld(5,8,AC_MSKB1)//[12:8]
    #define FDVT_DEBUG_INFO_1_FD_LOOP_CNT Fld(5,0,AC_MSKB0)//[4:0]
#define FDVT_DEBUG_INFO_2 (FD_BASE + 0x170)
    #define FDVT_DEBUG_INFO_2_RS_DETECT_H_CNT Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_DEBUG_INFO_2_RS_DETECT_V_CNT Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_DEBUG_INFO_3 (FD_BASE + 0x174)
    #define FDVT_DEBUG_INFO_3_FD_DETECT_X Fld(10,16,AC_MSKW32)//[25:16]
    #define FDVT_DEBUG_INFO_3_FD_DETECT_Y Fld(10,0,AC_MSKW10)//[9:0]
#define FDVT_RESULT (FD_BASE + 0x178)
    #define FDVT_RESULT_FD_PYRAMID0_NUM Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RESULT_FD_NUM Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_RESULT_1 (FD_BASE + 0x17C)
    #define FDVT_RESULT_1_FD_PYRAMID2_NUM Fld(12,16,AC_MSKW32)//[27:16]
    #define FDVT_RESULT_1_FD_PYRAMID1_NUM Fld(12,0,AC_MSKW10)//[11:0]
#define FDVT_DMA_CTL (FD_BASE + 0x180)
    #define FDVT_DMA_CTL_WRB_1_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define FDVT_DMA_CTL_WRB_0_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_DMA_CTL_WRA_1_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define FDVT_DMA_CTL_WRA_0_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define FDVT_DMA_CTL_RB_1_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FDVT_DMA_CTL_RB_0_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define FDVT_DMA_CTL_RA_1_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define FDVT_DMA_CTL_RA_0_EN Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_RPN_PACK_MODE (FD_BASE + 0x184)
    #define FDVT_RPN_PACK_MODE_IN_CHANNEL_PACK_3 Fld(2,12,AC_MSKB1)//[13:12]
    #define FDVT_RPN_PACK_MODE_IN_CHANNEL_PACK_2 Fld(2,8,AC_MSKB1)//[9:8]
    #define FDVT_RPN_PACK_MODE_IN_CHANNEL_PACK_1 Fld(2,4,AC_MSKB0)//[5:4]
    #define FDVT_RPN_PACK_MODE_IN_CHANNEL_PACK_0 Fld(2,0,AC_MSKB0)//[1:0]
#define FDVT_RSCON1 (FD_BASE + 0x188)
    #define FDVT_RSCON1_Y_MAG Fld(14,16,AC_MSKW32)//[29:16]
    #define FDVT_RSCON1_X_MAG Fld(14,0,AC_MSKW10)//[13:0]
#define FDVT_RSCON2 (FD_BASE + 0x18C)
    #define FDVT_RSCON2_YOFFSET Fld(9,16,AC_MSKW32)//[24:16]
    #define FDVT_RSCON2_XOFFSET Fld(9,0,AC_MSKW10)//[8:0]
#define FDVT_CONV2 (FD_BASE + 0x190)
    #define FDVT_CONV2_ACCUMULATOR_SHIFT_MODE_1 Fld(6,24,AC_MSKB3)//[29:24]
    #define FDVT_CONV2_BIAS_SHIFT_MODE_1 Fld(6,16,AC_MSKB2)//[21:16]
    #define FDVT_CONV2_DELTA_SHIFT_MODE Fld(6,8,AC_MSKB1)//[13:8]
    #define FDVT_CONV2_ACCUMULATOR_SHIFT_MODE Fld(6,0,AC_MSKB0)//[5:0]
#define FDVT_RPN_IMAGE_COORD (FD_BASE + 0x194)
    #define FDVT_RPN_IMAGE_COORD_IMAGE_COORD_SCALE Fld(15,4,AC_MSKDW)//[18:4]
    #define FDVT_RPN_IMAGE_COORD_IMAGE_COORD Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_SPARE_CELL (FD_BASE + 0x198)
    #define FDVT_SPARE_CELL_SPARE_CELL Fld(32,0,AC_FULLDW)//[31:0]
#define FDVT_CTRL (FD_BASE + 0x19C)
    #define FDVT_CTRL_WRB_1_PULTRA Fld(1,31,AC_MSKB3)//[31:31]
    #define FDVT_CTRL_WRB_1_ULTRA Fld(1,30,AC_MSKB3)//[30:30]
    #define FDVT_CTRL_WRB_0_PULTRA Fld(1,29,AC_MSKB3)//[29:29]
    #define FDVT_CTRL_WRB_0_ULTRA Fld(1,28,AC_MSKB3)//[28:28]
    #define FDVT_CTRL_WRA_1_PULTRA Fld(1,27,AC_MSKB3)//[27:27]
    #define FDVT_CTRL_WRA_1_ULTRA Fld(1,26,AC_MSKB3)//[26:26]
    #define FDVT_CTRL_WRA_0_PULTRA Fld(1,25,AC_MSKB3)//[25:25]
    #define FDVT_CTRL_WRA_0_ULTRA Fld(1,24,AC_MSKB3)//[24:24]
    #define FDVT_CTRL_RB_1_PULTRA Fld(1,23,AC_MSKB2)//[23:23]
    #define FDVT_CTRL_RB_1_ULTRA Fld(1,22,AC_MSKB2)//[22:22]
    #define FDVT_CTRL_RB_0_PULTRA Fld(1,21,AC_MSKB2)//[21:21]
    #define FDVT_CTRL_RB_0_ULTRA Fld(1,20,AC_MSKB2)//[20:20]
    #define FDVT_CTRL_RA_1_PULTRA Fld(1,19,AC_MSKB2)//[19:19]
    #define FDVT_CTRL_RA_1_ULTRA Fld(1,18,AC_MSKB2)//[18:18]
    #define FDVT_CTRL_RA_0_PULTRA Fld(1,17,AC_MSKB2)//[17:17]
    #define FDVT_CTRL_RA_0_ULTRA Fld(1,16,AC_MSKB2)//[16:16]
    #define FDVT_CTRL_DEBUG_MODULE_SEL Fld(3,13,AC_MSKB1)//[15:13]
    #define FDVT_CTRL_DEBUG_DATA_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define FDVT_CTRL_DCM_RPN_DIS Fld(1,6,AC_MSKB0)//[6:6]
    #define FDVT_CTRL_DCM_SHARE_MEM_DIS Fld(1,5,AC_MSKB0)//[5:5]
    #define FDVT_CTRL_DCM_DMA_DIS Fld(1,4,AC_MSKB0)//[4:4]
    #define FDVT_CTRL_DCM_FD_DIS Fld(1,3,AC_MSKB0)//[3:3]
    #define FDVT_CTRL_DCM_RS_DIS Fld(1,2,AC_MSKB0)//[2:2]
    #define FDVT_CTRL_DCM_YUV2RGB_DIS Fld(1,1,AC_MSKB0)//[1:1]
    #define FDVT_CTRL_DCM_SEQ_DIS Fld(1,0,AC_MSKB0)//[0:0]
#define FDVT_VERSION (FD_BASE + 0x1A0)
    #define FDVT_VERSION_YEAR Fld(16,16,AC_FULLW32)//[31:16]
    #define FDVT_VERSION_MONTH Fld(8,8,AC_FULLB1)//[15:8]
    #define FDVT_VERSION_DAY Fld(8,0,AC_FULLB0)//[7:0]
#define FDVT_ANCHOR_SHIFT0 (FD_BASE + 0x1A4)
    #define FDVT_ANCHOR_SHIFT0_ANCHOR_SHIFT_MODE_3 Fld(6,24,AC_MSKB3)//[29:24]
    #define FDVT_ANCHOR_SHIFT0_ANCHOR_SHIFT_MODE_2 Fld(6,16,AC_MSKB2)//[21:16]
    #define FDVT_ANCHOR_SHIFT0_ANCHOR_SHIFT_MODE_1 Fld(6,8,AC_MSKB1)//[13:8]
    #define FDVT_ANCHOR_SHIFT0_ANCHOR_SHIFT_MODE_0 Fld(6,0,AC_MSKB0)//[5:0]
#define FDVT_LANDMARK_SHIFT0 (FD_BASE + 0x1A8)
    #define FDVT_LANDMARK_SHIFT0_LANDMARK_SHIFT_MODE_3 Fld(6,24,AC_MSKB3)//[29:24]
    #define FDVT_LANDMARK_SHIFT0_LANDMARK_SHIFT_MODE_2 Fld(6,16,AC_MSKB2)//[21:16]
    #define FDVT_LANDMARK_SHIFT0_LANDMARK_SHIFT_MODE_1 Fld(6,8,AC_MSKB1)//[13:8]
    #define FDVT_LANDMARK_SHIFT0_LANDMARK_SHIFT_MODE_0 Fld(6,0,AC_MSKB0)//[5:0]
#define FDVT_ANCHOR_SHIFT1 (FD_BASE + 0x1AC)
    #define FDVT_ANCHOR_SHIFT1_ANCHOR_SHIFT_MODE_4 Fld(6,0,AC_MSKB0)//[5:0]
#define FDVT_LANDMARK_SHIFT1 (FD_BASE + 0x1B0)
    #define FDVT_LANDMARK_SHIFT1_LANDMARK_SHIFT_MODE_4 Fld(6,0,AC_MSKB0)//[5:0]

#endif

