/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _HW_DVI_H_
#define _HW_DVI_H_


#ifndef CC_UP8032_ATV
#define IO_VIRT_DVI (VDOIN_BASE)
#define IO_DVI_BASE (0x0000)
#else
#define IO_VIRT_DVI (VDOIN_BASE)
#define IO_DVI_BASE (0x4000)
#endif

#define CCH_SYS_01 (IO_VIRT_DVI+(IO_DVI_BASE+0x404))
    #define SYS_01_CCH_VHS_END      Fld(1,14,AC_MSKB1)

#define LPF_PIP_00 (IO_VIRT_DVI+(IO_DVI_BASE+0x420))
    #define CCH_VHS_END_MODE Fld(1,31,AC_MSKB3)//31
    #define DVI_VHS_END_MODE Fld(1,30,AC_MSKB3)//30

    #define DISP_R_INV              Fld(1,27,AC_MSKB3)//27
    #define DISP_R_MAIN_FREERUN     Fld(1,26,AC_MSKB3)//26
    #define DISP_R_MANUAL_VALUE     Fld(1,25,AC_MSKB3)//25
    #define DISP_R_MAIN_MANUAL_EN   Fld(1,24,AC_MSKB3)//24

    #define DVI_EN Fld(1,23,AC_MSKB2)//23
    #define MAIN_PROG_FLD_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define PIP_PROG_FLD_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define DVI_3D_PAT_MODE Fld(1,18,AC_MSKB2)//18
    #define DVI_3D_PAT_RIGHT Fld(1,17,AC_MSKB2)//17
    #define DVI_3D_PAT_LEFT Fld(1,16,AC_MSKB2)//16
    #define CCH_FLD_DET_EN Fld(1,15,AC_MSKB1)//15
    #define SP1_ANAIN Fld(1,14,AC_MSKB1)//[14:14]
    #define CCH_FIX_VCNT Fld(1,13,AC_MSKB1)//13
    #define DVI_3D_DISP_TOG Fld(1, 12, AC_MSKB1) //12
    #define CCH_CEN_4XSEL Fld(1, 11, AC_MSKB1) //11
    #define DVI_3D_VSYNC_TOG Fld(1,10,AC_MSKB1)//10
    #define DVI_3D_DISP_VAL Fld(1,9,AC_MSKB1)//9
    #define DVI_3D_MANUAL Fld(1,8,AC_MSKB1)//8
    #define DVI_3D_PIP_DISP_MASK_POL Fld(1,7,AC_MSKB0)//7
    #define DVI_3D_PIP_MASK_EN Fld(1,6,AC_MSKB0)//6
    #define DVI_3D_MAIN_DISP_MASK_POL Fld(1,5,AC_MSKB0)//5
    #define DVI_3D_MAIN_MASK_EN Fld(1,4,AC_MSKB0) //4
    #define DVI_3D_INTTGL Fld(1,3,AC_MSKB0)// 3
    #define DVI_3D_DISP_POL Fld(1,2,AC_MSKB0)//  2
    #define CCH_3D_INTTGL Fld(1,1,AC_MSKB0)// 1
    #define CCH_3D_DISP_POL Fld(1,0,AC_MSKB0) //0
#define VSRC_05 (IO_VIRT_DVI+(IO_DVI_BASE+0x42c))
    #define DVI_3D_Y_LFT Fld(4,28,AC_MSKB3)//[31:28]
    #define DVI_3D_CB_LFT Fld(4,24,AC_MSKB3)//[27:24]
    #define DVI_3D_CR_LFT Fld(4,20,AC_MSKB2)//[23:20]
    #define DVI_3D_SIZE_LFT Fld(4,16,AC_MSKB2)//[19:16]
    #define DVI_3D_XPOS_LFT Fld(8,8,AC_FULLB1)//[15:8]
    #define DVI_3D_YPOS_LFT Fld(8,0,AC_FULLB0)//[7:0]
#define VSRC_06 (IO_VIRT_DVI+(IO_DVI_BASE+0x430))
    #define DVI_3D_Y_RGT Fld(4,28,AC_MSKB3)//[31:28]
    #define DVI_3D_CB_RGT Fld(4,24,AC_MSKB3)//[27:24]
    #define DVI_3D_CR_RGT Fld(4,20,AC_MSKB2)//[23:20]
    #define DVI_3D_SIZE_RGT Fld(4,16,AC_MSKB2)//[19:16]
    #define DVI_3D_XPOS_RGT Fld(8,8,AC_FULLB1)//[15:8]
    #define DVI_3D_YPOS_RGT Fld(8,0,AC_FULLB0)//[7:0]
#define HDMI2_PATH_SEL (IO_VIRT_DVI+(IO_DVI_BASE+0x4b8))
    #define FLD_HDMI2_PATH_CCIR0 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_HDMI2_PATH_CCIR1 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HDMI2_PATH_W2D Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_HDMI2_PATH_AUD_CLK Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_HDMI2_PATH_AUD_CLK_MUX Fld(1,31,AC_MSKB3)//[31:31]
#define VFE_EE (IO_VIRT_DVI+(IO_DVI_BASE+0x7b8))
    #define DVI_3D_VPOL Fld(1,31,AC_MSKB3)//31
    #define DVI_3D_SEL Fld(1,30,AC_MSKB3)//30
    #define DVI_3D_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define DVI_3D_VACT Fld(12,16,AC_MSKW32)//[27:16]
    #define DVI_3D_VACT_SP1 Fld(8,8,AC_FULLB1)//[15:8]
    #define DVI_3D_VACT_SP2 Fld(8,0,AC_FULLB0)//[7:0]
#define VFE_EF (IO_VIRT_DVI+(IO_DVI_BASE+0x7bc))
    #define CCH_3D_POL Fld(1,31,AC_MSKB3)//31
    #define CCH_3D_SEL Fld(1,30,AC_MSKB3)//30
    #define CCH_3D_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define CCH_3D_VACT_SP1 Fld(8,8,AC_FULLB1)//[15:8]
    #define CCH_3D_VACT_SP2 Fld(8,0,AC_FULLB0)//[7:0]
#define DVI_00 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c0))
  #define DVI_00_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c0))
  #define DVI_00_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c1))
  #define DVI_00_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c2))
  #define DVI_00_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c3))
        #define DVI_VS_SEL Fld(1,31,AC_MSKB3)//31
        #define DVI_VPOS Fld(1, 30, AC_MSKB3)//30
    #define DVI_FLD_DET Fld(1, 29, AC_MSKB3) //29
    #define DVI_FLD_DET_INI Fld(1, 28, AC_MSKB3) //28
        #define DVI_SEL Fld(1, 27, AC_MSKB3)//27
    #define DVI_CEN_SEL Fld(1, 26, AC_MSKB3) //26
    #define DVI_HS_SEL Fld(1, 25, AC_MSKB3) //25
    #define DVI_AV_START12_0 Fld(13, 12, AC_MSKW21) //24:12
    #define DVI_AV_WIDTH Fld(12, 0, AC_MSKW10) //11:0
#define DVI_01 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c4))
  #define DVI_01_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c4))
  #define DVI_01_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c5))
  #define DVI_01_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c6))
  #define DVI_01_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c7))
    #define DVI_DE_MODE_H Fld(4, 28, AC_MSKB3) //31:28
    #define DVI_DE_MODE_V Fld(4, 24, AC_MSKB3) //27:24
    #define DVI_VDE_START11_0 Fld(12, 12, AC_MSKW21) //23:12
    #define DVI_VDE_WIDTH Fld(12, 0, AC_MSKW10) //11:0
#define DVI_02 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c8))
  #define DVI_02_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c8))
  #define DVI_02_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x7c9))
  #define DVI_02_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x7ca))
  #define DVI_02_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x7cb))
    #define DVI_YC Fld(1, 31, AC_MSKB3) //31
    #define DVI_FIX_VCNT Fld(1, 30, AC_MSKB3) //30
    #define DVI_VCNT_OFFSET_F0 Fld(3, 27, AC_MSKB3) //29:27
    #define DVI_VCNT_OFFSET_F1 Fld(3, 24, AC_MSKB3) //26:24
    #define SP0_DVI Fld(1, 23, AC_MSKB2) //23
    #define DVI_DE_SP Fld(1, 22, AC_MSKB2) //22
    #define DVI_DE_MODE Fld(1, 21, AC_MSKB2) //21
    #define DVI_DE0_OFF Fld(1, 20, AC_MSKB2) //20
    #define DVI_CRC_CLR Fld(1,19,AC_MSKB2)//19
    #define DVI_DET_EN Fld(1, 18, AC_MSKB2) //18
    #define DVI_CRC_START Fld(1, 17, AC_MSKB2) //17
    #define DVI_HS_POL Fld(1, 16, AC_MSKB2) //16
    #define DVI_VS_POL Fld(1, 15, AC_MSKB1) //15
    #define DVI_SP1_VS Fld(1, 14, AC_MSKB1) //14
    #define DVI_SP1_HS Fld(1, 13, AC_MSKB1) //13
    #define DVI_SP1_FLD Fld(1, 12, AC_MSKB1) //12
    #define DVI_BLANK_RESET Fld(1, 11, AC_MSKB1) //11
    #define DVI_BLANK_HOLD Fld(1, 10, AC_MSKB1) //10
    #define DVI_BLANK_START Fld(10, 0, AC_MSKW10) //9:0
#define DVI_03 (IO_VIRT_DVI+(IO_DVI_BASE+0x7cc))
  #define DVI_03_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x7cc))
  #define DVI_03_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x7cd))
  #define DVI_03_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x7ce))
  #define DVI_03_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x7cf))
    #define DVI_B7_INV Fld(1, 31, AC_MSKB3) //31
    #define DVI_B6_INV Fld(1, 30, AC_MSKB3) //30
    #define DVI_CNTL_SW Fld(1, 29, AC_MSKB3) //29
    #define DVI_DE_INV Fld(1, 28, AC_MSKB3) //28
    #define DVI_RB_SW Fld(1, 27, AC_MSKB3) //27
    #define DVI_MSB_SW Fld(1, 26, AC_MSKB3) //26
    #define DVI_VSRC Fld(1, 24, AC_MSKB3) //24
        //#define CCH_VDE_WIDTH Fld(12, 12, AC_MSKW21)//23:12
        #define CCH_AV_WIDTH Fld(12, 0, AC_MSKW10)//11:0
#define CCIR_00 (IO_VIRT_DVI+(IO_DVI_BASE+0x7d0))
  #define CCIR_00_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x7d0))
  #define CCIR_00_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x7d1))
  #define CCIR_00_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x7d2))
  #define CCIR_00_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x7d3))
    #define CCH_SRC24_SEL Fld(1, 31, AC_MSKB3) //31
    #define CCH_MUTE_SEL Fld(1, 30, AC_MSKB3) //30
    #define CCH_VS_SEL Fld(1, 29, AC_MSKB3) //29
    #define CCH_HS_SEL Fld(1, 28, AC_MSKB3) //28
    #define CCH_YC_SW Fld(1, 27, AC_MSKB3) //27
    #define CCH_YC Fld(1, 26, AC_MSKB3) //26
    #define CCH_FLD_DET Fld(1, 25, AC_MSKB3) //25
    #define CCH_FLD_DET_INI Fld(1, 24, AC_MSKB3) //24
    #define CCH_DE0_OFF Fld(1, 23, AC_MSKB2) //23
    #define CCIR656_VSRC Fld(1, 22, AC_MSKB2) //22
    #define CCH_SRC8_SEL Fld(1, 21, AC_MSKB2) //21
    #define CCH_SRC8_1X Fld(1, 20, AC_MSKB2) //20
    #define CCH_MSB_SW Fld(1, 19, AC_MSKB2) //19
    #define CCH_CBCR_SW Fld(1, 18, AC_MSKB2) //18
    #define CCH_CH_SW Fld(1, 17, AC_MSKB2) //17
    #define CCH_CLK_DIV Fld(1, 16, AC_MSKB2) //16
    #define CCH_RB_SW Fld(1, 15, AC_MSKB1) //15
    #define CCH_CKPT Fld(1, 14, AC_MSKB1) //14
    #define CCH_CFIL_EN Fld(1, 13, AC_MSKB1) //13
    #define CCH_VSRC Fld(1, 12, AC_MSKB1) //12
    #define CCH_SP1_FLD Fld(1, 10, AC_MSKB1) //10
    #define CCH_MODE Fld(2, 8, AC_MSKB1) //9:8
    #define CCH_LSB_EN Fld(1, 7, AC_MSKB0) //7
    #define CCH_V_DELAY Fld(1, 6, AC_MSKB0) //6
    #define CCH_HS_POL Fld(1, 5, AC_MSKB0) //5
    #define CCH_VS_POL Fld(1, 4, AC_MSKB0) //4
    #define CCH_HS_INV Fld(1, 3, AC_MSKB0) //3
    #define CCH_VS_INV Fld(1, 2, AC_MSKB0) //2
    #define CCH_FLD_INV Fld(1, 1, AC_MSKB0) //1
    #define CCH_CEN_SEL Fld(1, 0, AC_MSKB0) //0
#define CCIR_01 (IO_VIRT_DVI+(IO_DVI_BASE+0x7e8))
  #define CCIR_01_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x7e8))
  #define CCIR_01_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x7e9))
  #define CCIR_01_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x7ea))
  #define CCIR_01_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x7eb))
        #define CCH_SKIP_VBI_DVALID Fld(1, 31, AC_MSKB3)//31
        #define CCH_FLD_VPOS Fld(1, 30, AC_MSKB3) //30
        #define DVI_MUTE_SEL Fld(1, 29, AC_MSKB3)//29
        #define CCH_HMID_SEL Fld(1, 28, AC_MSKB3)//28
        #define CCH_DOLBY_EDR_METADATA_SEL Fld(1, 18, AC_MSKB2)//18
        #define CCH_DOLBY_PATH_SEL Fld(1, 17, AC_MSKB2)//17
        #define CCH_YC422_EXT_BIT Fld(1, 16, AC_MSKB2)//16
        #define DVI_OVF_DET Fld(1,15,AC_MSKB1)//15
        #define CCH_OVF_DET Fld(1,14,AC_MSKB1)//14
        #define DVI_HMID_SEL Fld(1,13,AC_MSKB1)//13
        #define CCH_AV_START Fld(13, 0, AC_MSKW10) //12:0

#define DVI_HDTV_01 (IO_VIRT_DVI+(IO_DVI_BASE+0x204))
  #define DVI_HDTV_01_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x204))
  #define DVI_HDTV_01_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x205))
  #define DVI_HDTV_01_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x206))
  #define DVI_HDTV_01_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x207))
        #define STA_CCH_FLD Fld(1, 31, AC_MSKB3)//31
        #define STA_CCH_DET_VPOS Fld(1, 30, AC_MSKB3)//30
        #define STA_DVI_FLD_VPOS Fld(1,29,AC_MSKB3)//29
        #define STA_DVI_DE_STABLE Fld(1, 28, AC_MSKB3)//28
                #define STA_DVI_HDELEN Fld(12,16,AC_MSKW32)//[27:16]
      #define STA_DVI_FLD Fld(1,15,AC_MSKB1)//15
      #define STA_DVI_FLD_COMP Fld(1,14,AC_MSKB1)//14
      #define STA_DVI_DE_ACT Fld(1,13,AC_MSKB1)//13
    #define STA_DVI_HTOTAL Fld(13, 0, AC_MSKW10) //12:0
#define DVI_HDTV_02 (IO_VIRT_DVI+(IO_DVI_BASE+0x208))
  #define DVI_HDTV_02_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x208))
  #define DVI_HDTV_02_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x209))
  #define DVI_HDTV_02_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x20a))
  #define DVI_HDTV_02_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x20b))
                #define STA_DVI_3D_ST Fld(4,28,AC_MSKB3)//[31:28]
                #define MAIN_DISP_R Fld(1,25,AC_MSKB3)//25
                #define STA_DVI_INT_DE Fld(1,24,AC_MSKB3)//24
             #define STA_DVI_VSLEN Fld(12,12,AC_MSKW21)//[23:12]
                #define STA_DVI_VTOTAL Fld(12, 0, AC_MSKW10) //11:0
#define DVI_HDTV_03 (IO_VIRT_DVI+(IO_DVI_BASE+0x20C))
    #define DVI_HDTV_03_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x20C))
    #define DVI_HDTV_03_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x20D))
    #define DVI_HDTV_03_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x20E))
    #define DVI_HDTV_03_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x20F))
        #define STA_CCH_HDELEN Fld(13, 19, AC_MSKW32)//31:19
        #define STA_CCH_3D_ST Fld(4,15,AC_MSKB2)//[18:15]
        #define STA_CCH_HTOTAL Fld(13,0,AC_MSKW10)//12:0
#define DVI_HDTV_04 (IO_VIRT_DVI+(IO_DVI_BASE+0x210))
    #define DVI_HDTV_04_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x210))
    #define DVI_HDTV_04_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x211))
    #define DVI_HDTV_04_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x212))
    #define DVI_HDTV_04_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x213))
            #define MAIN_DATA_SYNC_OVF Fld(1,31,AC_MSKB3)//[31:31]
                 #define PIP_DATA_SYNC_OVF Fld(1,30,AC_MSKB3)//[30:30]
            #define MAIN_MUTE Fld(1,29,AC_MSKB3)//[29:29]
            #define PIP2MDDI_MUTE Fld(1,28,AC_MSKB3)//[28:28]
            #define HDMI_VOUT_MUTE Fld(1,27,AC_MSKB3)//[27:27]
        #define STA_CCH_INT_DE Fld(1, 26, AC_MSKB2)//26
        #define STA_CCH_VSLEN Fld(13, 13, AC_MSKW21)//25:13
        #define STA_CCH_VTOTAL Fld(13, 0, AC_MSKW10)//12:0
#define DVI_HDTV_05 (IO_VIRT_DVI+(IO_DVI_BASE+0x214))
  #define DVI_HDTV_05_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x214))
  #define DVI_HDTV_05_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x215))
  #define DVI_HDTV_05_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x216))
  #define DVI_HDTV_05_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x217))
    #define DVI_STA_CRC_RDY Fld(1, 24, AC_MSKB3) //24
    #define DVI_STA_CRC_OUT_23_16 Fld(8, 16, AC_FULLB2) //23:16
    #define DVI_STA_CRC_OUT_15_8 Fld(8, 8, AC_FULLB1) //15:8
    #define DVI_STA_CRC_OUT_7_0 Fld(8, 0, AC_FULLB0) //7:0

#define CCIR_HDTV_06 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A0))
  #define CCIR_HDTV_06_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A0))
  #define CCIR_HDTV_06_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A1))
  #define CCIR_HDTV_06_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A2))
  #define CCIR_HDTV_06_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A3))
      #define CCH_VDE_WIDTH Fld(13, 16, AC_MSKW32)//28:16
    #define CCH_VS_START Fld(13,0,AC_MSKW10)//[12:0]

#define CCIR_HDTV_07 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A4))
  #define CCIR_HDTV_07_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A4))
  #define CCIR_HDTV_07_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A5))
  #define CCIR_HDTV_07_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A6))
  #define CCIR_HDTV_07_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A7))
    #define CCH_3D_VACT Fld(13,0,AC_MSKW32)//[12:0]

#define CCIR_HDTV_08 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A8))
    #define CCIR_HDTV_08_0 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A8))
    #define CCIR_HDTV_08_1 (IO_VIRT_DVI+(IO_DVI_BASE+0x7A9))
    #define CCIR_HDTV_08_2 (IO_VIRT_DVI+(IO_DVI_BASE+0x7Aa))
    #define CCIR_HDTV_08_3 (IO_VIRT_DVI+(IO_DVI_BASE+0x7Ab))
        #define CCH_VS_START_PIP Fld(13,0,AC_MSKW10)//[12:0]
        #define CCH_VDE_WIDTH_PIP Fld(13,16,AC_MSKW32)//[28:16]

#define CCIR_HDTV_09 (IO_VIRT_DVI+(IO_DVI_BASE+0x7AC))
        #define DVI_3D_VACT_PIP Fld(13,0,AC_MSKW10)//[12:0]
#define CCIR_VS_START_ECO (IO_VIRT_DVI+(IO_DVI_BASE+0x7F4))
        #define DVI_VS_START_MODE Fld(1, 31, AC_MSKB3)//31
        #define DVI_VS_START_MODE_PIP Fld(1, 30, AC_MSKB3) //30

#define CCIR_00_NEW (IO_VIRT_DVI+(IO_DVI_BASE+0x89C))
    #define CCH_SRC24_SEL_PIP Fld(1,31,AC_MSKB3)//[31:31]
    #define CCH_MUTE_SEL_PIP Fld(1,30,AC_MSKB3)//[30:30]
    #define CCH_VS_SEL_PIP Fld(1,29,AC_MSKB3)//[29:29]
    #define CCH_HS_SEL_PIP Fld(1,28,AC_MSKB3)//[28:28]
    #define CCH_YC_SW_PIP Fld(1,27,AC_MSKB3)//[27:27]
    #define CCH_YC_PIP Fld(1,26,AC_MSKB3)//[26:26]
    #define CCH_FLD_DET_PIP Fld(1,25,AC_MSKB3)//[25:25]
    #define CCH_FLD_DET_INI_PIP Fld(1,24,AC_MSKB3)//[24:24]
    #define CCH_DE0_OFF_PIP Fld(1,23,AC_MSKB2)//[23:23]
    #define CCIR656_VSRC_PIP Fld(1,22,AC_MSKB2)//[22:22]
    #define CCH_SRC8_SEL_PIP Fld(1,21,AC_MSKB2)//[21:21]
    #define CCH_SRC8_1X_PIP Fld(1,20,AC_MSKB2)//[20:20]
    #define CCH_MSB_SW_PIP Fld(1,19,AC_MSKB2)//[19:19]
    #define CCH_CBCR_SW_PIP Fld(1,18,AC_MSKB2)//[18:18]
    #define CCH_CH_SW_PIP Fld(1,17,AC_MSKB2)//[17:17]
    #define CCH_CLK_DIV_PIP Fld(1,16,AC_MSKB2)//[16:16]
    #define CCH_RB_SW_PIP Fld(1,15,AC_MSKB1)//[15:15]
    #define CCH_CKPT_PIP Fld(1,14,AC_MSKB1)//[14:14]
    #define CCH_CFIL_EN_PIP Fld(1,13,AC_MSKB1)//[13:13]
    #define CCH_VSRC_PIP Fld(1,12,AC_MSKB1)//[12:12]
    #define CCH_SP1_FLD_PIP Fld(1,10,AC_MSKB1)//[10:10]
    #define CCH_MODE_PIP Fld(2,8,AC_MSKB1)//[9:8]
    #define CCH_LSB_EN_PIP Fld(1,7,AC_MSKB0)//[7:7]
    #define CCH_V_DELAY_PIP Fld(1,6,AC_MSKB0)//[6:6]
    #define CCH_HS_POL_PIP Fld(1,5,AC_MSKB0)//[5:5]
    #define CCH_VS_POL_PIP Fld(1,4,AC_MSKB0)//[4:4]
    #define CCH_HS_INV_PIP Fld(1,3,AC_MSKB0)//[3:3]
    #define CCH_VS_INV_PIP Fld(1,2,AC_MSKB0)//[2:2]
    #define CCH_FLD_INV_PIP Fld(1,1,AC_MSKB0)//[1:1]
    #define CCH_CEN_SEL_PIP Fld(1,0,AC_MSKB0)//[0:0]
#define CCIR_01_NEW (IO_VIRT_DVI+(IO_DVI_BASE+0x8A0))
    #define CCH_SKIP_VBI_DVALID_PIP Fld(1,31,AC_MSKB3)//[31:31]
    #define CCH_FLD_VPOS_PIP Fld(1,30,AC_MSKB3)//[30:30]
    #define DVI_MUTE_SEL_PIP Fld(1,29,AC_MSKB3)//[29:29]
    #define CCH_HMID_SEL_PIP Fld(1,28,AC_MSKB3)//[28:28]
    //#define CCH_VS_START_PIP Fld(12,16,AC_MSKW32)//[27:16]
    #define DVI_OVF_DET_PIP Fld(1,15,AC_MSKB1)//[15:15]
    #define CCH_OVF_DET_PIP Fld(1,14,AC_MSKB1)//[14:14]
    #define DVI_HMID_SEL_PIP Fld(1,13,AC_MSKB1)//[13:13]
    #define CCH_AV_START_PIP Fld(13,0,AC_MSKW10)//[12:0]
#define CCIR_02_NEW (IO_VIRT_DVI+(IO_DVI_BASE+0x8A4))
    #define DVI_3D_VPOL_PIP Fld(1,31,AC_MSKB3)//[31:31]
    #define DVI_3D_SEL_PIP Fld(1,30,AC_MSKB3)//[30:30]
    #define DVI_3D_MODE_PIP Fld(2,28,AC_MSKB3)//[29:28]
    //#define DVI_3D_VACT_PIP Fld(12,16,AC_MSKW32)//[27:16]
    #define DVI_3D_VACT_SP1_PIP Fld(8,8,AC_FULLB1)//[15:8]
    #define DVI_3D_VACT_SP2_PIP Fld(8,0,AC_FULLB0)//[7:0]
#define CCIR_03_NEW (IO_VIRT_DVI+(IO_DVI_BASE+0x8A8))
    //#define CCH_VDE_WIDTH_PIP Fld(12,12,AC_MSKW21)//[23:12]
    #define CCH_AV_WIDTH_PIP Fld(12,0,AC_MSKW10)//[11:0]
#define CCIR_04_NEW (IO_VIRT_DVI+(IO_DVI_BASE+0x8AC))
    #define CCH_VCNT_OFFSET_F1_PIP Fld(2,30,AC_MSKB3)//[31:30]
    #define CCH_VCNT_OFFSET_F0_PIP Fld(2,28,AC_MSKB3)//[29:28]
    #define CCH_VDE_GATE_PIP Fld(1,18,AC_MSKB2)//[18:18]
    #define CCH_VDE_UP_EN_PIP Fld(1,17,AC_MSKB2)//[17:17]
    #define VBI_CCH_VBI_EN_PIP Fld(1,16,AC_MSKB2)//[16:16]
    #define CCH_3D_FPSEL_PIP Fld(1,15,AC_MSKB1)//[15:15]
    #define CCH_VHS_END_MODE_PIP Fld(1,14,AC_MSKB1)//[14:14]
    #define CCH_FLD_DET_EN_PIP Fld(1,13,AC_MSKB1)//[13:13]
    #define CCH_FIX_VCNT_PIP Fld(1,12,AC_MSKB1)//[12:12]
    #define CCH_CEN_4XSEL_PIP Fld(1,11,AC_MSKB1)//[11:11]
    #define CCH_3D_INTTGL_PIP Fld(1,10,AC_MSKB1)//[10:10]
    #define CCH_3D_DISP_POL_PIP Fld(1,9,AC_MSKB1)//[9:9]
    #define DVI_VDE_GATE_PIP Fld(1,8,AC_MSKB1)//[8:8]
    #define DVI_VDE_UP_EN_PIP Fld(1,7,AC_MSKB0)//[7:7]
    #define CCH_VHS_END_PIP Fld(1,6,AC_MSKB0)//[6:6]
    #define CCH_VSLEN_SEL_PIP Fld(1,5,AC_MSKB0)//[5:5]
    #define CCH_VIDEO_SEL Fld(1,3,AC_MSKB0)//[3:3]
#define CCIR_05_NEW (IO_VIRT_DVI+(IO_DVI_BASE + 0x2A0))
    #define STA_CCH_NEW_HTOTAL Fld(13,0,AC_MSKW10)//[12:0]
    #define STA_CCH_NEW_HDE Fld(13,19,AC_MSKW32)//[31:19]
#define CCIR_06_NEW (IO_VIRT_DVI+(IO_DVI_BASE + 0x2A4))
    #define STA_CCH_NEW_VTOTAL Fld(13,0,AC_MSKW10)//[12:0]
    #define STA_CCH_NEW_VSLEN Fld(13,13,AC_MSKDW)//[25:13]
#define CCIR_DITHER_EN (IO_VIRT_DVI+(IO_DVI_BASE + 0x7F4))
    #define CCIR0_DITHER_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define CCIR1_DITHER_EN Fld(1,28,AC_MSKB3)//[28:28]
#define CCIR0_DITHER_00 (IO_VIRT_DVI+(IO_DVI_BASE + 0xC94))
    #define CCIR0_DITHER_LFSR_EN Fld(1,6,AC_MSKB0)//[6:6]
#define CCIR0_DITHER_02 (IO_VIRT_DVI+(IO_DVI_BASE + 0xC9C))
    #define CCIR0_DRMOD_B Fld(2,16,AC_MSKB2)//[17:16]
    #define CCIR0_DRMOD_G Fld(2,14,AC_MSKB1)//[15:14]
    #define CCIR0_DRMOD_R Fld(2,12,AC_MSKB1)//[13:12]
#define CCIR1_DITHER_00 (IO_VIRT_DVI+(IO_DVI_BASE + 0xCA4))
    #define CCIR1_DITHER_LFSR_EN Fld(1,6,AC_MSKB0)//[6:6]
#define CCIR1_DITHER_02 (IO_VIRT_DVI+(IO_DVI_BASE + 0xCAC))
    #define CCIR1_DRMOD_B Fld(2,16,AC_MSKB2)//[17:16]
    #define CCIR1_DRMOD_G Fld(2,14,AC_MSKB1)//[15:14]
    #define CCIR1_DRMOD_R Fld(2,12,AC_MSKB1)//[13:12]
#endif

