/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _HW_HDMI21_AUD_H_
#define _HW_HDMI21_AUD_H_

#define DEF_HDMI21_AUD_BASE 0x608000
#define IO_HDMI21_AUD_BASE (IO_VIRT + DEF_HDMI21_AUD_BASE)

//Page HDMI21_AUDIO_1
#define H21MAC_RX_N_SVAL1 (IO_HDMI21_AUD_BASE + 0x800)
    #define H21MAC_RX_N_SVAL1_REG_N_VAL_SW_7_0_ Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_RX_N_SVAL1_REG_FM_VAL_SW Fld(2,22,AC_MSKB2)//[23:22]
    #define H21MAC_RX_N_SVAL1_REG_FS_VAL_SW Fld(6,16,AC_MSKB2)//[21:16]
    #define H21MAC_RX_N_SVAL1_REG_VCNT_MAX Fld(2,14,AC_MSKB1)//[15:14]
    #define H21MAC_RX_N_SVAL1_REG_MCLK4DAC Fld(2,12,AC_MSKB1)//[13:12]
    #define H21MAC_RX_N_SVAL1_REG_MCLK4HBRA Fld(2,10,AC_MSKB1)//[11:10]
    #define H21MAC_RX_N_SVAL1_REG_MCLK4DSD Fld(2,8,AC_MSKB1)//[9:8]
    #define H21MAC_RX_N_SVAL1_REG_CTS_DROPPED_AUTO_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define H21MAC_RX_N_SVAL1_REG_POST_HW_SW_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define H21MAC_RX_N_SVAL1_REG_UPLL_HW_SW_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define H21MAC_RX_N_SVAL1_REG_CTS_HW_SW_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define H21MAC_RX_N_SVAL1_REG_N_HW_SW_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define H21MAC_RX_N_SVAL1_REG_CTS_REUSED_AUTO_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_RX_N_SVAL1_REG_FS_HW_SW_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_RX_N_SVAL1_REG_ACR_INIT Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_RX_N_HVAL2 (IO_HDMI21_AUD_BASE + 0x804)
    #define H21MAC_RX_N_HVAL2_N_VAL_HW_15_8_ Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_RX_N_HVAL2_N_VAL_HW_7_0_ Fld(8,16,AC_FULLB2)//[23:16]
    #define H21MAC_RX_N_HVAL2_REG_N_VAL_SW_19_16_ Fld(4,8,AC_MSKB1)//[11:8]
    #define H21MAC_RX_N_HVAL2_REG_N_VAL_SW_15_8_ Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_RX_CTS_SVAL3 (IO_HDMI21_AUD_BASE + 0x808)
    #define H21MAC_RX_CTS_SVAL3_REG_CTS_VAL_SW_19_16_ Fld(4,24,AC_MSKB3)//[27:24]
    #define H21MAC_RX_CTS_SVAL3_REG_CTS_VAL_SW_15_8_ Fld(8,16,AC_FULLB2)//[23:16]
    #define H21MAC_RX_CTS_SVAL3_REG_CTS_VAL_SW_7_0_ Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_RX_CTS_SVAL3_N_VAL_HW_19_16_ Fld(4,0,AC_MSKB0)//[3:0]
#define H21MAC_RX_UPLL_SVAL (IO_HDMI21_AUD_BASE + 0x80C)
    #define H21MAC_RX_UPLL_SVAL_REG_UPLL_VAL_SW Fld(7,24,AC_MSKB3)//[30:24]
    #define H21MAC_RX_UPLL_SVAL_CTS_VAL_HW_19_16_ Fld(4,16,AC_MSKB2)//[19:16]
    #define H21MAC_RX_UPLL_SVAL_CTS_VAL_HW_15_8_ Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_RX_UPLL_SVAL_CTS_VAL_HW_7_0_ Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_RX_LK_WIN_SVAL (IO_HDMI21_AUD_BASE + 0x810)
    #define H21MAC_RX_LK_WIN_SVAL_REG_LK_WIN_SW_4_1_ Fld(4,25,AC_MSKB3)//[28:25]
    #define H21MAC_RX_LK_WIN_SVAL_REG_LK_WIN_SW_0_ Fld(1,24,AC_MSKB3)//[24:24]
    #define H21MAC_RX_LK_WIN_SVAL_POST_VAL_HW Fld(6,16,AC_MSKB2)//[21:16]
    #define H21MAC_RX_LK_WIN_SVAL_REG_POST_VAL_SW Fld(6,8,AC_MSKB1)//[13:8]
    #define H21MAC_RX_LK_WIN_SVAL_UPLL_VAL_HW Fld(7,0,AC_MSKB0)//[6:0]
#define H21MAC_RX_TCLK_FS (IO_HDMI21_AUD_BASE + 0x814)
    #define H21MAC_RX_TCLK_FS_RHDMI_AUD_SAMPLE_F_EXTN Fld(2,30,AC_MSKB3)//[31:30]
    #define H21MAC_RX_TCLK_FS_REG_FS_FILTER_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define H21MAC_RX_TCLK_FS_RHDMI_AUD_SAMPLE_F Fld(4,24,AC_MSKB3)//[27:24]
    #define H21MAC_RX_TCLK_FS_REG_LK_THRS_SVAL_19_16_ Fld(4,16,AC_MSKB2)//[19:16]
    #define H21MAC_RX_TCLK_FS_REG_LK_THRS_SVAL_15_8_ Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_RX_TCLK_FS_REG_LK_THRS_SVAL_7_0_ Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_AUD4AAC0_HLP (IO_HDMI21_AUD_BASE + 0x818)
    #define H21MAC_AUD4AAC0_HLP_REG_DAC_LAYOUT Fld(4,28,AC_MSKB3)//[31:28]
    #define H21MAC_AUD4AAC0_HLP_REG_DSD_LAYOUT Fld(4,24,AC_MSKB3)//[27:24]
    #define H21MAC_AUD4AAC0_HLP_AUD_CH_STAT7 Fld(7,17,AC_MSKB2)//[23:17]
    #define H21MAC_AUD4AAC0_HLP_INFO_IN_PCM_SIGNAL Fld(1,16,AC_MSKB2)//[16:16]
    #define H21MAC_AUD4AAC0_HLP_AUD_SAMPLE_F_COEFF Fld(4,12,AC_MSKB1)//[15:12]
    #define H21MAC_AUD4AAC0_HLP_BIT43 Fld(1,11,AC_MSKB1)//[11:11]
    #define H21MAC_AUD4AAC0_HLP_CGMS_A_VALIDITY Fld(1,10,AC_MSKB1)//[10:10]
    #define H21MAC_AUD4AAC0_HLP_CGMS_A Fld(2,8,AC_MSKB1)//[9:8]
    #define H21MAC_AUD4AAC0_HLP_REG_CTS_THRESH Fld(4,3,AC_MSKB0)//[6:3]
    #define H21MAC_AUD4AAC0_HLP_REG_MCLK_LOOPBACK Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_AUD4AAC0_HLP_REG_LOG_WIN_ENA Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_AUD4AAC0_HLP_REG_POST_DIV2_ENA Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_RX_AUDRX_CTRL (IO_HDMI21_AUD_BASE + 0x81C)
    #define H21MAC_RX_AUDRX_CTRL_REG_I2S_LENGTH_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define H21MAC_RX_AUDRX_CTRL_REG_INV_COR_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define H21MAC_RX_AUDRX_CTRL_REG_HW_MUTE_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define H21MAC_RX_AUDRX_CTRL_REG_PASS_SPDIF_ERR Fld(1,28,AC_MSKB3)//[28:28]
    #define H21MAC_RX_AUDRX_CTRL_REG_PASS_AUD_ERR Fld(1,27,AC_MSKB3)//[27:27]
    #define H21MAC_RX_AUDRX_CTRL_REG_I2S_MODE Fld(1,26,AC_MSKB3)//[26:26]
    #define H21MAC_RX_AUDRX_CTRL_REG_SPDIF_MODE Fld(1,25,AC_MSKB3)//[25:25]
    #define H21MAC_RX_AUDRX_CTRL_REG_SPDIF_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define H21MAC_RX_AUDRX_CTRL_REG_SD3_MAP Fld(2,22,AC_MSKB2)//[23:22]
    #define H21MAC_RX_AUDRX_CTRL_REG_SD2_MAP Fld(2,20,AC_MSKB2)//[21:20]
    #define H21MAC_RX_AUDRX_CTRL_REG_SD1_MAP Fld(2,18,AC_MSKB2)//[19:18]
    #define H21MAC_RX_AUDRX_CTRL_REG_SD0_MAP Fld(2,16,AC_MSKB2)//[17:16]
    #define H21MAC_RX_AUDRX_CTRL_REG_SD3_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define H21MAC_RX_AUDRX_CTRL_REG_SD2_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define H21MAC_RX_AUDRX_CTRL_REG_SD1_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define H21MAC_RX_AUDRX_CTRL_REG_SD0_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define H21MAC_RX_AUDRX_CTRL_REG_MCLK_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define H21MAC_RX_AUDRX_CTRL_REG_MUTE_FLAT Fld(1,10,AC_MSKB1)//[10:10]
    #define H21MAC_RX_AUDRX_CTRL_REG_VUCP Fld(1,9,AC_MSKB1)//[9:9]
    #define H21MAC_RX_AUDRX_CTRL_REG_PCM Fld(1,8,AC_MSKB1)//[8:8]
    #define H21MAC_RX_AUDRX_CTRL_REG_INVALID_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define H21MAC_RX_AUDRX_CTRL_REG_CLK_EDGE Fld(1,6,AC_MSKB0)//[6:6]
    #define H21MAC_RX_AUDRX_CTRL_REG_SIZE Fld(1,5,AC_MSKB0)//[5:5]
    #define H21MAC_RX_AUDRX_CTRL_REG_MSB Fld(1,4,AC_MSKB0)//[4:4]
    #define H21MAC_RX_AUDRX_CTRL_REG_WS Fld(1,3,AC_MSKB0)//[3:3]
    #define H21MAC_RX_AUDRX_CTRL_REG_JUSTIFY Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_RX_AUDRX_CTRL_REG_DATA_DIR Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_RX_AUDRX_CTRL_REG_1ST_BIT Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_RX_MUTE_DIV (IO_HDMI21_AUD_BASE + 0x820)
    #define H21MAC_RX_MUTE_DIV_REG_DIV_INCR Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_RX_MUTE_DIV_AUD_CH_NUM1 Fld(4,20,AC_MSKB2)//[23:20]
    #define H21MAC_RX_MUTE_DIV_AUD_SOURCE1 Fld(4,16,AC_MSKB2)//[19:16]
    #define H21MAC_RX_MUTE_DIV_BIT15_8 Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_RX_MUTE_DIV_BIT6_7 Fld(2,6,AC_MSKB0)//[7:6]
    #define H21MAC_RX_MUTE_DIV_BIT3_4_5 Fld(3,3,AC_MSKB0)//[5:3]
    #define H21MAC_RX_MUTE_DIV_BIT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_RX_MUTE_DIV_BIT1 Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_RX_MUTE_DIV_BIT0 Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_RX_CHST5 (IO_HDMI21_AUD_BASE + 0x824)
    #define H21MAC_RX_CHST5_AUD_ORG_FS Fld(4,28,AC_MSKB3)//[31:28]
    #define H21MAC_RX_CHST5_AUD_LENGTH Fld(3,25,AC_MSKB3)//[27:25]
    #define H21MAC_RX_CHST5_AUD_LENGTH_MAX Fld(1,24,AC_MSKB3)//[24:24]
    #define H21MAC_RX_CHST5_AUD_SAMPLE_F_EXTN Fld(2,22,AC_MSKB2)//[23:22]
    #define H21MAC_RX_CHST5_AUD_ACCURACY Fld(2,20,AC_MSKB2)//[21:20]
    #define H21MAC_RX_CHST5_AUD_SAMPLE_F Fld(4,16,AC_MSKB2)//[19:16]
    #define H21MAC_RX_CHST5_REG_CS_BIT15_8 Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_RX_CHST5_REG_SWAP Fld(4,4,AC_MSKB0)//[7:4]
    #define H21MAC_RX_CHST5_REG_CS_BIT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_RX_CHST5_REG_OW_EN Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_RX_TDM_CTRL1 (IO_HDMI21_AUD_BASE + 0x828)
    #define H21MAC_RX_TDM_CTRL1_REG_TDM_FS_MSB Fld(2,27,AC_MSKB3)//[28:27]
    #define H21MAC_RX_TDM_CTRL1_REG_TDM_CH_NUM Fld(2,25,AC_MSKB3)//[26:25]
    #define H21MAC_RX_TDM_CTRL1_REG_TDM_MODE Fld(1,24,AC_MSKB3)//[24:24]
    #define H21MAC_RX_TDM_CTRL1_REG_AUDIO_TOGGLE_MODE Fld(1,23,AC_MSKB2)//[23:23]
    #define H21MAC_RX_TDM_CTRL1_REG_SPDIF4TDM_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define H21MAC_RX_TDM_CTRL1_REG_SPDIF4I2S_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define H21MAC_RX_TDM_CTRL1_AAC_AUDIO_MUTE Fld(1,12,AC_MSKB1)//[12:12]
    #define H21MAC_RX_TDM_CTRL1_REG_MUTE_OUT_POL Fld(1,10,AC_MSKB1)//[10:10]
    #define H21MAC_RX_TDM_CTRL1_REG_AUDIO_MUTE Fld(1,9,AC_MSKB1)//[9:9]
    #define H21MAC_RX_TDM_CTRL1_REG_I2S_LENGTH Fld(4,4,AC_MSKB0)//[7:4]
    #define H21MAC_RX_TDM_CTRL1_REG_CH3_MUTE Fld(1,3,AC_MSKB0)//[3:3]
    #define H21MAC_RX_TDM_CTRL1_REG_CH2_MUTE Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_RX_TDM_CTRL1_REG_CH1_MUTE Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_RX_TDM_CTRL1_REG_CH0_MUTE Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_VID_XPCLK_EN (IO_HDMI21_AUD_BASE + 0x82C)
    #define H21MAC_VID_XPCLK_EN_REG_VRES_XCLK_DIFF Fld(4,28,AC_MSKB3)//[31:28]
    #define H21MAC_VID_XPCLK_EN_REG_VID_XCLKPCLK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define H21MAC_VID_XPCLK_EN_REG_VID_PCLK_CNT_BASE_7_0_ Fld(8,16,AC_FULLB2)//[23:16]
    #define H21MAC_VID_XPCLK_EN_REG_VID_PCLK_CNT_MULT_3_0_ Fld(4,8,AC_MSKB1)//[11:8]
    #define H21MAC_VID_XPCLK_EN_REG_TDM_FS_LEN Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_VID_XP_THRSH (IO_HDMI21_AUD_BASE + 0x830)
    #define H21MAC_VID_XP_THRSH_REG_XP_THRSH Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_VID_XP_THRSH_REG_XP_BASE_23_16_ Fld(8,16,AC_FULLB2)//[23:16]
    #define H21MAC_VID_XP_THRSH_REG_XP_BASE_15_8_ Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_VID_XP_THRSH_REG_XP_BASE_7_0_ Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_RX_APLL_POLE (IO_HDMI21_AUD_BASE + 0x834)
    #define H21MAC_RX_APLL_POLE_REG_MODOVRVAL Fld(2,30,AC_MSKB3)//[31:30]
    #define H21MAC_RX_APLL_POLE_REG_ZERO Fld(3,27,AC_MSKB3)//[29:27]
    #define H21MAC_RX_APLL_POLE_REG_POLE Fld(3,24,AC_MSKB3)//[26:24]
    #define H21MAC_RX_APLL_POLE_AAC_XCLK_IN_PCLK_23_16_ Fld(8,16,AC_FULLB2)//[23:16]
    #define H21MAC_RX_APLL_POLE_AAC_XCLK_IN_PCLK_15_8_ Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_RX_APLL_POLE_AAC_XCLK_IN_PCLK_7_0_ Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_RX_APLL_OVRCTRL (IO_HDMI21_AUD_BASE + 0x838)
    #define H21MAC_RX_APLL_OVRCTRL_REG_PREDIVSELOVR Fld(1,31,AC_MSKB3)//[31:31]
    #define H21MAC_RX_APLL_OVRCTRL_REG_MODOVR Fld(1,30,AC_MSKB3)//[30:30]
    #define H21MAC_RX_APLL_OVRCTRL_REG_SDINOVR Fld(1,29,AC_MSKB3)//[29:29]
    #define H21MAC_RX_APLL_OVRCTRL_REG_FS32OVR Fld(1,28,AC_MSKB3)//[28:28]
    #define H21MAC_RX_APLL_OVRCTRL_REG_USOVR Fld(1,27,AC_MSKB3)//[27:27]
    #define H21MAC_RX_APLL_OVRCTRL_REG_PREDIVSELOVRVAL Fld(1,26,AC_MSKB3)//[26:26]
    #define H21MAC_RX_APLL_OVRCTRL_REG_FS32OVRVAL Fld(1,25,AC_MSKB3)//[25:25]
    #define H21MAC_RX_APLL_OVRCTRL_REG_NCLKSEL Fld(1,24,AC_MSKB3)//[24:24]
    #define H21MAC_RX_APLL_OVRCTRL_REG_LFCTRL Fld(2,22,AC_MSKB2)//[23:22]
    #define H21MAC_RX_APLL_OVRCTRL_REG_CPCTRL Fld(3,19,AC_MSKB2)//[21:19]
    #define H21MAC_RX_APLL_OVRCTRL_REG_USOVRVAL Fld(3,16,AC_MSKB2)//[18:16]
    #define H21MAC_RX_APLL_OVRCTRL_REG_SDINOVRVAL Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_RX_APLL_OVRCTRL_REG_WRAP Fld(1,7,AC_MSKB0)//[7:7]
    #define H21MAC_RX_APLL_OVRCTRL_REG_SDREF Fld(3,4,AC_MSKB0)//[6:4]
    #define H21MAC_RX_APLL_OVRCTRL_REG_CLIP Fld(4,0,AC_MSKB0)//[3:0]
#define H21MAC_RX_NACR_STS2 (IO_HDMI21_AUD_BASE + 0x83C)
    #define H21MAC_RX_NACR_STS2_NAPLL_FBDIV_11_8_ Fld(4,24,AC_MSKB3)//[27:24]
    #define H21MAC_RX_NACR_STS2_NAPLL_FBDIV_7_0_ Fld(8,16,AC_FULLB2)//[23:16]
    #define H21MAC_RX_NACR_STS2_REG_NAPLL_CTL Fld(4,8,AC_MSKB1)//[11:8]
    #define H21MAC_RX_NACR_STS2_ACR_DPLL_LOCK Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_RX_NACR_STS6 (IO_HDMI21_AUD_BASE + 0x840)
    #define H21MAC_RX_NACR_STS6_FREQDIFF_11_4_ Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_RX_NACR_STS6_FREQDIFF_3_0_ Fld(4,20,AC_MSKB2)//[23:20]
    #define H21MAC_RX_NACR_STS6_NAPLL_FRAC_23_20_ Fld(4,16,AC_MSKB2)//[19:16]
    #define H21MAC_RX_NACR_STS6_NAPLL_FRAC_19_12_ Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_RX_NACR_STS6_NAPLL_FRAC_11_4_ Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_RX_APLL_REFDIV (IO_HDMI21_AUD_BASE + 0x844)
    #define H21MAC_RX_APLL_REFDIV_REG_APLL_REFDIV Fld(6,24,AC_MSKB3)//[29:24]
    #define H21MAC_RX_APLL_REFDIV_FREQDIFF_29_28_ Fld(2,16,AC_MSKB2)//[17:16]
    #define H21MAC_RX_APLL_REFDIV_FREQDIFF_27_20_ Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_RX_APLL_REFDIV_FREQDIFF_19_12_ Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_RX_AVG_WINDOW (IO_HDMI21_AUD_BASE + 0x848)
    #define H21MAC_RX_AVG_WINDOW_REG_AVG_WINDOW Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_RX_AVG_WINDOW_NAPLL_LOCK Fld(1,16,AC_MSKB2)//[16:16]
    #define H21MAC_RX_AVG_WINDOW_REG_APLL_BYPASS Fld(1,14,AC_MSKB1)//[14:14]
    #define H21MAC_RX_AVG_WINDOW_REG_APLL_FOUTVCOPD Fld(1,13,AC_MSKB1)//[13:13]
    #define H21MAC_RX_AVG_WINDOW_REG_APLL_FOUT4PHASEPD Fld(1,12,AC_MSKB1)//[12:12]
    #define H21MAC_RX_AVG_WINDOW_REG_APLL_FOUTPOSTDIVPD Fld(1,11,AC_MSKB1)//[11:11]
    #define H21MAC_RX_AVG_WINDOW_REG_APLL_DSMPD Fld(1,10,AC_MSKB1)//[10:10]
    #define H21MAC_RX_AVG_WINDOW_REG_APLL_DACPD Fld(1,9,AC_MSKB1)//[9:9]
    #define H21MAC_RX_AVG_WINDOW_REG_APLL_PD Fld(1,8,AC_MSKB1)//[8:8]
    #define H21MAC_RX_AVG_WINDOW_REG_APLL_POSTDIV2 Fld(3,4,AC_MSKB0)//[6:4]
    #define H21MAC_RX_AVG_WINDOW_REG_APLL_POSTDIV1 Fld(3,0,AC_MSKB0)//[2:0]
#define H21MAC_AEC3_CTRL (IO_HDMI21_AUD_BASE + 0x84C)
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL3_7_ Fld(1,31,AC_MSKB3)//[31:31]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL3_6_ Fld(1,30,AC_MSKB3)//[30:30]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL3_5_ Fld(1,29,AC_MSKB3)//[29:29]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL3_4_ Fld(1,28,AC_MSKB3)//[28:28]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL3_3_ Fld(1,27,AC_MSKB3)//[27:27]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL3_2_ Fld(1,26,AC_MSKB3)//[26:26]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL3_1_ Fld(1,25,AC_MSKB3)//[25:25]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL3_0_ Fld(1,24,AC_MSKB3)//[24:24]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL4_7_ Fld(1,23,AC_MSKB2)//[23:23]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL4_6_ Fld(1,22,AC_MSKB2)//[22:22]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL4_5_ Fld(1,21,AC_MSKB2)//[21:21]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL4_4_ Fld(1,20,AC_MSKB2)//[20:20]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL4_3_ Fld(1,19,AC_MSKB2)//[19:19]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL4_2_ Fld(1,18,AC_MSKB2)//[18:18]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL4_1_ Fld(1,17,AC_MSKB2)//[17:17]
    #define H21MAC_AEC3_CTRL_REG_AAC_CTRL4_0_ Fld(1,16,AC_MSKB2)//[16:16]
    #define H21MAC_AEC3_CTRL_REG_DACR_REF_CLK_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define H21MAC_AEC3_CTRL_REG_DACR_MCLK_OUT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_RX_AEC_EN1 (IO_HDMI21_AUD_BASE + 0x850)
    #define H21MAC_RX_AEC_EN1_REG_EXP_EN_7_0_ Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_RX_AEC_EN1_REG_CTRL_ACR_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define H21MAC_RX_AEC_EN1_REG_AAC_EXP_SEL Fld(1,22,AC_MSKB2)//[22:22]
    #define H21MAC_RX_AEC_EN1_REG_AAC_OUT_OFF_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define H21MAC_RX_AEC_EN1_AUD_DIV_MIN Fld(1,20,AC_MSKB2)//[20:20]
    #define H21MAC_RX_AEC_EN1_AAC_MUTE_STAT Fld(1,19,AC_MSKB2)//[19:19]
    #define H21MAC_RX_AEC_EN1_REG_AAC_ALL Fld(1,17,AC_MSKB2)//[17:17]
    #define H21MAC_RX_AEC_EN1_REG_AAC_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL_7_ Fld(1,15,AC_MSKB1)//[15:15]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL_6_ Fld(1,14,AC_MSKB1)//[14:14]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL_5_ Fld(1,13,AC_MSKB1)//[13:13]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL_4_ Fld(1,12,AC_MSKB1)//[12:12]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL_3_ Fld(1,11,AC_MSKB1)//[11:11]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL_2_ Fld(1,10,AC_MSKB1)//[10:10]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL_1_ Fld(1,9,AC_MSKB1)//[9:9]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL_0_ Fld(1,8,AC_MSKB1)//[8:8]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL2_7_ Fld(1,7,AC_MSKB0)//[7:7]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL2_6_ Fld(1,6,AC_MSKB0)//[6:6]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL2_5_ Fld(1,5,AC_MSKB0)//[5:5]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL2_4_ Fld(1,4,AC_MSKB0)//[4:4]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL2_3_ Fld(1,3,AC_MSKB0)//[3:3]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL2_2_ Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL2_1_ Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_RX_AEC_EN1_REG_AAC_CTRL2_0_ Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_AAC_CSC_ERR (IO_HDMI21_AUD_BASE + 0x854)
    #define H21MAC_AAC_CSC_ERR_REG_AAC_CSC_ERR Fld(5,24,AC_MSKB3)//[28:24]
    #define H21MAC_AAC_CSC_ERR_REG_PCLK_MAX Fld(7,17,AC_MSKB2)//[23:17]
    #define H21MAC_AAC_CSC_ERR_REG_PSTOP_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define H21MAC_AAC_CSC_ERR_REG_EXP_EN_23_16_ Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_AAC_CSC_ERR_REG_EXP_EN_15_8_ Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_AAC_EXP_CAPT_M (IO_HDMI21_AUD_BASE + 0x858)
    #define H21MAC_AAC_EXP_CAPT_M_REG_AAC_EXP_CAPT_15_8_ Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_AAC_EXP_CAPT_M_REG_AAC_EXP_CAPT_7_0_ Fld(8,16,AC_FULLB2)//[23:16]
    #define H21MAC_AAC_EXP_CAPT_M_REG_AAC_ASC_ERR Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_AAC_EXP_CAPT_M_REG_AAC_VSC_ERR Fld(4,0,AC_MSKB0)//[3:0]
#define H21MAC_ACRGCTRL0 (IO_HDMI21_AUD_BASE + 0x85C)
    #define H21MAC_ACRGCTRL0_REG_ACR_GEN_CTRL0 Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_ACRGCTRL0_REG_AAC_EXP_CAPT_23_16_ Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_RX_DEBUG_CLK_XPCNT (IO_HDMI21_AUD_BASE + 0x860)
    #define H21MAC_RX_DEBUG_CLK_XPCNT_AAC_XCLK_IN_DEBUG_CLK_23_0_ Fld(24,0,AC_MSKDW)//[23:0]
#define H21MAC_REG_AUD_00 (IO_HDMI21_AUD_BASE + 0x900)
    #define H21MAC_REG_AUD_00_PLL_CORE_ID Fld(1,31,AC_MSKB3)//[31:31]
    #define H21MAC_REG_AUD_00_C_CTSMUL4_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define H21MAC_REG_AUD_00_C_MUL4_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define H21MAC_REG_AUD_00_C_CTSDIV4_CARRY_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define H21MAC_REG_AUD_00_C_CTSDIV4_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define H21MAC_REG_AUD_00_C_NDIV4_CARRY_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define H21MAC_REG_AUD_00_C_NDIV4_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define H21MAC_REG_AUD_00_HAPLL_MOD Fld(25,0,AC_MSKDW)//[24:0]
#define H21MAC_REG_AUD_01 (IO_HDMI21_AUD_BASE + 0x904)
    #define H21MAC_REG_AUD_01_REG_FS_EXTRAC_OLD_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define H21MAC_REG_AUD_01_HW_HAS_HBRA_FEATURE Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_REG_AUD_01_HW_HAS_DSD_FEATURE Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_REG_AUD_03 (IO_HDMI21_AUD_BASE + 0x90C)
    #define H21MAC_REG_AUD_03_REG_VSI_HEADER Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_REG_AUD_03_REG_AIF_HEADER Fld(8,0,AC_FULLB0)//[7:0]
#define H21MAC_REG_AUD_04 (IO_HDMI21_AUD_BASE + 0x910)
    #define H21MAC_REG_AUD_04_REG_DACR_HS_RFRST Fld(1,23,AC_MSKB2)//[23:23]
    #define H21MAC_REG_AUD_04_REG_FB_HACR_RST Fld(1,22,AC_MSKB2)//[22:22]
    #define H21MAC_REG_AUD_04_REG_CLKRST_TMDS_RST Fld(1,21,AC_MSKB2)//[21:21]
    #define H21MAC_REG_AUD_04_REG_TMDS_HACR_RST Fld(1,20,AC_MSKB2)//[20:20]
    #define H21MAC_REG_AUD_04_REG_AUD_FIFO_HS_RST Fld(1,19,AC_MSKB2)//[19:19]
    #define H21MAC_REG_AUD_04_REG_AUD_HS_RST Fld(1,17,AC_MSKB2)//[17:17]
#define H21MAC_REG_AUD_05 (IO_HDMI21_AUD_BASE + 0x914)
    #define H21MAC_REG_AUD_05_REG_EXTERN_FS_VALUE Fld(2,16,AC_MSKB2)//[17:16]
#define H21MAC_REG_AUD_08 (IO_HDMI21_AUD_BASE + 0x920)
    #define H21MAC_REG_AUD_08_REG_LK_WIN_SW Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_REG_AUD_08_REG_POST_DIV2_ENA Fld(1,23,AC_MSKB2)//[23:23]
    #define H21MAC_REG_AUD_08_REG_FM_IN_VAL_SW Fld(2,21,AC_MSKB2)//[22:21]
    #define H21MAC_REG_AUD_08_REG_POST_VAL_SW Fld(6,14,AC_MSKW21)//[19:14]
    #define H21MAC_REG_AUD_08_REG_UPLL_VAL_SW Fld(7,7,AC_MSKW10)//[13:7]
    #define H21MAC_REG_AUD_08_XTAL_24M_SEL_ACR Fld(1,6,AC_MSKB0)//[6:6]
    #define H21MAC_REG_AUD_08_REG_FM_VAL_SW Fld(2,4,AC_MSKB0)//[5:4]
    #define H21MAC_REG_AUD_08_REG_FS_VAL_SW Fld(4,0,AC_MSKB0)//[3:0]
#define H21MAC_REG_AUD_09 (IO_HDMI21_AUD_BASE + 0x924)
    #define H21MAC_REG_AUD_09_POST_HW_SW_SEL Fld(1,24,AC_MSKB3)//[24:24]
    #define H21MAC_REG_AUD_09_UPLL_HW_SW_SEL Fld(1,23,AC_MSKB2)//[23:23]
    #define H21MAC_REG_AUD_09_CTS_HW_SW_SEL Fld(1,22,AC_MSKB2)//[22:22]
    #define H21MAC_REG_AUD_09_N_HW_SW_SEL Fld(1,21,AC_MSKB2)//[21:21]
    #define H21MAC_REG_AUD_09_FS_HW_SW_SEL Fld(1,20,AC_MSKB2)//[20:20]
    #define H21MAC_REG_AUD_09_REG_N_VAL_SW Fld(20,0,AC_MSKDW)//[19:0]
#define H21MAC_REG_AUD_10 (IO_HDMI21_AUD_BASE + 0x928)
    #define H21MAC_REG_AUD_10_REG_CTS_VALUE_SW Fld(20,0,AC_MSKDW)//[19:0]
#define H21MAC_REG_AUD_11 (IO_HDMI21_AUD_BASE + 0x92C)
    #define H21MAC_REG_AUD_11_REG_USE_OLD_PCW_SEL Fld(1,31,AC_MSKB3)//[31:31]
#define H21MAC_REG_AUD_14 (IO_HDMI21_AUD_BASE + 0x938)
    #define H21MAC_REG_AUD_14_REG_WRAP Fld(1,31,AC_MSKB3)//[31:31]
    #define H21MAC_REG_AUD_14_REG_CLIP Fld(4,27,AC_MSKB3)//[30:27]
    #define H21MAC_REG_AUD_14_REG_ZERO Fld(3,24,AC_MSKB3)//[26:24]
    #define H21MAC_REG_AUD_14_REG_POLE Fld(3,21,AC_MSKB2)//[23:21]
    #define H21MAC_REG_AUD_14_REG_LOG_WIN_ENA Fld(1,20,AC_MSKB2)//[20:20]
    #define H21MAC_REG_AUD_14_REG_LK_THRS_SVAL Fld(20,0,AC_MSKDW)//[19:0]
#define H21MAC_REG_AUD_15 (IO_HDMI21_AUD_BASE + 0x93C)
    #define H21MAC_REG_AUD_15_PAD_EXT_NCLK_SEL Fld(1,31,AC_MSKB3)//[31:31]
    #define H21MAC_REG_AUD_15_REG_NCLKSEL Fld(1,30,AC_MSKB3)//[30:30]
    #define H21MAC_REG_AUD_15_REG_CTS_DROPPED_AUTO_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define H21MAC_REG_AUD_15_REG_CTS_REUSED_AUTO_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define H21MAC_REG_AUD_15_REG_CTS_THRESH Fld(4,24,AC_MSKB3)//[27:24]
    #define H21MAC_REG_AUD_15_REG_ACR_INIT_WP Fld(1,23,AC_MSKB2)//[23:23]
    #define H21MAC_REG_AUD_15_REG_MODOVR Fld(1,22,AC_MSKB2)//[22:22]
    #define H21MAC_REG_AUD_15_REG_SDINOVR Fld(1,21,AC_MSKB2)//[21:21]
    #define H21MAC_REG_AUD_15_REG_FS32OVR Fld(1,20,AC_MSKB2)//[20:20]
    #define H21MAC_REG_AUD_15_REG_USOVR Fld(1,19,AC_MSKB2)//[19:19]
    #define H21MAC_REG_AUD_15_REG_MODOVRVAL Fld(3,16,AC_MSKB2)//[18:16]
    #define H21MAC_REG_AUD_15_REG_SDINOVRVAL_39_32 Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_REG_AUD_15_REG_FS32OVRVAL Fld(1,6,AC_MSKB0)//[6:6]
    #define H21MAC_REG_AUD_15_REG_USOVRVAL Fld(3,3,AC_MSKB0)//[5:3]
    #define H21MAC_REG_AUD_15_REG_SDREF Fld(3,0,AC_MSKB0)//[2:0]

//Page HDMI21_AUDIO_2
#define H21MAC_REG_AUD_16 (IO_HDMI21_AUD_BASE + 0x940)
    #define H21MAC_REG_AUD_16_REG_SDINOVRVAL_39_32 Fld(8,8,AC_FULLB1)//[15:8]
#define H21MAC_REG_AUD_17 (IO_HDMI21_AUD_BASE + 0x944)
    #define H21MAC_REG_AUD_17_NCLK_NCT_TH Fld(8,24,AC_FULLB3)//[31:24]
    #define H21MAC_REG_AUD_17_CTS_ROUGH_STEP Fld(8,16,AC_FULLB2)//[23:16]
    #define H21MAC_REG_AUD_17_CTS_FINE_STEP Fld(8,8,AC_FULLB1)//[15:8]
    #define H21MAC_REG_AUD_17_PTR_DIFF_HIGH_TH Fld(6,2,AC_MSKB0)//[7:2]
    #define H21MAC_REG_AUD_17_REG_PREDIVSELOVRVAL Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_REG_AUD_17_REG_PREDIVSELOVR Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_REG_AUD_18 (IO_HDMI21_AUD_BASE + 0x948)
    #define H21MAC_REG_AUD_18_PRE_STABLE_CNT_TH Fld(8,20,AC_MSKW32)//[27:20]
    #define H21MAC_REG_AUD_18_STABLE_CNT_TH Fld(16,4,AC_MSKDW)//[19:4]
    #define H21MAC_REG_AUD_18_CTS_HW_ADP_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define H21MAC_REG_AUD_18_CTS_LOCK_ALG Fld(3,0,AC_MSKB0)//[2:0]
#define H21MAC_REG_AUD_19 (IO_HDMI21_AUD_BASE + 0x94C)
    #define H21MAC_REG_AUD_19_CTS_REAL_STABLE_CNT_TH Fld(16,0,AC_FULLW10)//[15:0]
#define H21MAC_REG_AUD_20 (IO_HDMI21_AUD_BASE + 0x950)
    #define H21MAC_REG_AUD_20_PCW_DATA_SEL Fld(1,31,AC_MSKB3)//[31:31]
    #define H21MAC_REG_AUD_20_REG_HADDS2_PCW_SW Fld(31,0,AC_MSKDW)//[30:0]
#define H21MAC_REG_AUD_21 (IO_HDMI21_AUD_BASE + 0x954)
    #define H21MAC_REG_AUD_21_REG_HDMI21_AMUTE_INTR_CLR Fld(1,22,AC_MSKB2)//[22:22]
    #define H21MAC_REG_AUD_21_REG_HDMI21_AMUTE_CLR Fld(1,21,AC_MSKB2)//[21:21]
    #define H21MAC_REG_AUD_21_REG_HDMI21_AMUTE_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define H21MAC_REG_AUD_21_REG_AUTO_SET_MUTE_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define H21MAC_REG_AUD_21_REG_AUTO_CLR_MUTE_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define H21MAC_REG_AUD_21_REG_HDMI_MODE_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define H21MAC_REG_AUD_21_REG_PLL_STS_DACR_SEL Fld(1,16,AC_MSKB2)//[16:16]
    #define H21MAC_REG_AUD_21_REG_PD_ALL Fld(1,15,AC_MSKB1)//[15:15]
    #define H21MAC_REG_AUD_21_REG_DACR_MCLK_SEL Fld(1,13,AC_MSKB1)//[13:13]
    #define H21MAC_REG_AUD_21_PCW_DATA_SEL_FOR_40NM Fld(1,12,AC_MSKB1)//[12:12]
    #define H21MAC_REG_AUD_21_PCW_DATA_DIV Fld(2,10,AC_MSKB1)//[11:10]
    #define H21MAC_REG_AUD_21_PCW_DATA_X2_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define H21MAC_REG_AUD_21_FB_DIV_DATA_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define H21MAC_REG_AUD_21_PCW_CHG_SW Fld(1,7,AC_MSKB0)//[7:7]
    #define H21MAC_REG_AUD_21_FB_DIV_SW Fld(7,0,AC_MSKB0)//[6:0]
#define H21MAC_REG_AUD_22 (IO_HDMI21_AUD_BASE + 0x958)
    #define H21MAC_REG_AUD_22_REG_INTR_GEN_PLL_LOCK_CLR Fld(1,5,AC_MSKB0)//[5:5]
    #define H21MAC_REG_AUD_22_REG_INTR_GEN_AUDSAMPLE_CLR Fld(1,4,AC_MSKB0)//[4:4]
    #define H21MAC_REG_AUD_22_REG_INTR_GEN_OVERRUN_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define H21MAC_REG_AUD_22_REG_INTR_GEN_UNDERRUN_CLR Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_REG_AUD_22_REG_INTR_GEN_CP_SET_MUTE_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_REG_AUD_22_REG_INTR_PLL_UNLOCK_CLR Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_REG_AUD_23 (IO_HDMI21_AUD_BASE + 0x95C)
    #define H21MAC_REG_AUD_23_INTR_PLL_LOCK_MASK Fld(1,5,AC_MSKB0)//[5:5]
    #define H21MAC_REG_AUD_23_INTR_AUD_SAMPLE_CHG_MASK Fld(1,4,AC_MSKB0)//[4:4]
    #define H21MAC_REG_AUD_23_INTR_FIFO_OVERRUN_MASK Fld(1,3,AC_MSKB0)//[3:3]
    #define H21MAC_REG_AUD_23_INTR_FIFO_UNDERRUN_MASK Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_REG_AUD_23_INTR_CP_SET_MUTE_MASK Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_REG_AUD_23_INTR_PLL_UNLOCK_MASK Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_REG_AUD_24 (IO_HDMI21_AUD_BASE + 0x960)
    #define H21MAC_REG_AUD_24_AIF_PKT_CLR Fld(1,4,AC_MSKB0)//[4:4]
    #define H21MAC_REG_AUD_24_REG_USE_AIF4VSI Fld(1,3,AC_MSKB0)//[3:3]
#define H21MAC_REG_AUD_28 (IO_HDMI21_AUD_BASE + 0x970)
    #define H21MAC_REG_AUD_28_REG_HDMI21_AUD_INTR_P3_MASK Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_REG_AUD_28_REG_HDMI21_AUD_INTR_P2_MASK Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_REG_AUD_28_REG_HDMI21_AUDIO_OUT_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_RGS_AUD_00 (IO_HDMI21_AUD_BASE + 0x990)
    #define H21MAC_RGS_AUD_00_HDMI2_PCW_CHG Fld(1,31,AC_MSKB3)//[31:31]
    #define H21MAC_RGS_AUD_00_HDMI2_PCW Fld(31,0,AC_MSKDW)//[30:0]
#define H21MAC_RGS_AUD_01 (IO_HDMI21_AUD_BASE + 0x994)
    #define H21MAC_RGS_AUD_01_PLL_PRE_DIV_HW Fld(1,31,AC_MSKB3)//[31:31]
    #define H21MAC_RGS_AUD_01_US_HW Fld(3,28,AC_MSKB3)//[30:28]
    #define H21MAC_RGS_AUD_01_FS_HW Fld(1,27,AC_MSKB3)//[27:27]
    #define H21MAC_RGS_AUD_01_POST_DIV_HW Fld(6,21,AC_MSKW32)//[26:21]
    #define H21MAC_RGS_AUD_01_N_VALUE_HW Fld(20,0,AC_MSKDW)//[19:0]
#define H21MAC_RGS_AUD_02 (IO_HDMI21_AUD_BASE + 0x998)
    #define H21MAC_RGS_AUD_02_APLL_ACR_PLL_LOCK Fld(1,23,AC_MSKB2)//[23:23]
    #define H21MAC_RGS_AUD_02_APLL_ACR_PLL_UNLOCK Fld(1,22,AC_MSKB2)//[22:22]
    #define H21MAC_RGS_AUD_02_CTS_VALUDE_HW Fld(20,0,AC_MSKDW)//[19:0]
#define H21MAC_RGS_AUD_03 (IO_HDMI21_AUD_BASE + 0x99C)
    #define H21MAC_RGS_AUD_03_AUD_HBR_ON Fld(1,7,AC_MSKB0)//[7:7]
    #define H21MAC_RGS_AUD_03_AUD_DSD_ON Fld(1,6,AC_MSKB0)//[6:6]
    #define H21MAC_RGS_AUD_03_HDMI_LAOUT Fld(2,4,AC_MSKB0)//[5:4]
    #define H21MAC_RGS_AUD_03_CEA_CP_SET_MUTE Fld(1,3,AC_MSKB0)//[3:3]
    #define H21MAC_RGS_AUD_03_CEA_CP_CLR_MUTE Fld(1,2,AC_MSKB0)//[2:2]
#define H21MAC_RGS_AUD_04 (IO_HDMI21_AUD_BASE + 0x9A0)
    #define H21MAC_RGS_AUD_04_INTR_APLL_LOCK Fld(1,5,AC_MSKB0)//[5:5]
    #define H21MAC_RGS_AUD_04_INTR_APLL_UNLOCK Fld(1,4,AC_MSKB0)//[4:4]
    #define H21MAC_RGS_AUD_04_INTR_CP_SET_MUTE Fld(1,3,AC_MSKB0)//[3:3]
    #define H21MAC_RGS_AUD_04_INTR_FIFO_UNDERRUN Fld(1,2,AC_MSKB0)//[2:2]
    #define H21MAC_RGS_AUD_04_INTR_FIFO_OVERRUN Fld(1,1,AC_MSKB0)//[1:1]
    #define H21MAC_RGS_AUD_04_INTR_AUD_SAMPLE_CHG Fld(1,0,AC_MSKB0)//[0:0]
#define H21MAC_RGS_AUD_0X (IO_HDMI21_AUD_BASE + 0xFFC)
    #define H21MAC_RGS_AUD_0X_AACR_RESET Fld(1,0,AC_MSKB0)//[0:0]

#endif //#ifndef _HW_HDMI2P1_AUD_H_
