/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _HW_HDMI21_ANA_H_
#define _HW_HDMI21_ANA_H_
#include "x_hal_5381.h"

//---------------------------HDMI21 Rx PHY ---------------------------//

#define IO_HDMI21_RX_PHY_BASE 0x02034000

// PHY-A
#define HD21PHY_EQ_FIFO_CFG_0000 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0000)
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_BG_EN Fld(2,30,AC_MSKB3)//[31:30]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_TERM_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_TESTE Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_BIAS_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_BIAS_SEL Fld(2,25,AC_MSKB3)//[26:25]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_CDRRST Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_CDRSTOP Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_CH0_CDRLPI Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_BBPD_DES_PDB Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_CH1_CDRLPI Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_OFST_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0000_REG_RG_HDMI_CH2_CDRLPI Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0004 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0004)
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_CHCK_CDRLPI Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_CKDIV2_RSTB Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_CKGEN_HR_RSTB Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_CKGEN_OS_RSTB Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_CKGEN_RSTB Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_CLK_SYNC_INV Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_DAC_CTRL Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_DAC_LSB Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_DAC_MON Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_DAC_PWDB Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_DAC_PWD_CTRL Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_DEEPCLRCLKPDB Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_DEEPCLRCLKRSTN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_DEEP_DIV_DIV3_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0004_REG_RG_HDMI_DEEP_DIV_DIV12_A Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0008 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0008)
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_DEEP_DIV_DIV12_B Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_DEEP_DIV_DIV12_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_DES_HR_SEL Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_DFEBIAS_FBDIS Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_DFE_SYNC_CK_INV Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_DFE_PWDB Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_EQ0_BAND Fld(3,21,AC_MSKB2)//[23:21]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_EQ1_BAND Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_EQ2_BAND Fld(3,13,AC_MSKB1)//[15:13]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_FEOC_BAND Fld(3,10,AC_MSKB1)//[12:10]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_HDMI21_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_FEOC_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_FE_AMP_MON_CTRL Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_HF_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_PI_DATA_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0008_REG_RG_HDMI_KIGAIN Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_000C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x000C)
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_KPGAIN Fld(3,29,AC_MSKB3)//[31:29]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_PI_EDGE_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_PI_EDBG_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_PI_XDBG_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_POSTDIV_PDB Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_POST_DIV_RSTN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_POST_DIV_SEL Fld(3,21,AC_MSKB2)//[23:21]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_R2R_CK_SEL Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_RXFE_AMP_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_RXFE_SD_DCTEST_EN Fld(2,17,AC_MSKB2)//[18:17]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_RXFE_SD_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_RXFE_DATA_SD_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_RXFE_SD_LPF_CTRL Fld(2,13,AC_MSKB1)//[14:13]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_SIGNCHG Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_000C_REG_RG_HDMI_MDPLL_REF_ADA_DA_SEL Fld(1,6,AC_MSKB0)//[6:6]
#define HD21PHY_EQ_FIFO_CFG_0010 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0010)
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_RXFE_SD_OSCAL_EN Fld(2,30,AC_MSKB3)//[31:30]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_SAOC_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_RXFE_SD_VCM_SEL Fld(2,27,AC_MSKB3)//[28:27]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_RXFE_SD_VDM_SEL Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_RXFE_VCM_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_RXMODE_HF Fld(2,21,AC_MSKB2)//[22:21]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_RXMODE_HR Fld(2,19,AC_MSKB2)//[20:19]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_RXMODE_OS Fld(2,17,AC_MSKB2)//[18:17]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_TAP_PWDB Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_VCM_SEL Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_VCO_HBAND Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_ATEST_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_PLL_FIFO_CK_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_POST_DIV_2_DIV3_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_POST_DIV_2_DIV3_RSTN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_MON18_SEL Fld(3,5,AC_MSKB0)//[7:5]
    #define HD21PHY_EQ_FIFO_CFG_0010_REG_RG_HDMI_POST_DIV_2_SEL Fld(4,1,AC_MSKB0)//[4:1]
#define HD21PHY_EQ_FIFO_CFG_0014 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0014)
    #define HD21PHY_EQ_FIFO_CFG_0014_REG_RG_HDMI_CH2_RXFE_OS_MON_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0014_REG_RG_HDMI_CH1_RXFE_OS_MON_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0014_REG_RG_HDMI_CH0_RXFE_OS_MON_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0014_REG_RG_HDMI_CHCK_RXFE_OS_MON_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0014_REG_RG_HDMI_FM_SEL Fld(12,16,AC_MSKW32)//[27:16]
    #define HD21PHY_EQ_FIFO_CFG_0014_REG_RG_HDMI_RXFE_CKD_VDM_SEL Fld(3,13,AC_MSKB1)//[15:13]
    #define HD21PHY_EQ_FIFO_CFG_0014_REG_RG_HDMI_FM_SEL2 Fld(12,0,AC_MSKW10)//[11:0]
#define HD21PHY_EQ_FIFO_CFG_0018 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0018)
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CH0_ATT_RESERVE Fld(2,30,AC_MSKB3)//[31:30]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CH0_RXFE_OS_MON_SEL Fld(2,28,AC_MSKB3)//[29:28]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CH0_VGA_RESERVE Fld(2,26,AC_MSKB3)//[27:26]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CH1_ATT_RESERVE Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CH1_RXFE_OS_MON_SEL Fld(2,22,AC_MSKB2)//[23:22]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CH1_VGA_RESERVE Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CH2_ATT_RESERVE Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CH2_RXFE_OS_MON_SEL Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CH2_VGA_RESERVE Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CHCK_ATT_RESERVE Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CHCK_RXFE_OS_MON_SEL Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_CHCK_VGA_RESERVE Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_RXFE_CKD_DCTEST_EN Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_RXFE_CKD_LPF_CTRL Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_RXFE_CKD_OSCAL_EN Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_0018_REG_RG_HDMI_RXFE_CKD_VCM_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_001C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x001C)
    #define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_REV Fld(32,0,AC_FULLDW)//[31:0]
		#define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_REV_22_20 Fld(3,20,AC_MSKB2)//[22:20]
	    #define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_3LANE_MODE Fld(1,16,AC_MSKB2)//[16:16]
	    #define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_REV_BIT14 Fld(1,14,AC_MSKB1)//[14:14]
		#define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_REV_BIT11 Fld(1,11,AC_MSKB1)//[11:11]
	    #define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_REV_BIT9 Fld(1,9,AC_MSKB1)//[9:9]
	    #define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_LOOPBACK_7_6 Fld(2,6,AC_MSKB0)//[7:6]
	    #define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_LOOPBACK_5_4 Fld(2,4,AC_MSKB0)//[5:4]
	    #define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_REV_BIT4 Fld(1,4,AC_MSKB0)//[4:4]
	    #define HD21PHY_EQ_FIFO_CFG_001C_REG_RG_HDMI_L2_IMPSEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_0020 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0020)
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_BC Fld(2,30,AC_MSKB3)//[31:30]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_BPA Fld(3,27,AC_MSKB3)//[29:27]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_BPB Fld(2,25,AC_MSKB3)//[26:25]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_CLKSQ_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_BR Fld(3,21,AC_MSKB2)//[23:21]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_CLKSQ_HYS_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_CLKSQ_LPF_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_CLKSQ_VOD_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_DEBUG_SEL Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_FBKDIV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_FBKSEL Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_IBAND_LVROD_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_FC_DLY Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_KBAND_PREDIV Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_LOAD_HDMI_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0020_REG_RG_HDMI_MDPLL_LVROD_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0024 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0024)
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_ICP Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_MODE Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_TCL_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_PREDIV Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_POSDIV0 Fld(3,21,AC_MSKB2)//[23:21]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_POSDIV1 Fld(3,18,AC_MSKB2)//[20:18]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_RST_DLY Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_TST_CK_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_TST_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_TST_OD_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_TST_OP_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_TST_SEL Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21PHY_EQ_FIFO_CFG_0024_REG_RG_HDMI_MDPLL_IBAND Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_0028 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0028)
    #define HD21PHY_EQ_FIFO_CFG_0028_REG_RG_HDMI_MDPLL_RESERVE0 Fld(16,16,AC_MSKDW)//[31:16]
#define HD21PHY_EQ_FIFO_CFG_002C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x002C)
    #define HD21PHY_EQ_FIFO_CFG_002C_REG_RG_HDMI_PLL_BG_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_002C_REG_RG_HDMI_PLL_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_002C_REG_RG_HDMI_PLL_IC Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_002C_REG_RG_HDMI_PLL_IR Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_002C_REG_RG_HDMI_PLL_BC Fld(5,11,AC_MSKB1)//[15:11]
    #define HD21PHY_EQ_FIFO_CFG_002C_REG_RG_HDMI_PLL_BR Fld(4,4,AC_MSKB0)//[7:4]
#define HD21PHY_EQ_FIFO_CFG_0030 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0030)
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_BP Fld(5,27,AC_MSKB3)//[31:27]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_BP2 Fld(2,25,AC_MSKB3)//[26:25]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_VREF_RANGE_SEL Fld(3,22,AC_MSKW32)//[24:22]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_POSDIV Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_PREDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_KBAND_PREDIV Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_IBAND Fld(10,6,AC_MSKW10)//[15:6]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_VCO_HBAND Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_FBKSEL Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_LVROD_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_MONREF_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0030_REG_RG_HDMI_PLL_LVR_REFSEL Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_0034 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0034)
    #define HD21PHY_EQ_FIFO_CFG_0034_REG_RG_HDMI_PLL_FBKDIV Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0034_REG_RG_HDMI_PLL_MONCK_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0034_REG_RG_HDMI_PLL_MONVC_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0034_REG_RG_HDMI_PLL_KVSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0034_REG_RG_HDMI_PLL_RST_DLY Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_0034_REG_RG_HDMI_PLL_FC_DLY Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0034_REG_RG_HDMI_PLL_LOAD_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0034_REG_RG_HDMI_PLL_DEBUG_SEL Fld(1,14,AC_MSKB1)//[14:14]
#define HD21PHY_EQ_FIFO_CFG_0038 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0038)
    #define HD21PHY_EQ_FIFO_CFG_0038_REG_RG_HDMI_PLL_RESERVE Fld(16,16,AC_MSKDW)//[31:16]
#define HD21PHY_EQ_FIFO_CFG_003C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x003C)
    #define HD21PHY_EQ_FIFO_CFG_003C_REG_RGS_HDMI_CH0_CDRLPO Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_003C_REG_RGS_HDMI_CH1_CDRLPO Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_003C_REG_RGS_HDMI_CH2_CDRLPO Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_003C_REG_RGS_HDMI_CHCK_CDRLPO Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0040 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0040)
    #define HD21PHY_EQ_FIFO_CFG_0040_REG_RGS_HDMI_IMDPLL_DIG_MON Fld(8,24,AC_FULLB3)//[31:24]
#define HD21PHY_EQ_FIFO_CFG_0044 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0044)
    #define HD21PHY_EQ_FIFO_CFG_0044_REG_RGS_HDMI_IPLL_DIG_MON Fld(8,24,AC_FULLB3)//[31:24]

// PHY-D
#define HD21PHY_EQ_FIFO_CFG_0048 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0048)
    #define HD21PHY_EQ_FIFO_CFG_0048_REG_DIV4_SEL_LCK Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_0048_REG_DIV4_SEL_L2 Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_0048_REG_DIV4_SEL_L1 Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21PHY_EQ_FIFO_CFG_0048_REG_DIV4_SEL_L0 Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_0048_REG_LANE_TESTBUS_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_0048_REG_GP_TESTBUS_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_004C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x004C)
    #define HD21PHY_EQ_FIFO_CFG_004C_REG_SW_RST Fld(16,0,AC_FULLW10)//[15:0]
    	#define HD21PHY_EQ_FIFO_CFG_004C_REG_SW_RST_BIT15 Fld(1,15,AC_MSKB1)//[15:15]
    	#define HD21PHY_EQ_FIFO_CFG_004C_REG_SW_RST_BIT8 Fld(1,8,AC_MSKB1)//[8:8]
    	#define HD21PHY_EQ_FIFO_CFG_004C_REG_SW_RST_BIT4_CONVERT_FIFO Fld(1,4,AC_MSKB0)//[4:4]
    	#define HD21PHY_EQ_FIFO_CFG_004C_REG_SW_RST_BIT2 Fld(1,2,AC_MSKB0)//[2:2]
    	#define HD21PHY_EQ_FIFO_CFG_004C_REG_SW_RST_BIT1_PREDFF_FIFO Fld(1,1,AC_MSKB0)//[1:1]
    	#define HD21PHY_EQ_FIFO_CFG_004C_REG_SW_RST_BIT0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0050 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0050)
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_SYNC_AUTO Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_LINK_INV Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_TMDS_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_DFF_INV_L3 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_DFF_INV_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_DFF_INV_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_DFF_INV_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_PIPE_INV_L3 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_PIPE_INV_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_PIPE_INV_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0050_REG_HDMI_PIPE_INV_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0054 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0054)
    #define HD21PHY_EQ_FIFO_CFG_0054_REG_TEST_BUS_IN_H Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_0054_REG_TEST_BUS_IN_L Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_0058 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0058)
    #define HD21PHY_EQ_FIFO_CFG_0058_REG_TEST_BUS_IN_H Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_005C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x005C)
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_DAC_MON_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_DAC_LSB_OV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_DAC_CTRL_OV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CLK_SYNC_INV_OV_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CKGEN_RSTB_OV_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CKGEN_OS_RSTB_OV_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CKGEN_HR_RSTB_OV_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CKDIV2_RSTB_OV_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CHCK_CDRLPI_OV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CH2_CDRLPI_OV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_OFST_EN_OV_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CH1_CDRLPI_OV_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_BBPD_DES_PDB_OV_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CH0_CDRLPI_OV_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CDRSTOP_OV_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_CDRRST_OV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_BIAS_SEL_OV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_BIAS_EN_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_TESTE_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_TERM_EN_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_RG_HDMI_BG_EN_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_REV_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_TEST_SEC_WRITE_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_TEST_SEC_SWITCH_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_TEST_SEC_EN_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_RXFE_CKD_OS0_SEL_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_RXFE_CKD_OS1_SEL_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_RXFE_SD_OS0_SEL_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_RXFE_SD_OS1_SEL_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_MDPLL_REFCK_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_CHCK_PIMODE_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_005C_REG_DA_HDMI_CH2_PIMODE_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0060 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0060)
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_RXFE_SD_DCTEST_EN_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_RXFE_AMP_EN_OV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_R2R_CK_SEL_OV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_POST_DIV_SEL_OV_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_POST_DIV_RSTN_OV_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_POSTDIV_PDB_OV_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_PI_XDBG_EN_OV_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_PI_EDBG_EN_OV_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_PI_EDGE_EN_OV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_KPGAIN_OV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_KIGAIN_OV_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_PI_DATA_EN_OV_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_HF_SEL_OV_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_FE_AMP_MON_CTRL_OV_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_FEOC_EN_OV_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_HDMI21_MODE_OV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_FEOC_BAND_OV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_EQ2_BAND_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_EQ1_BAND_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_EQ0_BAND_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DFE_PWDB_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DFE_SYNC_CK_INV_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DFEBIAS_FBDIS_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DES_HR_SEL_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DEEP_DIV_DIV12_EN_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DEEP_DIV_DIV12_B_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DEEP_DIV_DIV12_A_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DEEP_DIV_DIV3_SEL_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DEEPCLRCLKRSTN_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DEEPCLRCLKPDB_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DAC_PWD_CTRL_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0060_REG_RG_HDMI_DAC_PWDB_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0064 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0064)
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_CH0_LEQ_RESERVE_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_CH0_RXFE_OS_MON_SEL_OV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_CH0_ATT_RESERVE_OV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_FM_SEL2_OV_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXFE_CKD_VDM_SEL_OV_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_FM_SEL_OV_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_CHCK_RXFE_OS_MON_EN_OV_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_CH2_RXFE_OS_MON_EN_OV_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_CH1_RXFE_OS_MON_EN_OV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_CH0_RXFE_OS_MON_EN_OV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_POST_DIV_2_SEL_OV_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_MON18_SEL_OV_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_POST_DIV_2_DIV3_RSTN_OV_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_POST_DIV_2_DIV3_EN_OV_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_PLL_FIFO_CK_EN_OV_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_ATEST_EN_OV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_VCO_HBAND_OV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_VCM_SEL_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_TAP_PWDB_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXMODE_OS_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXMODE_HR_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXMODE_HF_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXFE_VCM_EN_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXFE_SD_VDM_SEL_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXFE_SD_VCM_SEL_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_SAOC_EN_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXFE_SD_OSCAL_EN_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_MDPLL_REF_ADA_DA_SEL_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_SIGNCHG_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXFE_SD_LPF_CTRL_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXFE_DATA_SD_EN_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0064_REG_RG_HDMI_RXFE_SD_EN_OV_EN Fld(1,0,AC_MSKB0)//[0:0]

//Page HDMI2P1_EQ_FIFO1_2_P1_2
#define HD21PHY_EQ_FIFO_CFG_0068 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0068)
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_FC_DLY_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_IBAND_LVROD_EN_OV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_FBKSEL_OV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_FBKDIV_OV_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_EN_OV_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_DEBUG_SEL_OV_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_CLKSQ_VOD_EN_OV_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_CLKSQ_LPF_EN_OV_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_CLKSQ_HYS_EN_OV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_BR_OV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_CLKSQ_EN_OV_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_BPB_OV_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_BPA_OV_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_MDPLL_BC_OV_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_REV_OV_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_RXFE_CKD_VCM_SEL_OV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_RXFE_CKD_OSCAL_EN_OV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_RXFE_CKD_LPF_CTRL_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_RXFE_CKD_DCTEST_EN_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CHCK_VGA_RESERVE_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CHCK_LEQ_RESERVE_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CHCK_RXFE_OS_MON_SEL_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CHCK_ATT_RESERVE_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CH2_VGA_RESERVE_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CH2_LEQ_RESERVE_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CH2_RXFE_OS_MON_SEL_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CH2_ATT_RESERVE_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CH1_VGA_RESERVE_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CH1_LEQ_RESERVE_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CH1_RXFE_OS_MON_SEL_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CH1_ATT_RESERVE_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0068_REG_RG_HDMI_CH0_VGA_RESERVE_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_006C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x006C)
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_FBKSEL_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_VCO_HBAND_OV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_IBAND_OV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_KBAND_PREDIV_OV_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_PREDIV_OV_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_POSDIV_OV_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_VREF_RANGE_SEL_OV_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_BP2_OV_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_BP_OV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_BR_OV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_BC_OV_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_IR_OV_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_IC_OV_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_EN_OV_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_PLL_BG_EN_OV_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_RESERVE0_OV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_IBAND_OV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_TST_SEL_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_TST_OP_EN_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_TST_OD_EN_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_TST_EN_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_TST_CK_EN_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_RST_DLY_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_POSDIV1_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_POSDIV0_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_PREDIV_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_TCL_EN_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_MODE_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_ICP_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_LVROD_EN_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_LOAD_HDMI_EN_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_006C_REG_RG_HDMI_MDPLL_KBAND_PREDIV_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0070 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0070)
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_LEV1_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_LEV0_OV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_LEQ_G_OV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_EDBGMON_OV_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_E1_OV_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_E0_OV_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_DAC_XDBG_OV_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_D1L_OV_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_D1H_OV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_D0L_OV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_D0H_OV_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_ATT_G_OV_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH2_CALEN_DIV5_OV_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH2_CALEN_OV_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH1_CALEN_DIV5_OV_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH1_CALEN_OV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_CALEN_DIV5_OV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CH0_CALEN_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CHCK_CALEN_DIV5_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_DA_HDMI_CHCK_CALEN_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_RESERVE_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_DEBUG_SEL_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_LOAD_EN_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_FC_DLY_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_RST_DLY_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_KVSEL_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_MONVC_EN_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_MONCK_EN_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_FBKDIV_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_LVR_REFSEL_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_MONREF_EN_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0070_REG_RG_HDMI_PLL_LVROD_EN_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0074 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0074)
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH2_D1H_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH2_D0L_OV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH2_D0H_OV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH2_ATT_G_OV_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_XDBGD_OV_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_XDBG_OV_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_VGA_G_OV_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_TAP5_OV_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_TAP4_OV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_TAP3_OV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_TAP2_OV_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_OFST_OV_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_LEV1_OV_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_LEV0_OV_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_LEQ_G_OV_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_EDBGMON_OV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_E1_OV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_E0_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_DAC_XDBG_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_D1L_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_D1H_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_D0L_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_D0H_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH1_ATT_G_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH0_XDBGD_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH0_XDBG_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH0_VGA_G_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH0_TAP5_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH0_TAP4_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH0_TAP3_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH0_TAP2_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0074_REG_DA_HDMI_CH0_OFST_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0078 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0078)
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_TAP4_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_TAP3_OV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_TAP2_OV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_OFST_OV_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_LEV1_OV_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_LEV0_OV_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_LEQ_G_OV_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_EDBGMON_OV_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_E1_OV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_E0_OV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_DAC_XDBG_OV_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_D1L_OV_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_D1H_OV_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_D0L_OV_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_D0H_OV_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CHCK_ATT_G_OV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_XDBGD_OV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_XDBG_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_VGA_G_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_TAP5_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_TAP4_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_TAP3_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_TAP2_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_OFST_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_LEV1_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_LEV0_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_LEQ_G_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_EDBGMON_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_E1_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_E0_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_DAC_XDBG_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0078_REG_DA_HDMI_CH2_D1L_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_007C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x007C)
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CH1_PIMODE_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CH0_PIMODE_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_IMPSEL_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CH2_DFE_DAC_SYNC_CK_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CH1_DFE_DAC_SYNC_CK_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CH0_DFE_DAC_SYNC_CK_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CHCK_DFE_DAC_SYNC_CK_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_DEEP_STA_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CHCK_XDBGD_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CHCK_XDBG_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CHCK_VGA_G_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_007C_REG_DA_HDMI_CHCK_TAP5_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0080 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0080)
    #define HD21PHY_EQ_FIFO_CFG_0080_REG_DA_HDMI_CH0_D1L_OV Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0080_REG_DA_HDMI_CH0_D1H_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0080_REG_DA_HDMI_CH0_D0L_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0080_REG_DA_HDMI_CH0_D0H_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0084 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0084)
    #define HD21PHY_EQ_FIFO_CFG_0084_REG_DA_HDMI_CH0_EDBGMON_OV Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0084_REG_DA_HDMI_CH0_E1_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0084_REG_DA_HDMI_CH0_E0_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0084_REG_DA_HDMI_CH0_DAC_XDBG_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0088 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0088)
    #define HD21PHY_EQ_FIFO_CFG_0088_REG_DA_HDMI_CH0_TAP2_OV Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_0088_REG_DA_HDMI_CH0_OFST_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0088_REG_DA_HDMI_CH0_LEV1_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0088_REG_DA_HDMI_CH0_LEV0_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_008C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x008C)
    #define HD21PHY_EQ_FIFO_CFG_008C_REG_DA_HDMI_CH0_XDBGD_OV Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_008C_REG_DA_HDMI_CH0_XDBG_OV Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_008C_REG_DA_HDMI_CH0_TAP5_OV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_008C_REG_DA_HDMI_CH0_TAP4_OV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_008C_REG_DA_HDMI_CH0_TAP3_OV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_0090 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0090)
    #define HD21PHY_EQ_FIFO_CFG_0090_REG_DA_HDMI_CH1_D1L_OV Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0090_REG_DA_HDMI_CH1_D1H_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0090_REG_DA_HDMI_CH1_D0L_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0090_REG_DA_HDMI_CH1_D0H_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0094 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0094)
    #define HD21PHY_EQ_FIFO_CFG_0094_REG_DA_HDMI_CH1_EDBGMON_OV Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0094_REG_DA_HDMI_CH1_E1_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0094_REG_DA_HDMI_CH1_E0_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0094_REG_DA_HDMI_CH1_DAC_XDBG_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0098 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0098)
    #define HD21PHY_EQ_FIFO_CFG_0098_REG_DA_HDMI_CH1_TAP2_OV Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_0098_REG_DA_HDMI_CH1_OFST_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0098_REG_DA_HDMI_CH1_LEV1_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0098_REG_DA_HDMI_CH1_LEV0_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_009C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x009C)
    #define HD21PHY_EQ_FIFO_CFG_009C_REG_DA_HDMI_CH1_XDBGD_OV Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_009C_REG_DA_HDMI_CH1_XDBG_OV Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_009C_REG_DA_HDMI_CH1_TAP5_OV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_009C_REG_DA_HDMI_CH1_TAP4_OV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_009C_REG_DA_HDMI_CH1_TAP3_OV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_00A0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00A0)
    #define HD21PHY_EQ_FIFO_CFG_00A0_REG_DA_HDMI_CH2_D1L_OV Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_00A0_REG_DA_HDMI_CH2_D1H_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_00A0_REG_DA_HDMI_CH2_D0L_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_00A0_REG_DA_HDMI_CH2_D0H_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_00A4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00A4)
    #define HD21PHY_EQ_FIFO_CFG_00A4_REG_DA_HDMI_CH2_EDBGMON_OV Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_00A4_REG_DA_HDMI_CH2_E1_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_00A4_REG_DA_HDMI_CH2_E0_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_00A4_REG_DA_HDMI_CH2_DAC_XDBG_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_00A8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00A8)
    #define HD21PHY_EQ_FIFO_CFG_00A8_REG_DA_HDMI_CH2_TAP2_OV Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_00A8_REG_DA_HDMI_CH2_OFST_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_00A8_REG_DA_HDMI_CH2_LEV1_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_00A8_REG_DA_HDMI_CH2_LEV0_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_00AC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00AC)
    #define HD21PHY_EQ_FIFO_CFG_00AC_REG_DA_HDMI_CH2_XDBGD_OV Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_00AC_REG_DA_HDMI_CH2_XDBG_OV Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_00AC_REG_DA_HDMI_CH2_TAP5_OV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_00AC_REG_DA_HDMI_CH2_TAP4_OV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_00AC_REG_DA_HDMI_CH2_TAP3_OV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_00B0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00B0)
    #define HD21PHY_EQ_FIFO_CFG_00B0_REG_DA_HDMI_CHCK_D1L_OV Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_00B0_REG_DA_HDMI_CHCK_D1H_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_00B0_REG_DA_HDMI_CHCK_D0L_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_00B0_REG_DA_HDMI_CHCK_D0H_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_00B4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00B4)
    #define HD21PHY_EQ_FIFO_CFG_00B4_REG_DA_HDMI_CHCK_EDBGMON_OV Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_00B4_REG_DA_HDMI_CHCK_E1_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_00B4_REG_DA_HDMI_CHCK_E0_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_00B4_REG_DA_HDMI_CHCK_DAC_XDBG_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_00B8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00B8)
    #define HD21PHY_EQ_FIFO_CFG_00B8_REG_DA_HDMI_CHCK_TAP2_OV Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_00B8_REG_DA_HDMI_CHCK_OFST_OV Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_00B8_REG_DA_HDMI_CHCK_LEV1_OV Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_00B8_REG_DA_HDMI_CHCK_LEV0_OV Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_00BC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00BC)
    #define HD21PHY_EQ_FIFO_CFG_00BC_REG_DA_HDMI_CHCK_XDBGD_OV Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_00BC_REG_DA_HDMI_CHCK_XDBG_OV Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_00BC_REG_DA_HDMI_CHCK_TAP5_OV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_00BC_REG_DA_HDMI_CHCK_TAP4_OV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_00BC_REG_DA_HDMI_CHCK_TAP3_OV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_00C0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00C0)
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CHCK_LEQ_G_OV Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CH2_LEQ_G_OV Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CH1_LEQ_G_OV Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CH0_LEQ_G_OV Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CH2_CALEN_DIV5_OV Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CH2_CALEN_OV Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CH1_CALEN_DIV5_OV Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CH1_CALEN_OV Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CH0_CALEN_DIV5_OV Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CH0_CALEN_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CHCK_CALEN_DIV5_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_00C0_REG_DA_HDMI_CHCK_CALEN_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_00C4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00C4)
    #define HD21PHY_EQ_FIFO_CFG_00C4_REG_DA_HDMI_CHCK_ATT_G_OV Fld(2,30,AC_MSKB3)//[31:30]
    #define HD21PHY_EQ_FIFO_CFG_00C4_REG_DA_HDMI_CHCK_VGA_G_OV Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_00C4_REG_DA_HDMI_CH2_ATT_G_OV Fld(2,22,AC_MSKB2)//[23:22]
    #define HD21PHY_EQ_FIFO_CFG_00C4_REG_DA_HDMI_CH2_VGA_G_OV Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_00C4_REG_DA_HDMI_CH1_ATT_G_OV Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_00C4_REG_DA_HDMI_CH1_VGA_G_OV Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_00C4_REG_DA_HDMI_CH0_VGA_G_OV Fld(5,0,AC_MSKB0)//[4:0]
    #define HD21PHY_EQ_FIFO_CFG_00C4_REG_DA_HDMI_CH0_ATT_G_OV Fld(2,6,AC_MSKB0)//[7:6]
#define HD21PHY_EQ_FIFO_CFG_00C8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00C8)
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_AD_HDMI_TEST_SEC_READ Fld(2,26,AC_MSKB3)//[27:26]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_TEST_SEC_WRITE_OV Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_TEST_SEC_SWITCH_OV Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_TEST_SEC_EN_OV Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_MDPLL_REFCK_OV Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_CHCK_PIMODE_OV Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_CH2_PIMODE_OV Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_CH1_PIMODE_OV Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_CH0_PIMODE_OV Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_IMPSEL_OV Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_CH2_DFE_DAC_SYNC_CK_OV Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_CH1_DFE_DAC_SYNC_CK_OV Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_CH0_DFE_DAC_SYNC_CK_OV Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_CHCK_DFE_DAC_SYNC_CK_OV Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_00C8_REG_DA_HDMI_DEEP_STA_OV Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_00CC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00CC)
    #define HD21PHY_EQ_FIFO_CFG_00CC_REG_DA_HDMI_RXFE_CKD_OS0_SEL_OV Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_00CC_REG_DA_HDMI_RXFE_CKD_OS1_SEL_OV Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_00CC_REG_DA_HDMI_RXFE_SD_OS0_SEL_OV Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_00CC_REG_DA_HDMI_RXFE_SD_OS1_SEL_OV Fld(5,0,AC_MSKB0)//[4:0]

//Page HDMI2P1_EQ_FIFO1_2_P1_3
#define HD21PHY_EQ_FIFO_CFG_00D0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00D0)
    #define HD21PHY_EQ_FIFO_CFG_00D0_REG_DA_HDMI_REV_H_OV Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_00D0_REG_DA_HDMI_REV_L_OV Fld(16,0,AC_FULLW10)//[15:0]
		#define HD21PHY_EQ_FIFO_CFG_00D0_REG_RG_HDMI_LCK_IMPSEL	Fld(4,28,AC_MSKB3)//[31:28]    
		#define HD21PHY_EQ_FIFO_CFG_00D0_REG_RG_HDMI_L1_IMPSEL Fld(4,10,AC_MSKB1)//[13:10]
#define HD21PHY_EQ_FIFO_CFG_00D4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00D4)
    #define HD21PHY_EQ_FIFO_CFG_00D4_REG_AD_HDMI_REV_H Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_00D4_REG_AD_HDMI_REV_L Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_00E0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00E0)
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_ICP_03G Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_ICP_06G Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_ICP_08G Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_ICP_10G Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_ICP_12G Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_PREDIV_03G Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_PREDIV_06G Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_PREDIV_08G Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_PREDIV_10G Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_00E0_REG_RG_HDMI_MDPLL_PREDIV_12G Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_00E4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00E4)
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_BR_03G Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_BR_06G Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_BR_08G Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_BR_10G Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_BR_12G Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_KBAND_PREDIV_03G Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_KBAND_PREDIV_06G Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_KBAND_PREDIV_08G Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_KBAND_PREDIV_10G Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_00E4_REG_RG_HDMI_MDPLL_KBAND_PREDIV_12G Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_00E8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00E8)
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BPA_03G Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BPA_06G Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BPA_08G Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BPA_10G Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BPA_12G Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BC_03G Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BC_06G Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BC_08G Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BC_10G Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_00E8_REG_RG_HDMI_MDPLL_BC_12G Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_00EC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00EC)
    #define HD21PHY_EQ_FIFO_CFG_00EC_REG_RG_HDMI_MDPLL_BPB_10G Fld(2,28,AC_MSKB3)//[29:28]
    #define HD21PHY_EQ_FIFO_CFG_00EC_REG_RG_HDMI_MDPLL_IBAND_10G Fld(10,16,AC_MSKW32)//[25:16]
    #define HD21PHY_EQ_FIFO_CFG_00EC_REG_RG_HDMI_MDPLL_BPB_12G Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_00EC_REG_RG_HDMI_MDPLL_IBAND_12G Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_00F0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00F0)
    #define HD21PHY_EQ_FIFO_CFG_00F0_REG_RG_HDMI_MDPLL_BPB_06G Fld(2,28,AC_MSKB3)//[29:28]
    #define HD21PHY_EQ_FIFO_CFG_00F0_REG_RG_HDMI_MDPLL_IBAND_06G Fld(10,16,AC_MSKW32)//[25:16]
    #define HD21PHY_EQ_FIFO_CFG_00F0_REG_RG_HDMI_MDPLL_BPB_08G Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_00F0_REG_RG_HDMI_MDPLL_IBAND_08G Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_00F4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00F4)
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_FBKSEL_03G Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_FBKSEL_06G Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_FBKSEL_08G Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_FBKSEL_10G Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_FBKSEL_12G Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_TCL_EN_03G Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_TCL_EN_06G Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_TCL_EN_08G Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_TCL_EN_10G Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_TCL_EN_12G Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_BPB_03G Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_00F4_REG_RG_HDMI_MDPLL_IBAND_03G Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_00F8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00F8)
    #define HD21PHY_EQ_FIFO_CFG_00F8_REG_RG_HDMI_MDPLL_FBKDIV_06G Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_00F8_REG_RG_HDMI_MDPLL_FBKDIV_08G Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_00F8_REG_RG_HDMI_MDPLL_FBKDIV_10G Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_00F8_REG_RG_HDMI_MDPLL_FBKDIV_12G Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_00FC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x00FC)
    #define HD21PHY_EQ_FIFO_CFG_00FC_REG_RG_HDMI_MDPLL_POSDIV0_03G Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_00FC_REG_RG_HDMI_MDPLL_POSDIV0_06G Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_00FC_REG_RG_HDMI_MDPLL_POSDIV0_08G Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_00FC_REG_RG_HDMI_MDPLL_POSDIV0_10G Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_00FC_REG_RG_HDMI_MDPLL_POSDIV0_12G Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_00FC_REG_RG_HDMI_MDPLL_FBKDIV_03G Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0100 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0100)
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_EN_03G Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_EN_06G Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_EN_08G Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_EN_10G Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_EN_12G Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_LOAD_EN_03G Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_LOAD_EN_06G Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_LOAD_EN_08G Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_LOAD_EN_10G Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_LOAD_EN_12G Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_POSDIV1_03G Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_POSDIV1_06G Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_POSDIV1_08G Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_POSDIV1_10G Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_0100_REG_RG_HDMI_MDPLL_POSDIV1_12G Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_0104 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0104)
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_POSDIV_03G Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_POSDIV_06G Fld(2,22,AC_MSKB2)//[23:22]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_POSDIV_08G Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_POSDIV_10G Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_POSDIV_12G Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_FBKSEL_03G Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_FBKSEL_06G Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_FBKSEL_08G Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_FBKSEL_10G Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_FBKSEL_12G Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_PREDIV_03G Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_PREDIV_06G Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_PREDIV_08G Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_PREDIV_10G Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_0104_REG_RG_HDMI_PLL_PREDIV_12G Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_0108 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0108)
    #define HD21PHY_EQ_FIFO_CFG_0108_REG_RG_HDMI_PLL_FBKDIV_06G Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0108_REG_RG_HDMI_PLL_FBKDIV_08G Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0108_REG_RG_HDMI_PLL_FBKDIV_10G Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0108_REG_RG_HDMI_PLL_FBKDIV_12G Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_010C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x010C)
    #define HD21PHY_EQ_FIFO_CFG_010C_REG_RG_HDMI_PLL_BR_03G Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_010C_REG_RG_HDMI_PLL_BR_06G Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_010C_REG_RG_HDMI_PLL_BR_08G Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_010C_REG_RG_HDMI_PLL_BR_10G Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_010C_REG_RG_HDMI_PLL_BR_12G Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_010C_REG_RG_HDMI_PLL_FBKDIV_03G Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0110 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0110)
    #define HD21PHY_EQ_FIFO_CFG_0110_REG_RG_HDMI_PLL_BC_06G Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_0110_REG_RG_HDMI_PLL_BC_08G Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_0110_REG_RG_HDMI_PLL_BC_10G Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_0110_REG_RG_HDMI_PLL_BC_12G Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_0114 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0114)
    #define HD21PHY_EQ_FIFO_CFG_0114_REG_RG_HDMI_PLL_IC_12G Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_0114_REG_RG_HDMI_PLL_IR_03G Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_0114_REG_RG_HDMI_PLL_IR_06G Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_0114_REG_RG_HDMI_PLL_IR_08G Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_0114_REG_RG_HDMI_PLL_IR_10G Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_0114_REG_RG_HDMI_PLL_IR_12G Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_0114_REG_RG_HDMI_PLL_BC_03G Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_0118 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0118)
    #define HD21PHY_EQ_FIFO_CFG_0118_REG_RG_HDMI_PLL_BP_10G Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_0118_REG_RG_HDMI_PLL_BP_12G Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_0118_REG_RG_HDMI_PLL_IC_03G Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_0118_REG_RG_HDMI_PLL_IC_06G Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_0118_REG_RG_HDMI_PLL_IC_08G Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_0118_REG_RG_HDMI_PLL_IC_10G Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_011C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x011C)
    #define HD21PHY_EQ_FIFO_CFG_011C_REG_RG_HDMI_PLL_BP_03G Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_011C_REG_RG_HDMI_PLL_BP_06G Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_011C_REG_RG_HDMI_PLL_BP_08G Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_0120 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0120)
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_KBAND_PREDIV_03G Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_KBAND_PREDIV_06G Fld(2,22,AC_MSKB2)//[23:22]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_KBAND_PREDIV_08G Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_KBAND_PREDIV_10G Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_KBAND_PREDIV_12G Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_VCO_HBAND_03G Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_VCO_HBAND_06G Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_VCO_HBAND_08G Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_VCO_HBAND_10G Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_VCO_HBAND_12G Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_BP2_03G Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_BP2_06G Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_BP2_08G Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_BP2_10G Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_0120_REG_RG_HDMI_PLL_BP2_12G Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_0124 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0124)
    #define HD21PHY_EQ_FIFO_CFG_0124_REG_RG_HDMI_PLL_KVSEL_10G Fld(2,28,AC_MSKB3)//[29:28]
    #define HD21PHY_EQ_FIFO_CFG_0124_REG_RG_HDMI_PLL_IBAND_10G Fld(10,16,AC_MSKW32)//[25:16]
    #define HD21PHY_EQ_FIFO_CFG_0124_REG_RG_HDMI_PLL_KVSEL_12G Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_0124_REG_RG_HDMI_PLL_IBAND_12G Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_0128 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0128)
    #define HD21PHY_EQ_FIFO_CFG_0128_REG_RG_HDMI_PLL_KVSEL_06G Fld(2,28,AC_MSKB3)//[29:28]
    #define HD21PHY_EQ_FIFO_CFG_0128_REG_RG_HDMI_PLL_IBAND_06G Fld(10,16,AC_MSKW32)//[25:16]
    #define HD21PHY_EQ_FIFO_CFG_0128_REG_RG_HDMI_PLL_KVSEL_08G Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_0128_REG_RG_HDMI_PLL_IBAND_08G Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_012C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x012C)
    #define HD21PHY_EQ_FIFO_CFG_012C_REG_RG_HDMI_PLL_LOAD_EN_03G Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_012C_REG_RG_HDMI_PLL_LOAD_EN_06G Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_012C_REG_RG_HDMI_PLL_LOAD_EN_08G Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_012C_REG_RG_HDMI_PLL_LOAD_EN_10G Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_012C_REG_RG_HDMI_PLL_LOAD_EN_12G Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_012C_REG_RG_HDMI_PLL_KVSEL_03G Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_012C_REG_RG_HDMI_PLL_IBAND_03G Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_0130 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0130)
    #define HD21PHY_EQ_FIFO_CFG_0130_REG_RG_HDMI_VCO_HBAND_03G Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0130_REG_RG_HDMI_VCO_HBAND_06G Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0130_REG_RG_HDMI_VCO_HBAND_08G Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0130_REG_RG_HDMI_VCO_HBAND_10G Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0130_REG_RG_HDMI_VCO_HBAND_12G Fld(1,20,AC_MSKB2)//[20:20]
#define HD21PHY_EQ_FIFO_CFG_0134 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0134)
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_BIAS_EN_03G Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_BIAS_EN_06G Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_BIAS_EN_08G Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_BIAS_EN_10G Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_BIAS_EN_12G Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_TERM_EN_03G Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_TERM_EN_06G Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_TERM_EN_08G Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_TERM_EN_10G Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_TERM_EN_12G Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_DES_HR_SEL_03G Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_DES_HR_SEL_06G Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_DES_HR_SEL_08G Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_DES_HR_SEL_10G Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0134_REG_RG_HDMI_DES_HR_SEL_12G Fld(1,15,AC_MSKB1)//[15:15]
#define HD21PHY_EQ_FIFO_CFG_0138 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0138)
    #define HD21PHY_EQ_FIFO_CFG_0138_REG_RG_HDMI_EQ1_BAND_08G Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_0138_REG_RG_HDMI_EQ1_BAND_10G Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_0138_REG_RG_HDMI_EQ1_BAND_12G Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_0138_REG_RG_HDMI_EQ0_BAND_03G Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_0138_REG_RG_HDMI_EQ0_BAND_06G Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_0138_REG_RG_HDMI_EQ0_BAND_08G Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_0138_REG_RG_HDMI_EQ0_BAND_10G Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_0138_REG_RG_HDMI_EQ0_BAND_12G Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_013C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x013C)
    #define HD21PHY_EQ_FIFO_CFG_013C_REG_RG_HDMI_FEOC_BAND_12G Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_013C_REG_RG_HDMI_EQ2_BAND_03G Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_013C_REG_RG_HDMI_EQ2_BAND_06G Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_013C_REG_RG_HDMI_EQ2_BAND_08G Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_013C_REG_RG_HDMI_EQ2_BAND_10G Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_013C_REG_RG_HDMI_EQ2_BAND_12G Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_013C_REG_RG_HDMI_EQ1_BAND_03G Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_013C_REG_RG_HDMI_EQ1_BAND_06G Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_0140 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0140)
    #define HD21PHY_EQ_FIFO_CFG_0140_REG_RG_HDMI_FEOC_BAND_03G Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_0140_REG_RG_HDMI_FEOC_BAND_06G Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_0140_REG_RG_HDMI_FEOC_BAND_08G Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_0140_REG_RG_HDMI_FEOC_BAND_10G Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_0144 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0144)
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_OSCAL_EN_03G Fld(2,28,AC_MSKB3)//[29:28]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_OSCAL_EN_06G Fld(2,26,AC_MSKB3)//[27:26]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_OSCAL_EN_08G Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_OSCAL_EN_10G Fld(2,22,AC_MSKB2)//[23:22]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_OSCAL_EN_12G Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_DATA_SD_EN_03G Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_DATA_SD_EN_06G Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_DATA_SD_EN_08G Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_DATA_SD_EN_10G Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_DCTEST_EN_03G Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_DCTEST_EN_06G Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_DCTEST_EN_08G Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_DCTEST_EN_10G Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_0144_REG_RG_HDMI_RXFE_SD_DCTEST_EN_12G Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_0148 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0148)
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_HF_SEL_03G Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_HF_SEL_06G Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_HF_SEL_08G Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_HF_SEL_10G Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_HF_SEL_12G Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_RXFE_VCM_EN_03G Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_RXFE_VCM_EN_06G Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_RXFE_VCM_EN_08G Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_RXFE_VCM_EN_10G Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0148_REG_RG_HDMI_RXFE_VCM_EN_12G Fld(1,5,AC_MSKB0)//[5:5]
#define HD21PHY_EQ_FIFO_CFG_014C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x014C)
    #define HD21PHY_EQ_FIFO_CFG_014C_REG_RG_HDMI_KPGAIN_08G Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_014C_REG_RG_HDMI_KPGAIN_10G Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_014C_REG_RG_HDMI_KPGAIN_12G Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_014C_REG_RG_HDMI_KIGAIN_03G Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_014C_REG_RG_HDMI_KIGAIN_06G Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_014C_REG_RG_HDMI_KIGAIN_08G Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_014C_REG_RG_HDMI_KIGAIN_10G Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_014C_REG_RG_HDMI_KIGAIN_12G Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_0150 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0150)
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_RXMODE_HF_03G Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_RXMODE_HF_06G Fld(2,22,AC_MSKB2)//[23:22]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_RXMODE_HF_08G Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_RXMODE_HF_10G Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_RXMODE_HF_12G Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_SIGNCHG_03G Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_SIGNCHG_06G Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_SIGNCHG_08G Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_SIGNCHG_10G Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_SIGNCHG_12G Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_KPGAIN_03G Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_0150_REG_RG_HDMI_KPGAIN_06G Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_0154 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0154)
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_3LANE_MODE_03G Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_3LANE_MODE_06G Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_3LANE_MODE_08G Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_3LANE_MODE_10G Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_3LANE_MODE_12G Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_OS_03G Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_OS_06G Fld(2,22,AC_MSKB2)//[23:22]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_OS_08G Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_OS_10G Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_OS_12G Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_HR_03G Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_HR_06G Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_HR_08G Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_HR_10G Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_0154_REG_RG_HDMI_RXMODE_HR_12G Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_0158 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0158)
    #define HD21PHY_EQ_FIFO_CFG_0158_REG_DA_HDMI_IMPSEL_06G Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_0158_REG_DA_HDMI_IMPSEL_08G Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_0158_REG_DA_HDMI_IMPSEL_10G Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_0158_REG_DA_HDMI_IMPSEL_12G Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_015C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x015C)
    #define HD21PHY_EQ_FIFO_CFG_015C_REG_RG_HDMI_RXFE_CKD_OSCAL_EN_03G Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_015C_REG_RG_HDMI_RXFE_CKD_OSCAL_EN_06G Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_015C_REG_RG_HDMI_RXFE_CKD_OSCAL_EN_08G Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21PHY_EQ_FIFO_CFG_015C_REG_RG_HDMI_RXFE_CKD_OSCAL_EN_10G Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_015C_REG_RG_HDMI_RXFE_CKD_OSCAL_EN_12G Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_015C_REG_DA_HDMI_IMPSEL_03G Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_0160 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0160)
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_MODE_HW_CONFIG Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_DEBUG_SEL_HW_CONFIG Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_FC_DLY_HW_CONFIG Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_RST_DLY_HW_CONFIG Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_IBAND_LVROD_EN_HW_CONFIG Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_LVROD_EN_HW_CONFIG Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_TST_SEL_HW_CONFIG Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_TST_CK_EN_HW_CONFIG Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_TST_OP_EN_HW_CONFIG Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_TST_OD_EN_HW_CONFIG Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_TST_EN_HW_CONFIG Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_CLKSQ_VOD_EN_HW_CONFIG Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_CLKSQ_LPF_EN_HW_CONFIG Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_CLKSQ_HYS_EN_HW_CONFIG Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0160_REG_RG_HDMI_MDPLL_CLKSQ_EN_HW_CONFIG Fld(1,0,AC_MSKB0)//[0:0]

//Page HDMI2P1_EQ_FIFO1_2_P1_4
#define HD21PHY_EQ_FIFO_CFG_0164 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0164)
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_PLL_DEBUG_SEL_HW_CONFIG Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_PLL_MONVC_EN_HW_CONFIG Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_PLL_LVR_REFSEL_HW_CONFIG Fld(2,28,AC_MSKB3)//[29:28]
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_PLL_LVROD_EN_HW_CONFIG Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_PLL_MONREF_EN_HW_CONFIG Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_PLL_MONCK_EN_HW_CONFIG Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_PLL_VREF_RANGE_SEL_HW_CONFIG Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_PLL_FC_DLY_HW_CONFIG Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_PLL_RST_DLY_HW_CONFIG Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0164_REG_RG_HDMI_MDPLL_RESERVE0_HW_CONFIG Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_0168 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0168)
    #define HD21PHY_EQ_FIFO_CFG_0168_REG_RG_HDMI_DAC_LSB_HW_CONFIG Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_0168_REG_RG_HDMI_DAC_CTRL_HW_CONFIG Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_0168_REG_RG_HDMI_CLK_SYNC_INV_HW_CONFIG Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0168_REG_RG_HDMI_PLL_RESERVE_HW_CONFIG Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_016C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x016C)
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_RXFE_CKD_VDM_SEL_HW_CONFIG Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_VCM_SEL_HW_CONFIG Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_RXFE_SD_VDM_SEL_HW_CONFIG Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_RXFE_SD_VCM_SEL_HW_CONFIG Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_RXFE_SD_LPF_CTRL_HW_CONFIG Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_OFST_EN_HW_CONFIG Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_BIAS_SEL_HW_CONFIG Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_BG_EN_HW_CONFIG Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_BBPD_DES_PDB_HW_CONFIG Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_DAC_PWD_CTRL_HW_CONFIG Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_DAC_PWDB_HW_CONFIG Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_016C_REG_RG_HDMI_DAC_MON_HW_CONFIG Fld(6,0,AC_MSKB0)//[5:0]
#define HD21PHY_EQ_FIFO_CFG_0170 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0170)
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_RXFE_CKD_VCM_SEL_HW_CONFIG Fld(2,28,AC_MSKB3)//[29:28]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_RXFE_CKD_LPF_CTRL_HW_CONFIG Fld(2,26,AC_MSKB3)//[27:26]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_RXFE_CKD_DCTEST_EN_HW_CONFIG Fld(2,24,AC_MSKB3)//[25:24]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CHCK_VGA_RESERVE_HW_CONFIG Fld(2,22,AC_MSKB2)//[23:22]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CHCK_LEQ_RESERVE_HW_CONFIG Fld(2,20,AC_MSKB2)//[21:20]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CHCK_ATT_RESERVE_HW_CONFIG Fld(2,18,AC_MSKB2)//[19:18]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CH2_VGA_RESERVE_HW_CONFIG Fld(2,16,AC_MSKB2)//[17:16]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CH2_LEQ_RESERVE_HW_CONFIG Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CH2_ATT_RESERVE_HW_CONFIG Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CH1_VGA_RESERVE_HW_CONFIG Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CH1_LEQ_RESERVE_HW_CONFIG Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CH1_ATT_RESERVE_HW_CONFIG Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CH0_VGA_RESERVE_HW_CONFIG Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CH0_LEQ_RESERVE_HW_CONFIG Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_0170_REG_RG_HDMI_CH0_ATT_RESERVE_HW_CONFIG Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_0174 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0174)
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_CH0_CDRLPI_HW_CONFIG Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_CDRSTOP_HW_CONFIG Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_POST_DIV_RSTN_HW_CONFIG Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_POSTDIV_PDB_HW_CONFIG Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_POST_DIV_2_SEL_HW_CONFIG Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_POST_DIV_2_DIV3_RSTN_HW_CONFIG Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_POST_DIV_2_DIV3_EN_HW_CONFIG Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_POST_DIV_SEL_HW_CONFIG Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_TAP_PWDB_HW_CONFIG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_DFE_PWDB_HW_CONFIG Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_DFE_SYNC_CK_INV_HW_CONFIG Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_DFEBIAS_FBDIS_HW_CONFIG Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_DEEP_DIV_DIV12_EN_HW_CONFIG Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_DEEP_DIV_DIV12_B_HW_CONFIG Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_DEEP_DIV_DIV12_A_HW_CONFIG Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_DEEP_DIV_DIV3_SEL_HW_CONFIG Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_DEEPCLRCLKRSTN_HW_CONFIG Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0174_REG_RG_HDMI_DEEPCLRCLKPDB_HW_CONFIG Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0178 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0178)
    #define HD21PHY_EQ_FIFO_CFG_0178_REG_RG_HDMI_PLL_FIFO_CK_EN_HW_CONFIG Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0178_REG_RG_HDMI_MDPLL_REF_ADA_DA_SEL_HW_CONFIG Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0178_REG_RG_HDMI_R2R_CK_SEL_HW_CONFIG Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0178_REG_RG_HDMI_HDMI21_MODE_HW_CONFIG Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0178_REG_RG_HDMI_CHCK_CDRLPI_HW_CONFIG Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_0178_REG_RG_HDMI_CH2_CDRLPI_HW_CONFIG Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_0178_REG_RG_HDMI_CH1_CDRLPI_HW_CONFIG Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_017C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x017C)
    #define HD21PHY_EQ_FIFO_CFG_017C_REG_RG_HDMI_REV_H_HW_CONFIG Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_017C_REG_RG_HDMI_REV_L_HW_CONFIG Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_0180 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0180)
    #define HD21PHY_EQ_FIFO_CFG_0180_REG_RG_HDMI_ATEST_EN_HW_CONFIG Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0180_REG_RG_HDMI_FM_SEL2_HW_CONFIG Fld(12,16,AC_MSKW32)//[27:16]
    #define HD21PHY_EQ_FIFO_CFG_0180_REG_RG_HDMI_FM_SEL_HW_CONFIG Fld(12,0,AC_MSKW10)//[11:0]
#define HD21PHY_EQ_FIFO_CFG_0184 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0184)
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_CHCK_RXFE_OS_MON_EN_HW_CONFIG Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_CH2_RXFE_OS_MON_EN_HW_CONFIG Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_CH1_RXFE_OS_MON_EN_HW_CONFIG Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_CH0_RXFE_OS_MON_EN_HW_CONFIG Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_CHCK_RXFE_OS_MON_SEL_HW_CONFIG Fld(2,14,AC_MSKB1)//[15:14]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_CH2_RXFE_OS_MON_SEL_HW_CONFIG Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_CH1_RXFE_OS_MON_SEL_HW_CONFIG Fld(2,10,AC_MSKB1)//[11:10]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_CH0_RXFE_OS_MON_SEL_HW_CONFIG Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_MON18_SEL_HW_CONFIG Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_TESTE_HW_CONFIG Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0184_REG_RG_HDMI_FE_AMP_MON_CTRL_HW_CONFIG Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_0188 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0188)
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_RG_CAL_100N_SET Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_LNCK_PHY_LOS_OV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_LNCK_PHY_LOS_OV Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_LN2_PHY_LOS_OV_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_LN2_PHY_LOS_OV Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_LN2_PHY_LOS_XOR Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_RG_LNX_SW_SD_KIWIN Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_RG_LNX_PCS_MODE Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_XFI_LNX_SIG_REDET_SW Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_XLAUI_LNX_SIG_REDET Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_ANLT_LNX_BLOCK_LOCK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_ANLT_LNX_AN_DONE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_CDRCTL_LNX_AN_DET_PRD Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_CDRCTL_LNX_SW_RX_POR_RDY Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_CDRCTL_LNX_RXPLL_FREQ_LOCK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_PLLCTL_LNX_SW_RX_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_SIGDET_LNX_FLAGL_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0188_REG_SIGDET_LNX_FLAGH_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_018C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x018C)
    #define HD21PHY_EQ_FIFO_CFG_018C_REG_RG_LNX_SW_SD_KO_OPT Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_018C_REG_RG_LNX_SW_SD_KI_OPT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_018C_REG_RG_LNX_SW_SD_SAM1TH Fld(2,6,AC_MSKB0)//[7:6]
    #define HD21PHY_EQ_FIFO_CFG_018C_REG_RG_LNX_SW_SD_WINTIME Fld(2,4,AC_MSKB0)//[5:4]
    #define HD21PHY_EQ_FIFO_CFG_018C_REG_RG_LNX_SW_SD_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_018C_REG_RG_LNX_SW_FORCE_SD_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_018C_REG_RG_LNX_SW_SD_OUT Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_018C_REG_RG_LNX_SW_FORCE_SD_OUT Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0190 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0190)
    #define HD21PHY_EQ_FIFO_CFG_0190_REG_SIGDET_FLAGL_SEL Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0190_REG_SIGDET_FLAGH_SEL Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0194 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0194)
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN3_LTP_REQ Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN2_LTP_REQ Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN1_LTP_REQ Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN0_LTP_REQ Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_TRAINING_EN_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_ENABLE_4LANE_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_SCRAMBLING_ENABLE_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN3_LTP_SET_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN2_LTP_SET_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN1_LTP_SET_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN0_LTP_SET_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_FRL_START_CLR_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_FRL_START_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_FLT_UPDATE_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_FLT_READY_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN3_LTP_REQ_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN2_LTP_REQ_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN1_LTP_REQ_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0194_REG_LN0_LTP_REQ_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0198 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0198)
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_TMDS_RATIO Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_FRL_RATE_SEL Fld(2,28,AC_MSKB3)//[29:28]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_FRL_RATE Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_TRAINING_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_ENABLE_4LANE Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_SCRAMBLING_ENABLE Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_LN3_LTP_SET Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_LN2_LTP_SET Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_LN1_LTP_SET Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_LN0_LTP_SET Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_FRL_START_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_FRL_START Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_FLT_UPDATE Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0198_REG_FLT_READY Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_01A0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x01A0)
    #define HD21PHY_EQ_FIFO_CFG_01A0_REG_CLKDET0_C_CKDT_H Fld(10,16,AC_MSKW32)//[25:16]
    #define HD21PHY_EQ_FIFO_CFG_01A0_REG_CLKDET0_C_CLK_DIV Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_01A4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x01A4)
    #define HD21PHY_EQ_FIFO_CFG_01A4_REG_CLKDET0_CK_PERIOD Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_01A4_REG_CLKDET0_C_INBAND_THR Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_01A4_REG_CLKDET0_C_CKDT_L Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_01A8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x01A8)
    #define HD21PHY_EQ_FIFO_CFG_01A8_REG_CLKDET1_C_CKDT_H Fld(10,16,AC_MSKW32)//[25:16]
    #define HD21PHY_EQ_FIFO_CFG_01A8_REG_CLKDET1_C_CLK_DIV Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_01AC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x01AC)
    #define HD21PHY_EQ_FIFO_CFG_01AC_REG_CLKDET1_CK_PERIOD Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_01AC_REG_CLKDET1_C_INBAND_THR Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_01AC_REG_CLKDET1_C_CKDT_L Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_01B0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x01B0)
    #define HD21PHY_EQ_FIFO_CFG_01B0_REG_CLKDET2_C_CKDT_H Fld(10,16,AC_MSKW32)//[25:16]
    #define HD21PHY_EQ_FIFO_CFG_01B0_REG_CLKDET2_C_CLK_DIV Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_01B4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x01B4)
    #define HD21PHY_EQ_FIFO_CFG_01B4_REG_CLKDET2_CK_PERIOD Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_01B4_REG_CLKDET2_C_INBAND_THR Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_01B4_REG_CLKDET2_C_CKDT_L Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_EQ_FIFO_CFG_01B8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x01B8)
    #define HD21PHY_EQ_FIFO_CFG_01B8_REG_XTAL_FREQ Fld(8,0,AC_FULLB0)//[7:0]

//HDMI2P1_EQ_FIFO3
#define HD21PHY_EQ_FIFO_CFG_0200 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0200)
    #define HD21PHY_EQ_FIFO_CFG_0200_REG_HEND_RG_HDMI_MDPLL_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0200_REG_HST_RG_HDMI_MDPLL_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0204 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0204)
    #define HD21PHY_EQ_FIFO_CFG_0204_REG_VEND_RG_HDMI_MDPLL_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0204_REG_VST_RG_HDMI_MDPLL_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0208 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0208)
    #define HD21PHY_EQ_FIFO_CFG_0208_REG_CTRL_RG_HDMI_MDPLL_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_020C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x020C)
    #define HD21PHY_EQ_FIFO_CFG_020C_REG_HEND_MDPLL_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_020C_REG_HST_MDPLL_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0210 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0210)
    #define HD21PHY_EQ_FIFO_CFG_0210_REG_VEND_MDPLL_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0210_REG_VST_MDPLL_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0214 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0214)
    #define HD21PHY_EQ_FIFO_CFG_0214_REG_CTRL_MDPLL_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0218 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0218)
    #define HD21PHY_EQ_FIFO_CFG_0218_REG_HEND_RG_HDMI_PLL_BG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0218_REG_HST_RG_HDMI_PLL_BG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_021C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x021C)
    #define HD21PHY_EQ_FIFO_CFG_021C_REG_VEND_RG_HDMI_PLL_BG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_021C_REG_VST_RG_HDMI_PLL_BG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0220 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0220)
    #define HD21PHY_EQ_FIFO_CFG_0220_REG_CTRL_RG_HDMI_PLL_BG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0224 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0224)
    #define HD21PHY_EQ_FIFO_CFG_0224_REG_HEND_RG_HDMI_PLL_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0224_REG_HST_RG_HDMI_PLL_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0228 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0228)
    #define HD21PHY_EQ_FIFO_CFG_0228_REG_VEND_RG_HDMI_PLL_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0228_REG_VST_RG_HDMI_PLL_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_022C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x022C)
    #define HD21PHY_EQ_FIFO_CFG_022C_REG_CTRL_RG_HDMI_PLL_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0230 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0230)
    #define HD21PHY_EQ_FIFO_CFG_0230_REG_HEND_HDMIRXPLL_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0230_REG_HST_HDMIRXPLL_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0234 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0234)
    #define HD21PHY_EQ_FIFO_CFG_0234_REG_VEND_HDMIRXPLL_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0234_REG_VST_HDMIRXPLL_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0238 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0238)
    #define HD21PHY_EQ_FIFO_CFG_0238_REG_CTRL_HDMIRXPLL_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_023C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x023C)
    #define HD21PHY_EQ_FIFO_CFG_023C_REG_HEND_RG_HDMI_PI_DATA_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_023C_REG_HST_RG_HDMI_PI_DATA_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0240 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0240)
    #define HD21PHY_EQ_FIFO_CFG_0240_REG_VEND_RG_HDMI_PI_DATA_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0240_REG_VST_RG_HDMI_PI_DATA_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0244 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0244)
    #define HD21PHY_EQ_FIFO_CFG_0244_REG_CTRL_RG_HDMI_PI_DATA_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0248 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0248)
    #define HD21PHY_EQ_FIFO_CFG_0248_REG_HEND_RG_HDMI_PI_EDGE_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0248_REG_HST_RG_HDMI_PI_EDGE_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_024C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x024C)
    #define HD21PHY_EQ_FIFO_CFG_024C_REG_VEND_RG_HDMI_PI_EDGE_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_024C_REG_VST_RG_HDMI_PI_EDGE_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0250 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0250)
    #define HD21PHY_EQ_FIFO_CFG_0250_REG_CTRL_RG_HDMI_PI_EDGE_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0254 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0254)
    #define HD21PHY_EQ_FIFO_CFG_0254_REG_HEND_RG_HDMI_PI_XDBG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0254_REG_HST_RG_HDMI_PI_XDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0258 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0258)
    #define HD21PHY_EQ_FIFO_CFG_0258_REG_VEND_RG_HDMI_PI_XDBG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0258_REG_VST_RG_HDMI_PI_XDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_025C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x025C)
    #define HD21PHY_EQ_FIFO_CFG_025C_REG_CTRL_RG_HDMI_PI_XDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0260 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0260)
    #define HD21PHY_EQ_FIFO_CFG_0260_REG_HEND_RG_HDMI_PI_EDBG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0260_REG_HST_RG_HDMI_PI_EDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0264 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0264)
    #define HD21PHY_EQ_FIFO_CFG_0264_REG_VEND_RG_HDMI_PI_EDBG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0264_REG_VST_RG_HDMI_PI_EDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0268 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0268)
    #define HD21PHY_EQ_FIFO_CFG_0268_REG_CTRL_RG_HDMI_PI_EDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_026C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x026C)
    #define HD21PHY_EQ_FIFO_CFG_026C_REG_HEND_RG_HDMI_SAOC_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_026C_REG_HST_RG_HDMI_SAOC_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0270 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0270)
    #define HD21PHY_EQ_FIFO_CFG_0270_REG_VEND_RG_HDMI_SAOC_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0270_REG_VST_RG_HDMI_SAOC_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0274 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0274)
    #define HD21PHY_EQ_FIFO_CFG_0274_REG_CTRL_RG_HDMI_SAOC_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0278 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0278)
    #define HD21PHY_EQ_FIFO_CFG_0278_REG_HEND_RG_HDMI_FEOC_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0278_REG_HST_RG_HDMI_FEOC_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_027C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x027C)
    #define HD21PHY_EQ_FIFO_CFG_027C_REG_VEND_RG_HDMI_FEOC_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_027C_REG_VST_RG_HDMI_FEOC_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0280 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0280)
    #define HD21PHY_EQ_FIFO_CFG_0280_REG_CTRL_RG_HDMI_FEOC_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0284 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0284)
    #define HD21PHY_EQ_FIFO_CFG_0284_REG_HEND_PIEDBG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0284_REG_HST_PIEDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0288 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0288)
    #define HD21PHY_EQ_FIFO_CFG_0288_REG_VEND_PIEDBG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0288_REG_VST_PIEDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_028C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x028C)
    #define HD21PHY_EQ_FIFO_CFG_028C_REG_CTRL_PIEDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0290 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0290)
    #define HD21PHY_EQ_FIFO_CFG_0290_REG_HEND_OSCAL_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0290_REG_HST_OSCAL_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0294 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0294)
    #define HD21PHY_EQ_FIFO_CFG_0294_REG_VEND_OSCAL_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0294_REG_VST_OSCAL_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0298 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0298)
    #define HD21PHY_EQ_FIFO_CFG_0298_REG_CTRL_OSCAL_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_029C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x029C)
    #define HD21PHY_EQ_FIFO_CFG_029C_REG_HEND_PLLCTL_LNX_SW_RX_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_029C_REG_HST_PLLCTL_LNX_SW_RX_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02A0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02A0)
    #define HD21PHY_EQ_FIFO_CFG_02A0_REG_VEND_PLLCTL_LNX_SW_RX_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02A0_REG_VST_PLLCTL_LNX_SW_RX_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02A4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02A4)
    #define HD21PHY_EQ_FIFO_CFG_02A4_REG_CTRL_PLLCTL_LNX_SW_RX_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02A8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02A8)
    #define HD21PHY_EQ_FIFO_CFG_02A8_REG_HEND_RG_HDMI_RXFE_SD_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02A8_REG_HST_RG_HDMI_RXFE_SD_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02AC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02AC)
    #define HD21PHY_EQ_FIFO_CFG_02AC_REG_VEND_RG_HDMI_RXFE_SD_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02AC_REG_VST_RG_HDMI_RXFE_SD_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02B0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02B0)
    #define HD21PHY_EQ_FIFO_CFG_02B0_REG_CTRL_RG_HDMI_RXFE_SD_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02B4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02B4)
    #define HD21PHY_EQ_FIFO_CFG_02B4_REG_HEND_RG_HDMI_CDRRST_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02B4_REG_HST_RG_HDMI_CDRRST_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02B8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02B8)
    #define HD21PHY_EQ_FIFO_CFG_02B8_REG_VEND_RG_HDMI_CDRRST_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02B8_REG_VST_RG_HDMI_CDRRST_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02BC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02BC)
    #define HD21PHY_EQ_FIFO_CFG_02BC_REG_CTRL_RG_HDMI_CDRRST_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02C0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02C0)
    #define HD21PHY_EQ_FIFO_CFG_02C0_REG_HEND_CDR_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02C0_REG_HST_CDR_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02C4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02C4)
    #define HD21PHY_EQ_FIFO_CFG_02C4_REG_VEND_CDR_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02C4_REG_VST_CDR_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02C8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02C8)
    #define HD21PHY_EQ_FIFO_CFG_02C8_REG_CTRL_CDR_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02CC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02CC)
    #define HD21PHY_EQ_FIFO_CFG_02CC_REG_HEND_LEQ_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02CC_REG_HST_LEQ_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02D0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02D0)
    #define HD21PHY_EQ_FIFO_CFG_02D0_REG_VEND_LEQ_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02D0_REG_VST_LEQ_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02D4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02D4)
    #define HD21PHY_EQ_FIFO_CFG_02D4_REG_CTRL_LEQ_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02D8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02D8)
    #define HD21PHY_EQ_FIFO_CFG_02D8_REG_HEND_LEQ_LEAK_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02D8_REG_HST_LEQ_LEAK_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02DC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02DC)
    #define HD21PHY_EQ_FIFO_CFG_02DC_REG_VEND_LEQ_LEAK_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02DC_REG_VST_LEQ_LEAK_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02E0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02E0)
    #define HD21PHY_EQ_FIFO_CFG_02E0_REG_CTRL_LEQ_LEAK_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02E4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02E4)
    #define HD21PHY_EQ_FIFO_CFG_02E4_REG_HEND_LEQ_LEN_CTRL_3_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02E4_REG_HST_LEQ_LEN_CTRL_3_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02E8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02E8)
    #define HD21PHY_EQ_FIFO_CFG_02E8_REG_VEND_LEQ_LEN_CTRL_3_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02E8_REG_VST_LEQ_LEN_CTRL_3_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02EC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02EC)
    #define HD21PHY_EQ_FIFO_CFG_02EC_REG_CTRL_LEQ_LEN_CTRL_3_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02F0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02F0)
    #define HD21PHY_EQ_FIFO_CFG_02F0_REG_HEND_LEQ_LEN_CTRL_2_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02F0_REG_HST_LEQ_LEN_CTRL_2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02F4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02F4)
    #define HD21PHY_EQ_FIFO_CFG_02F4_REG_VEND_LEQ_LEN_CTRL_2_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02F4_REG_VST_LEQ_LEN_CTRL_2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02F8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02F8)
    #define HD21PHY_EQ_FIFO_CFG_02F8_REG_CTRL_LEQ_LEN_CTRL_2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_02FC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x02FC)
    #define HD21PHY_EQ_FIFO_CFG_02FC_REG_HEND_LEQ_LEN_CTRL_1_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_02FC_REG_HST_LEQ_LEN_CTRL_1_GPO Fld(8,0,AC_FULLB0)//[7:0]

#define HD21PHY_EQ_FIFO_CFG_0300 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0300)
    #define HD21PHY_EQ_FIFO_CFG_0300_REG_VEND_LEQ_LEN_CTRL_1_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0300_REG_VST_LEQ_LEN_CTRL_1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0304 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0304)
    #define HD21PHY_EQ_FIFO_CFG_0304_REG_CTRL_LEQ_LEN_CTRL_1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0308 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0308)
    #define HD21PHY_EQ_FIFO_CFG_0308_REG_HEND_LEQ_LEN_CTRL_0_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0308_REG_HST_LEQ_LEN_CTRL_0_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_030C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x030C)
    #define HD21PHY_EQ_FIFO_CFG_030C_REG_VEND_LEQ_LEN_CTRL_0_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_030C_REG_VST_LEQ_LEN_CTRL_0_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0310 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0310)
    #define HD21PHY_EQ_FIFO_CFG_0310_REG_CTRL_LEQ_LEN_CTRL_0_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0314 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0314)
    #define HD21PHY_EQ_FIFO_CFG_0314_REG_HEND_LEQ_PF_CTRL_3_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0314_REG_HST_LEQ_PF_CTRL_3_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0318 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0318)
    #define HD21PHY_EQ_FIFO_CFG_0318_REG_VEND_LEQ_PF_CTRL_3_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0318_REG_VST_LEQ_PF_CTRL_3_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_031C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x031C)
    #define HD21PHY_EQ_FIFO_CFG_031C_REG_CTRL_LEQ_PF_CTRL_3_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0320 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0320)
    #define HD21PHY_EQ_FIFO_CFG_0320_REG_HEND_LEQ_PF_CTRL_2_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0320_REG_HST_LEQ_PF_CTRL_2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0324 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0324)
    #define HD21PHY_EQ_FIFO_CFG_0324_REG_VEND_LEQ_PF_CTRL_2_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0324_REG_VST_LEQ_PF_CTRL_2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0328 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0328)
    #define HD21PHY_EQ_FIFO_CFG_0328_REG_CTRL_LEQ_PF_CTRL_2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_032C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x032C)
    #define HD21PHY_EQ_FIFO_CFG_032C_REG_HEND_LEQ_PF_CTRL_1_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_032C_REG_HST_LEQ_PF_CTRL_1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0330 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0330)
    #define HD21PHY_EQ_FIFO_CFG_0330_REG_VEND_LEQ_PF_CTRL_1_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0330_REG_VST_LEQ_PF_CTRL_1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0334 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0334)
    #define HD21PHY_EQ_FIFO_CFG_0334_REG_CTRL_LEQ_PF_CTRL_1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0338 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0338)
    #define HD21PHY_EQ_FIFO_CFG_0338_REG_HEND_LEQ_PF_CTRL_0_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0338_REG_HST_LEQ_PF_CTRL_0_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_033C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x033C)
    #define HD21PHY_EQ_FIFO_CFG_033C_REG_VEND_LEQ_PF_CTRL_0_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_033C_REG_VST_LEQ_PF_CTRL_0_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0340 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0340)
    #define HD21PHY_EQ_FIFO_CFG_0340_REG_CTRL_LEQ_PF_CTRL_0_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0344 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0344)
    #define HD21PHY_EQ_FIFO_CFG_0344_REG_HEND_LEQ_AVG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0344_REG_HST_LEQ_AVG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0348 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0348)
    #define HD21PHY_EQ_FIFO_CFG_0348_REG_VEND_LEQ_AVG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0348_REG_VST_LEQ_AVG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_034C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x034C)
    #define HD21PHY_EQ_FIFO_CFG_034C_REG_CTRL_LEQ_AVG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0350 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0350)
    #define HD21PHY_EQ_FIFO_CFG_0350_REG_HEND_DFE_TAP_EN_N1_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0350_REG_HST_DFE_TAP_EN_N1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0354 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0354)
    #define HD21PHY_EQ_FIFO_CFG_0354_REG_VEND_DFE_TAP_EN_N1_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0354_REG_VST_DFE_TAP_EN_N1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0358 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0358)
    #define HD21PHY_EQ_FIFO_CFG_0358_REG_CTRL_DFE_TAP_EN_N1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_035C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x035C)
    #define HD21PHY_EQ_FIFO_CFG_035C_REG_HEND_DFE_TAP_EN_0_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_035C_REG_HST_DFE_TAP_EN_0_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0360 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0360)
    #define HD21PHY_EQ_FIFO_CFG_0360_REG_VEND_DFE_TAP_EN_0_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0360_REG_VST_DFE_TAP_EN_0_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0364 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0364)
    #define HD21PHY_EQ_FIFO_CFG_0364_REG_CTRL_DFE_TAP_EN_0_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0368 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0368)
    #define HD21PHY_EQ_FIFO_CFG_0368_REG_HEND_DFE_TAP_EN_1_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0368_REG_HST_DFE_TAP_EN_1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_036C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x036C)
    #define HD21PHY_EQ_FIFO_CFG_036C_REG_VEND_DFE_TAP_EN_1_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_036C_REG_VST_DFE_TAP_EN_1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0370 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0370)
    #define HD21PHY_EQ_FIFO_CFG_0370_REG_CTRL_DFE_TAP_EN_1_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0374 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0374)
    #define HD21PHY_EQ_FIFO_CFG_0374_REG_HEND_DFE_TAP_EN_2_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0374_REG_HST_DFE_TAP_EN_2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0378 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0378)
    #define HD21PHY_EQ_FIFO_CFG_0378_REG_VEND_DFE_TAP_EN_2_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0378_REG_VST_DFE_TAP_EN_2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_037C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x037C)
    #define HD21PHY_EQ_FIFO_CFG_037C_REG_CTRL_DFE_TAP_EN_2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0380 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0380)
    #define HD21PHY_EQ_FIFO_CFG_0380_REG_HEND_DFE_TAP_EN_3_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0380_REG_HST_DFE_TAP_EN_3_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0384 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0384)
    #define HD21PHY_EQ_FIFO_CFG_0384_REG_VEND_DFE_TAP_EN_3_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0384_REG_VST_DFE_TAP_EN_3_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0388 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0388)
    #define HD21PHY_EQ_FIFO_CFG_0388_REG_CTRL_DFE_TAP_EN_3_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_038C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x038C)
    #define HD21PHY_EQ_FIFO_CFG_038C_REG_HEND_DFE_TAP_EN_4_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_038C_REG_HST_DFE_TAP_EN_4_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0390 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0390)
    #define HD21PHY_EQ_FIFO_CFG_0390_REG_VEND_DFE_TAP_EN_4_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0390_REG_VST_DFE_TAP_EN_4_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0394 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0394)
    #define HD21PHY_EQ_FIFO_CFG_0394_REG_CTRL_DFE_TAP_EN_4_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0398 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0398)
    #define HD21PHY_EQ_FIFO_CFG_0398_REG_HEND_DFE_TAP_EN_5_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0398_REG_HST_DFE_TAP_EN_5_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_039C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x039C)
    #define HD21PHY_EQ_FIFO_CFG_039C_REG_VEND_DFE_TAP_EN_5_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_039C_REG_VST_DFE_TAP_EN_5_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03A0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03A0)
    #define HD21PHY_EQ_FIFO_CFG_03A0_REG_CTRL_DFE_TAP_EN_5_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03A4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03A4)
    #define HD21PHY_EQ_FIFO_CFG_03A4_REG_HEND_XDBG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03A4_REG_HST_XDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03A8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03A8)
    #define HD21PHY_EQ_FIFO_CFG_03A8_REG_VEND_XDBG_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03A8_REG_VST_XDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03AC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03AC)
    #define HD21PHY_EQ_FIFO_CFG_03AC_REG_CTRL_XDBG_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03B0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03B0)
    #define HD21PHY_EQ_FIFO_CFG_03B0_REG_HEND_VGA_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03B0_REG_HST_VGA_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03B4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03B4)
    #define HD21PHY_EQ_FIFO_CFG_03B4_REG_VEND_VGA_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03B4_REG_VST_VGA_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03B8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03B8)
    #define HD21PHY_EQ_FIFO_CFG_03B8_REG_CTRL_VGA_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03BC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03BC)
    #define HD21PHY_EQ_FIFO_CFG_03BC_REG_HEND_CYC_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03BC_REG_HST_CYC_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03C0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03C0)
    #define HD21PHY_EQ_FIFO_CFG_03C0_REG_VEND_CYC_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03C0_REG_VST_CYC_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03C4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03C4)
    #define HD21PHY_EQ_FIFO_CFG_03C4_REG_CTRL_CYC_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03C8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03C8)
    #define HD21PHY_EQ_FIFO_CFG_03C8_REG_HEND_ALG_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03C8_REG_HST_ALG_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03CC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03CC)
    #define HD21PHY_EQ_FIFO_CFG_03CC_REG_VEND_ALG_DONE_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03CC_REG_VST_ALG_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03D0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03D0)
    #define HD21PHY_EQ_FIFO_CFG_03D0_REG_GPO_DUMMY0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03D0_REG_CTRL_ALG_DONE_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03D4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03D4)
    #define HD21PHY_EQ_FIFO_CFG_03D4_REG_HEND_RG_HDMI_RXFE_AMP_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03D4_REG_HST_RG_HDMI_RXFE_AMP_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03D8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03D8)
    #define HD21PHY_EQ_FIFO_CFG_03D8_REG_VEND_RG_HDMI_RXFE_AMP_EN_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03D8_REG_VST_RG_HDMI_RXFE_AMP_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03DC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03DC)
    #define HD21PHY_EQ_FIFO_CFG_03DC_REG_GPO_DUMMY1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03DC_REG_GPO_DUMMY1_ECO_WRITE_LATENCY Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_03DC_REG_CTRL_RG_HDMI_RXFE_AMP_EN_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03E0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03E0)
    #define HD21PHY_EQ_FIFO_CFG_03E0_REG_HEND_REF_RST_B_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03E0_REG_HST_REF_RST_B_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03E4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03E4)
    #define HD21PHY_EQ_FIFO_CFG_03E4_REG_VEND_REF_RST_B_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03E4_REG_VST_REF_RST_B_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03E8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03E8)
    #define HD21PHY_EQ_FIFO_CFG_03E8_REG_EN_STATE5 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_03E8_REG_STATE5_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_03E8_REG_LNX_PHY_LOS_GPO_SHOT Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_03E8_REG_HDMIRXPLL_DONE_GPO_SHOT Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_03E8_REG_LNX_PHY_LOS_GPO_OV Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_03E8_REG_HDMIRXPLL_DONE_GPO_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_03E8_REG_CTRL_REF_RST_B_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03EC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03EC)
    #define HD21PHY_EQ_FIFO_CFG_03EC_REG_TIME_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_03EC_REG_TIME_CNT_THR_HI Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_03EC_REG_TIME_CNT_THR Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03F0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03F0)
    #define HD21PHY_EQ_FIFO_CFG_03F0_REG_GPO_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_03F0_REG_GPO_STATE_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_03F0_REG_GPO_STATE Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_03F0_REG_CLR_MASK Fld(5,3,AC_MSKB0)//[7:3]
    #define HD21PHY_EQ_FIFO_CFG_03F0_REG_RST_MASK Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_03F4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03F4)
    #define HD21PHY_EQ_FIFO_CFG_03F4_REG_HEND_REF_RST_B_ST2_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03F4_REG_HST_REF_RST_B_ST2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03F8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03F8)
    #define HD21PHY_EQ_FIFO_CFG_03F8_REG_VEND_REF_RST_B_ST2_GPO Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03F8_REG_VST_REF_RST_B_ST2_GPO Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_03FC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x03FC)
    #define HD21PHY_EQ_FIFO_CFG_03FC_REG_GPO_DUMMY2 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_03FC_REG_CTRL_REF_RST_B_ST2_GPO Fld(8,0,AC_FULLB0)//[7:0]

//Page HDMI2P1_EQ_FIFO4_5
#define HD21PHY_EQ_FIFO_CFG_0400 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0400)
    #define HD21PHY_EQ_FIFO_CFG_0400_REG_DBG_EVEN_VALID_CNT_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0400_REG_DBG_EVEN_VALID_CNT_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0400_REG_DBG_EVEN_VALID_CNT_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0400_REG_DBG_EVEN_VALID_CNT_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0404 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0404)
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_RO_PIEDBG_DIV5EN_LCK Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_RO_PIEDBG_DIV5EN_L2 Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_RO_PIEDBG_DIV5EN_L1 Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_RO_PIEDBG_DIV5EN_L0 Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_EQ_EDBG_CNT_RDY_INT_LCK Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_EQ_EDBG_CNT_RDY_INT_L2 Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_EQ_EDBG_CNT_RDY_INT_L1 Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_EQ_EDBG_CNT_RDY_INT_L0 Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_SYNC_EDBG_CNT_EN_LCK Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_SYNC_EDBG_CNT_EN_L2 Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_SYNC_EDBG_CNT_EN_L1 Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_SYNC_EDBG_CNT_EN_L0 Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_PIEDBG_CAL_LATE_LCK Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_PIEDBG_CAL_LATE_L2 Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_PIEDBG_CAL_LATE_L1 Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_PIEDBG_CAL_LATE_L0 Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_RG_EQ_EDBG_CNT_RDY_O_LCK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_RG_EQ_EDBG_CNT_RDY_O_L2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_RG_EQ_EDBG_CNT_RDY_O_L1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_RG_EQ_EDBG_CNT_RDY_O_L0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_PIEDBG_CAL_EARLY_LCK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_PIEDBG_CAL_EARLY_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_PIEDBG_CAL_EARLY_L1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_PIEDBG_CAL_EARLY_L0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_EDBG_ODD_ENABLE_LCK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_EDBG_ODD_ENABLE_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_EDBG_ODD_ENABLE_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_EDBG_ODD_ENABLE_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_EDBG_EVEN_ENABLE_LCK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_EDBG_EVEN_ENABLE_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_EDBG_EVEN_ENABLE_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0404_REG_DBG_EDBG_EVEN_ENABLE_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0408 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0408)
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CALEN_LCK Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CALEN_L2 Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CALEN_L1 Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CALEN_L0 Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_LATE_LCK Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_LATE_L2 Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_LATE_L1 Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_LATE_L0 Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_EARLY_LCK Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_EARLY_L2 Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_EARLY_L1 Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_EARLY_L0 Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_DONE_LCK Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_DONE_L2 Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_DONE_L1 Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_RO_PIEDBG_CAL_DONE_L0 Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_DBG_PIEDBG_ST_LCK Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_DBG_PIEDBG_ST_L2 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_DBG_PIEDBG_ST_L1 Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_0408_REG_DBG_PIEDBG_ST_L0 Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_040C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x040C)
    #define HD21PHY_EQ_FIFO_CFG_040C_REG_DBG_ODD_VALID_CNT_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_040C_REG_DBG_ODD_VALID_CNT_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_040C_REG_DBG_ODD_VALID_CNT_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_040C_REG_DBG_ODD_VALID_CNT_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0410 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0410)
    #define HD21PHY_EQ_FIFO_CFG_0410_REG_DBG_PIEDBG_CAL_TEMP_LCK Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0410_REG_DBG_PIEDBG_CAL_TEMP_L2 Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_0410_REG_DBG_PIEDBG_CAL_TEMP_L1 Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_0410_REG_DBG_PIEDBG_CAL_TEMP_L0 Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0414 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0414)
    #define HD21PHY_EQ_FIFO_CFG_0414_REG_RG_EQ_EVEN_ERR_PAT_O_L1 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0414_REG_RG_EQ_EVEN_ERR_PAT_O_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0418 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0418)
    #define HD21PHY_EQ_FIFO_CFG_0418_REG_RG_EQ_EVEN_ERR_PAT_O_LCK Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0418_REG_RG_EQ_EVEN_ERR_PAT_O_L2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_041C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x041C)
    #define HD21PHY_EQ_FIFO_CFG_041C_REG_RG_EQ_ODD_ERR_PAT_O_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_041C_REG_RG_EQ_ODD_ERR_PAT_O_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_041C_REG_RG_EQ_ODD_ERR_PAT_O_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_041C_REG_RG_EQ_ODD_ERR_PAT_O_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0420 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0420)
    #define HD21PHY_EQ_FIFO_CFG_0420_REG_RO_LEQ_OS_L0 Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0420_REG_RG_EQ_EVEN_ERR_CNT_O_L0L Fld(20,0,AC_MSKDW)//[19:0]
#define HD21PHY_EQ_FIFO_CFG_0424 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0424)
    #define HD21PHY_EQ_FIFO_CFG_0424_REG_RO_LEQ_OS_L1 Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0424_REG_RG_EQ_EVEN_ERR_CNT_O_L1L Fld(20,0,AC_MSKDW)//[19:0]
#define HD21PHY_EQ_FIFO_CFG_0428 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0428)
    #define HD21PHY_EQ_FIFO_CFG_0428_REG_RO_LEQ_OS_L2 Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0428_REG_RG_EQ_EVEN_ERR_CNT_O_L2L Fld(20,0,AC_MSKDW)//[19:0]
#define HD21PHY_EQ_FIFO_CFG_042C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x042C)
    #define HD21PHY_EQ_FIFO_CFG_042C_REG_RO_LEQ_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_042C_REG_RG_EQ_EVEN_ERR_CNT_O_LCKL Fld(20,0,AC_MSKDW)//[19:0]
#define HD21PHY_EQ_FIFO_CFG_0430 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0430)
    #define HD21PHY_EQ_FIFO_CFG_0430_REG_RO_PIEDBG_CAL_DATA_L0 Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0430_REG_RG_EQ_ODD_ERR_CNT_O_L0L Fld(20,0,AC_MSKDW)//[19:0]
#define HD21PHY_EQ_FIFO_CFG_0434 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0434)
    #define HD21PHY_EQ_FIFO_CFG_0434_REG_RO_PIEDBG_CAL_DATA_L1 Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0434_REG_RG_EQ_ODD_ERR_CNT_O_L1L Fld(20,0,AC_MSKDW)//[19:0]
#define HD21PHY_EQ_FIFO_CFG_0438 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0438)
    #define HD21PHY_EQ_FIFO_CFG_0438_REG_RO_PIEDBG_CAL_DATA_L2 Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0438_REG_RG_EQ_ODD_ERR_CNT_O_L2L Fld(20,0,AC_MSKDW)//[19:0]
#define HD21PHY_EQ_FIFO_CFG_043C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x043C)
    #define HD21PHY_EQ_FIFO_CFG_043C_REG_RO_PIEDBG_CAL_DATA_LCK Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_043C_REG_RG_EQ_ODD_ERR_CNT_O_LCKL Fld(20,0,AC_MSKDW)//[19:0]
#define HD21PHY_EQ_FIFO_CFG_0440 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0440)
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_RG_ATT_BOT_LIM Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_RG_ATT_TOP_LIM Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_RG_ATT_INIT_VAL Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_RG_ATT_GAIN Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_DFE_RST_B Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_DFE_TAP_EN_N1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_DAC_OS_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_LEQ_AVG_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_LEQ_LEAK_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_LEQ_INIT_SET Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_LEQ_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_LEQ_RST_B Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_VGA_INIT_SET Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_VGA_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_VGA_RST_B Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_ATT_AVG_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_ATT_INIT_SET Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_ATT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_ATT_RST_B Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0440_REG_RETIME_RST_B Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0444 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0444)
    #define HD21PHY_EQ_FIFO_CFG_0444_REG_RG_ATT_AVG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_0444_REG_RG_DFE_TAP_REF Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0448 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0448)
    #define HD21PHY_EQ_FIFO_CFG_0448_REG_RG_VGA_BOT_LIM Fld(6,24,AC_MSKB3)//[29:24]
    #define HD21PHY_EQ_FIFO_CFG_0448_REG_RG_VGA_TOP_LIM Fld(6,16,AC_MSKB2)//[21:16]
    #define HD21PHY_EQ_FIFO_CFG_0448_REG_RG_VGA_INIT_VAL Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21PHY_EQ_FIFO_CFG_0448_REG_RG_VGA_GAIN Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_044C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x044C)
    #define HD21PHY_EQ_FIFO_CFG_044C_REG_RG_LEQ_LEAK_TARGET Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_044C_REG_RG_LEQ_LEAK_GAIN Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_PF_CTRL Fld(4,20,AC_MSKB2)//[23:20]
	    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_PF_CTRL3 Fld(1,23,AC_MSKB2)//[23:23]
	    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_PF_CTRL2 Fld(1,22,AC_MSKB2)//[22:22]
	    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_PF_CTRL1 Fld(1,21,AC_MSKB2)//[21:21]
	    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_PF_CTRL0 Fld(1,20,AC_MSKB2)//[20:20]    
    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_LEN_CTRL Fld(4,16,AC_MSKB2)//[19:16]
	    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_LEN_CTRL3 Fld(1,19,AC_MSKB2)//[19:19]
	    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_LEN_CTRL2 Fld(1,18,AC_MSKB2)//[18:18]
	    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_LEN_CTRL1 Fld(1,17,AC_MSKB2)//[17:17]
	    #define HD21PHY_EQ_FIFO_CFG_044C_REG_LEQ_LEN_CTRL0 Fld(1,16,AC_MSKB2)//[16:16]    
    #define HD21PHY_EQ_FIFO_CFG_044C_REG_RG_LEQ_BOT_LIM Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_044C_REG_RG_LEQ_TOP_LIM Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_044C_REG_RG_LEQ_INIT_VAL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_044C_REG_RG_LEQ_GAIN Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_0450 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0450)
    #define HD21PHY_EQ_FIFO_CFG_0450_REG_DFE_TAP_EN Fld(6,8,AC_MSKB1)//[13:8]
		#define HD21PHY_EQ_FIFO_CFG_0450_REG_DFE_TAP_EN_5 Fld(1,13,AC_MSKB1)//[13:13]
		#define HD21PHY_EQ_FIFO_CFG_0450_REG_DFE_TAP_EN_4 Fld(1,12,AC_MSKB1)//[12:12]
		#define HD21PHY_EQ_FIFO_CFG_0450_REG_DFE_TAP_EN_3 Fld(1,11,AC_MSKB1)//[11:11]
		#define HD21PHY_EQ_FIFO_CFG_0450_REG_DFE_TAP_EN_2 Fld(1,10,AC_MSKB1)//[10:10]
		#define HD21PHY_EQ_FIFO_CFG_0450_REG_DFE_TAP_EN_1 Fld(1,9,AC_MSKB1)//[9:9]
		#define HD21PHY_EQ_FIFO_CFG_0450_REG_DFE_TAP_EN_0 Fld(1,8,AC_MSKB1)//[8:8]	
    #define HD21PHY_EQ_FIFO_CFG_0450_REG_RG_LEQ_AVG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_0454 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0454)
    #define HD21PHY_EQ_FIFO_CFG_0454_REG_RG_DFE_GAIN_TAP5 Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_0454_REG_RG_DFE_GAIN_TAP4 Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_0454_REG_RG_DFE_GAIN_TAP3 Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_0454_REG_RG_DFE_GAIN_TAP2 Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_0454_REG_RG_DFE_GAIN_TAP1 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_0454_REG_RG_DFE_GAIN_TAP0 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_0454_REG_RG_DFE_GAIN_TAPN1 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_0458 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0458)
    #define HD21PHY_EQ_FIFO_CFG_0458_REG_RG_DFE_TOP_LIM_TAP1 Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0458_REG_RG_DFE_TOP_LIM_TAP0 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0458_REG_RG_DFE_TOP_LIM_TAPN1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0458_REG_RG_DFE_INIT_VAL Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_045C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x045C)
    #define HD21PHY_EQ_FIFO_CFG_045C_REG_RG_DFE_BOT_LIM_TAP0 Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_045C_REG_RG_DFE_BOT_LIM_TAPN1 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_045C_REG_RG_DFE_TOP_LIM_TAP3TN Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_045C_REG_RG_DFE_TOP_LIM_TAP2 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_0460 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0460)
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_RG_DFE_ALG_SEL Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_DFE_TAPN1_LOGIC_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_RG_DFE_DLEV1_LOGIC_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_RG_DFE_DLEV0_LOGIC_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_RG_DFE_DAC_LOAD_INIT Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_DFE_INIT_SET Fld(6,20,AC_MSKW32)//[25:20]
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_DFE_INIT_SET_N1 Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_RG_DFE_BOT_LIM_TAP3TN Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_RG_DFE_BOT_LIM_TAP2 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_0460_REG_RG_DFE_BOT_LIM_TAP1 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0464 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0464)
    #define HD21PHY_EQ_FIFO_CFG_0464_REG_RG_DFE_BOT_LIM_D Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0464_REG_RG_DFE_TOP_LIM_DLEV1 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0464_REG_RG_DFE_TOP_LIM_DLEV0 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0464_REG_RG_DFE_TOP_LIM_D Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0468 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0468)
    #define HD21PHY_EQ_FIFO_CFG_0468_REG_RG_XDBG_GAIN Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_0468_REG_RG_XDBG_ALG_SEL Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0468_REG_XDBG_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0468_REG_XDBG_RST_B Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0468_REG_RG_DFE_BOT_LIM_DLEV1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0468_REG_RG_DFE_BOT_LIM_DLEV0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_046C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x046C)
    #define HD21PHY_EQ_FIFO_CFG_046C_REG_XDBG_LEN_CTRL Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_046C_REG_RG_XDBG_LOGIC_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_046C_REG_RG_XDBG_DAC_LOAD_INIT Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_046C_REG_XDBG_INIT_SET Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_046C_REG_RG_XDBG_BOT_LIM Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_046C_REG_RG_XDBG_TOP_LIM Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_046C_REG_RG_XDBG_INIT_VAL Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0470 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0470)
    #define HD21PHY_EQ_FIFO_CFG_0470_REG_RG_DFE_DLEV_LOGIC_FORCE_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0470_REG_RG_DFE_DLEV_SHIFT_B0_CYC_SEL Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_0470_REG_RG_DFE_DLEV1_SHIFT_FORCE Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0470_REG_RG_DFE_DLEV0_SHIFT_FORCE Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0470_REG_RG_DFE_DLEV_SHIFT_FORCE_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0470_REG_CYC_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0470_REG_CYC_RST_B Fld(1,20,AC_MSKB2)//[20:20]
	#define HD21PHY_EQ_FIFO_CFG_0470_REG_RG_XDBG_RATIO Fld(4,16,AC_MSKB2)//[19:16]    
    #define HD21PHY_EQ_FIFO_CFG_0470_REG_RG_XDBG_DAC_BOT_LIM_XDBG Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0470_REG_RG_XDBG_DAC_TOP_LIM_XDBG Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0474 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0474)
    #define HD21PHY_EQ_FIFO_CFG_0474_REG_RG_DFE_TAPN1_LOGIC_CYC_SEL Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_0474_REG_RG_DFE_DLEV1_LOGIC_INIT1 Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_0474_REG_RG_DFE_DLEV1_LOGIC_INIT0 Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_0474_REG_RG_DFE_DLEV0_LOGIC_INIT1 Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_0474_REG_RG_DFE_DLEV0_LOGIC_INIT0 Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_0474_REG_RG_DFE_DLEV_LOGIC_CYC_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_0474_REG_RG_DFE_DLEV1_LOGIC_FORCE Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_0474_REG_RG_DFE_DLEV0_LOGIC_FORCE Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_0478 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0478)
    #define HD21PHY_EQ_FIFO_CFG_0478_REG_RG_XDBG0_LOGIC_INIT Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0478_REG_RG_XDBG_LOGIC_FORCE Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_0478_REG_RG_XDBG_LOGIC_CYC_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_0478_REG_RG_XDBG_LOGIC_FORCE_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0478_REG_RG_XDBG_SHIFT_B0_CYC_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_0478_REG_RG_XDBG_SHIFT_FORCE Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_0478_REG_RG_XDBG_SHIFT_FORCE_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0478_REG_RG_SW_EQ_DFE_DLEV_INIT_LOGIC_CYC_SEL Fld(4,0,AC_MSKB0)//[3:0]
    #define HD21PHY_EQ_FIFO_CFG_0478_REG_RG_SW_EQ_DFE_INIT_LOGIC_SWAP Fld(1,8,AC_MSKB1)//[8:8]
#define HD21PHY_EQ_FIFO_CFG_047C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x047C)
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_RG_PI_MODE Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_RG_EQOSC_LF_SEL Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_RG_CAL_1US_SET Fld(9,16,AC_MSKW32)//[24:16]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_RG_SIM_FAST_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_PICAL_RST_B Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_EQOSC_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_EQOSC_RST_B Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_RG_SAOSC_LF_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_SAOSC_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_SAOSC_RST_B Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_047C_REG_RG_XDBG1_LOGIC_INIT Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0480 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0480)
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_PIEDBG_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_EDBG_RST_B Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_FORCE_PIEDBG_4TH_DONE Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_FORCE_PIEDBG_3RD_DONE Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_FORCE_PIEDBG_2ND_DONE Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_FORCE_PIEDBG_1ST_DONE Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_FORCE_PIEDBG_CALEN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_PIEDBG_TIME_SEL Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_PIEDBG_INI_TIME_SEL Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_PIEDBG_KPGAIN2 Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_PIEDBG_KPGAIN1 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_0480_REG_RG_PIEDBG_CDRLPI Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0484 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0484)
    #define HD21PHY_EQ_FIFO_CFG_0484_REG_RG_EQ_EDBG_MON_SEL Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0484_REG_RG_EQ_CNT_GATING Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0484_REG_RG_EQ_EDBG_CNT_EN Fld(1,20,AC_MSKB2)//[20:20]
    	#define HD21PHY_EQ_FIFO_CFG_0484_REG_RG_EQ_EDBG_CNT_TARGET Fld(20,0,AC_MSKDW)//[19:0]
    #define HD21PHY_EQ_FIFO_CFG_0484_REG_RG_EQ_EDBG_CNT_TARGET_H Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_0484_REG_RG_EQ_EDBG_CNT_TARGET_L Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_0488 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0488)
    #define HD21PHY_EQ_FIFO_CFG_0488_REG_RG_EQ_EDBG_Y Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0488_REG_RG_EQ_EDBG_X Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_0488_REG_RG_EQ_TARGET_PAT Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0488_REG_RG_EQ_PAT_MASK Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0490 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0490)
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_LEQ_PF_CTRL_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_LEQ_LEN_CTRL_OV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_DFE_RST_B_OV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_DFE_TAP_EN_N1_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_DAC_OS_EN_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_LEQ_AVG_EN_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_LEQ_LEAK_EN_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_LEQ_EN_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_LEQ_RST_B_OV_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_VGA_EN_OV_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_VGA_RST_B_OV_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_ATT_EN_OV_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_ATT_RST_B_OV_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_0490_REG_RETIME_RST_B_OV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0498 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0498)
    #define HD21PHY_EQ_FIFO_CFG_0498_REG_CYC_EN_OV_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0498_REG_CYC_RST_B_OV_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0498_REG_XDBG_EN_OV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_0498_REG_XDBG_RST_B_OV_EN Fld(1,3,AC_MSKB0)//[3:3]
#define HD21PHY_EQ_FIFO_CFG_049C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x049C)
    #define HD21PHY_EQ_FIFO_CFG_049C_REG_PIEDBG_EN_OV_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_049C_REG_EDBG_RST_B_OV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_049C_REG_PICAL_RST_B_OV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_049C_REG_EQOSC_EN_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_049C_REG_EQOSC_RST_B_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_049C_REG_SAOSC_EN_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_049C_REG_SAOSC_RST_B_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
#define HD21PHY_EQ_FIFO_CFG_04A0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04A0)
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP5_EN_OUT_INT_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP4_EN_OUT_INT_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP3_EN_OUT_INT_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP2_EN_OUT_INT_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP1_EN_OUT_INT_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP0_EN_OUT_INT_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP_EN_N1_OUT_INT_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_ATT_EN_OUT_INT_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_LEQ_EN_OUT_INT_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_VGA_EN_OUT_INT_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_XDBG_EN_OUT_INT_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP5_EN_OV_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP4_EN_OV_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP3_EN_OV_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP2_EN_OV_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP1_EN_OV_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_DFE_TAP0_EN_OV_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_RX_RST_B Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_04A0_REG_RX_RST_B_OV_EN Fld(1,7,AC_MSKB0)//[7:7]
  
//Page HDMI2P1_EQ_FIFO4_5_P0_2  
#define HD21PHY_EQ_FIFO_CFG_04A4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04A4)
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_EDBG_LCK Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_EDGE_LCK Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_DLEV_LCK Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_DATA_LCK Fld(1,28,AC_MSKB3)//[28:28]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_EDBG_L2 Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_EDGE_L2 Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_DLEV_L2 Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_DATA_L2 Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_EDBG_L1 Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_EDGE_L1 Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_DLEV_L1 Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_DATA_L1 Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_EDBG_L0 Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_EDGE_L0 Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_DLEV_L0 Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_REVERSE_DATA_L0 Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_EDBG_LCK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_EDGE_LCK Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_DLEV_LCK Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_DATA_LCK Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_EDBG_L2 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_EDGE_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_DLEV_L2 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_DATA_L2 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_EDBG_L1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_EDGE_L1 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_DLEV_L1 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_DATA_L1 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_EDBG_L0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_EDGE_L0 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_DLEV_L0 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_04A4_REG_DATA_INV_DATA_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_04A8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04A8)
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_RATIO_REVERSE_LCK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_RATIO_REVERSE_L2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_RATIO_REVERSE_EDGE_LCK Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_RATIO_REVERSE_EDGE_L2 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_PRBS_REVERSE_LCK Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_PRBS_REVERSE_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_PRBS_REVERSE_L1 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_PRBS_REVERSE_L0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_RATIO_INV_EDGE_LCK Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_RATIO_INV_EDGE_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_RATIO_INV_LCK Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_RATIO_INV_L2 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_PRBS_INV_LCK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_PRBS_INV_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_PRBS_INV_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_04A8_REG_PRBS_INV_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_04AC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04AC)
    #define HD21PHY_EQ_FIFO_CFG_04AC_REG_PRBS_ERRCNT_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_04AC_REG_PRBS_CNT_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_04AC_REG_PRBS7LOCKTHR Fld(11,0,AC_MSKW10)//[10:0]
#define HD21PHY_EQ_FIFO_CFG_04B0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04B0)
    #define HD21PHY_EQ_FIFO_CFG_04B0_REG_HD21_PHY_PRBS15_ERRCNT_L0 Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_04B0_REG_HD21_PHY_PRBS7_ERRCNT_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_04B4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04B4)
    #define HD21PHY_EQ_FIFO_CFG_04B4_REG_HD21_PHY_PRBS15_ERRCNT_L1 Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_04B4_REG_HD21_PHY_PRBS7_ERRCNT_L1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_04B8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04B8)
    #define HD21PHY_EQ_FIFO_CFG_04B8_REG_HD21_PHY_PRBS15_ERRCNT_L2 Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_04B8_REG_HD21_PHY_PRBS7_ERRCNT_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_04BC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04BC)
    #define HD21PHY_EQ_FIFO_CFG_04BC_REG_HD21_PHY_PRBS15_ERRCNT_LCK Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_04BC_REG_HD21_PHY_PRBS7_ERRCNT_LCK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_04C0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04C0)
    #define HD21PHY_EQ_FIFO_CFG_04C0_REG_M_COMPARE_TIMES Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_04C0_REG_CAL_PERIOD Fld(12,0,AC_MSKW10)//[11:0]
    #define HD21PHY_EQ_FIFO_CFG_04C0_REG_RATIO_DETECT_FORCE_ENABLE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_04C0_REG_M_MSTAR_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_04C0_REG_RATIO_DETECT_RESET Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_04C0_REG_RATIO_DETECT_ENABLE Fld(1,12,AC_MSKB1)//[12:12]
#define HD21PHY_EQ_FIFO_CFG_04C4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04C4)
    #define HD21PHY_EQ_FIFO_CFG_04C4_REG_M_MIN_VALUE Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_04C4_REG_21_20_RATIO Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_04C4_REG_20_14_RATIO Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_04C4_REG_DA_HDMI_CH_LEQ_G_RATIO_20 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_04C4_REG_DA_HDMI_CH_LEQ_G_RATIO_21 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_04C8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04C8)
    #define HD21PHY_EQ_FIFO_CFG_04C8_REG_06G_THR Fld(6,24,AC_MSKB3)//[29:24]
    #define HD21PHY_EQ_FIFO_CFG_04C8_REG_08G_THR Fld(6,16,AC_MSKB2)//[21:16]
    #define HD21PHY_EQ_FIFO_CFG_04C8_REG_10G_THR Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21PHY_EQ_FIFO_CFG_04C8_REG_12G_THR Fld(6,0,AC_MSKB0)//[5:0]
#define HD21PHY_EQ_FIFO_CFG_04CC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04CC)
    #define HD21PHY_EQ_FIFO_CFG_04CC_REG_MSTAR_COMPARE_TIMES Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_04CC_REG_TIME_OUT_THR Fld(12,0,AC_MSKW10)//[11:0]
#define HD21PHY_EQ_FIFO_CFG_04D0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04D0)
    #define HD21PHY_EQ_FIFO_CFG_04D0_REG_MIN_COUNT_LATCH Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_04D0_REG_MAX_COUNT_LATCH Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21PHY_EQ_FIFO_CFG_04D0_REG_TURN_OFF_LANE3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_04D0_REG_RATIO_DETECT_BUSY Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_04D0_REG_RATIO_DETECT_DONE Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_04D0_REG_FORCE_HD20_ENABLE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_04D0_REG_FORCE_HD21_12G_ENABLE Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_04D0_REG_RATIO_DETECT_RESULT Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_04D4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04D4)
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_XDBG_INT_MODE Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_XDBG_INT_ACK Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_XDBG_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_VGA_INT_MODE Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_VGA_INT_ACK Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_VGA_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_LEQ_INT_MODE Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_LEQ_INT_ACK Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_LEQ_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_TAPN1_INT_MODE Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_TAPN1_INT_ACK Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_TAP1_INT_MODE Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_TAP1_INT_ACK Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_TAP0_INT_MODE Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_TAP0_INT_ACK Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_INT_MODE Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_INT_ACK Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_ATT_INT_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_ATT_INT_ACK Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_ATT_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_TAP_EN_N1 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_04D4_REG_RG_DFE_TAP_EN Fld(6,0,AC_MSKB0)//[5:0]
#define HD21PHY_EQ_FIFO_CFG_04D8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04D8)
    #define HD21PHY_EQ_FIFO_CFG_04D8_REG_NO_INPUT_DET Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_04D8_REG_LATCH_CLK_INV Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_04D8_REG_L3_MAX_TRAN_CNT Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21PHY_EQ_FIFO_CFG_04D8_REG_ENABLE_SYNC_COUNT Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_04D8_REG_SYNC_GPO_COUNT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_04D8_REG_C_DATA_SYNC_AUTO Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_04D8_REG_DATA_RESERVD_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_04D8_REG_DATA_PN_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_04DC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04DC)
    #define HD21PHY_EQ_FIFO_CFG_04DC_REG_RG_EQ_FEOS_INIT Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_04DC_REG_RG_EQ_FEOS_CNT_BOT_LIM Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_04DC_REG_RG_EQ_FEOS_CNT_TOP_LIM Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_04DC_REG_RG_EQ_FEOS_GAIN Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_04E0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04E0)
    #define HD21PHY_EQ_FIFO_CFG_04E0_REG_GPO_STATE_LCK Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_04E0_REG_GPO_STATE_L2 Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_04E0_REG_GPO_STATE_L1 Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_04E0_REG_GPO_STATE_L0 Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_04E0_REG_LOWER_RANGE Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_04E0_REG_UPPER_RANGE Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_04E4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04E4)
    #define HD21PHY_EQ_FIFO_CFG_04E4_REG_PMAD_RXCALIB_SW_RST Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_04E4_REG_RG_CAL_CYC_TIME Fld(2,12,AC_MSKB1)//[13:12]
    #define HD21PHY_EQ_FIFO_CFG_04E4_REG_RG_CAL_OUT_OS Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_04E4_REG_RG_CAL_OS_PULSE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_04E4_REG_RG_CAL_CYC Fld(2,2,AC_MSKB0)//[3:2]
    #define HD21PHY_EQ_FIFO_CFG_04E4_REG_RG_CAL_STB Fld(2,0,AC_MSKB0)//[1:0]
#define HD21PHY_EQ_FIFO_CFG_04E8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04E8)
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP5_EN_OUT_L1 Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP4_EN_OUT_L1 Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP3_EN_OUT_L1 Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP2_EN_OUT_L1 Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP1_EN_OUT_L1 Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP0_EN_OUT_L1 Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP_EN_N1_OUT_L1 Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_ATT_EN_OUT_L1 Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_LEQ_EN_OUT_L1 Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_VGA_EN_OUT_L1 Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_XDBG_EN_OUT_L1 Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP5_EN_OUT_L0 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP4_EN_OUT_L0 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP3_EN_OUT_L0 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP2_EN_OUT_L0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP1_EN_OUT_L0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP0_EN_OUT_L0 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_DFE_TAP_EN_N1_OUT_L0 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_ATT_EN_OUT_L0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_LEQ_EN_OUT_L0 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_VGA_EN_OUT_L0 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_04E8_REG_XDBG_EN_OUT_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_04EC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04EC)
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP5_EN_OUT_LCK Fld(1,26,AC_MSKB3)//[26:26]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP4_EN_OUT_LCK Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP3_EN_OUT_LCK Fld(1,24,AC_MSKB3)//[24:24]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP2_EN_OUT_LCK Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP1_EN_OUT_LCK Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP0_EN_OUT_LCK Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP_EN_N1_OUT_LCK Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_ATT_EN_OUT_LCK Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_LEQ_EN_OUT_LCK Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_VGA_EN_OUT_LCK Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_XDBG_EN_OUT_LCK Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP5_EN_OUT_L2 Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP4_EN_OUT_L2 Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP3_EN_OUT_L2 Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP2_EN_OUT_L2 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP1_EN_OUT_L2 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP0_EN_OUT_L2 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_DFE_TAP_EN_N1_OUT_L2 Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_ATT_EN_OUT_L2 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_LEQ_EN_OUT_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_VGA_EN_OUT_L2 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_04EC_REG_XDBG_EN_OUT_L2 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_04F0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04F0)
    #define HD21PHY_EQ_FIFO_CFG_04F0_REG_RG_HDMI_CDRRST_RATIO_20 Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_04F0_REG_RG_HDMI_CDRRST_RATIO_21 Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_04F0_REG_C_IRQ_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_04F4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04F4)
    #define HD21PHY_EQ_FIFO_CFG_04F4_REG_C_IRQ_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_04F8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04F8)
    #define HD21PHY_EQ_FIFO_CFG_04F8_REG_C_IRQ_CLR Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_04FC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x04FC)
    #define HD21PHY_EQ_FIFO_CFG_04FC_REG_HD21_IRQ_STATUS Fld(16,0,AC_FULLW10)//[15:0]

   
#define HD21PHY_EQ_FIFO_CFG_0500 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0500)
    #define HD21PHY_EQ_FIFO_CFG_0500_REG_LK_REC_CLR Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0500_REG_LK_REC_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0500_REG_CLK_VALID_U Fld(13,16,AC_MSKW32)//[28:16]
    #define HD21PHY_EQ_FIFO_CFG_0500_REG_CLK_VALID_L Fld(12,4,AC_MSKW10)//[15:4]
    #define HD21PHY_EQ_FIFO_CFG_0500_REG_CLK_STABLE_OUT Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0500_REG_CLK_BIG_CHG_STS Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_0500_REG_CLK_DET_EN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0504 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0504)
    #define HD21PHY_EQ_FIFO_CFG_0504_REG_CR_LK_REC_L0 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_0508 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0508)
    #define HD21PHY_EQ_FIFO_CFG_0508_REG_HDMI2P1_10G_MID Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_0508_REG_HDMI2P1_12G_MID Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_050C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x050C)
    #define HD21PHY_EQ_FIFO_CFG_050C_REG_HDMI2P1_6G_MID Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_050C_REG_HDMI2P1_8G_MID Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_0510 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0510)
    #define HD21PHY_EQ_FIFO_CFG_0510_REG_MAINLINK_CRLOSE_THR_12G Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0510_REG_MAINLINK_CRLOCK_THR_12G Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0510_REG_HDMI2P1_3G_MID Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_0514 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0514)
    #define HD21PHY_EQ_FIFO_CFG_0514_REG_MAINLINK_CRLOSE_THR_8G Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0514_REG_MAINLINK_CRLOCK_THR_8G Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0514_REG_MAINLINK_CRLOSE_THR_10G Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0514_REG_MAINLINK_CRLOCK_THR_10G Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0518 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0518)
    #define HD21PHY_EQ_FIFO_CFG_0518_REG_MAINLINK_CRLOSE_THR_3G Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0518_REG_MAINLINK_CRLOCK_THR_3G Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0518_REG_MAINLINK_CRLOSE_THR_6G Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0518_REG_MAINLINK_CRLOCK_THR_6G Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0520 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0520)
    #define HD21PHY_EQ_FIFO_CFG_0520_REG_CLOCK_XTAL_DIVIDER_8G Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0520_REG_CLOCK_XTAL_DIVIDER_10G Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0520_REG_CLOCK_XTAL_DIVIDER_12G Fld(8,8,AC_FULLB1)//[15:8]
#define HD21PHY_EQ_FIFO_CFG_0524 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0524)
    #define HD21PHY_EQ_FIFO_CFG_0524_REG_CLOCK_XTAL_DIVIDER_1P4 Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0524_REG_CLOCK_XTAL_DIVIDER_2P0 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0524_REG_CLOCK_XTAL_DIVIDER_3G Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0524_REG_CLOCK_XTAL_DIVIDER_6G Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0528 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0528)
    #define HD21PHY_EQ_FIFO_CFG_0528_REG_CR_LOCK_TH Fld(5,20,AC_MSKW32)//[24:20]
    #define HD21PHY_EQ_FIFO_CFG_0528_REG_ENABLE_RESET_AUTO_EQ_RESET_CLK Fld(1,18,AC_MSKB2)//[18:18]
    #define HD21PHY_EQ_FIFO_CFG_0528_REG_BYPASS_BIG_CHG Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0528_REG_DIG_LOCK_MODE Fld(1,16,AC_MSKB2)//[16:16]
    #define HD21PHY_EQ_FIFO_CFG_0528_REG_CR_DONE_CNT_HOLD_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_052C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x052C)
    #define HD21PHY_EQ_FIFO_CFG_052C_REG_DATA_SEL Fld(1,20,AC_MSKB2)//[20:20]
    #define HD21PHY_EQ_FIFO_CFG_052C_REG_MIDDLE_THR_NEW_MODE Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_052C_REG_MIDDLE_THR_SEL Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_052C_REG_FREQ_DET_STATUS Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_052C_REG_CLK_INVALID Fld(2,8,AC_MSKB1)//[9:8]
    #define HD21PHY_EQ_FIFO_CFG_052C_REG_FB_CLK_DET_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_052C_REG_H14_600M_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_052C_REG_CR_UNLOCK_TH Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_053C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x053C)
    #define HD21PHY_EQ_FIFO_CFG_053C_REG_RO_LNCK_GLOBAL_PMD_SIGNAL_DETECT Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_053C_REG_RO_LN2_GLOBAL_PMD_SIGNAL_DETECT Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_EQ_FIFO_CFG_053C_REG_LNCK_PHY_LOS Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_053C_REG_LN2_PHY_LOS Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_053C_REG_AD_HDMI_CKDTO Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_053C_REG_AD_HDMI_SDTO Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0540 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0540)
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_EN0_LCK Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_EN0_L2 Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_DIR0_LCK Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_DIR0_L2 Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_OUT0_LCK Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_OUT0_L2 Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_EN0_L1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_DIR0_L1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_OUT0_L1 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_EN0_L0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_DIR0_L0 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0540_REG_RO_CAL_OUT0_L0 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_0544 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0544)
    #define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP1_0_LCK Fld(4,28,AC_MSKB3)//[31:28]
    	#define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP1_0_LCK_DONE Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP1_0_L2 Fld(4,24,AC_MSKB3)//[27:24]
    	#define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP1_0_L2_DONE Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP1_0_L1 Fld(4,20,AC_MSKB2)//[23:20]
    	#define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP1_0_L1_DONE Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP1_0_L0 Fld(4,16,AC_MSKB2)//[19:16]
    	#define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP1_0_L0_DONE Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP0_0_LCK Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP0_0_L2 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP0_0_L1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_0544_REG_DBG_RXCAL_GRP0_0_L0 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_0548 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0548)
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_EN1_LCK Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_DIR1_LCK Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_OUT1_LCK Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_EN1_L2 Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_DIR1_L2 Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_OUT1_L2 Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_EN1_L1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_DIR1_L1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_OUT1_L1 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_EN1_L0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_DIR1_L0 Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_EQ_FIFO_CFG_0548_REG_RO_CAL_OUT1_L0 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_054C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x054C)
    #define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP1_1_LCK Fld(4,28,AC_MSKB3)//[31:28]
    	#define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP1_1_LCK_DONE Fld(1,29,AC_MSKB3)//[29:29]
    #define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP1_1_L2 Fld(4,24,AC_MSKB3)//[27:24]
    	#define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP1_1_L2_DONE Fld(1,25,AC_MSKB3)//[25:25]
    #define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP1_1_L1 Fld(4,20,AC_MSKB2)//[23:20]
    	#define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP1_1_L1_DONE Fld(1,21,AC_MSKB2)//[21:21]
    #define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP1_1_L0 Fld(4,16,AC_MSKB2)//[19:16]
    	#define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP1_1_L0_DONE Fld(1,17,AC_MSKB2)//[17:17]
    #define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP0_1_LCK Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP0_1_L2 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP0_1_L1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_054C_REG_DBG_RXCAL_GRP0_1_L0 Fld(4,0,AC_MSKB0)//[3:0]
  
//Page HDMI2P1_EQ_FIFO4_5_P0_3  
#define HD21PHY_EQ_FIFO_CFG_0550 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0550)
    #define HD21PHY_EQ_FIFO_CFG_0550_REG_DBG_XDBGD_CTRL_LCK Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0550_REG_DBG_XDBGD_CTRL_L2 Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_0550_REG_DBG_XDBGD_CTRL_L1 Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_0550_REG_DBG_XDBGD_CTRL_L0 Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0554 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0554)
    #define HD21PHY_EQ_FIFO_CFG_0554_REG_RO_XDBGD_CTRL_LCK Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0554_REG_RO_XDBGD_CTRL_L2 Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_0554_REG_RO_XDBGD_CTRL_L1 Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_0554_REG_RO_XDBGD_CTRL_L0 Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0558 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0558)
    #define HD21PHY_EQ_FIFO_CFG_0558_REG_RO_PIEDGE_CAL_DATA_LCK Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0558_REG_RO_PIEDGE_CAL_DATA_L2 Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_0558_REG_RO_PIEDGE_CAL_DATA_L1 Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_0558_REG_RO_PIEDGE_CAL_DATA_L0 Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_055C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x055C)
    #define HD21PHY_EQ_FIFO_CFG_055C_REG_DBG_ATT_CTRL_LCK Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_055C_REG_DBG_ATT_CTRL_L2 Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_055C_REG_DBG_ATT_CTRL_L1 Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_055C_REG_DBG_ATT_CTRL_L0 Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_055C_REG_RO_PI_MODE_LCK Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_055C_REG_RO_PI_MODE_L2 Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_EQ_FIFO_CFG_055C_REG_RO_PI_MODE_L1 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_EQ_FIFO_CFG_055C_REG_RO_PI_MODE_L0 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_EQ_FIFO_CFG_0560 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0560)
    #define HD21PHY_EQ_FIFO_CFG_0560_REG_DBG_CYC_OUT_L1 Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_0560_REG_DBG_CYC_OUT_L0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_0564 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0564)
    #define HD21PHY_EQ_FIFO_CFG_0564_REG_DBG_CYC_OUT_LCK Fld(16,16,AC_FULLW32)//[31:16]
    #define HD21PHY_EQ_FIFO_CFG_0564_REG_DBG_CYC_OUT_L2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_EQ_FIFO_CFG_0568 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0568)
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV1_SHIFT_SEL_LCK Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV1_SHIFT_SEL_L2 Fld(1,27,AC_MSKB3)//[27:27]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV1_SHIFT_SEL_L1 Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV1_SHIFT_SEL_L0 Fld(1,19,AC_MSKB2)//[19:19]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV0_LOGIC_SEL_LCK Fld(3,28,AC_MSKB3)//[30:28]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV0_LOGIC_SEL_L2 Fld(3,24,AC_MSKB3)//[26:24]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV0_LOGIC_SEL_L1 Fld(3,20,AC_MSKB2)//[22:20]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV0_LOGIC_SEL_L0 Fld(3,16,AC_MSKB2)//[18:16]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV0_SHIFT_SEL_LCK Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV0_SHIFT_SEL_L2 Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV0_SHIFT_SEL_L1 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV0_SHIFT_SEL_L0 Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV1_LOGIC_SEL_LCK Fld(3,12,AC_MSKB1)//[14:12]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV1_LOGIC_SEL_L2 Fld(3,8,AC_MSKB1)//[10:8]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV1_LOGIC_SEL_L1 Fld(3,4,AC_MSKB0)//[6:4]
    #define HD21PHY_EQ_FIFO_CFG_0568_REG_DBG_DFE_DLEV1_LOGIC_SEL_L0 Fld(3,0,AC_MSKB0)//[2:0]
#define HD21PHY_EQ_FIFO_CFG_056C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x056C)
    #define HD21PHY_EQ_FIFO_CFG_056C_REG_DBG_DFE_TAP0_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_056C_REG_DBG_DFE_TAP0_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_056C_REG_DBG_DFE_TAP0_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_056C_REG_DBG_DFE_TAP0_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0570 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0570)
    #define HD21PHY_EQ_FIFO_CFG_0570_REG_DBG_DFE_TAP1_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0570_REG_DBG_DFE_TAP1_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0570_REG_DBG_DFE_TAP1_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0570_REG_DBG_DFE_TAP1_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0574 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0574)
    #define HD21PHY_EQ_FIFO_CFG_0574_REG_DBG_DFE_TAP1_NORMALIZED_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0574_REG_DBG_DFE_TAP1_NORMALIZED_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0574_REG_DBG_DFE_TAP1_NORMALIZED_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0574_REG_DBG_DFE_TAP1_NORMALIZED_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0578 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0578)
    #define HD21PHY_EQ_FIFO_CFG_0578_REG_DBG_DFE_TAP2_LCK Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_0578_REG_DBG_DFE_TAP2_L2 Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_0578_REG_DBG_DFE_TAP2_L1 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_0578_REG_DBG_DFE_TAP2_L0 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_057C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x057C)
    #define HD21PHY_EQ_FIFO_CFG_057C_REG_DBG_DFE_TAP4_LCK Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_057C_REG_DBG_DFE_TAP4_L2 Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_057C_REG_DBG_DFE_TAP4_L1 Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_057C_REG_DBG_DFE_TAP4_L0 Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_057C_REG_DBG_DFE_TAP3_LCK Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_057C_REG_DBG_DFE_TAP3_L2 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_057C_REG_DBG_DFE_TAP3_L1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_057C_REG_DBG_DFE_TAP3_L0 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_0580 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0580)
    #define HD21PHY_EQ_FIFO_CFG_0580_REG_DBG_LEQ_CTRL_LCK Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_0580_REG_DBG_LEQ_CTRL_L2 Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_0580_REG_DBG_LEQ_CTRL_L1 Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_0580_REG_DBG_LEQ_CTRL_L0 Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_0580_REG_DBG_DFE_TAP5_LCK Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_0580_REG_DBG_DFE_TAP5_L2 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_0580_REG_DBG_DFE_TAP5_L1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_0580_REG_DBG_DFE_TAP5_L0 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_0584 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0584)
    #define HD21PHY_EQ_FIFO_CFG_0584_REG_DBG_DFE_TAPN1_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0584_REG_DBG_DFE_TAPN1_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0584_REG_DBG_DFE_TAPN1_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0584_REG_DBG_DFE_TAPN1_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0588 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0588)
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_RO_DFE_DLEV1_SHIFT_SEL_LCK Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_RO_DFE_DLEV0_SHIFT_SEL_LCK Fld(1,30,AC_MSKB3)//[30:30]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_DBG_VGA_CTRL_BIN_LCK Fld(6,24,AC_MSKB3)//[29:24]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_RO_DFE_DLEV1_SHIFT_SEL_L2 Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_RO_DFE_DLEV0_SHIFT_SEL_L2 Fld(1,22,AC_MSKB2)//[22:22]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_DBG_VGA_CTRL_BIN_L2 Fld(6,16,AC_MSKB2)//[21:16]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_RO_DFE_DLEV1_SHIFT_SEL_L1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_RO_DFE_DLEV0_SHIFT_SEL_L1 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_DBG_VGA_CTRL_BIN_L1 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_RO_DFE_DLEV1_SHIFT_SEL_L0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_RO_DFE_DLEV0_SHIFT_SEL_L0 Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_EQ_FIFO_CFG_0588_REG_DBG_VGA_CTRL_BIN_L0 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21PHY_EQ_FIFO_CFG_058C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x058C)
    #define HD21PHY_EQ_FIFO_CFG_058C_REG_RO_XDBG_SHIFT_SEL_LCK Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_058C_REG_RO_XDBG_SHIFT_SEL_L2 Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_058C_REG_DBG_XDBG_CTRL_LCK Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_058C_REG_DBG_XDBG_CTRL_L2 Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_058C_REG_RO_XDBG_SHIFT_SEL_L1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_058C_REG_DBG_XDBG_CTRL_L1 Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_058C_REG_RO_XDBG_SHIFT_SEL_L0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_058C_REG_DBG_XDBG_CTRL_L0 Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0590 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0590)
    #define HD21PHY_EQ_FIFO_CFG_0590_REG_DBG_XDBG_DAC_XDBG_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0590_REG_DBG_XDBG_DAC_XDBG_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0590_REG_DBG_XDBG_DAC_XDBG_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0590_REG_DBG_XDBG_DAC_XDBG_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_0594 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0594)
    #define HD21PHY_EQ_FIFO_CFG_0594_REG_DBG_XDBG_SHIFT_SEL_LCK Fld(1,31,AC_MSKB3)//[31:31]
    #define HD21PHY_EQ_FIFO_CFG_0594_REG_DBG_XDBG_SHIFT_SEL_L2 Fld(1,23,AC_MSKB2)//[23:23]
    #define HD21PHY_EQ_FIFO_CFG_0594_REG_DBG_XDBG_LOGIC_SEL_LCK Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_0594_REG_DBG_XDBG_LOGIC_SEL_L2 Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_0594_REG_DBG_XDBG_SHIFT_SEL_L1 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_EQ_FIFO_CFG_0594_REG_DBG_XDBG_LOGIC_SEL_L1 Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_0594_REG_DBG_XDBG_SHIFT_SEL_L0 Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_EQ_FIFO_CFG_0594_REG_DBG_XDBG_LOGIC_SEL_L0 Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_0598 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x0598)
    #define HD21PHY_EQ_FIFO_CFG_0598_REG_RO_D0H_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_0598_REG_RO_D0H_OS_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_0598_REG_RO_D0H_OS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_0598_REG_RO_D0H_OS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_059C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x059C)
    #define HD21PHY_EQ_FIFO_CFG_059C_REG_RO_D0L_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_059C_REG_RO_D0L_OS_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_059C_REG_RO_D0L_OS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_059C_REG_RO_D0L_OS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05A0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05A0)
    #define HD21PHY_EQ_FIFO_CFG_05A0_REG_RO_D1H_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05A0_REG_RO_D1H_OS_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05A0_REG_RO_D1H_OS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05A0_REG_RO_D1H_OS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05A4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05A4)
    #define HD21PHY_EQ_FIFO_CFG_05A4_REG_RO_D1L_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05A4_REG_RO_D1L_OS_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05A4_REG_RO_D1L_OS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05A4_REG_RO_D1L_OS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05A8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05A8)
    #define HD21PHY_EQ_FIFO_CFG_05A8_REG_RO_DFE_DAC_D0H_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05A8_REG_RO_DFE_DAC_D0H_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05A8_REG_RO_DFE_DAC_D0H_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05A8_REG_RO_DFE_DAC_D0H_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05AC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05AC)
    #define HD21PHY_EQ_FIFO_CFG_05AC_REG_RO_DFE_DAC_D0L_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05AC_REG_RO_DFE_DAC_D0L_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05AC_REG_RO_DFE_DAC_D0L_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05AC_REG_RO_DFE_DAC_D0L_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05B0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05B0)
    #define HD21PHY_EQ_FIFO_CFG_05B0_REG_RO_DFE_DAC_D1H_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05B0_REG_RO_DFE_DAC_D1H_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05B0_REG_RO_DFE_DAC_D1H_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05B0_REG_RO_DFE_DAC_D1H_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05B4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05B4)
    #define HD21PHY_EQ_FIFO_CFG_05B4_REG_RO_DFE_DAC_D1L_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05B4_REG_RO_DFE_DAC_D1L_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05B4_REG_RO_DFE_DAC_D1L_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05B4_REG_RO_DFE_DAC_D1L_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05B8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05B8)
    #define HD21PHY_EQ_FIFO_CFG_05B8_REG_RO_DFE_DAC_DLEV0_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05B8_REG_RO_DFE_DAC_DLEV0_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05B8_REG_RO_DFE_DAC_DLEV0_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05B8_REG_RO_DFE_DAC_DLEV0_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05BC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05BC)
    #define HD21PHY_EQ_FIFO_CFG_05BC_REG_RO_DFE_DAC_DLEV1_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05BC_REG_RO_DFE_DAC_DLEV1_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05BC_REG_RO_DFE_DAC_DLEV1_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05BC_REG_RO_DFE_DAC_DLEV1_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05C0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05C0)
    #define HD21PHY_EQ_FIFO_CFG_05C0_REG_RO_VGA_CTRL_LCK Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_05C0_REG_RO_VGA_CTRL_L2 Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_05C0_REG_RO_VGA_CTRL_L1 Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_05C0_REG_RO_VGA_CTRL_L0 Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_05C0_REG_RO_ATT_CTRL_LCK Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_05C0_REG_RO_ATT_CTRL_L2 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_05C0_REG_RO_ATT_CTRL_L1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_05C0_REG_RO_ATT_CTRL_L0 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_05C4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05C4)
    #define HD21PHY_EQ_FIFO_CFG_05C4_REG_RO_DFE_TAP0_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05C4_REG_RO_DFE_TAP0_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05C4_REG_RO_DFE_TAP0_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05C4_REG_RO_DFE_TAP0_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05C8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05C8)
    #define HD21PHY_EQ_FIFO_CFG_05C8_REG_RO_DFE_TAP1_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05C8_REG_RO_DFE_TAP1_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05C8_REG_RO_DFE_TAP1_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05C8_REG_RO_DFE_TAP1_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05CC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05CC)
    #define HD21PHY_EQ_FIFO_CFG_05CC_REG_RO_DFE_TAP2_LCK Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_05CC_REG_RO_DFE_TAP2_L2 Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_05CC_REG_RO_DFE_TAP2_L1 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_05CC_REG_RO_DFE_TAP2_L0 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_05D0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05D0)
    #define HD21PHY_EQ_FIFO_CFG_05D0_REG_RO_DFE_TAP4_LCK Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_05D0_REG_RO_DFE_TAP4_L2 Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_05D0_REG_RO_DFE_TAP4_L1 Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_05D0_REG_RO_DFE_TAP4_L0 Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_05D0_REG_RO_DFE_TAP3_LCK Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_05D0_REG_RO_DFE_TAP3_L2 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_05D0_REG_RO_DFE_TAP3_L1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_05D0_REG_RO_DFE_TAP3_L0 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_05D4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05D4)
    #define HD21PHY_EQ_FIFO_CFG_05D4_REG_RO_LEQ_CTRL_LCK Fld(4,28,AC_MSKB3)//[31:28]
    #define HD21PHY_EQ_FIFO_CFG_05D4_REG_RO_LEQ_CTRL_L2 Fld(4,24,AC_MSKB3)//[27:24]
    #define HD21PHY_EQ_FIFO_CFG_05D4_REG_RO_LEQ_CTRL_L1 Fld(4,20,AC_MSKB2)//[23:20]
    #define HD21PHY_EQ_FIFO_CFG_05D4_REG_RO_LEQ_CTRL_L0 Fld(4,16,AC_MSKB2)//[19:16]
    #define HD21PHY_EQ_FIFO_CFG_05D4_REG_RO_DFE_TAP5_LCK Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_EQ_FIFO_CFG_05D4_REG_RO_DFE_TAP5_L2 Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_EQ_FIFO_CFG_05D4_REG_RO_DFE_TAP5_L1 Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_EQ_FIFO_CFG_05D4_REG_RO_DFE_TAP5_L0 Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_EQ_FIFO_CFG_05D8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05D8)
    #define HD21PHY_EQ_FIFO_CFG_05D8_REG_RO_DFE_TAPN1_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05D8_REG_RO_DFE_TAPN1_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05D8_REG_RO_DFE_TAPN1_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05D8_REG_RO_DFE_TAPN1_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05DC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05DC)
    #define HD21PHY_EQ_FIFO_CFG_05DC_REG_RO_DLEV0_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05DC_REG_RO_DLEV0_OS_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05DC_REG_RO_DLEV0_OS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05DC_REG_RO_DLEV0_OS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05E0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05E0)
    #define HD21PHY_EQ_FIFO_CFG_05E0_REG_RO_DLEV1_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05E0_REG_RO_DLEV1_OS_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05E0_REG_RO_DLEV1_OS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05E0_REG_RO_DLEV1_OS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05E4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05E4)
    #define HD21PHY_EQ_FIFO_CFG_05E4_REG_RO_E0_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05E4_REG_RO_E0_OS_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05E4_REG_RO_E0_OS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05E4_REG_RO_E0_OS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05E8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05E8)
    #define HD21PHY_EQ_FIFO_CFG_05E8_REG_RO_E1_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05E8_REG_RO_E1_OS_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05E8_REG_RO_E1_OS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05E8_REG_RO_E1_OS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05EC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05EC)
    #define HD21PHY_EQ_FIFO_CFG_05EC_REG_RO_EDBG_OS_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05EC_REG_RO_EDBG_OS_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05EC_REG_RO_EDBG_OS_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05EC_REG_RO_EDBG_OS_L0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_EQ_FIFO_CFG_05F0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05F0)
    #define HD21PHY_EQ_FIFO_CFG_05F0_REG_RO_VGA_CTRL_BIN_LCK Fld(6,24,AC_MSKB3)//[29:24]
    #define HD21PHY_EQ_FIFO_CFG_05F0_REG_RO_VGA_CTRL_BIN_L2 Fld(6,16,AC_MSKB2)//[21:16]
    #define HD21PHY_EQ_FIFO_CFG_05F0_REG_RO_VGA_CTRL_BIN_L1 Fld(6,8,AC_MSKB1)//[13:8]
    #define HD21PHY_EQ_FIFO_CFG_05F0_REG_RO_VGA_CTRL_BIN_L0 Fld(6,0,AC_MSKB0)//[5:0]
#define HD21PHY_EQ_FIFO_CFG_05F4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05F4)
    #define HD21PHY_EQ_FIFO_CFG_05F4_REG_RO_VGA_IDAC_LCK Fld(5,24,AC_MSKB3)//[28:24]
    #define HD21PHY_EQ_FIFO_CFG_05F4_REG_RO_VGA_IDAC_L2 Fld(5,16,AC_MSKB2)//[20:16]
    #define HD21PHY_EQ_FIFO_CFG_05F4_REG_RO_VGA_IDAC_L1 Fld(5,8,AC_MSKB1)//[12:8]
    #define HD21PHY_EQ_FIFO_CFG_05F4_REG_RO_VGA_IDAC_L0 Fld(5,0,AC_MSKB0)//[4:0]
#define HD21PHY_EQ_FIFO_CFG_05F8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05F8)
    #define HD21PHY_EQ_FIFO_CFG_05F8_REG_RO_XDBG_CTRL_LCK Fld(7,24,AC_MSKB3)//[30:24]
    #define HD21PHY_EQ_FIFO_CFG_05F8_REG_RO_XDBG_CTRL_L2 Fld(7,16,AC_MSKB2)//[22:16]
    #define HD21PHY_EQ_FIFO_CFG_05F8_REG_RO_XDBG_CTRL_L1 Fld(7,8,AC_MSKB1)//[14:8]
    #define HD21PHY_EQ_FIFO_CFG_05F8_REG_RO_XDBG_CTRL_L0 Fld(7,0,AC_MSKB0)//[6:0]
#define HD21PHY_EQ_FIFO_CFG_05FC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x05FC)
    #define HD21PHY_EQ_FIFO_CFG_05FC_REG_RO_XDBG_DAC_XDBG_LCK Fld(8,24,AC_FULLB3)//[31:24]
    #define HD21PHY_EQ_FIFO_CFG_05FC_REG_RO_XDBG_DAC_XDBG_L2 Fld(8,16,AC_FULLB2)//[23:16]
    #define HD21PHY_EQ_FIFO_CFG_05FC_REG_RO_XDBG_DAC_XDBG_L1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_EQ_FIFO_CFG_05FC_REG_RO_XDBG_DAC_XDBG_L0 Fld(8,0,AC_FULLB0)//[7:0]

//Train_top	
#define HD21PHY_TRAIN_CFG_0600 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x600)
    #define HD21PHY_TRAIN_CFG_0600_REG_TESTBUS_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_0600_REG_SOFT_RST Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_0604 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x604)
    #define HD21PHY_TRAIN_CFG_0604_REG_RESET_TIMER Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_0604_REG_RETRAIN_ANY_TIME Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_0604_REG_FRL_RATE_WRITE_RETRAIN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_TRAIN_CFG_0604_REG_FRL_START_CLR_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_TRAIN_CFG_0604_REG_FRL_START_SET_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_TRAIN_CFG_0604_REG_LN3_LTP_REQ_3LANE_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_TRAIN_CFG_0604_REG_XTAL_FRQ Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_TRAIN_CFG_0608 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x608)
    #define HD21PHY_TRAIN_CFG_0608_REG_FRL_FAIL_LTP_REQ Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_0608_REG_FLT_UPDATE_MD Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_TRAIN_CFG_0608_REG_REQ_UPDATE_DELAY_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_TRAIN_CFG_0608_REG_REQ_UPDATE_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_TRAIN_CFG_0608_REG_FLT_READY Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_TRAIN_CFG_0608_REG_MAX_FFE Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_0608_REG_MAX_FRL_RATE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_060C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x60C)
    #define HD21PHY_TRAIN_CFG_060C_REG_LN3_EQ_LTP_REQ Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_060C_REG_LN2_EQ_LTP_REQ Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_060C_REG_LN1_EQ_LTP_REQ Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_060C_REG_LN0_EQ_LTP_REQ Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_0610 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x610)
    #define HD21PHY_TRAIN_CFG_0610_REG_FLT_UPDATE_AFTER_RATE_CHG Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_0610_REG_FLT_UPDATE_REQ_NEQ_REGEN Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_0610_REG_FLT_UPDATE_TWICE_REGEN Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_TRAIN_CFG_0610_REG_FLT_UPDATE_RATE_CHG_REGEN Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_TRAIN_CFG_0610_REG_FLT_UPDATE_NO_REQ_READ_REGEN Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_TRAIN_CFG_0610_REG_FLT_UPDATE_NO_UPDATE_READ_REGEN Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_TRAIN_CFG_0610_REG_DIS_FFE_TRAIN_OV Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_TRAIN_CFG_0610_REG_DIS_FFE_TRAIN_OVEN Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_TRAIN_CFG_0610_REG_CHK_SR_SSB_TIME_UP_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_TRAIN_CFG_0610_REG_REDUCE_RATE_SR_SSB_UNLOCK Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_TRAIN_CFG_0610_REG_REDUCE_RATE_DEC_UNSTABLE Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_TRAIN_CFG_0610_REG_BYPASS_CHK_SR_SSB Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_TRAIN_CFG_0610_REG_BYPASS_CHK_DEC Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_TRAIN_CFG_0610_REG_FRL_TRAIN_WAIT_ST2_ONLY_MAX_FFE Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_TRAIN_CFG_0610_REG_FRL_TRAIN_WAIT_ST2 Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_TRAIN_CFG_0610_REG_FRL_TRAIN_WAIT_ST1 Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_TRAIN_CFG_0614 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x614)
    #define HD21PHY_TRAIN_CFG_0614_REG_SPECIFIED_LN3_FFE_MD Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_0614_REG_SPECIFIED_LN2_FFE_MD Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_0614_REG_SPECIFIED_LN1_FFE_MD Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_TRAIN_CFG_0614_REG_SPECIFIED_LN0_FFE_MD Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_TRAIN_CFG_0614_REG_SPECIFIED_FRL_RATE Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_0614_REG_SPECIFIED_FRL_RATE_MD Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_TRAIN_CFG_0614_REG_LTP_34_PLL_MD Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_TRAIN_CFG_0614_REG_LTP_34_REQ_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_TRAIN_CFG_0614_REG_LTP_34_REQ_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_TRAIN_CFG_0614_REG_DONT_CARE_FRL_RATE_CHG_CLR Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_TRAIN_CFG_0614_REG_DONT_CARE_FLT_REQ_READ Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_TRAIN_CFG_0614_REG_DONT_CARE_FLT_UPDATE_READ Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_TRAIN_CFG_0618 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x618)
    #define HD21PHY_TRAIN_CFG_0618_REG_SPECIFIED_LN3_FFE Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_0618_REG_SPECIFIED_LN2_FFE Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_0618_REG_SPECIFIED_LN1_FFE Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_0618_REG_SPECIFIED_LN0_FFE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_061C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x61C)
    #define HD21PHY_TRAIN_CFG_061C_REG_REDUCE_RATE_DEC_UNSTABLE_CNT Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_061C_REG_FRL_TRAINING_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_TRAIN_CFG_061C_REG_FRL_TRAINING_OVEN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_TRAIN_CFG_0620 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x620)
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L3_OV_TRIG Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L2_OV_TRIG Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L1_OV_TRIG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L0_OV_TRIG Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L3_OVEN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L2_OVEN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L1_OVEN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L0_OVEN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L3_OV Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L2_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L1_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_TRAIN_CFG_0620_REG_RETUNE_PLL_L0_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_TRAIN_CFG_0624 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x624)
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L3_OV_TRIG Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L2_OV_TRIG Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L1_OV_TRIG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L0_OV_TRIG Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L3_OVEN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L2_OVEN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L1_OVEN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L0_OVEN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L3_OV Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L2_OV Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L1_OV Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_TRAIN_CFG_0624_REG_RETUNE_ALG_L0_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_TRAIN_CFG_0628 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x628)
    #define HD21PHY_TRAIN_CFG_0628_REG_LN3_OPT_FFE_OV_TRIG Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_0628_REG_LN2_OPT_FFE_OV_TRIG Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_0628_REG_LN1_OPT_FFE_OV_TRIG Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_TRAIN_CFG_0628_REG_LN0_OPT_FFE_OV_TRIG Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_TRAIN_CFG_0628_REG_LN3_FFE_DONE_OV_TRIG Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_TRAIN_CFG_0628_REG_LN2_FFE_DONE_OV_TRIG Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_TRAIN_CFG_0628_REG_LN1_FFE_DONE_OV_TRIG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_TRAIN_CFG_0628_REG_LN0_FFE_DONE_OV_TRIG Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_TRAIN_CFG_0628_REG_LOOP_OV_TRIG Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_TRAIN_CFG_0628_REG_LOOP_OVEN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_TRAIN_CFG_0628_REG_LOOP_OV Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_TRAIN_CFG_062C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x62C)
    #define HD21PHY_TRAIN_CFG_062C_REG_LN3_FFE_DONE_OV Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN2_FFE_DONE_OV Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN1_FFE_DONE_OV Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN0_FFE_DONE_OV Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN3_OPT_FFE_OVEN Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN2_OPT_FFE_OVEN Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN1_OPT_FFE_OVEN Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN0_OPT_FFE_OVEN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN3_FFE_DONE_OVEN Fld(1,3,AC_MSKB0)//[3:3]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN2_FFE_DONE_OVEN Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN1_FFE_DONE_OVEN Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_TRAIN_CFG_062C_REG_LN0_FFE_DONE_OVEN Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_TRAIN_CFG_0630 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x630)
    #define HD21PHY_TRAIN_CFG_0630_REG_LN3_OPT_FFE_OV Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_0630_REG_LN2_OPT_FFE_OV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_0630_REG_LN1_OPT_FFE_OV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_0630_REG_LN0_OPT_FFE_OV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_0634 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x634)
    #define HD21PHY_TRAIN_CFG_0634_REG_LN3_FFE_OV_TRIG Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_0634_REG_LN2_FFE_OV_TRIG Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_0634_REG_LN1_FFE_OV_TRIG Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_TRAIN_CFG_0634_REG_LN0_FFE_OV_TRIG Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_TRAIN_CFG_0634_REG_LN3_LTP_OV_TRIG Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_TRAIN_CFG_0634_REG_LN2_LTP_OV_TRIG Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_TRAIN_CFG_0634_REG_LN1_LTP_OV_TRIG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_TRAIN_CFG_0634_REG_LN0_LTP_OV_TRIG Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_TRAIN_CFG_0634_REG_FRL_RETRAIN_DIFFERENT_RATE Fld(1,7,AC_MSKB0)//[7:7]
    #define HD21PHY_TRAIN_CFG_0634_REG_FRL_RETRAIN_SAME_RATE Fld(1,6,AC_MSKB0)//[6:6]
    #define HD21PHY_TRAIN_CFG_0634_REG_FRL_TRAIN_FSM_ST_OV_TRIG Fld(1,5,AC_MSKB0)//[5:5]
    #define HD21PHY_TRAIN_CFG_0634_REG_FRL_TRAIN_FSM_ST_OVEN Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_TRAIN_CFG_0634_REG_FRL_TRAIN_FSM_ST_OV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_0638 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x638)
    #define HD21PHY_TRAIN_CFG_0638_REG_LN3_LTP_OV Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_0638_REG_LN2_LTP_OV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_0638_REG_LN1_LTP_OV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_0638_REG_LN0_LTP_OV Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_063C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x63C)
    #define HD21PHY_TRAIN_CFG_063C_REG_LN3_FFE_OV Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_063C_REG_LN2_FFE_OV Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_063C_REG_LN1_FFE_OV Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_063C_REG_LN0_FFE_OV Fld(4,0,AC_MSKB0)//[3:0]
		
#define HD21PHY_TRAIN_CFG_0640 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x640)
    #define HD21PHY_TRAIN_CFG_0640_REG_LTP_REQ_SW_TRIG Fld(1,11,AC_MSKB1)//[11:11]
    #define HD21PHY_TRAIN_CFG_0640_REG_FRL_START_CLR_SW_TRIG Fld(1,10,AC_MSKB1)//[10:10]
    #define HD21PHY_TRAIN_CFG_0640_REG_FRL_START_SW_TRIG Fld(1,9,AC_MSKB1)//[9:9]
    #define HD21PHY_TRAIN_CFG_0640_REG_FLT_UPDATE_SW_TRIG Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_TRAIN_CFG_0640_REG_LTP_REQ_DONT_CARE_UPDATE_CLR Fld(1,2,AC_MSKB0)//[2:2]
    #define HD21PHY_TRAIN_CFG_0640_REG_FLT_UPDATE_KEEP_HW_MD Fld(1,1,AC_MSKB0)//[1:1]
    #define HD21PHY_TRAIN_CFG_0640_REG_FRL_TRAIN_SW_MD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_TRAIN_CFG_0644 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x644)
    #define HD21PHY_TRAIN_CFG_0644_REG_LN3_LTP_REQ_SW Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_0644_REG_LN2_LTP_REQ_SW Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_0644_REG_LN1_LTP_REQ_SW Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_0644_REG_LN0_LTP_REQ_SW Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_0648 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x648)
    #define HD21PHY_TRAIN_CFG_0648_REG_LN3_LTP_REQ_SW_TRIG Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_0648_REG_LN2_LTP_REQ_SW_TRIG Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_0648_REG_LN1_LTP_REQ_SW_TRIG Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_0648_REG_LN0_LTP_REQ_SW_TRIG Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_064C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x64C)
    #define HD21PHY_TRAIN_CFG_064C_REG_RESET_FLT_UPDATE_TIMER Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_064C_REG_FLT_UPDATE_TIMER_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_064C_REG_FLT_UPDATE_TIMER Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_TRAIN_CFG_0650 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x650)
    #define HD21PHY_TRAIN_CFG_0650_REG_RESET_REQ_UPDATE_DELAY_TIMER Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_0650_REG_REQ_UPDATE_DELAY_TIMER_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_0650_REG_REQ_UPDATE_DELAY_TIMER Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_TRAIN_CFG_0654 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x654)
    #define HD21PHY_TRAIN_CFG_0654_REG_RESET_CHK_LINK_QUAL_START_TIMER Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_0654_REG_CHK_LINK_QUAL_START_TIMER_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_0654_REG_CHK_LINK_QUAL_START_TIMER Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_TRAIN_CFG_0658 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x658)
    #define HD21PHY_TRAIN_CFG_0658_REG_RESET_CHK_LINK_QUAL_END_TIMER Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_0658_REG_CHK_LINK_QUAL_END_TIMER_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_0658_REG_CHK_LINK_QUAL_END_TIMER Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_TRAIN_CFG_065C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x65C)
    #define HD21PHY_TRAIN_CFG_065C_REG_RESET_CHK_SR_SSB_TIMER Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_065C_REG_CHK_SR_SSB_TIMER_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_065C_REG_CHK_SR_SSB_TIMER Fld(10,0,AC_MSKW10)//[9:0]
#define HD21PHY_TRAIN_CFG_0660 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x660)
    #define HD21PHY_TRAIN_CFG_0660_REG_LN1_TAP_N1_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_0660_REG_LN0_TAP_N1_TH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_0664 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x664)
    #define HD21PHY_TRAIN_CFG_0664_REG_LN3_TAP_N1_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_0664_REG_LN2_TAP_N1_TH Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_0668 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x668)
    #define HD21PHY_TRAIN_CFG_0668_REG_LINK_VALID_TH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_066C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x66C)
    #define HD21PHY_TRAIN_CFG_066C_REG_LINK_ERROR_TH Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_0670 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x670)
    #define HD21PHY_TRAIN_CFG_0670_REG_LINK_ERROR_CNT_MD Fld(1,0,AC_MSKB0)//[0:0]
#define HD21PHY_TRAIN_CFG_0680 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x680)
    #define HD21PHY_TRAIN_CFG_0680_REG_ABS_TAP_N1_L0_FFE1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_0680_REG_ABS_TAP_N1_L0_FFE0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_0684 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x684)
    #define HD21PHY_TRAIN_CFG_0684_REG_ABS_TAP_N1_L0_FFE3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_0684_REG_ABS_TAP_N1_L0_FFE2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_0688 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x688)
    #define HD21PHY_TRAIN_CFG_0688_REG_ABS_TAP_N1_L1_FFE1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_0688_REG_ABS_TAP_N1_L1_FFE0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_068C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x68C)
    #define HD21PHY_TRAIN_CFG_068C_REG_ABS_TAP_N1_L1_FFE3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_068C_REG_ABS_TAP_N1_L1_FFE2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_0690 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x690)
    #define HD21PHY_TRAIN_CFG_0690_REG_ABS_TAP_N1_L2_FFE1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_0690_REG_ABS_TAP_N1_L2_FFE0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_0694 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x694)
    #define HD21PHY_TRAIN_CFG_0694_REG_ABS_TAP_N1_L2_FFE3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_0694_REG_ABS_TAP_N1_L2_FFE2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_0698 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x698)
    #define HD21PHY_TRAIN_CFG_0698_REG_ABS_TAP_N1_L3_FFE1 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_0698_REG_ABS_TAP_N1_L3_FFE0 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_069C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x69C)
    #define HD21PHY_TRAIN_CFG_069C_REG_ABS_TAP_N1_L3_FFE3 Fld(8,8,AC_FULLB1)//[15:8]
    #define HD21PHY_TRAIN_CFG_069C_REG_ABS_TAP_N1_L3_FFE2 Fld(8,0,AC_FULLB0)//[7:0]
#define HD21PHY_TRAIN_CFG_06A0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6A0)
    #define HD21PHY_TRAIN_CFG_06A0_REG_FFE_DONE_L3 Fld(1,15,AC_MSKB1)//[15:15]
    #define HD21PHY_TRAIN_CFG_06A0_REG_FFE_DONE_L2 Fld(1,14,AC_MSKB1)//[14:14]
    #define HD21PHY_TRAIN_CFG_06A0_REG_FFE_DONE_L1 Fld(1,13,AC_MSKB1)//[13:13]
    #define HD21PHY_TRAIN_CFG_06A0_REG_FFE_DONE_L0 Fld(1,12,AC_MSKB1)//[12:12]
    #define HD21PHY_TRAIN_CFG_06A0_REG_LOOP Fld(1,8,AC_MSKB1)//[8:8]
    #define HD21PHY_TRAIN_CFG_06A0_REG_NORMAL_TRAIN_DONE Fld(1,4,AC_MSKB0)//[4:4]
    #define HD21PHY_TRAIN_CFG_06A0_REG_NORMAL_TRAIN_FSM Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_06A4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6A4)
    #define HD21PHY_TRAIN_CFG_06A4_REG_LN3_OPT_FFE Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_06A4_REG_LN2_OPT_FFE Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_06A4_REG_LN1_OPT_FFE Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_06A4_REG_LN0_OPT_FFE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_06A8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6A8)
    #define HD21PHY_TRAIN_CFG_06A8_REG_LN3_LTP_REQ Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_06A8_REG_LN2_LTP_REQ Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_06A8_REG_LN1_LTP_REQ Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_06A8_REG_LN0_LTP_REQ Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_06AC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6AC)
    #define HD21PHY_TRAIN_CFG_06AC_REG_LN3_LTP_SET Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_06AC_REG_LN2_LTP_SET Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_06AC_REG_LN1_LTP_SET Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_06AC_REG_LN0_LTP_SET Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_06B0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6B0)
    #define HD21PHY_TRAIN_CFG_06B0_REG_LN3_FFE_REQ Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_06B0_REG_LN2_FFE_REQ Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_06B0_REG_LN1_FFE_REQ Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_06B0_REG_LN0_FFE_REQ Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_06B4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6B4)
    #define HD21PHY_TRAIN_CFG_06B4_REG_LN3_FFE_SET Fld(4,12,AC_MSKB1)//[15:12]
    #define HD21PHY_TRAIN_CFG_06B4_REG_LN2_FFE_SET Fld(4,8,AC_MSKB1)//[11:8]
    #define HD21PHY_TRAIN_CFG_06B4_REG_LN1_FFE_SET Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_06B4_REG_LN0_FFE_SET Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_06BC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6BC)
    #define HD21PHY_TRAIN_CFG_06BC_REG_FFE_LEVELS Fld(4,4,AC_MSKB0)//[7:4]
    #define HD21PHY_TRAIN_CFG_06BC_REG_FRL_RATE Fld(4,0,AC_MSKB0)//[3:0]
#define HD21PHY_TRAIN_CFG_06C0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6C0)
    #define HD21PHY_TRAIN_CFG_06C0_REG_LN0_VALID_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_06C4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6C4)
    #define HD21PHY_TRAIN_CFG_06C4_REG_LN1_VALID_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_06C8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6C8)
    #define HD21PHY_TRAIN_CFG_06C8_REG_LN2_VALID_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_06CC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6CC)
    #define HD21PHY_TRAIN_CFG_06CC_REG_LN3_VALID_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_06D0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6D0)
    #define HD21PHY_TRAIN_CFG_06D0_REG_LN0_ERROR_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_06D4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6D4)
    #define HD21PHY_TRAIN_CFG_06D4_REG_LN1_ERROR_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_06D8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6D8)
    #define HD21PHY_TRAIN_CFG_06D8_REG_LN2_ERROR_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_06DC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x6DC)
    #define HD21PHY_TRAIN_CFG_06DC_REG_LN3_ERROR_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_0780 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x780)
    #define HD21PHY_TRAIN_CFG_0780_REG_IRQ_FINAL_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_0784 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x784)
    #define HD21PHY_TRAIN_CFG_0784_REG_IRQ_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_0788 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x788)
    #define HD21PHY_TRAIN_CFG_0788_REG_IRQ_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_078C (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x78C)
    #define HD21PHY_TRAIN_CFG_078C_REG_IRQ_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_0790 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x790)
    #define HD21PHY_TRAIN_CFG_0790_REG_IRQ_CLR Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07C0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7C0)
    #define HD21PHY_TRAIN_CFG_07C0_REG_RESERVED0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07C4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7C4)
    #define HD21PHY_TRAIN_CFG_07C4_REG_RESERVED1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07C8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7C8)
    #define HD21PHY_TRAIN_CFG_07C8_REG_RESERVED2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07CC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7CC)
    #define HD21PHY_TRAIN_CFG_07CC_REG_RESERVED3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07D0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7D0)
    #define HD21PHY_TRAIN_CFG_07D0_REG_RESERVED4 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07D4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7D4)
    #define HD21PHY_TRAIN_CFG_07D4_REG_RESERVED5 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07D8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7D8)
    #define HD21PHY_TRAIN_CFG_07D8_REG_RESERVED6 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07DC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7DC)
    #define HD21PHY_TRAIN_CFG_07DC_REG_RESERVED7 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07E0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7E0)
    #define HD21PHY_TRAIN_CFG_07E0_REG_RESERVED_RD0 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07E4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7E4)
    #define HD21PHY_TRAIN_CFG_07E4_REG_RESERVED_RD1 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07E8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7E8)
    #define HD21PHY_TRAIN_CFG_07E8_REG_RESERVED_RD2 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07EC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7EC)
    #define HD21PHY_TRAIN_CFG_07EC_REG_RESERVED_RD3 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07F0 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7F0)
    #define HD21PHY_TRAIN_CFG_07F0_REG_RESERVED_RD4 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07F4 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7F4)
    #define HD21PHY_TRAIN_CFG_07F4_REG_RESERVED_RD5 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07F8 (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7F8)
    #define HD21PHY_TRAIN_CFG_07F8_REG_RESERVED_RD6 Fld(16,0,AC_FULLW10)//[15:0]
#define HD21PHY_TRAIN_CFG_07FC (IO_VIRT + IO_HDMI21_RX_PHY_BASE + 0x7FC)
    #define HD21PHY_TRAIN_CFG_07FC_REG_RESERVED_RD7 Fld(16,0,AC_FULLW10)//[15:0]

#endif
