#ifndef _HW_PLLGP_H_
#define _HW_PLLGP_H_

#define IO_LVDSTX_PLL_BASE	(IO_VIRT + 0x34000)
#define IO_PLLGP_BASE 		(IO_VIRT + 0x33000)

//LVDSTX PLL
#define REG_LVDSTX_PLL_CFG0 (IO_LVDSTX_PLL_BASE + 0x100)
    //#define REG_LVDSTX_PLL_CFG0_VPLL_XTAL_DIV Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_TRIM Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_RASEL Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_RBSEL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_CKDIV Fld(2,6,AC_MSKB0)//[7:6] new
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_PWD Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_CKEN Fld(1,4,AC_MSKB0)//[4:4]  new
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_LFP_EN Fld(1,3,AC_MSKB0)//[3:3]  new
    //#define REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_COMP_PWD Fld(1,4,AC_MSKB0)//[4:4]
    //#define REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_PRE_PWD Fld(1,3,AC_MSKB0)//[3:3]
    //#define REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_TX_PWD Fld(1,2,AC_MSKB0)//[2:2]
    //#define REG_LVDSTX_PLL_CFG0_VPLL_BG_LVDS_PWD Fld(1,1,AC_MSKB0)//[1:1]
    //#define REG_LVDSTX_PLL_CFG0_VPLL_BIAS_BYP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_LVDSTX_PLL_CFG1 (IO_LVDSTX_PLL_BASE + 0x104)
    #define REG_LVDSTX_PLL_CFG1_VPLL_PWD Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV Fld(11,20,AC_MSKW32)//[30:20]
    #define REG_LVDSTX_PLL_CFG1_VPLL_PREDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define REG_LVDSTX_PLL_CFG1_VPLL_POSDIV Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_LVDSTX_PLL_CFG1_VPLL_REFSEL Fld(2,13,AC_MSKB1)//[14:13]
    #define REG_LVDSTX_PLL_CFG1_VPLL_LVDSEN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_LVDSTX_PLL_CFG1_VPLL_VB1EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_LVDSTX_PLL_CFG1_VPLL_MLVDSEN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_LVDSTX_PLL_CFG1_VPLL_EPIEN Fld(1,9,AC_MSKB1)//[9:9]
        #define LVDSTX_PLL_POST_SEL Fld(4,9,AC_MSKB1)//[12:9]
        #define LVDSTX_PLL_POST_LVDSEN  (1<<3)
        #define LVDSTX_PLL_POST_VB1EN   (1<<2)
        #define LVDSTX_PLL_POST_MINIEN  (1<<1)
        #define LVDSTX_PLL_POST_EPIEN   (1<<0)
    #define REG_LVDSTX_PLL_CFG1_VPLL_CK_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_LVDSTX_PLL_CFG1_VPLL_LVDSCHL_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV3 Fld(2,5,AC_MSKB0)//[6:5]  new
    #define REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_LVDSTX_PLL_CFG2 (IO_LVDSTX_PLL_BASE + 0x108)
    //#define REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_CTRL Fld(2,30,AC_MSKB3)//[31:30]
    //#define REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_EN Fld(1,23,AC_MSKB2)//[23:23]
    //#define REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_LOAD Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_LVDSTX_PLL_CFG2_VPLL_VODEN Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_LVDSTX_PLL_CFG2_VPLL_BAND Fld(7,24,AC_MSKB3)//[30:24]
    #define REG_LVDSTX_PLL_CFG2_VPLL_VREF_RANGE_SEL Fld(2,22,AC_MSKB2)//[23:22]  new
    #define REG_LVDSTX_PLL_CFG2_VPLL_LOAD_EN Fld(1,21,AC_MSKB2)//[21:21]  new
    #define REG_LVDSTX_PLL_CFG2_VPLL_SLEEP_EN Fld(1,20,AC_MSKB2)//[20:20]  new
    #define REG_LVDSTX_PLL_CFG2_VPLL_RST_DLY Fld(2,18,AC_MSKB2)//[19:18]  new
    #define REG_LVDSTX_PLL_CFG2_VPLL_KBAND_PREDIV Fld(2,16,AC_MSKB2)//[17:16]  new
    #define REG_LVDSTX_PLL_CFG2_VPLL_IC Fld(4,12,AC_MSKB1)//[15:12]  new
    #define REG_LVDSTX_PLL_CFG2_VPLL_IR Fld(4,8,AC_MSKB1)//[11:8]  new
    #define REG_LVDSTX_PLL_CFG2_VPLL_BC Fld(5,3,AC_MSKB0)//[7:3]
    //#define REG_LVDSTX_PLL_CFG2_VPLL_DLY_DATA Fld(4,16,AC_MSKB2)//[19:16]
    //#define REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKA Fld(4,12,AC_MSKB1)//[15:12]
    //#define REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKB Fld(4,8,AC_MSKB1)//[11:8]
    //#define REG_LVDSTX_PLL_CFG2_VPLL_BIC Fld(3,5,AC_MSKB0)//[7:5]
    //#define REG_LVDSTX_PLL_CFG2_VPLL_BC Fld(2,3,AC_MSKB0)//[4:3]
    //#define REG_LVDSTX_PLL_CFG2_VPLL_DIVEN Fld(3,0,AC_MSKB0)//[2:0]
#define REG_LVDSTX_PLL_CFG3 (IO_LVDSTX_PLL_BASE + 0x10C)
    //#define REG_LVDSTX_PLL_CFG3_VPLL_BIR Fld(4,28,AC_MSKB3)//[31:28]
    #define REG_LVDSTX_PLL_CFG3_VPLL_BP Fld(5,27,AC_MSKB3)//[31:27]
    #define REG_LVDSTX_PLL_CFG3_VPLL_BP2 Fld(2,25,AC_MSKB3)//[26:25]  new
    #define REG_LVDSTX_PLL_CFG3_VPLL_MONREF_EN Fld(1,20,AC_MSKB3)//[24:24]  new
    #define REG_LVDSTX_PLL_CFG3_VPLL_BR Fld(4,20,AC_MSKB2)//[23:20]
    #define REG_LVDSTX_PLL_CFG3_VPLL_MONVC_EN Fld(1,19,AC_MSKB2)//[19:19]  new
    #define REG_LVDSTX_PLL_CFG3_VPLL_MONCK_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_LVDSTX_PLL_CFG3_VPLL_CLKTX_EN Fld(1,17,AC_MSKB2)//[17:17]  new
    #define REG_LVDSTX_PLL_CFG3_VPLL_IPATH_GAIN_SEL Fld(3,13,AC_MSKB1)//[15:13]
    #define REG_LVDSTX_PLL_CFG3_VPLL_IPATH_IDAC Fld(13,0,AC_MSKW10)//[12:0]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_FPEN Fld(1,18,AC_MSKB2)//[18:18]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_FMEN Fld(1,17,AC_MSKB2)//[17:17]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_TST_CKENB Fld(1,16,AC_MSKB2)//[16:16]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_TST_SEL Fld(3,13,AC_MSKB1)//[15:13]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_CHL_SEL Fld(2,11,AC_MSKB1)//[12:11]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_XTAL_MONEN Fld(1,10,AC_MSKB1)//[10:10]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_BG_MONEN Fld(1,9,AC_MSKB1)//[9:9]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_REF_MONEN Fld(1,8,AC_MSKB1)//[8:8]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
    //#define REG_LVDSTX_PLL_CFG3_VPLL_RESERVE_BIT7 Fld(1,7,AC_MSKB0)//[7:7]
#define REG_LVDSTX_PLL_CFG4 (IO_LVDSTX_PLL_BASE + 0x110)
    #define REG_LVDSTX_PLL_CFG4_VPLL_IPATH_SDM_DI_EN Fld(1,31,AC_MSKB3)//[31:31]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_IPATH_SDM_DI_LS Fld(2,29,AC_MSKB3)//[30:29]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_IPATH_SDM_IFM Fld(1,28,AC_MSKB3)//[28:28]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_IPATH_SDM_OUT Fld(1,27,AC_MSKB3)//[27:27]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_IPATH_DEBUG_SEL Fld(3,24,AC_MSKB3)//[26:24]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_IPATH_SDM_ORD Fld(2,22,AC_MSKB2)//[23:22]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_FC_DLY Fld(2,20,AC_MSKB2)//[21:20]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_DL_CODE Fld(2,18,AC_MSKB2)//[19:18]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_LVR_REFSEL Fld(2,16,AC_MSKB2)//[17:16]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_HIKVCO_SEL Fld(1,15,AC_MSKB1)//[15:15]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_PPML_EN Fld(1,14,AC_MSKB1)//[14:14]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_TCONX2_EN Fld(1,13,AC_MSKB1)//[13:13]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_TST_CKEN Fld(1,12,AC_MSKB1)//[12:12]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_TST_SEL Fld(3,9,AC_MSKB1)//[11:9]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_TST_DIV Fld(2,6,AC_MSKB0)//[7:6]  new
    #define REG_LVDSTX_PLL_CFG4_VPLL_BG_MONEN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_LVDSTX_PLL_CFG4_VPLL_TCON_OLD_EN Fld(1,4,AC_MSKB0)//[4:4] new
#if 0
    #define REG_LVDSTX_PLL_CFG4_PPLL_PWD Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV Fld(7,24,AC_MSKB3)//[30:24]
    #define REG_LVDSTX_PLL_CFG4_PPLL_PREDIV Fld(2,22,AC_MSKB2)//[23:22]
    #define REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define REG_LVDSTX_PLL_CFG4_PPLL_POSDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2 Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_LVDSTX_PLL_CFG4_PPLL_REFSEL Fld(2,14,AC_MSKB1)//[15:14]
       #define PPLL_REFSEL_IDP  0
       #define PPLL_REFSEL_DDDS 1
       #define PPLL_REFSEL_VPLL 2
    #define REG_LVDSTX_PLL_CFG4_PPLL_DIVEN Fld(3,11,AC_MSKB1)//[13:11]
    #define REG_LVDSTX_PLL_CFG4_PPLL_BP Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_LVDSTX_PLL_CFG4_PPLL_BR Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_LVDSTX_PLL_CFG4_PPLL_LF Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_LVDSTX_PLL_CFG4_PPLL_VODEN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_LVDSTX_PLL_CFG4_PPLL_MONEN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_LVDSTX_PLL_CFG4_PPLL_MONCKEN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_LVDSTX_PLL_CFG4_PPLL_FMEN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_LVDSTX_PLL_CFG4_PPLL_TSTEN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_LVDSTX_PLL_CFG4_PPLL_TST_DIV2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_LVDSTX_PLL_CFG4_PPLL_RESERVE Fld(2,0,AC_MSKB0)//[1:0]

#define RGS_LVDSTX_PLL_CFG0 (IO_LVDSTX_PLL_BASE + 0x114)
    #define REG_LVDSTX_PLL_CFG0_VPLL_CAL_CPLT Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_LVDSTX_PLL_CFG0_VPLL_CAL_FAIL Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_LVDSTX_PLL_CFG0_VPLL_CAL_STATE Fld(6,24,AC_MSKB3)//[29:24]
#endif
#define REG_LVDSTX_PLL_CFG5 (IO_LVDSTX_PLL_BASE + 0x114)
    #define REG_LVDSTX_PLL_CFG5_VPLL_RESERVE Fld(8,24,AC_MSKB3)//[31:24]
    #define REG_LVDSTX_PLL_CFG5_VPLL_TCON2_DIV3P5_EN Fld(1,23,AC_MSKB2)//[23:23]  new
    #define REG_LVDSTX_PLL_CFG5_VPLL_TCON2_DIV9 Fld(2,21,AC_MSKB2)//[22:21]  new
    #define REG_LVDSTX_PLL_CFG5_VPLL_TCON2_DIV32 Fld(3,18,AC_MSKB2)//[20:18]  new
    #define REG_LVDSTX_PLL_CFG5_VPLL_TCON_DIV3P5_EN Fld(1,15,AC_MSKB1)//[15:15]  new
    #define REG_LVDSTX_PLL_CFG5_VPLL_TCON_DIV9 Fld(2,13,AC_MSKB1)//[14:13]  new
    #define REG_LVDSTX_PLL_CFG5_VPLL_TCON_DIV32 Fld(3,10,AC_MSKB1)//[12:10]  new
    #define REG_LVDSTX_PLL_CFG5_PPLL_PWD Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_LVDSTX_PLL_CFG5_PPLL_SDM_PCW_CHG Fld(1,6,AC_MSKB0)//[6:6]  new
    #define REG_LVDSTX_PLL_CFG5_PPLL_BP Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_LVDSTX_PLL_CFG5_PPLL_BR Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_LVDSTX_PLL_CFG5_PPLL_RST_DLY Fld(2,2,AC_MSKB0)//[3:2]  new
    #define REG_LVDSTX_PLL_CFG5_PPLL_SDM_HREN Fld(1,1,AC_MSKB0)//[1:1]  new
#define REG_LVDSTX_PLL_CFG6 (IO_LVDSTX_PLL_BASE + 0x118)
    #define REG_LVDSTX_PLL_CFG6_PPLL_SDM_PCW Fld(32,0,AC_FULLDW)//[31:0]  new
#define REG_LVDSTX_PLL_CFG7 (IO_LVDSTX_PLL_BASE + 0x11C)
    #define REG_LVDSTX_PLL_CFG7_PPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define REG_LVDSTX_PLL_CFG7_PPLL_SDM_FRA_EN Fld(1,27,AC_MSKB3)//[27:27]  new
    #define REG_LVDSTX_PLL_CFG7_PPLL_PREDIV Fld(2,25,AC_MSKB3)//[26:25]
    #define REG_LVDSTX_PLL_CFG7_PPLL_DIV3_EN Fld(1,24,AC_MSKB3)//[24:24]  new
    #define REG_LVDSTX_PLL_CFG7_PPLL_GLITCH_FREE_EN Fld(1,23,AC_MSKB2)//[23:23]  new
    #define REG_LVDSTX_PLL_CFG7_PPLL_BLP Fld(1,22,AC_MSKB2)//[22:22]  new
    #define REG_LVDSTX_PLL_CFG7_PPLL_LVROD_EN Fld(1,21,AC_MSKB2)//[21:21]  new
    #define REG_LVDSTX_PLL_CFG7_PPLL_MONVC_EN Fld(1,20,AC_MSKB2)//[20:20]  new
    #define REG_LVDSTX_PLL_CFG7_PPLL_MONCK_EN Fld(1,19,AC_MSKB2)//[19:19]  new
    #define REG_LVDSTX_PLL_CFG7_PPLL_MONREF_EN Fld(1,18,AC_MSKB2)//[18:18]  new
    #define REG_LVDSTX_PLL_CFG7_PPLL_RESERVE Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_LVDSTX_PLL_CFG7_PPLL_REFSEL Fld(2,14,AC_MSKB1)//[15:14]
       #define PPLL_REFSEL_DDDS2  0  // new
       #define PPLL_REFSEL_DDDS1  1  // new
       #define PPLL_REFSEL_VPLL   2
    #define REG_LVDSTX_PLL_CFG7_PPLL_POSDIV2 Fld(2,12,AC_MSKB1)//[13:12]
#define RGS_LVDSTX_PLL_CFG0 (IO_LVDSTX_PLL_BASE + 0x120)
    #define RGS_LVDSTX_PLL_CFG0_VPLL_IPLL_DIG_MON Fld(6,26,AC_MSKB3)//[31:26]  new
    #define RGS_LVDSTX_PLL_CFG0_VPLL_KBAND_CPLT Fld(1,25,AC_MSKB3)//[25:25]  new

//#define REG_LVDS_TX_PLL_CFG (IO_LVDSTX_PLL_BASE+0x60)
    //#define REG_LVDS_TX_PLL_CFG_VPLL_BG_CKEN Fld(1,7,AC_MSKB0)//[7:7]

//PLL Group
#define REG_PLL_GROUP_CFG0 (IO_PLLGP_BASE + 0x000)
    #define FLD_RG_SYSPLL_SDM_PCW Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_SYSPLL_SDM_PCW_CHG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_SYSPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_SYSPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_SYSPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_SYSPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_SYSPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_SYSPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG1 (IO_PLLGP_BASE + 0x004)
    #define FLD_RG_VDECPLL_SDM_PCW Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_VDECPLL_SDM_PCW_CHG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_VDECPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_VDECPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_VDECPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_VDECPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_VDECPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_VDECPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG2 (IO_PLLGP_BASE + 0x008)
    #define FLD_RG_VDECSOCPLL_SDM_PCW Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_VDECSOCPLL_SDM_PCW_CHG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_VDECSOCPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_VDECSOCPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_VDECSOCPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_VDECSOCPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_VDECSOCPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_VDECSOCPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG3 (IO_PLLGP_BASE + 0x00C)
    #define FLD_RG_DMUXPLL_SDM_PCW Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_DMUXPLL_SDM_PCW_CHG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_DMUXPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_DMUXPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_DMUXPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_DMUXPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_DMUXPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_DMUXPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG4 (IO_PLLGP_BASE + 0x010)
    #define FLD_RG_DMUXBACKPLL_SDM_PCW Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_DMUXBACKPLL_SDM_PCW_CHG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_DMUXBACKPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_DMUXBACKPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_DMUXBACKPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_DMUXBACKPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_DMUXBACKPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_DMUXBACKPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG5 (IO_PLLGP_BASE + 0x014)
    #define FLD_RG_MJCPLL_SDM_PCW Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_MJCPLL_SDM_PCW_CHG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_MJCPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_MJCPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_MJCPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_MJCPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_MJCPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_MJCPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG6 (IO_PLLGP_BASE + 0x018)
    #define FLD_RG_VGAPLL_SDM_PCW Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_VGAPLL_SDM_PCW_CHG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_VGAPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_VGAPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_VGAPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_VGAPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_VGAPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_VGAPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG7 (IO_PLLGP_BASE + 0x01C)
    #define FLD_RG_APUPLL_SDM_PCW Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_APUPLL_SDM_PCW_CHG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_APUPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_APUPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_APUPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_APUPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_APUPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_APUPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG8 (IO_PLLGP_BASE + 0x020)
    #define FLD_RG_ENGPLL_SDM_PCW Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_ENGPLL_SDM_PCW_CHG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_ENGPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_ENGPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_ENGPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_ENGPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_ENGPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_ENGPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG9 (IO_PLLGP_BASE + 0x024)
    #define FLD_RG_TMDSPLL1_SDM_PCW Fld(32,0,AC_FULLDW)//[31:0]
#define REG_PLL_GROUP_CFG10 (IO_PLLGP_BASE + 0x028)
    #define FLD_RG_TMDSPLL1_SDM_PCW_CHG Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_TMDSPLL1_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_TMDSPLL1_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_TMDSPLL1_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_TMDSPLL1_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_TMDSPLL1_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_TMDSPLL1_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG11 (IO_PLLGP_BASE + 0x02C)
    #define FLD_RG_TMDSPLL2_SDM_PCW Fld(32,0,AC_FULLDW)//[31:0]
#define REG_PLL_GROUP_CFG12 (IO_PLLGP_BASE + 0x030)
    #define FLD_RG_TMDSPLL2_SDM_PCW_CHG Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_TMDSPLL2_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_TMDSPLL2_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_TMDSPLL2_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_TMDSPLL2_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_TMDSPLL2_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_TMDSPLL2_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG13 (IO_PLLGP_BASE + 0x034)
    #define FLD_RG_CILINKPLL_SDM_PCW Fld(32,0,AC_FULLDW)//[31:0]
#define REG_PLL_GROUP_CFG14 (IO_PLLGP_BASE + 0x038)
    #define FLD_RG_CILINKPLL_SDM_PCW_CHG Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_CILINKPLL_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_CILINKPLL_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_CILINKPLL_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_CILINKPLL_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_CILINKPLL_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_CILINKPLL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG15 (IO_PLLGP_BASE + 0x03C)
    #define FLD_RG_APLL2_RESERVE Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_APLL2_SDM_FRA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_APLL2_DIV3_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_APLL2_GLITCH_FREE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_APLL2_BLP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_APLL2_POSDIV Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_APLL2_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG16 (IO_PLLGP_BASE + 0x040)
    #define FLD_RG_HADDS1_PWDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_HADDS1_MONEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_HADDS1_VSP_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_HADDS1_REFCLK_SEL Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_HADDS1_CKSEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_HADDS1_PRE_DIV2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_HADDS1_HF Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_HADDS1_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_HADDS1_RESERVE Fld(4,16,AC_MSKB2)//[19:16]
#define REG_PLL_GROUP_CFG17 (IO_PLLGP_BASE + 0x044)
    #define FLD_RG_HADDS2_PWDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_HADDS2_MONEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_HADDS2_VSP_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_HADDS2_REFCLK_SEL Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_HADDS2_CKSEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_HADDS2_PRE_DIV2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_HADDS2_HF Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_HADDS2_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_HADDS2_RESERVE Fld(4,16,AC_MSKB2)//[19:16]
#define REG_PLL_GROUP_CFG18 (IO_PLLGP_BASE + 0x048)
    #define FLD_RG_DDDS1_PWDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_DDDS1_MONEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_DDDS1_CKSEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_DDDS1_PRE_DIV2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_DDDS1_HF Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_DDDS1_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_DDDS1_RESERVE Fld(4,16,AC_MSKB2)//[19:16]
#define REG_PLL_GROUP_CFG19 (IO_PLLGP_BASE + 0x04C)
    #define FLD_RG_DDDS2_PWDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_DDDS2_MONEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_DDDS2_CKSEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_DDDS2_PRE_DIV2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_DDDS2_HF Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_DDDS2_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_DDDS2_RESERVE Fld(4,16,AC_MSKB2)//[19:16]
#define REG_PLL_GROUP_CFG20 (IO_PLLGP_BASE + 0x050)
    #define FLD_RG_DMDDS_PWDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_DMDDS_MONEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_DMDDS_VSP_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_DMDDS_REFCLK_SEL Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_DMDDS_CKSEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_DMDDS_PRE_DIV2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_DMDDS_HF Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_DMDDS_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_DMDDS_RESERVE Fld(4,16,AC_MSKB2)//[19:16]
#define REG_PLL_GROUP_CFG21 (IO_PLLGP_BASE + 0x054)
    #define FLD_RG_DMUX_STC_DDS_PWDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_DMUX_STC_DDS_MONEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_DMUX_STC_DDS_VSP_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_DMUX_STC_DDS_REFCLK_SEL Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_DMUX_STC_DDS_CKSEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_DMUX_STC_DDS_PRE_DIV2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_DMUX_STC_DDS_HF Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_DMUX_STC_DDS_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_DMUX_STC_DDS_RESERVE Fld(4,16,AC_MSKB2)//[19:16]
#define REG_PLL_GROUP_CFG22 (IO_PLLGP_BASE + 0x058)
    #define FLD_RG_VGAPLL_SDDS_PD_PDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_VGAPLL_SDDS_PD_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_VGATL_BIAS_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_XDDS_PWDB Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_XDDS_CKSEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_VGAPLL_CKO_SEL Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_RG_XDDS_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_XDDS_HF Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_VGAPLL_R_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_RG_VGAPLL_G_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_VGAPLL_B_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_VGAPLL_RTB_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_VGAPLL_ENTL Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_RG_VGAPLL_INTH_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_RG_VGAPLL_EXTH_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_RG_VGAPLL_SDDS_FBKSEL Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_TL_REFCK_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_VGAPLL_SDDS_HSEL Fld(2,5,AC_MSKB0)//[6:5]
    #define FLD_RG_VGAPLL_SDDS_HPOR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_VGATL_RESERVE Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_XDDS_MONEN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG23 (IO_PLLGP_BASE + 0x05C)
    #define FLD_RG_VGATL_TSELA Fld(4,28,AC_MSKB3)//[31:28]
    #define FLD_RG_VGATL_TSELB Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_RG_XDDS_CKSEL_MON Fld(4,20,AC_MSKB2)//[23:20]
#define REG_PLL_GROUP_CFG24 (IO_PLLGP_BASE + 0x060)
    #define FLD_RG_PLLGP_TST_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_PLLGP_LVROD_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_PLLGP_VOD_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_VGATL_LDO_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_VGATL_LDO_LPF_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_VGATL_LDO_LVROD_EN Fld(2,25,AC_MSKB3)//[26:25]
    #define FLD_RG_VGATL_LDO_MON_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_SYSPLL_LDO_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_SYSPLL_LDO_LPF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_SYSPLL_LDO_LVROD_EN Fld(2,20,AC_MSKB2)//[21:20]
    #define FLD_RG_SYSPLL_LDO_MON_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_RG_APLL2_LDO_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_APLL2_LDO_LPF_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_APLL2_LDO_LVROD_EN Fld(2,15,AC_MSKW21)//[16:15]
    #define FLD_RG_APLL2_LDO_MON_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_RG_APLL2_DIV6_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_RG_APLL2_DIV8_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_APLL2_DIV8_DIV10_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_RG_PLLGP_TSTMUX Fld(4,7,AC_MSKW10)//[10:7]
    #define FLD_RG_PLLGP_MONREF_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_PLLGP_TSTCK_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_PLLGP_TST_SEL Fld(2,3,AC_MSKB0)//[4:3]
    #define FLD_RG_PLLGP_TSTOD_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_PLLGP_A2DCK_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_PLLGP_TSTOP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG26 (IO_PLLGP_BASE + 0x064)
    #define FLD_RG_PLLGP_RESERVE Fld(32,0,AC_FULLDW)//[31:0]
#define RGS_PLLGP_NORMAL_CFG0 (IO_PLLGP_BASE + 0x068)
    #define FLD_RGS_HADDS1_CAP_STATE Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RGS_XDDS_CAP_STATE Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RGS_HADDS2_CAP_STATE Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RGS_DDDS1_CAP_STATE Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RGS_DDDS2_CAP_STATE Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RGS_DMDDS_CAP_STATE Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RGS_DMUX_STC_DDS_CAP_STATE Fld(1,25,AC_MSKB3)//[25:25]

//VGA_NORMAL
#define REG_VGANORM_CFG0 (IO_PLLGP_BASE + 0x200)
    #define FLD_RG_SHORT_FEO Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_ADCTEST_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_RG_VREFGEN4FE_PWD Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_VDC_P_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_VDC_N_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_CAP_EN Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_RG_ADCVREFP Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_RG_IGEN_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_RG_FE_OFFSET_N Fld(3,0,AC_MSKB0)//[2:0]
#define REG_VGANORM_CFG1 (IO_PLLGP_BASE + 0x204)
    #define FLD_RG_CLAMP_MIDDLE_1 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_FE_OFFSET_P1 Fld(3,27,AC_MSKB3)//[29:27]
    #define FLD_RG_FE_1_PWD Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_COPBIAS_1 Fld(3,23,AC_MSKW32)//[25:23]
    #define FLD_RG_COP_1_PWD Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_CLAMP_GATE_1 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_MUXCAP_EN1 Fld(5,16,AC_MSKB2)//[20:16]
    #define FLD_RG_CLAMP_MIDDLE_2 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_RG_FE_OFFSET_P2 Fld(3,11,AC_MSKB1)//[13:11]
    #define FLD_RG_FE_2_PWD Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_RG_COPBIAS_2 Fld(3,7,AC_MSKW10)//[9:7]
    #define FLD_RG_COP_2_PWD Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_CLAMP_GATE_2 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_MUXCAP_EN2 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_VGANORM_CFG2 (IO_PLLGP_BASE + 0x208)
    #define FLD_RG_CLAMP_MIDDLE_3 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_FE_OFFSET_P3 Fld(3,27,AC_MSKB3)//[29:27]
    #define FLD_RG_FE_3_PWD Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_COPBIAS_3 Fld(3,23,AC_MSKW32)//[25:23]
    #define FLD_RG_COP_3_PWD Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_CLAMP_GATE_3 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_MUXCAP_EN3 Fld(5,16,AC_MSKB2)//[20:16]
    #define FLD_RG_VGAADC1_IO_PWD Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_RG_VGAADC1_MON_SEL Fld(2,13,AC_MSKB1)//[14:13]
    #define FLD_RG_VGAADC1_LDO_SEL Fld(2,11,AC_MSKB1)//[12:11]
    #define FLD_RG_VGAADC1_VREF_SEL Fld(2,9,AC_MSKB1)//[10:9]
    #define FLD_RG_VGAADC1_DIV_SEL Fld(2,7,AC_MSKW10)//[8:7]
    #define FLD_RG_VGAADC1_PHSEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_VGAADC1_DC_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_VGAADC1_CK_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_VGAADC1_CK_PWD Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_RG_VGAADC1_CORE_PWD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_VGAADC1_LSF_EN Fld(1,1,AC_MSKB0)//[1:1]
#define REG_VGANORM_CFG3 (IO_PLLGP_BASE + 0x20C)
    #define FLD_RG_VGAADC1_REV0 Fld(4,19,AC_MSKB2)//[22:19]
    #define FLD_RG_VGAADC1_REV1 Fld(4,15,AC_MSKW21)//[18:15]
    #define FLD_RG_VGAADC2_IO_PWD Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_RG_VGAADC2_MON_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define FLD_RG_VGAADC2_LDO_SEL Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_RG_VGAADC2_VREF_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_VGAADC2_DIV_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define FLD_RG_VGAADC2_PHSEL Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_VGAADC2_DC_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_VGAADC2_CK_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_RG_VGAADC2_CK_PWD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_VGAADC2_CORE_PWD Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_VGAADC2_LSF_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_VGANORM_CFG4 (IO_PLLGP_BASE + 0x210)
    #define FLD_RG_VGAADC2_REV0 Fld(4,19,AC_MSKB2)//[22:19]
    #define FLD_RG_VGAADC2_REV1 Fld(4,15,AC_MSKW21)//[18:15]
    #define FLD_RG_VGAADC3_IO_PWD Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_RG_VGAADC3_MON_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define FLD_RG_VGAADC3_LDO_SEL Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_RG_VGAADC3_VREF_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_VGAADC3_DIV_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define FLD_RG_VGAADC3_PHSEL Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_VGAADC3_DC_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_VGAADC3_CK_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_RG_VGAADC3_CK_PWD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_VGAADC3_CORE_PWD Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_VGAADC3_LSF_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_VGANORM_CFG5 (IO_PLLGP_BASE + 0x214)
    #define FLD_RG_VGAADC3_REV0 Fld(4,19,AC_MSKB2)//[22:19]
    #define FLD_RG_VGAADC3_REV1 Fld(4,15,AC_MSKW21)//[18:15]
    #define FLD_RG_RGB_REV0 Fld(8,7,AC_MSKW10)//[14:7]
#define REG_VGANORM_CFG6 (IO_PLLGP_BASE + 0x218)
    #define FLD_RG_RGB_REV1 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_RELATCH_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_CLKOSEL_3 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_CLKOSEL_2 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_CLKOSEL_1 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_CLKINV_EN Fld(1,19,AC_MSKB2)//[19:19]
#define RGS_VGANORM_CFG0 (IO_PLLGP_BASE + 0x21C)
    #define FLD_RGS_YPBPR_ABUSE Fld(1,31,AC_MSKB3)//[31:31]

#endif /* _HW_PLLGP_H_ */
