/******************************************************************************
 *
 * 2017 (c) Lattice Semiconductor Corporation
 * 
 * This program is free software; you can redistribute it and/or
 * modify it only under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation, and not any later version.
 * 
 * This program is distributed "AS IS" WITHOUT ANY WARRANTY of any kind,
 * whether express or implied, including without limitation the implied warranty
 * of MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE or NON-INFRINGEMENT.
 * See the GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 * 
 * You may contact Lattice Semiconductor Corporation at 
 * 111 SW 5th Ave, Suite 700, Portland, OR 97204.
 *
 *****************************************************************************/
/**
 * @file  sii9438_regs.h
 *
 * @brief Defines SiI9438 Receiver Register Info.
 *
 *****************************************************************************/
#ifndef _SII9438_REGS_H_
#define _SII9438_REGS_H_

#define BASE_ADDRESS 0x0000

enum Page_t {
	TX_TOP_REG	= (BASE_ADDRESS | 0x0000),
	TX_SW_TPI_REG	= (BASE_ADDRESS | 0x0100),
	TX_HW_TPI_REG	= (BASE_ADDRESS | 0x0200),
	TX_EARC_REG	= (BASE_ADDRESS | 0x0300),
	TX_PHY_REG	= (BASE_ADDRESS | 0x0400),
};

/*****************  TX VIENNA TOP (6000-60FF) ***************/
/* SYS Vendor ID Low byte Register*/
#define REG_ADDR__VND_IDL				(TX_TOP_REG | 0x0000)
	/* (ReadOnly, Bits 7:0)*/
	/* Vendor ID Low byte Sil_Internal((01h))*/
	#define BIT_MSK__VND_IDL__REG_VHDL_IDL			0xFF

/* SYS Vendor ID High byte Register*/
#define REG_ADDR__VND_IDH				(TX_TOP_REG | 0x0001)
	/* (ReadOnly, Bits 7:0)*/
	/* Vendor ID High byte Sil_Internal((00h))*/
	#define BIT_MSK__VND_IDH__REG_VHDL_IDH			0xFF

/* SYS Device ID Low byte Register*/
#define REG_ADDR__DEV_IDL				(TX_TOP_REG | 0x0002)
	/* (ReadOnly, Bits 7:0)*/
	/* Device ID Low byte
     case (mhl_en arc_en ethernet_en repeater_en)
       4'b0000: dev_idl_bo =  8'h85;
       4'b1100: dev_idl_bo =  8'h87;
       4'b1111: dev_idl_bo =  8'h89;
       default:dev_idl_bo =  8'hFF;*/
	#define BIT_MSK__DEV_IDL__DEV_IDL			0xFF

/* SYS Device ID High byte Register*/
#define REG_ADDR__DEV_IDH				(TX_TOP_REG | 0x0003)
	/* (ReadOnly, Bits 7:0)*/
	/* Device ID High byteSil_Internal(: 0x94)*/
	#define BIT_MSK__DEV_IDH__REG_DEV_IDH			0xFF

/* SYS Device Revision Register*/
#define REG_ADDR__DEV_REV				(TX_TOP_REG | 0x0004)
	/* (ReadOnly, Bits 7:0)*/
	/* bit [7:4] - Device Revision (Major Number)
	 bit [3:0] - Device Revision (Minor Number)*/
	#define BIT_MSK__DEV_REV__DEV_REV_ID			0xFF

/* Software Reset #2 Register */
#define REG_ADDR__SRST2					(TX_TOP_REG | 0x0006)
	/* (ReadWrite, Bits 3) */
	/* reset Tx audio FIFO */
	#define BIT_MSK__SRST2__REG_RST_TX_FIFO_N		0x08
	/* (ReadWrite, Bits 1)*/
	/* Reset Tx audio in*/
	#define BIT_MSK__SRST2__REG_RST_4CLK_AUDIO_IN_N		0x02

/* IO Output Enable Register*/
#define REG_ADDR__IO_OEN				(TX_TOP_REG | 0x0009)
	/* (ReadWrite, Bits 7)*/
	/* MUTE output enable*/
	#define BIT_MSK__IO_OEN__REG_MUTE_OEN			0x80

/* GPIO out ctrl Register */
#define REG_ADDR__GPIO_I_CTRL				(TX_TOP_REG | 0x000C)
	/* (ReadWrite, Bits 5:0)
	 * GPIO I value */
	#define BIT_MSK__GPIO_I_CTRL__REG_GPIO_I		0x3F

/* GPIO OEN ctrl Register */
#define REG_ADDR__GPIO_OEN_CTRL				(TX_TOP_REG | 0x000D)
	/* (ReadWrite, Bits 5:0) */
	/* GIO output enable value: "0" enable output */
	#define BIT_MSK__GPIO_OEN_CTRL__REG_GPIO_OEN		0x3F

/* GPIO  pe ctrl Register */
#define REG_ADDR__GPIO_PE_CTRL				(TX_TOP_REG | 0x000E)
	/* (ReadWrite, Bits 5:0) */
	/* GPIO output pull up enable.  "1" enable */
	#define BIT_MSK__GPIO_PE_CTRL__REG_GPIO_PE		0x3F

/* GPIO  pu ctrl Register */
#define REG_ADDR__GPIO_PU_CTRL				(TX_TOP_REG | 0x000F)
	/* (ReadWrite, Bits 5:0) */
	/* GPIO output pull up value. */
	#define BIT_MSK__GPIO_PU_CTRL__REG_GPIO_PU		0x3F

/* GPIO input status Register */
#define REG_ADDR__GPIO_C_CTRL				(TX_TOP_REG | 0x0010)

/* Timer CTRL Register*/
#define REG_ADDR__TIMER_CTRL				(TX_TOP_REG | 0x0012)
	/* (ReadWrite, Bits 1:0)*/
	/* Control for the timer:
		bit 0: 1: enable the timer; 0: disable the timer
		bit 1: selects the mode:  0 = one shot; 1 = continuous*/
	#define BIT_MSK__TIMER_CTRL__REG_TIMER_CONFIG		0x03
	#define BIT_MASK__TIMER_CTRL__REG_TIMER_CONFIG_ENABLE	0x01
	#define BIT_MASK__TIMER_CTRL__REG_TIMER_CONFIG_MODE	0x02


/* Timer value #0 Register*/
#define REG_ADDR__TIMER_VAL0				(TX_TOP_REG | 0x0013)
	/* (ReadWrite, Bits 7:0)*/
	/* data[7:0] is the value of timer. The timer counts down to 0
	 * and then issues an interrupt. In one-shot mode it then stops;
	 * in continuous mode it then re-loads the value and restarts.
	 * Note that reg_timer_data will not be loaded into the logic
	 * until TIMER_VAL1 is written.*/
	#define BIT_MSK__TIMER_VAL0__REG_TIMER_DATA_B7_B0	0xFF

/* Timer value #1 Register*/
#define REG_ADDR__TIMER_VAL1				(TX_TOP_REG | 0x0014)
	/* (ReadWrite, Bits 7:0)*/
	/* data[15:8] is the value of timer. The timer counts down to 0 and
	 * then issues an interrupt. In one-shot mode it then stops;
	 * in continuous mode it then re-loads the value and restarts.
	 * Note that reg_timer_data will not be loaded into the logic
	 * until TIMER_VAL1 is written.*/
	#define BIT_MSK__TIMER_VAL1__REG_TIMER_DATA_B15_B8	0xFF

/* Timer value #2 Register*/
#define REG_ADDR__TIMER_SCALE1				(TX_TOP_REG | 0x0015)
	/* (ReadWrite, Bits 7:0)*/
	/* scale[7:0] is the value of the scale timer. The main timer only
	 * decrements when the scale timer reaches zero. The scale timer is
	 * always continuous. This can be used to multiply the clock period
	 * of the timer clock by the scale value (+1).
	 * Note that reg_timer_scale will not be loaded into the logic
	 * until TIMER_SCALE2 is written.*/
	#define BIT_MSK__TIMER_SCALE1__REG_TIMER_SCALE_B7_B0	0xFF

/* Timer value #3 Register*/
#define REG_ADDR__TIMER_SCALE2				(TX_TOP_REG | 0x0016)
	/* (ReadWrite, Bits 7:0)*/
	/* scale[7:0] is the value of the scale timer. The main timer only
	 * decrements when the scale timer reaches zero. The scale timer is
	 * always continuous. This can be used to multiply the clock period
	 * of the timer clock by the scale value (+1).
	 * Note that reg_timer_scale will not be loaded into the logic
	 * until TIMER_SCALE2 is written.*/
	#define BIT_MSK__TIMER_SCALE2__REG_TIMER_SCALE_B15_B8	0xFF

/* I2C address for eARC Tx SW TPI */
#define REG_ADDR__I2C_ADDR0				(TX_TOP_REG | 0x0018)

/* I2C address for eARC Tx HW TPI */
#define REG_ADDR__I2C_ADDR1				(TX_TOP_REG | 0x0019)

/* MCLK control for PHY ref clk Register*/
#define REG_ADDR__MCLK_PHY				(TX_TOP_REG | 0x001B)
	/* (ReadWrite, Bits 1:0)*/
	/* div2, div4 generation of MCLK
		00: same clock. No division
		01: div2
		10: div4
		11: 1'b0 - no clock*/
	#define BIT_MSK__MCLK_PHY__REG_MCLK_DIV			0x03
	#define BIT_MSK__MCLK_PHY__REG_MCLK_NO_DIV		0x00
	#define BIT_MSK__MCLK_PHY__REG_MCLK_DIV_2		0x01
	#define BIT_MSK__MCLK_PHY__REG_MCLK_DIV_4		0x02
	#define BIT_MSK__MCLK_PHY__REG_MCLK_DIV_NO_CLK		0x03

/* clock select */
#define REG_ADDR__CLK_SEL				(TX_TOP_REG | 0x0020)
	#define BIT_MSK__BY_PASS_CLK_EXT			0x02

/* Chip ID DDC Register */
#define REG_ADDR__CHIP_ID_I2C				(TX_TOP_REG | 0x0024)
	/* (ReadWrite, Bits 7:0)*/
	/* bit #7: enable overwrite
	bit #6: "1" means Tx
	bits [3:0]: device ID with bits 7:4 of device ID hardcoded to 3*/
	#define BIT_MASK__CHIP_ID_I2C_TX			0x40
	#define BIT_MSK__CHIP_ID_I2C__REG_CHIP_ID_LI2C		0xFF

/* I2C Addr #2 Register */
#define REG_ADDR__I2C_ADDR2				(TX_TOP_REG | 0x0029)

/* I2C Addr #3 Register */
#define REG_ADDR__I2C_ADDR3				(TX_TOP_REG | 0x002A)

/* I2C Addr #4 Register */
#define REG_ADDR__I2C_ADDR4				(TX_TOP_REG | 0x002B)

/* I2C Config Register */
#define REG_ADDR__I2C_CONFIG				(TX_TOP_REG | 0x002C)
	/* (ReadWrite, Bits 0) */
	/* Set to 1 to expose the other slave addresses
	 * beside slave address 0x60 */
	#define BIT_MSK__I2C_CONFIG__REG_EXPOSE_SLAVE_ADDR	0x01

/* Interrupt State Register */
#define REG_ADDR__TOP_INTR_STATE			(TX_TOP_REG | 0x0030)

	/* (ReadOnly, Bits 0)*/
	/* Interrupt state bit value.  It shows whether the interrupt output
	 * signal on INT pin is active or not.  1 indicates that at least one
	 * masked interrupt has been asserted. This bit can only be cleared by
	 * SW; either by unmasking all asserted interrupts or by clearing
	 * all asserted interrupts.*/
	#define BIT_MSK__TOP_INTR_STATE__INTR_STATE_TOP		0x01

/* Interrupt Source #1 Register */
#define REG_ADDR__TOP_INTR1				(TX_TOP_REG | 0x0031)
	/* (ReadWrite, Bits 5)*/
	/* "1" means clock detect status from rx digital logic changed.
	 * For status check reg_rx_clk_detected*/
	#define BIT_MSK__TOP_INTR1__REG_TOP_INTR_STAT5		0x20
	/* (ReadWrite, Bits 4)*/
	/* "1" means rx_freq_zone changed. For status check RX_FREQ_ZONE*/
	#define BIT_MSK__TOP_INTR1__REG_TOP_INTR_STAT4		0x10
	/* (ReadWrite, Bits 3)*/
	/* "1" means lock detect status changed. For status check
	 * viola_status #1*/
	#define BIT_MSK__TOP_INTR1__REG_TOP_INTR_STAT3		0x08
	/* (ReadWrite, Bits 2)*/
	/* "1" means clock detect status from Viola PHY changed.
	 * For status check viola_status bit #0*/
	#define BIT_MSK__TOP_INTR1__REG_TOP_INTR_STAT2		0x04
	/* (ReadWrite, Bits 1)*/
	/* timer interrupt*/
	#define BIT_MSK__TOP_INTR1__REG_TOP_INTR_STAT1		0x02
	/* (ReadWrite, Bits 0)*/
	/* "1" software enabled interrupt from TOP_INT_CTRL bit #3*/
	#define BIT_MSK__TOP_INTR1__REG_TOP_INTR_STAT0		0x01

/* Interrupt Source #2 Register */
#define REG_ADDR__TOP_INTR2				(TX_TOP_REG | 0x0032)
	/* (ReadWrite, Bits 7) */
	/* "1" means GPIO1 changed from 1 to 0
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR2__REG_TOP_INTR_STAT13		0x80
	/* (ReadWrite, Bits 6) */
	/* "1" means GPIO0 changed from 1 to 0
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR2__REG_TOP_INTR_STAT12		0x40
	/* (ReadWrite, Bits 5) */
	/* "1" means GPIO5 changed from 0 to 1
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR2__REG_TOP_INTR_STAT11		0x20
	/* (ReadWrite, Bits 4) */
	/* "1" means GPIO4 changed from 0 to 1
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR2__REG_TOP_INTR_STAT10		0x10
	/* (ReadWrite, Bits 3) */
	/* "1" means GPIO3 changed from 0 to 1
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR2__REG_TOP_INTR_STAT9		0x08
	/* (ReadWrite, Bits 2) */
	/* "1" means GPIO2 changed from 0 to 1
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR2__REG_TOP_INTR_STAT8		0x04
	/* (ReadWrite, Bits 1) */
	/* "1" means GPIO1 changed from 0 to 1
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR2__REG_TOP_INTR_STAT7		0x02
	/* (ReadWrite, Bits 0) */
	/* "1" means GPIO0 changed from 0 to 1
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR2__REG_TOP_INTR_STAT6		0x01

	/* INT[9:6], INT[12], INT[13];
	 * 1 - enable; 0 - disable (default)
	 * GPIO0 to GPIO3 : 0 to 1 changes
	 * GPIO0 and GPIO1: 1 to 0 changes */
	#define BIT_MASK__TOP_INTR2__REG_INTR_GEN_GPIO		0xCF

/* Interrupt Source #3 Register */
#define REG_ADDR__TOP_INTR3				(TX_TOP_REG | 0x0033)
	/* (ReadWrite, Bits 3) */
	/* "1" means GPIO5 changed from 1 to 0
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR3__REG_TOP_INTR_STAT17		0x08
	/* (ReadWrite, Bits 2) */
	/* "1" means GPIO4 changed from 1 to 0
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR3__REG_TOP_INTR_STAT16		0x04
	/* (ReadWrite, Bits 1) */
	/* "1" means GPIO3 changed from 1 to 0
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR3__REG_TOP_INTR_STAT15		0x02
	/* (ReadWrite, Bits 0) */
	/* "1" means GPIO2 changed from 1 to 0
	 * For status check reg. 0xC (GPIO_I_CTRL) */
	#define BIT_MSK__TOP_INTR3__REG_TOP_INTR_STAT14		0x01

	/* GPIO2 and GPIO3: 1 to 0 changes*/
	#define BIT_MASK__TOP_INTR3__REG_INTR_GEN_GPIO		0x03

/* Interrupt #1 Mask Register */
#define REG_ADDR__TOP_INTR1_MASK			(TX_TOP_REG | 0x0034)
	#define BIT_MASK__TOP_INTR1_MASK__TOP_TIMER		0x02

/* Interrupt #2 Mask Register */
#define REG_ADDR__TOP_INTR2_MASK			(TX_TOP_REG | 0x0035)
	/* (ReadWrite, Bits 7:0) */
	/* Enable for INT[13:6]: 1 - enable; 0 - disable (default) */
	#define BIT_MSK__TOP_INTR2_MASK__REG_INTR_MASK_B13_B6		0xFF

	/* Enable for INT[9:6], INT[12], INT[13];
	 * 1 - enable; 0 - disable (default)
	 * GPIO0 to GPIO3 : 0 to 1 changes
	 * GPIO0 and GPIO1: 1 to 0 changes */
	#define BIT_MASK__TOP_INTR2_MASK__REG_INTR_MASK_GEN_GPIO	0xCF

/* Interrupt #3 Mask Register */
#define REG_ADDR__TOP_INTR3_MASK			(TX_TOP_REG | 0x0036)
	/* (ReadWrite, Bits 3:0) */
	/* Enable for INT[17:14]: 1 - enable; 0 - disable (default) */
	#define BIT_MSK__TOP_INTR3_MASK__REG_INTR_MASK_B17_B14		0x0F

	/* GPIO2 and GPIO3: 1 to 0 changes*/
	#define BIT_MASK__TOP_INTR3_MASK__REG_INTR_MASK_GEN_GPIO	0x03

/* Interrupt Control Register */
#define REG_ADDR__TOP_INT_CTRL				(TX_TOP_REG | 0x0037)
	/* (ReadWrite, Bits 7)*/
	/* Mask for the final interrupt before goes to pin IRQ*/
	#define BIT_MSK__TOP_INT_CTRL__REG_GLOBAL_INTR_MASK	0x80

/* Kill Switch Reg */
#define REG_ADDR__TOP_SWHRST				(TX_TOP_REG | 0x00FF)

/* RX Freq Measure Value #0 Register*/
#define REG_ADDR__RX_FREQ_VAL0				(TX_TOP_REG | 0x0038)
	/* (ReadOnly, Bits 7:0)*/
	/* rx measured clock frequency
	 * (Fmeas = 20MHz/rx_freq_win * rx_freq_val)*/
	#define BIT_MSK__RX_FREQ_VAL0__REG_RX_FREQ_VAL_B7_B0	0xFF

/* RX Freq Measure Value #1 Register*/
#define REG_ADDR__RX_FREQ_VAL1				(TX_TOP_REG | 0x0039)
	/* (ReadOnly, Bits 7:0)*/
	/* rx measured clock frequency
	 * (Fmeas = 20MHz/rx_freq_win * rx_freq_val)*/
	#define BIT_MSK__RX_FREQ_VAL1__REG_RX_FREQ_VAL_B15_B8	0xFF

/*****************  TX EARC (6A00-60FF) ********************/

/* Audio In I2S Mode Register */
#define REG_ADDR__AUD_MODE				(TX_EARC_REG | 0x0000)
	/* (ReadWrite, Bits 0) */
	/* Audio input enable
	 * 0 - audio inputs disabled (default)
	 * 1 - audio inputs enabled */
	#define BIT_MSK__AUD_MODE__REG_AUD_IN_EN		0x01
	/* (ReadOnly, Bits 1) */
	/* Reference clock detect status: 0: clock stopped; 1: clock running
	 * Reference clock is either from SCK for I2S/DSD or
	 * from MCLK for SPDIF */
	#define BIT_MSK__AUD_MODE__I2S_CLK_STATUS		0x02

/* Audio IN I2S Data In Map Register*/
#define REG_ADDR__I2S_IN_MAP				(TX_EARC_REG | 0x0001)
	/* (ReadWrite, Bits 7:6)*/
	/* Channel map to FIFO #3 (for HDMI layout 1):
	"00" - map SD0 to FIFO #3
	"01" - map SD1 to FIFO #3
	"10" - map SD2 to FIFO #3
	"11" - map SD3 to FIFO #3 (default)*/
	#define BIT_MSK__I2S_IN_MAP__REG_FIFO3_MAP		0xC0
	/* (ReadWrite, Bits 5:4)*/
	/* Channel map to FIFO #2 (for HDMI layout 1):
	"00" - map SD0 to FIFO #2
	"01" - map SD1 to FIFO #2
	"10" - map SD2 to FIFO #2 (default)
	"11" - map SD3 to FIFO #2*/
	#define BIT_MSK__I2S_IN_MAP__REG_FIFO2_MAP		0x30
	/* (ReadWrite, Bits 3:2)*/
	/* Channel map to FIFO #1 (for HDMI layout 1):
	"00" - map SD0 to FIFO #1
	"01" - map SD1 to FIFO #1 (default)
	"10" - map SD2 to FIFO #1
	"11" - map SD3 to FIFO #1*/
	#define BIT_MSK__I2S_IN_MAP__REG_FIFO1_MAP		0x0C
	/* (ReadWrite, Bits 1:0)*/
	/* Channel map to FIFO #0 (for HDMI layout 0 or 1):
	"00" - map SD0 to FIFO #0 (default)
	"01" - map SD1 to FIFO #0
	"10" - map SD2 to FIFO #0
	"11" - map SD3 to FIFO #0*/
	#define BIT_MSK__I2S_IN_MAP__REG_FIFO0_MAP		0x03

/* Audio In I2S Control Register */
#define REG_ADDR__I2S_IN_CTRL				(TX_EARC_REG | 0x0002)
	/* (ReadWrite, Bits 6)*/
	/* SCK: Sample edge rising/falling
	0 - Sample edge is falling: SD3-SD0 and WS source should
	 change state on the rising edge of the SCK
	1 - Sample edge is rising (default): SD3-SD0 and WS source
	 should change state on the falling edge of SCK*/
	#define BIT_MSK__I2S_IN_CTRL__REG_I2S_IN_SCK_EDGE	0x40
	/* (ReadWrite, Bits 5)*/
	/* Order of the Channel Status bits in the High Bitrate stream:
	0 - Left and Right sample have consecutive C bits (default)
	1 - Left and Right sample have the same C bits*/
	#define BIT_MSK__I2S_IN_CTRL__REG_CBIT_ORDER		0x20
	/* (ReadWrite, Bits 4)*/
	/* V bit value: 0 - For PCM data (default) "1" - compressed*/
	#define BIT_MSK__I2S_IN_CTRL__REG_VBIT			0x10
	/* (ReadWrite, Bits 3)*/
	/* WS: Left/Right polarity:
	 *  0 - Left polarity when Word Select is low (default)*/
	#define BIT_MSK__I2S_IN_CTRL__REG_I2S_IN_WS		0x08
	/* (ReadWrite, Bits 2)*/
	/* SD: Left-; Right-justified:
	 *  "0" - data is Left justified;
	 *  "1" - data is right justified (default)*/
	#define BIT_MSK__I2S_IN_CTRL__REG_I2S_IN_JUSTIFY	0x04
	/* (ReadWrite, Bits 1)*/
	/* SD: MSb/LSb first: 0 - MSb first (default); 1 - LSb first*/
	#define BIT_MSK__I2S_IN_CTRL__REG_I2S_IN_DATA_DIR	0x02
	/* (ReadWrite, Bits 0)*/
	/* WS to SD: 1st-bit shift: "0" - 1st-bit shift; Philips spec.*/
	#define BIT_MSK__I2S_IN_CTRL__REG_I2S_IN_1ST_BIT	0x01


/* Audio In I2S Channel Status #1 Register */
#define REG_ADDR__I2S_CHST0				(TX_EARC_REG | 0x0003)
/*	#define BIT_MASK__AUDIO_FORMAT				0x02
	#define BIT_MASK__AUDIO_TYPE_MASK			0x38
	#define BIT_MASK__AUDIO_TYPE_SHIFT			0x03

	#define BIT_MASK__TWO_CHANNEL_WITHOUT_PRE_EMPHASIS	0x00
	#define BIT_MASK__TWO_CHANNEL_WITH_PRE_EMPHASIS		0x01
	#define BIT_MASK__MULTI_CHANNEL_LPCM			0x20
	#define BIT_MASK__NON_LPCM				0x00
	#define BIT_MASK__TWO_CHANNEL_ENCRYPTED_LPCM		0x04
	#define BIT_MASK__ENCRYPTED_NON_LPCM			0x05
	#define BIT_MASK__MULTI_CHANNEL_ENCRYPTED		0x06
*/
#define BIT_MASK__MULTI_CHANNEL_LPCM				0x20
#define BIT_MASK__NON_LPCM					0x02

/* Audio In I2S Channel Status #2 Register*/
#define REG_ADDR__I2S_CHST1				(TX_EARC_REG | 0x0004)
	/* (ReadWrite, Bits 7:0)*/
	/* The information in this register is send in Channel Status field
	 * across HDMI link.
	Category code. Please refer to SPDIF spec for detailed description.*/
	#define BIT_MSK__I2S_CHST1__REG_CBIT1			0xFF

/* Audio In I2S Channel Status #3 Register*/
#define REG_ADDR__I2S_CHST2				(TX_EARC_REG | 0x0005)
	/* (ReadWrite, Bits 7:4)*/
	/* The information in this register is send in Channel Status
	 * field across HDMI link
	 * Channel Number. Please refer to SPDIF spec
	 * for detailed description.*/
	#define BIT_MSK__I2S_CHST2__REG_CBIT2B			0xF0
	/* (ReadWrite, Bits 3:0)*/
	/* The information in this register is send in Channel Status
	 * field across HDMI link.
	 * Source number. Please refer to SPDIF spec for detailed description.*/
	#define BIT_MSK__I2S_CHST2__REG_CBIT2A			0x0F

/* Audio in I2S Channel Status #4 Register*/
#define REG_ADDR__I2S_CHST3				(TX_EARC_REG | 0x0006)
	/* (ReadWrite, Bits 7:4)*/
	/* [5:4] Clock accuracy
	[7:6] Sampling frequency extension with sampling frequency
	 bits 24 to 27
	hbra_on; aud_sample_freq[5:0];  Audio Rate
	1'b0; 2'b00; 4'b0100; 22.05 kHz (n/a)
	1'b0; 2'b00; 4'b0000; 44.1 kHz
	1'b0; 2'b00; 4'b1000; 88.2 kHz
	1'b0; 2'b00; 4'b1100; 176.4 kHz
	1'b0; 2'b00; 4'b1101; 352.8 kHz
	1'b0; 2'b10; 4'b1101; 705.6 kHz
	1'b0; 2'b01; 4'b1101; 1411.2 kHz (n/a)
	1'b0; 2'b00; 4'b0110; 24 kHz (n/a)
	1'b0; 2'b00; 4'b0010; 48 kHz
	1'b0; 2'b00; 4'b1010; 96 kHz
	1'b0; 2'b00; 4'b1110; 192 kHz
	1'b0; 2'b00; 4'b0101; 384 kHz
	1'b0; 2'b00; 4'b1001; 768 kHz
	1'b0; 2'b01; 4'b0101; 1536 kHz (n/a)
	1'b0; 2'b00; 4'b0011; 32 kHz
	1'b0; 2'b00; 4'b1011; 64 kHz
	1'b0; 2'b10; 4'b1011; 128 kHz
	1'b0; 2'b01; 4'b1011; 256 kHz
	1'b0; 2'b11; 4'b1011; 512 kHz
	1'b0; 2'b11; 4'b0101; 1024 kHz (n/a)
	1'b1; 2'b00; 4'b1100; HBRA 176.4 kHz
	1'b1; 2'b00; 4'b1101; HBRA 352.8 kHz
	1'b1; 2'b10; 4'b1101; HBRA 705.6 kHz
	1'b1; 2'b01; 4'b1101; HBRA 1411.2 kHz
	1'b1; 2'b00; 4'b1110; HBRA 192 kHz
	1'b1; 2'b00; 4'b0101; HBRA 384 kHz
	1'b1; 2'b00; 4'b1001; HBRA 768 kHz
	1'b1; 2'b01; 4'b0101; HBRA 1536 kHz
	1'b1; 2'b10; 4'b1011; HBRA 128 kHz
	1'b1; 2'b01; 4'b1011; HBRA 256 kHz
	1'b1; 2'b11; 4'b1011; HBRA 512 kHz
	1'b1; 2'b11; 4'b0101; HBRA 1024 kHz*/
	#define BIT_MSK__I2S_CHST3__REG_CBIT3B			0xF0
	/* (ReadWrite, Bits 3:0)*/
	/* The information in this register is send in Channel Status field
	 * across HDMI link.
	 * Please refer to SPDIF spec for detailed description.
	 * Sampling frequency set by software
	 * (inserted into I2S stream or into SPDIF if fs_overrride is enabled).
	 * These bits correspond to the Channel Status bits 24; 25; 26;27;
	 * where bit 24 = LSB and 27 = MSB:
	27 26 25 24
	"0   1   0   0" - Fs =   22.05 kHz
	"0   0   0   0" - Fs =   44.1 kHz
	"1   0   0   0" - Fs =   88.2 kHz
	"1   1   0   0" - Fs = 176.4 kHz
	"0   1   1   0" - Fs =   24 kHz
	"0   0   1   0" - Fs =   48 kHz
	"1   0   1   0" - Fs =   96 kHz
	"1   1   1   0" - Fs = 192 kHz
	"0   0   1   1" - Fs =   32 kHz
	"1  0  0  1" -  Fs =  768 kHz*

	All other frequencies (default)*/
	#define BIT_MSK__I2S_CHST3__REG_CBIT3A			0x0F

/* Audio In I2S Channel Status #5 Register*/
#define REG_ADDR__I2S_CHST4				(TX_EARC_REG | 0x0007)
	/* (ReadWrite, Bits 7:4)*/
	/* Original Fs*/
	#define BIT_MSK__I2S_CHST4__REG_CBIT4B			0xF0
	/* (ReadWrite, Bits 3:0)*/
	/* Reg_cbit[32] : The information in this register is
	 * send in Channel Status field
"1011" - 24 bits (default);
"1001" - 23 bits;
"0101" - 22 bits;
"1101" - 21 bits;
"0011" - 20 bits
"1010" - 20 bits
"1000" - 19 bits
"0100" - 18 bits
"1100" - 17 bits
"0010" - 16 bits
"0000" - not indicated*/
	#define BIT_MSK__I2S_CHST4__REG_CBIT4A			0x0F

							/* 40-47 */
#define REG_ADDR_TX_EARC__I2S_CHST5			(TX_EARC_REG | 0x0008)
	#define BIT_MASK__I2S_CHST5__EARC_LAYOUT		0x08

							/* 48-55 */
#define REG_ADDR_TX_EARC__I2S_CHST6			(TX_EARC_REG | 0x0009)

	#define BIT_MASK__I2S_CHST6__EARC_MUTE			0x02
	#define BIT_MASK__I2S_CHST6__EARC_CA0_CA4		0xF8
	#define BIT_MASK__I2S_CHST6__EARC_CA0_CA4_SHIFT		0x03
	#define BIT_MASK__I2S_CHST6__EARC_CA0_CA7		0xFF

							/* 56-63 */
#define REG_ADDR_I2S_CS_EXTRA1				(TX_EARC_REG | 0x000A)
	#define BIT_MASK__I2S_CS_EXTRA1__EARC_CA5_CA7		0x07
	#define BIT_MASK__I2S_CS_EXTRA1__EARC_CA5_CA7_SHIFT	0x05

#define REG_ADDR_I2S_CS_EXTRA2				(TX_EARC_REG | 0x000B)
#define BIT_MASK__I2S_CS_EXTRA2__EARC_LFE			0x03
#define BIT_MASK__I2S_CS_EXTRA2__EARC_MUTE			0x04
#define BIT_MASK__I2S_CS_EXTRA2__EARC_MUTE_SHIFT		0x02
#define BIT_MASK__I2S_CS_EXTRA2__EARC_LSV			0x78
#define BIT_MASK__I2S_CS_EXTRA2__EARC_LSV_SHIFT			0x03
#define BIT_MASK__I2S_CS_EXTRA2__EARC_DM_INH			0x80
#define BIT_MASK__I2S_CS_EXTRA2__EARC_DM_INH_SHIFT		0x07

/* Audio In I2S Input Size Register*/
#define REG_ADDR__I2S_IN_SIZE				(TX_EARC_REG | 0x000C)
	/* (ReadWrite, Bits 7:4)*/
	/* "1" swap left with right. Bit #4 for SD0; #5 for SD1;
	 * #6 for SD2; #7 for SD3*/
	#define BIT_MSK__I2S_IN_SIZE__REG_CH_IN_SWAP		0xF0
	/* (ReadWrite, Bits 3:0)*/
	/* The information in this register is used for the extraction
	 * of the I2S data from the input stream.
	Number of the valid bits in the input I2S stream; default is 24:
	"1011" - 24 bits (default);
	"1001" - 23 bits;
	"0101" - 22 bits;
	"1101" - 21 bits;
	"1010" - 20 bits
	"1000" - 19 bits
	"0100" - 18 bits
	"1100" - 17 bits
	"0010" - 16 bits*/
	#define BIT_MSK__I2S_IN_SIZE__REG_I2S_IN_LENGTH 0x0F

/* TX CS Extra Pointer Register */
#define REG_ADDR__I2S_CS_PTR				(TX_EARC_REG | 0x000D)
	/* (ReadWrite, Bits 5) */
	/* tells starting byte of inserting 2 extra channel status bytes */
	#define BIT_MSK__I2S_CS_PTR__REG_CS_UPDATE_EN		0x20
	/* tells starting byte of inserting 2 extra channel status bytes */
	#define BIT_MSK__I2S_CS_PTR__REG_CS_PTR			0x1F
	#define BIT_MSK__I2S_CS_PTR__REG_CS_OFFSET		0x11

/* TX Audio In SPDIF Mode Register */
#define REG_ADDR__TX_SPDIF_MODE				(TX_EARC_REG | 0x000E)
	/* (ReadWrite, Bits 4)*/
	/* when enabled then max # for 2UI is adjusted by adding +1 to it*/
	#define BIT_MSK__TX_SPDIF_MODE__REG_MAX_2UI_ADJ_EN	0x10
	/* (ReadWrite, Bits 3)*/
	/* enable to except value specified in F Premable register*/
	#define BIT_MSK__TX_SPDIF_MODE__REG_F_PREAMBLE_EN	0x08
	/* (ReadWrite, Bits 2)*/
	/* "1" to bypass sampling logic*/
	#define BIT_MSK__TX_SPDIF_MODE__REG_TX_BYP_SAMPLER	0x04
	/* (ReadWrite, Bits 1)*/
	/* SPDIF input enable.
	* 0 - SPDIF input stream is disabled (default)
	* 1 - SPDIF input stream is enabled.
	* NOTE: This bit must also be set in case of parallel audio input
	* if the audio format is SPDIF in order to ensure correct use of
	* audio header type.*/
	#define BIT_MSK__TX_SPDIF_MODE__REG_TX_SPDIF_EN		0x02

/* TX Audio IN SPDIF Channel Status #1 Register */
#define REG_ADDR__TX_CHST0				(TX_EARC_REG | 0x0017)

/* TX Audio IN SPDIF Channel Status #2 Register*/
#define REG_ADDR__TX_CHST1				(TX_EARC_REG | 0x0018)
	/* (ReadOnly, Bits 7:0) */
	/* Category Code. Bit 8 - LSB; bit 15 - MSB */
	#define BIT_MSK__TX_CHST1__BIT15_8			0xFF

/* TX Audio IN SPDIF Channel Status #3 Register */
#define REG_ADDR__TX_CHST2				(TX_EARC_REG | 0x0019)
	/* (ReadOnly, Bits 7:4)*/
	/* Channel number; bit 20 - LSB; bit 23 MSB:
	"0000" - Do not take into account
	"1000" - A (Left channel for stereo channel format)
	"0100" - B (right channel for stereo channel format)
	"1100" - C
	- - - - -
	"1111" - O

	The Channel number is specific to the channel */
	#define BIT_MSK__TX_CHST2__AUD_CH_NUM1			0xF0
	/* (ReadOnly, Bits 3:0)*/
	/* Source number; bit 16 - LSB; bit 19 MSB:
	"0000" - Do not take into account
	"1000" - 1
	"0100" - 2
	"1100" - 3
	- - - - -
	"1111" - 15

	The source number is specific to the channel */
	#define BIT_MSK__TX_CHST2__AUD_SOURCE1			0x0F

/* TX Audio IN SPDIF Channel Status #4 Register */
#define REG_ADDR__TX_CHST3				(TX_EARC_REG | 0x001A)
	/* (ReadOnly, Bits 7:6) */
	/* Sampling frequency Extension.These bits correspond to the Channel
	 * Status bits 30; 31; where bit 30 = LSB and 31 = MSB.
	Sampling frequency extension with sampling frequency bits 24 to 27:
	31 30 27 26 25 24
	"0   0   0   1   0   1" - Fs = 384 kHz
	"0   1   0   1   0   1" - Fs = 1536 kHz
	"1   1   0   1   0   1" - Fs = 1024 kHz
	"0   0   1   1   0   1" - Fs = 3528 kHz
	"1   0   1   1   0   1" - Fs = 7056 kHz
	"0   1   1   1   0   1" - Fs = 14112 kHz
	"0   0   1   0   1   1" - Fs = 64 kHz
	"1   0   1   0   1   1" - Fs = 128 kHz
	"0   1   1   0   1   1" - Fs = 256 kHz
	"1   1   1   0   1   1" - Fs = 512 kHz*/
	#define BIT_MSK__TX_CHST3__AUD_SAMPLE_F_EXTN		0xC0
	/* (ReadOnly, Bits 5:4) */
	/* Clock accuracy:
	"00" Level II
	"10" Level I
	"01" Level III */
	#define BIT_MSK__TX_CHST3__AUD_ACCURACY			0x30
	/* (ReadOnly, Bits 3:0) */
	/* Sampling frequency.These bits correspond to the Channel Status \
	 * bits 24; 25; 26;27; where bit 24 = LSB and 27 = MSB:
	27 26 25 24
	"0   1   0   0" - Fs =   22.05 kHz
	"0   0   0   0" - Fs =   44.1 kHz
	"1   0   0   0" - Fs =   88.2 kHz
	"1   1   0   0" - Fs = 176.4 kHz
	"0   1   1   0" - Fs =   24 kHz
	"0   0   1   0" - Fs =   48 kHz
	"1   0   1   0" - Fs =   96 kHz
	"1   1   1   0" - Fs = 192 kHz
	"0   0   1   1" - Fs =   32 kHz
	"1  0  0  1" -  Fs =  768 kHz (192 x 4) for High Bit Rate Audio
	"? ? ? ?" -  Fs =  384 kHz (94 x 4) for High Bit Rate Audio
	"0   0   0   1" Sampling frequency not indicated */
	#define BIT_MSK__TX_CHST3__AUD_SAMPLE_F			0x0F

/* Audio Out SPDIF Channel Status #5 Register */
#define REG_ADDR__TX_CHST4				(TX_EARC_REG | 0x001B)
	/* (ReadOnly, Bits 7:4)*/
	/* Original Fs*/
	#define BIT_MSK__TX_CHST4__AUD_ORG_FS			0xF0
	/* (ReadOnly, Bits 3:1)*/
	/* Channel Status bits 33 to 35; where bit 33 = LSB and 35 = MSB
		      max 24                               max 20
	"000"      not indiacated (default)          not indiacated (default)
	"001"      20 bits                                 16 bits
	"010"      22 bits                                 18 bits
	"100"      23 bits                                 19 bits
	"101"      24 bits                                 20 bits
	"110"      21 bits                                 17 bits */
	#define BIT_MSK__TX_CHST4__AUD_LENGTH			0x0E
	/* (ReadOnly, Bits 0)*/
	/* Channel Status bits32:
	"0" - Max audio sample word length is 20 bits
	"1" - Max audio sample word length is 24 bits */
	#define BIT_MSK__TX_CHST4__AUD_LENGTH_MAX		0x01

/* TX Audio IN SPDIF Channel Status #6 Register*/
#define REG_ADDR__TX_CHST5				(TX_EARC_REG | 0x001C)
	/* (ReadOnly, Bits 7:4)*/
	/* Audio sampling frequency coefficient. These bits correspond to the
	 * Channel Status bits 44; 45; 46;47; where bit 44 = LSB and 47 = MSB:
	47 46 45 44
	"0   0   0   0" - Fs_coeff =   No indication
	"1   0   0   0" - Fs_coeff =   Equal to transmission sampling frequency
	"0   1   0   0" - Fs_coeff =   1/2
	"1   1   0   0" - Fs_coeff =   1/4
	"0   0   1   0" - Fs_coeff =   1/8
	"1   0   1   0" - Fs_coeff =   1/16
	"0   1   1   0" - Fs_coeff =   1/32
	"1   1   1   0" - Fs_coeff =   Reserved
	"0   0   0   1" - Fs_coeff =   Reserved
	"1   0   0   1" - Fs_coeff =   Reserved
	"0   1   0   1" - Fs_coeff =   Reserved
	"1   1   0   1" - Fs_coeff =   x32
	"0   0   1   1" - Fs_coeff =   x16
	"1   0   1   1" - Fs_coeff =   x8
	"0   1   1   1" - Fs_coeff =   x4
	"1   1   1   1" - Fs_coeff =   x2*/
	#define BIT_MSK__TX_CHST5__AUD_SAMPLE_F_COEFF		0xF0
	/* (ReadOnly, Bits 3)*/
	/* Not indicated.*/
	#define BIT_MSK__TX_CHST5__BIT43			0x08
	/* (ReadOnly, Bits 2) */
	/* CGMS-A validity
	0 - No indication
	1 - CGMS-A valid */
	#define BIT_MSK__TX_CHST5__CGMS_A_VALIDITY		0x04
	/* (ReadOnly, Bits 1:0) */
	/* CGMS-A */
	#define BIT_MSK__TX_CHST5__CGMS_A			0x03

/* TX Audio IN SPDIF Channel Status #7 Register */
#define REG_ADDR__TX_CHST6				(TX_EARC_REG | 0x001D)
	/* (ReadOnly, Bits 7:1) */
	/* Reserved (0000000). */
	#define BIT_MSK__TX_CHST6__BIT55_49			0xFE
	/* (ReadOnly, Bits 0) */
	/* Information hidden in PCM signal;
	0 - No indication
	1 - Additional information in LSB */
	#define BIT_MSK__TX_CHST6__INFO_IN_PCM_SIGNAL		0x01

/* TX CS Extra Byte#1 Register */
#define REG_ADDR__TX_CS_EXTRA1				(TX_EARC_REG | 0x001E)
	/* (ReadOnly, Bits 7:0) */
	/* Extra Channel Status byte #1. pointed by I2S_CS_PTR */
	#define BIT_MSK__TX_CS_EXTRA1__AUD_CS_EXTR1		0xFF

/* TX CS Extra Byte#2 Register */
#define REG_ADDR__TX_CS_EXTRA2				(TX_EARC_REG | 0x001F)
	/* (ReadOnly, Bits 7:0) */
	/* Extra Channel Status byte #2 */
	#define BIT_MSK__TX_CS_EXTRA2__AUD_CS_EXTR2		0xFF

/* TX DSD Audio Config Register */
#define REG_ADDR__TX_SPDIF_CS_CTRL			(TX_EARC_REG | 0x0021)
	/* (ReadWrite, Bits 1)*/
	/* override SPDIF V bit*/
	#define BIT_MSK__TX_SPDIF_CS_CTRL__REG_VBIT_OVERRIDE	0x02
	/* (ReadWrite, Bits 0) */
	/* override SPDIF Channel Status; share the same Channel
	 * Status registers with I2S and DSD */
	#define BIT_MSK__TX_SPDIF_CS_CTRL__REG_CBIT_OVERRIDE	0x01


/* Tx SPDIF B Sync Ctrl Register */
#define REG_ADDR__BSYNC_CTRL				(TX_EARC_REG | 0x0028)

/* Bsync Preamble Value Register */
#define REG_ADDR__BSYNC_VAL				(TX_EARC_REG | 0x0029)

/* Tx CS Debug1 Register */
#define REG_ADDR__TX_CS_DEBUG1				(TX_EARC_REG | 0x002D)

/* Tx CS Debug2 Register */
#define REG_ADDR__TX_CS_DEBUG2				(TX_EARC_REG | 0x002E)

/* Tx CS Debug3 Register */
#define REG_ADDR__TX_CS_DEBUG3				(TX_EARC_REG | 0x002F)

/* tx mute control */
#define REG_ADDR__MUTE_CTRL				(TX_EARC_REG | 0x0030)
	/* mute zero data send over earc */
	#define BIT_MSK__MUTE_CTRL__REG_MUTE_EN			0x01

/* tx mute control 2 */
#define REG_ADDR__TX_MUTE_CTRL_2			(TX_EARC_REG | 0x0031)
/* tx mute control 3 */
#define REG_ADDR__TX_MUTE_CTRL_3			(TX_EARC_REG | 0x0032)

/* TX Mute ctrl 4 Register*/
#define REG_ADDR__TX_HW_MUTE_ST				(TX_EARC_REG | 0x0033)
	/* (ReadOnly, Bits 0)*/
	/* 1: the hardware mute condition is detected;
	 * it will trigger interrupt (reg_intr_tx_stat15).
	 * Only if the interrupt bit is cleared the mute status
	 * is release (mute_out = 0)*/
	#define BIT_MSK__TX_HW_MUTE_ST__TX_MUTE_HW		0x01

/* Comma Detect13 Register*/
#define REG_ADDR__COMMA_DET13				(TX_EARC_REG | 0x004D)
	/* (ReadWrite, Bits 7:0)*/
	/* comma detect success when got
	 * reg_comma_detect_thrd number of 10msCOMMAs.*/
	#define BIT_MSK__COMMA_DET13__REG_COMMA_DETECT_THRD_B7_B0 0xFF

/* PKT TOP TX12 Register*/
#define REG_ADDR__PKT_TOP_TX12				(TX_EARC_REG | 0x005C)
	/* (ReadWrite, Bits 0)*/
	/* clear ecc error counter*/
	#define BIT_MSK__PKT_TOP_TX12__REG_CMC_TX_PKT_ECC_ERR_CLR	0x01

/* PKT TOP TX13 Register*/
#define REG_ADDR__PKT_TOP_TX13				(TX_EARC_REG | 0x005D)
	/* (ReadOnly, Bits 7:0)*/
	/* count for ecc errors*/
	#define BIT_MSK__PKT_TOP_TX13__REG_CMC_TX_PKT_ECC_ERR_CNT_B7_B0	0xFF

/* PKT TOP TX14 Register*/
#define REG_ADDR__PKT_TOP_TX14				(TX_EARC_REG | 0x005E)
	/* (ReadOnly, Bits 7:0)*/
	/* */
	#define BIT_MSK__PKT_TOP_TX14__REG_CMC_TX_PKT_ECC_ERR_CNT_B15_B8 0xFF

/* PKT TOP TX15 Register*/
#define REG_ADDR__PKT_TOP_TX15				(TX_EARC_REG | 0x0065)
	/* (ReadWrite, Bits 0)*/
	/* clear ecc error fix counter*/
	#define BIT_MSK__PKT_TOP_TX15__REG_CMC_TX_PKT_ECC_FIX_CLR	0x01

/* PKT TOP TX16 Register*/
#define REG_ADDR__PKT_TOP_TX16				(TX_EARC_REG | 0x0066)
	/* (ReadOnly, Bits 7:0)*/
	/* count for ecc errors fixed*/
	#define BIT_MSK__PKT_TOP_TX16__REG_CMC_TX_PKT_ECC_FIX_CNT_B7_B0	0xFF

/* PKT TOP TX17 Register*/
#define REG_ADDR__PKT_TOP_TX17				(TX_EARC_REG | 0x0067)
	/* (ReadOnly, Bits 7:0)*/
	/* */
	#define BIT_MSK__PKT_TOP_TX17__REG_CMC_TX_PKT_ECC_FIX_CNT_B15_B8 0xFF

/* DISC_DISCONN_TX3  Register */
#define REG_ADDR__DISC_DISCONN_TX3			(TX_EARC_REG | 0x0073)
	/* (ReadWrite, Bits 7:0) */
	/* From start monitoring for commas to timeout due to no response
	 * to start of heartbeat sequence; unit is ms */
	#define BIT_MSK__DISC_DISCONN_TX3__REG_TX_TIMEOUT	0xFF

/* DISC_DISCONN_TX4  Register*/
#define REG_ADDR__DISC_DISCONN_TX4			(TX_EARC_REG | 0x0074)
	/* (ReadWrite, Bits 7)*/
	/* tx timeout software override enable; 1- use reg_tx_timeout_sw_ctrl*/
	#define BIT_MSK__DISC_DISCONN_TX4__REG_TX_TIMEOUT_SW_CTRL_EN 0x80
	/* (ReadWrite, Bits 6)*/
	/* tx timeout software override value*/
	#define BIT_MSK__DISC_DISCONN_TX4__REG_TX_TIMEOUT_SW_CTRL 0x40
	/* (ReadWrite, Bits 1:0)*/
	/* From start monitoring for commas to timeout due to no response to
	 * start of heartbeat sequence; unit is ms*/
	#define BIT_MSK__DISC_DISCONN_TX4__REG_TX_TIMEOUT_B9_B8 0x03

/* DISC_DISCONN_TX7  Register */
#define REG_ADDR__DISC_DISCONN_TX7			(TX_EARC_REG | 0x0077)
	/* (ReadOnly, Bits 7) */
	/* "1" means tx is in EARC and connection is established; "0" means
	 * tx exits from EARC state and connection is lost */
	#define BIT_MSK__DISC_DISCONN_TX7__REG_TX_EARC_CONNECTION_STATUS 0x80
	/* (ReadOnly, Bits 2:0)*/
	/* tx discovery and disconnect state; for debug*/
	#define BIT_MSK__DISC_DISCONN_TX7__REG_TX_DISC_DISCONN_STATE_B2_B0 0x07

/* DISC_DISCONN_TX8  Register*/
#define REG_ADDR__DISC_DISCONN_TX8			(TX_EARC_REG | 0x0078)
	/* (ReadWrite, Bits 7)*/
	/* state mode select; 1-new mode; no IDLE2; 0- old mode with IDLE2*/
	#define BIT_MSK__DISC_DISCONN_TX8__TX_DISC_CONN_ST_NO_IDLE2	0x80
	/* (ReadWrite, Bits 6)*/
	/* 1-eARC state can be disabled by HPD going low;
	 * 0- eARC state can not be disabled by HDP going low*/
	#define BIT_MSK__DISC_DISCONN_TX8__REG_TX_HPD_DISABLE_EARC_EN	0x40
	/* (ReadWrite, Bits 3)*/
	/* tx discovery and disconnect state override enable*/
	#define BIT_MSK__DISC_DISCONN_TX8__REG_TX_DISC_CONN_ST_OVERRIDE_EN 0x08
	/* (ReadWrite, Bits 2:0)*/
	/* tx discovery and disconnect state override value*/
	#define BIT_MSK__DISC_DISCONN_TX8__REG_TX_DISC_DISCON_ST_OVR_B2_B0 0x07


/* CMC_MASTER_TX7  Register*/
#define REG_ADDR__CMC_MASTER_TX7			(TX_EARC_REG | 0x0087)
	/* (ReadWrite, Bits 7:0)*/
	/* eARC Tx/Source status at offset 0xD1 on eARC. Each bit will be sent
	 * by heartbeat over eARC if the corresponding bit in register at 0x88
	 * is set. HDMI HPD from the pin will be sent if 0x88[0] is not set
	 * eARC_Valid from eARC discovery state machine will be sent if 0x88[7]
	 * is not set*/
	#define BIT_MSK__CMC_MASTER_TX7__REG_TX_HB_STATUS_OVERRIDE_B7_B0 \
								0xFF
	/* HDMI HPD Status */
	#define BIT_MASK__CMC_MASTER_TX7__REG_TX_HB_STATUS_OVERRIDE_B0 \
								0x01
	/* CAP CNG CONF HPD Status */
	#define BIT_MASK__CMC_MASTER_TX7__REG_TX_HB_STATUS_OVERRIDE_B3 \
								0x08
	/* STAT CHNG CONF HPD Status */
	#define BIT_MASK__CMC_MASTER_TX7__REG_TX_HB_STATUS_OVERRIDE_B4 \
								0x10

/* CMC_MASTER_TX8  Register*/
#define REG_ADDR__CMC_MASTER_TX8			(TX_EARC_REG | 0x0088)
	/* (ReadWrite, Bits 7:0)*/
	/* eARC Tx/Source status override register.
	 * Please see the description for the register at 0x87*/
	#define BIT_MSK__CMC_MASTER_TX8__REG_TX_STATUS_OVERRIDE_EN_B7_B0 \
								0xFF
	/* HDMI HPD status override enable */
	#define BIT_MASK__CMC_MASTER_TX8__REG_TX_HDMI_HPD_STAT_OVERRIDE	0x01
	/* CAP_CNG_CONF status override enable */
	#define BIT_MASK__CMC_MASTER_TX8__REG_TX_CAP_CNG_CONF_OVR	0x08
	/* STAT_CHNG_CONF status override enable */
	#define BIT_MASK__CMC_MASTER_TX8__REG_TX_STAT_CHNG_CONF_OVR	0x10

/* CMC_MASTER_TX16  Register*/
#define REG_ADDR__CMC_MASTER_TX16			(TX_EARC_REG | 0x0090)
	/* (ReadWrite, Bits 1)*/
	#define BIT_MSK__CMC_MASTER_TX16__REG_CEC_ARC_TERM	0x02
	/* (ReadWrite, Bits 0)*/
	#define BIT_MSK__CMC_MASTER_TX16__REG_CEC_ARC_INIT	0x01

#define REG_ADDR__CMC_MASTER_TX19			(TX_EARC_REG | 0x0093)
	/* (ReadOnly, Bits 7:0)*/
	/* eARC Rx/Sink status at offset 0xD0 on eARC.
	 *  Fetched by heartbeat over eARC CMC
	bit 0: eARC_HPD
	bit 3: Re_Read_EDID*/
	#define BIT_MSK__CMC_MASTER_TX19__REG_RX_HB_STATUS_B7_B0	0xFF
	#define BIT_MSK__CMC_MASTER_TX19___EARC_HPD		0x01
	#define BIT_MSK__CMC_MASTER_TX19___CAP_CHNG		0x08
	#define BIT_MSK__CMC_MASTER_TX19___STAT_CHNG		0x10

/* CMC_MASTER_TX21  Register*/
#define REG_ADDR__CMC_MASTER_TX21			(TX_EARC_REG | 0x0095)
	/* (ReadWrite, Bits 7:0)*/
	/* software access address*/
	#define BIT_MSK__CMC_MASTER_TX21__REG_SW_ACC_ADDR_B7_B0 0xFF

/* CMC_MASTER_TX22  Register*/
#define REG_ADDR__CMC_MASTER_TX22			(TX_EARC_REG | 0x0096)
	/* (ReadWrite, Bits 7:0)*/
	/* software access offset*/
	#define BIT_MSK__CMC_MASTER_TX22__REG_SW_ACC_OFFSET_B7_B0	0xFF

/* CMC_MASTER_TX23  Register*/
#define REG_ADDR__CMC_MASTER_TX23			(TX_EARC_REG | 0x0097)
	/* (ReadWrite, Bits 7:0)*/
	/* software write data*/
	#define BIT_MSK__CMC_MASTER_TX23__REG_SW_ACC_WDATA_B7_B0	0xFF

/* CMC_MASTER_TX24  Register*/
#define REG_ADDR__CMC_MASTER_TX24			(TX_EARC_REG | 0x0098)
	/* (ReadOnly, Bits 7:0)*/
	/* software read back data*/
	#define BIT_MSK__CMC_MASTER_TX24__REG_SW_ACC_RDATA_B7_B0	0xFF

/* CMC_MASTER_TX25  Register*/
#define REG_ADDR__CMC_MASTER_TX25			(TX_EARC_REG | 0x0099)
	/* (ReadOnly, Bits 7:0)*/
	/* software access status
	bit0-"1" means SW access done and succeed
	bit1-"1" means SW access failed*/
	#define BIT_MSK__CMC_MASTER_TX25__REG_SW_ACC_STATUS_B7_B0	0xFF
	#define BIT_MASK__SW_ACCESS_SUCCESS			0x01
	#define BIT_MASK__SW_ACCESS_FAILED			0x02

/* CMC_MASTER_TX26  Register*/
#define REG_ADDR__CMC_MASTER_TX26			(TX_EARC_REG | 0x009A)
	/* (ReadWrite, Bits 1:0)*/
	/* software access opcode; 1-write; 2-read; others-unvalid*/
	#define BIT_MSK__CMC_MASTER_TX26__REG_SW_ACC_OP_B1_B0	0x03
	#define BIT_MSK__CMC_MASTER_TX26__REG_SW_ACC_OP_WRITE	0x01
	#define BIT_MSK__CMC_MASTER_TX26__REG_SW_ACC_OP_READ	0x02

/* CMC_MASTER_TX27  Register*/
#define REG_ADDR__CMC_MASTER_TX27			(TX_EARC_REG | 0x009B)
	/* (ReadWrite, Bits 7:2)*/
	/* wait cycle numbers before new access is granted*/
	#define BIT_MSK__CMC_MASTER_TX27__WAIT_CYC_BF_NEW_GNT_B5_B0	0xFC
	/* (ReadWrite, Bits 1)*/
	/* the override value*/
	#define BIT_MSK__CMC_MASTER_TX27__HPD_IN_OVRD_VAL	0x02
	/* (ReadWrite, Bits 0)*/
	/* 1- override the input HPD value*/
	#define BIT_MSK__CMC_MASTER_TX27__HPD_IN_OVRD		0x01

/* Interrupt State Register */
#define REG_ADDR__INTR_STATE				(TX_EARC_REG | 0x00B0)

	/* (ReadOnly, Bits 0)*/
	/* Interrupt state bit value. It shows whether the interrupt output
	 * signal on INT pin is active or not.  1' indicates that at least one
	 * masked interrupt has been asserted. This bit can only be cleared by
	 * SW; either by unmasking all asserted interrupts or by clearing all
	 * asserted interrupts.*/
	#define BIT_MSK__INTR_STATE__INTR_STATE			0x01

/* Interrupt Source #0 Register */
#define REG_ADDR__INTR0					(TX_EARC_REG | 0x00B1)

/* Interrupt Source #1 Register */
#define REG_ADDR__INTR1					(TX_EARC_REG | 0x00B2)
	/* (ReadWrite, Bits 7)*/
	/* "1'" detected mute exceptiom & set MUTE_OUT.
	 *  Read mute status register for details*/
	#define BIT_MSK__INTR1__REG_INTR_TX_STAT15		0x80
	/* (ReadWrite, Bits 4)*/
	/* "1" Tx spdif Fs changed*/
	#define BIT_MSK__INTR1__REG_INTR_TX_STAT12		0x10
	/* (ReadWrite, Bits 3)*/
	/* Tx sync FIFO betwwen I2S and SPDIF is in error;
	 *  because tried to pop from empty FIFO*/
	#define BIT_MSK__INTR1__REG_INTR_TX_STAT11		0x08
	/* (ReadWrite, Bits 2)*/
	/* TX CMDC discovery state jumps to DISC1*/
	#define BIT_MSK__INTR1__REG_INTR_TX_STAT10		0x04
	/* (ReadWrite, Bits 1)*/
	/* TX CMDC discovery state jumps to IDLE2*/
	#define BIT_MSK__INTR1__REG_INTR_TX_STAT9		0x02
	/* (ReadWrite, Bits 0)*/
	/* Tx sync FIFO betwwen I2S and SPDIF is half full (4) from pop side*/
	#define BIT_MSK__INTR1__REG_INTR_TX_STAT8 0x01

/* Interrupt Source #2 Register */
#define REG_ADDR__INTR2					(TX_EARC_REG | 0x00B3)
	/* (ReadWrite, Bits 7)*/
	/* packet received timeout interrupt*/
	#define BIT_MSK__INTR2__REG_INTR_TX_STAT23		0x80
	/* (ReadWrite, Bits 6)*/
	/* "1" means common mode channel data transaction aborts (failed)*/
	#define BIT_MSK__INTR2__REG_INTR_TX_STAT22		0x40
	/* (ReadWrite, Bits 5)*/
	/* SPDIF parity error. Write "1" to clear*/
	#define BIT_MSK__INTR2__REG_INTR_TX_STAT21		0x20
	/* (ReadWrite, Bits 4)*/
	/* Did not found expected preamble.
	 * Asserted if set to 1.
	 * Write '1' to clear this bit.*/
	#define BIT_MSK__INTR2__REG_INTR_TX_STAT20		0x10
	/* (ReadWrite, Bits 3)*/
	/* DSD stream got invalid sequence:
	 * more then 24 bits of the same value.
	 * Asserted if set to 1. Write 1 to clear*/
	#define BIT_MSK__INTR2__REG_INTR_TX_STAT19		0x08
	/* (ReadWrite, Bits 2)*/
	/* New preamble forced to drop sample.
	 * Asserted if set to 1. Write '1' to clear this bit.*/
	#define BIT_MSK__INTR2__REG_INTR_TX_STAT18		0x04
	/* (ReadWrite, Bits 1)*/
	/* Input SPDIF stream had bi-phase error.
	 * Asserted if set to 1. Write '1' to clear this bit.*/
	#define BIT_MSK__INTR2__REG_INTR_TX_STAT17		0x02
	/* (ReadWrite, Bits 0)*/
	/* "1" means that the reference clock has either stopped or started.
	 * For status check reg. 0x00 (AUD_MODE) bit #2*/
	#define BIT_MSK__INTR2__REG_INTR_TX_STAT16		0x01

/* Interrupt Source #3 Register */
#define REG_ADDR__INTR3					(TX_EARC_REG | 0x00B4)
	/* (ReadWrite, Bits 7)*/
	/* "1" means that TX heartbeat failed*/
	#define BIT_MSK__INTR3__REG_INTR_TX_STAT31		0x80
	/* (ReadWrite, Bits 6)*/
	/* "1" means that tx heartbeat status changed.*/
	#define BIT_MSK__INTR3__REG_INTR_TX_STAT30		0x40
	/* (ReadWrite, Bits 5)*/
	/* ackdw retry interrupt*/
	#define BIT_MSK__INTR3__REG_INTR_TX_STAT29		0x20
	/* (ReadWrite, Bits 4)*/
	/* cont retry interrupt*/
	#define BIT_MSK__INTR3__REG_INTR_TX_STAT28		0x10
	/* (ReadWrite, Bits 3)*/
	/* Tx discovery timeout due to no comma received*/
	#define BIT_MSK__INTR3__REG_INTR_TX_STAT27		0x08
	/* (ReadWrite, Bits 2)*/
	/* Tx heartbeat is successful*/
	#define BIT_MSK__INTR3__REG_INTR_TX_STAT26		0x04
	/* (ReadWrite, Bits 1)*/
	/* Tx received NACK after sending device ID*/
	#define BIT_MSK__INTR3__REG_INTR_TX_STAT25		0x02
	/* (ReadWrite, Bits 0)*/
	/* wrong packet received interrupt*/
	#define BIT_MSK__INTR3__REG_INTR_TX_STAT24		0x01

/* Interrupt Source #4 Register */
#define REG_ADDR__INTR4					(TX_EARC_REG | 0x00B5)
	/* (ReadWrite, Bits 7)*/
	/* "1" means that the pkt tx received has uncorrectable parity err*/
	#define BIT_MSK__INTR4__REG_INTR_TX_STAT39		0x80
	/* (ReadWrite, Bits 6)*/
	/* "1" means the channel status gets changed*/
	#define BIT_MSK__INTR4__REG_INTR_TX_STAT38		0x40
	/* (ReadWrite, Bits 5)*/
	/* "1" means the left and right channel status are not identical;
	 * only if "reg_lr_match_en" is set this interrupt will be enabled*/
	#define BIT_MSK__INTR4__REG_INTR_TX_STAT37		0x20
	/* (ReadWrite, Bits 4)*/
	/* TX CMDC discovery state jumps to eARC*/
	#define BIT_MSK__INTR4__REG_INTR_TX_STAT36		0x10
	/* (ReadWrite, Bits 3)*/
	/* TX CMDC discovery state jumps to ARC*/
	#define BIT_MSK__INTR4__REG_INTR_TX_STAT35		0x08
	/* (ReadWrite, Bits 2)*/
	/* TX CMDC discovery state jumps to DISC2*/
	#define BIT_MSK__INTR4__REG_INTR_TX_STAT34		0x04
	/* (ReadWrite, Bits 1)*/
	/* "1" tx audi spdif new fs changed*/
	#define BIT_MSK__INTR4__REG_INTR_TX_STAT33		0x02
	/* (ReadWrite, Bits 0)*/
	/* "1" means that tx heartbeat lost*/
	#define BIT_MSK__INTR4__REG_INTR_TX_STAT32		0x01

/* Interrupt Source #5 Register */
#define REG_ADDR__INTR5					(TX_EARC_REG | 0x00B6)
	/* (ReadWrite, Bits 7)*/
	/* "1" means that received rx heartbeat status bit[7] changed.*/
	#define BIT_MSK__INTR5__REG_INTR_TX_STAT47		0x80
	/* (ReadWrite, Bits 6)*/
	/* "1" means that received rx heartbeat status bit[6] changed.*/
	#define BIT_MSK__INTR5__REG_INTR_TX_STAT46		0x40
	/* (ReadWrite, Bits 5)*/
	/* "1" means that received rx heartbeat status bit[5] changed.*/
	#define BIT_MSK__INTR5__REG_INTR_TX_STAT45		0x20
	/* (ReadWrite, Bits 4)*/
	/* "1" means that received rx heartbeat status bit[4] changed.
	 * (STAT_CHNG) changed*/
	#define BIT_MSK__INTR5__REG_INTR_TX_STAT44		0x10
	/* (ReadWrite, Bits 3)*/
	/* "1" means that received rx heartbeat status bit[3]
	 * (CAP_CHNG) changed.*/
	#define BIT_MSK__INTR5__REG_INTR_TX_STAT43		0x08
	/* (ReadWrite, Bits 2)*/
	/* "1" means that received rx heartbeat status bit[2].*/
	#define BIT_MSK__INTR5__REG_INTR_TX_STAT42		0x04
	/* (ReadWrite, Bits 1)*/
	/* "1" means that received rx heartbeat status bit[1] changed.*/
	#define BIT_MSK__INTR5__REG_INTR_TX_STAT41		0x02
	/* (ReadWrite, Bits 0)*/
	/* "1" means that received rx heartbeat status bit[0]
	 * (eARC-HPD) changed.*/
	#define BIT_MSK__INTR5__REG_INTR_TX_STAT40		0x01

/* Interrupt Source #6 Register */
#define REG_ADDR__INTR6					(TX_EARC_REG | 0x00B7)
	/* (ReadWrite, Bits 5)*/
	/* "1" means that tx earc connection status changed*/
	#define BIT_MSK__INTR6__REG_INTR_TX_STAT53		0x20
	/* (ReadWrite, Bits 4)*/
	/* "1" means that pkt transmit state timeout*/
	#define BIT_MSK__INTR6__REG_INTR_TX_STAT52		0x10
	/* (ReadWrite, Bits 3)*/
	/* "1" means that software access is  done*/
	#define BIT_MSK__INTR6__REG_INTR_TX_STAT51		0x08
	/* (ReadWrite, Bits 2)*/
	/* "1" means that received rx heartbeat status changed.*/
	#define BIT_MSK__INTR6__REG_INTR_TX_STAT50 0x04
	/* (ReadWrite, Bits 1)*/
	/* "1" means that one pkt ecc err is fixed*/
	#define BIT_MSK__INTR6__REG_INTR_TX_STAT49		0x02
	/* (ReadWrite, Bits 0)*/
	/* "1" means that the pkt tx received has uncorrectable ecc err*/
	#define BIT_MSK__INTR6__REG_INTR_TX_STAT48		0x01

/* Interrupt #0 Mask Register */
#define REG_ADDR__INTR0_MASK				(TX_EARC_REG | 0x00B8)
	#define BIT_MASK_TX__FIFO_FULL_ERR			0x20

	/* TX CMDC discovery state jumps to IDLE1*/
	#define BIT_MASK__INTR0_MASK__STATE_IDLE1		0x04

/* Interrupt #1 Mask Register */
#define REG_ADDR__INTR1_MASK				(TX_EARC_REG | 0x00B9)
	#define BIT_MASK_TX__ENCRYPING				0x20

	/* TX CMDC discovery state jumps to DISC1*/
	#define BIT_MASK__INTR1_MASK__STATE_DISC1		0x04
	/* (ReadWrite, Bits 1)*/
	/* TX CMDC discovery state jumps to IDLE2*/
	#define BIT_MASK__INTR1_MASK__STATE_IDLE2		0x02
	/* "1'" detected mute exceptiom & set MUTE_OUT.
	 *  Read mute status register for details*/
	#define BIT_MASK__INTR1_MASK__MUTE_EXCEP_DET		0x80

/* Interrupt #2 Mask Register */
#define REG_ADDR__INTR2_MASK				(TX_EARC_REG | 0x00BA)
	#define BIT_MASK_TX__CLK_CHANGED			0x01

/* Interrupt #3 Mask Register */
#define REG_ADDR__INTR3_MASK				(TX_EARC_REG | 0x00BB)
	#define BIT_MASK_TX__HEARTBEAT_SUCCESS			0x04
	#define BIT_MASK_TX__TIMEOUT_NO_COMMA			0x08
	#define BIT_MASK_TX__HEARTBEAT_STATUS_CHANGE		0x40
	#define BIT_MASK_TX__HEARTBEAT_FAILED			0x80

/* Interrupt #4 Mask Register */
#define REG_ADDR__INTR4_MASK				(TX_EARC_REG | 0x00BC)
	#define BIT_MASK_TX__HEARTBEAT_LOST			0x01
	/* channel status gets changed*/
	#define BIT_MASK__INTR4_MASK__CH_STATUS_CHANGED		0x40

	#define BIT_MASK__INTR4_MASK__STATE_EARC		0x10
	#define BIT_MASK__INTR4_MASK__STATE_ARC			0x08
	#define BIT_MASK__INTR4_MASK__STATE_DISC2		0x04

#define REG_ADDR__INTR5_MASK				(TX_EARC_REG | 0x00BD)
	#define BIT_MASK_TX__EARC_HPD				0x01
	#define BIT_MASK__INTR5_MASK__CAP_CHNG			0x08
	#define BIT_MASK_TX__STAT_CHNG				0x10
#define REG_ADDR__INTR6_MASK				(TX_EARC_REG | 0x00BE)
	#define BIT_MASK_TX__SW_ACCESS_DONE			0x08
	#define BIT_MASK_TX__EARC_CONN_CHANGE			0x20
	#define BIT_MASK__INT6_MASK__ECC_ERR_FIXED		0x02
	#define BIT_MASK__INT6_MASK__ECC_ERR			0x01

/* Test Ctrl Register */
#define REG_ADDR__TEST_CTRL				(TX_EARC_REG | 0X00D0)
	/* (ReadWrite, Bits 5:4)*/
	/* Select from which pipe-line to observe data:
	"00" from tx I2S
	"01" from tx spdif
	"10" from rx spdif
	"11" from rx i2s*/
	#define BIT_MSK__TEST_CTRL__REG_OBS_PIPE_SEL		0x30
	/* (ReadWrite, Bits 3:1)*/
	/* control test mode for input data:
	"000" set input data on ch0 to AA; ch1 to 55; ch2 to AA and ch3 to 55
	"001" increment each channel every sample
	"010" set each channel to shifted out test value
	"011" set each channel to constant test value
	"111" will allow input data to go thru
	everything else reserved*/
	#define BIT_MSK__TEST_CTRL__REG_TEST_MODE		0x0E
	/* (ReadWrite, Bits 0)*/
	/* enable test mode based on test_mode control*/
	#define BIT_MSK__TEST_CTRL__REG_TEST_EN			0x01

/* Tx CS BCH ECC Pointer Register*/
#define REG_ADDR__TX_CS_ECC_PTR				(TX_EARC_REG | 0x00DB)
	/* (ReadWrite, Bits 7:0)*/
	/* offset pointer within Channel Status array for BCH ECC pattern*/
	#define BIT_MSK__TX_CS_ECC_PTR__REG_TX_CS_ECC_PTR	0xFF

/* Tx CS BCH ECC Mask Register*/
#define REG_ADDR__TX_CS_ECC_MASK			(TX_EARC_REG | 0x00DC)
	/* (ReadWrite, Bits 7:0)*/
	/* mask for the BCH ECC pattern in Channel Status array.
	 * Only bits set to "1" are used*/
	#define BIT_MSK__TX_CS_ECC_MASK__REG_TX_CS_ECC_MASK	0xFF

/* Tx CS BCH ECC Pattern Register*/
#define REG_ADDR__TX_CS_ECC_PATTERN			(TX_EARC_REG | 0x00DD)
	/* (ReadWrite, Bits 7:0)*/
	/* pattern to compare against to see if BCh ECC is on.
	 * Only bits set by mask will be compared*/
	#define BIT_MSK__TX_CS_ECC_PATTERN__REG_TX_CS_ECC_PATTERN	0xFF

/* BCH Control Register*/
#define REG_ADDR__BCH_CTRL				(TX_EARC_REG | 0x00DE)
	/* (ReadWrite, Bits 7)*/
	/* BCH interleaving enable; default "0" means disabled*/
	#define BIT_MSK__BCH_CTRL__REG_BCHINTV_EN		0x80
	/* (ReadWrite, Bits 6:5)*/
	/* 00 Disable ECC
	01 Turn on ECC if CS word shows 16-bit word length
	10 Turn on ECC if ECC enable bit is 1
	11 Turn on ECC if both the above items are true*/
	#define BIT_MSK__BCH_CTRL__REG_ECC_EN			0x60
	#define BIT_MSK__BCH_CTRL__REG_ECC_ENABLE		0x40
	#define BIT_MSK__BCH_CTRL__REG_ECC_DISABLE		0x00

/* BCH Status Register*/
#define REG_ADDR__BCH_STAT				(TX_EARC_REG | 0x00DF)
	/* (ReadOnly, Bits 0)*/
	/* 1:ecc decoding is ongoing*/
	#define BIT_MSK__BCH_STAT__ECC_ENC_ON			0x01

/* EDID Interrupt Source Reg */
#define REG_ADDR__EDID_INTR				(TX_EARC_REG | 0x00E0)

/* EDID Interrupt Mask Reg */
#define REG_ADDR__EDID_INTR_MASK			(TX_EARC_REG | 0x00E1)
	/* (ReadWrite, Bits 0) */
	/* Enable INT[0]: 1 - enable; 0 - disable (default) */
	#define BIT_MSK__EDID_INTR_MASK__REG_INTR_MASK0		0x01
	/* (ReadWrite, Bits 1) */
	/* Enable INT[1]: 1 - enable; 0 - disable (default) */
	#define BIT_MSK__EDID_INTR_MASK__REG_INTR_MASK1		0x02

/* EDID Control Reg */
#define REG_ADDR__EDID_CTRL				(TX_EARC_REG | 0x00E2)
	/* (ReadWrite, Bits 6)*/
	/* This bit need to be 1 for HDMI mode and 0 for MHL*/
	#define BIT_MSK__EDID_CTRL__REG_EDID_HDMI_MHL_MODE	0x40
	/* (ReadWrite, Bits 5)*/
	/* the Most Singnificant Bit of reg_edid_fifo_addr
	If more than 256 Bytes EDID is required this bit is combined with
	 reg_edid_fifo_addr[7:0] to generate 9 bits address for
	 EDID FIFO access. The 9 bit address will be:
	  {reg_edid_fifo_addr_msb reg_edid_fifo_addr[7:0]}.
	Otherwise set this bit as "0"*/
	#define BIT_MSK__EDID_CTRL__REG_EDID_FIFO_ADDR_MSB	0x20
	/* (ReadWrite, Bits 4)*/
	/* 0: Do not increment EDID FIFO address pointer
	1: Increment EDID FIFO address pointer automatically*/
	#define BIT_MSK__EDID_CTRL__REG_EDID_FIFO_ADDR_AUTO	0x10
	/* (ReadWrite, Bits 3)*/
	/* 1: Enable EDID FIFO access all the time
	0: I2C can only access EDID FIFO after MHL established*/
	#define BIT_MSK__EDID_CTRL__REG_EDID_FIFO_ACCESS_ALWAYS_EN	0x08
	/* (ReadWrite, Bits 2:1)*/
	/* 00: Downstream-retrived EDID data will be written into FIFO
	 *  from 0x000 - 0x07F (1st half)
	01: Downstream-retrived EDID data will be written into FIFO
	 from 0x080 - 0x0FF (2nd half)
	10: Downstream-retrived EDID data will be written into FIFO
	 from 0x100 - 0x17F (3rd half)
	11: Downstream-retrived EDID data will be written into FIFO
	 from 0x180 - 0x1FF (4th half)
	If only 256 byte FIFO is used always tie Bit[2] to zero*/
	#define BIT_MSK__EDID_CTRL__REG_EDID_FIFO_BLOCK_SEL	0x06
	#define BIT_MSK__EDID_CTRL__REG_EDID_FIFO_B_SEL		0x02
	/* (ReadWrite, Bits 0)*/
	/* 0: Disable EDID' function
	1: Enable EDID' function*/
	#define BIT_MSK__EDID_CTRL__REG_EDID_MODE_EN		0x01

/* EDID FIFO Addr Reg */
#define REG_ADDR__EDID_FIFO_ADDR			(TX_EARC_REG | 0x00E3)

/* EDID FIFO Data Reg */
#define REG_ADDR__EDID_FIFO_DATA			(TX_EARC_REG | 0x00E4)

/* EDID DDC Segment Pointer 0  Reg */
#define REG_ADDR__EDID_START_EXT0			(TX_EARC_REG | 0x00E8)
	/* (ReadWrite, Bits 0)*/
	/* Start to get EDID block 0. Self-resetting to 0.*/
	#define BIT_MSK__EDID_START_EXT0__REG_GET_EDID_START_0	0x01

/* EDID DDC Segment Pointer 1 Reg*/
#define REG_ADDR__EDID_START_EXT1			(TX_EARC_REG | 0x00E9)
	/* (ReadWrite, Bits 7)*/
	/* Start to get EDID block 8. Self-resetting to 0.*/
	#define BIT_MSK__EDID_START_EXT1__REG_GET_EDID_START_8	0x80
	/* (ReadWrite, Bits 6)*/
	/* Start to get EDID block 7. Self-resetting to 0.*/
	#define BIT_MSK__EDID_START_EXT1__REG_GET_EDID_START_7	0x40
	/* (ReadWrite, Bits 5)*/
	/* Start to get EDID block 6. Self-resetting to 0.*/
	#define BIT_MSK__EDID_START_EXT1__REG_GET_EDID_START_6	0x20
	/* (ReadWrite, Bits 4)*/
	/* Start to get EDID block 5. Self-resetting to 0.*/
	#define BIT_MSK__EDID_START_EXT1__REG_GET_EDID_START_5	0x10
	/* (ReadWrite, Bits 3)*/
	/* Start to get EDID block 4. Self-resetting to 0.*/
	#define BIT_MSK__EDID_START_EXT1__REG_GET_EDID_START_4	0x08
	/* (ReadWrite, Bits 2)*/
	/* Start to get EDID block 3. Self-resetting to 0.*/
	#define BIT_MSK__EDID_START_EXT1__REG_GET_EDID_START_3	0x04
	/* (ReadWrite, Bits 1)*/
	/* Start to get EDID block 2. Self-resetting to 0.*/
	#define BIT_MSK__EDID_START_EXT1__REG_GET_EDID_START_2	0x02
	/* (ReadWrite, Bits 0)*/
	/* Start to get EDID block 1. Self-resetting to 0.*/
	#define BIT_MSK__EDID_START_EXT1__REG_GET_EDID_START_1	0x01

/* EDID Restart Reg */
#define REG_ADDR__EDID_RST				(TX_EARC_REG | 0x00EB)

/* EDID Max Addr Reg*/
#define REG_ADDR__EDID_MAX_ADDR				(TX_EARC_REG | 0x00EC)
	/* (ReadWrite, Bits 6:0)*/
	/* the maximux EDID byte number to access:
		0: access 1 byte
		1: access 2 bytes
		2: access 3 bytes

		127: access 128 bytes*/
	#define BIT_MSK__EDID_MAX_ADDR__REG_EDID_ADDR_MAX	0x7F

/* EDID Address Reg*/
#define REG_ADDR__EDID_DEV_ADDR				(TX_EARC_REG | 0x00ED)
	/* (ReadWrite, Bits 7:0)*/
	/* EDID Device Address*/
	#define BIT_MSK__EDID_DEV_ADDR__REG_EDID_DA		0xFF

/*****************  TX SW TPI (6800-68FF)*********************/

/* LM DDC Register */
#define REG_ADDR__LM_DDC				(TX_SW_TPI_REG | 0x009C)

/* DDC I2C Status Register*/
#define REG_ADDR__DDC_STATUS				(TX_SW_TPI_REG | 0x00C2)
	/* (ReadWrite, Bits 6)*/
	/* When read get the status from hardware: to clear write "0"*/
	#define BIT_MSK__DDC_STATUS__REG_DDC_BUS_LOW		0x40
	/* (ReadWrite, Bits 5)*/
	/* When read get the status from hardware: to clear write "0"*/
	#define BIT_MSK__DDC_STATUS__REG_DDC_NO_ACK		0x20
	/* (ReadOnly, Bits 4)*/
	/* DDC in programming mode*/
	#define BIT_MSK__DDC_STATUS__DDC_I2C_IN_PROG		0x10
	/* (ReadOnly, Bits 3)*/
	/* DDC fifo full*/
	#define BIT_MSK__DDC_STATUS__DDC_FIFO_FULL		0x08
	/* (ReadOnly, Bits 2)*/
	/* DDC FIFO is empty*/
	#define BIT_MSK__DDC_STATUS__DDC_FIFO_EMPTY		0x04
	/* (ReadOnly, Bits 1)*/
	/* DDC fifo read in use*/
	#define BIT_MSK__DDC_STATUS__DDC_FIFO_READ_IN_SUE	0x02
	/* (ReadOnly, Bits 0)*/
	/* DDC fifo write in use*/
	#define BIT_MSK__DDC_STATUS__DDC_FIFO_WRITE_IN_USE	0x01

/*****************  PHY (viola) (6400-64FF)*********************/
/* Viola status Register*/
#define REG_ADDR__VIOLA_STATUS				(TX_PHY_REG | 0x0060)
	/* (ReadWrite, Bits 7)*/
	/* rx fifo reset*/
	#define BIT_MSK__VIOLA_STATUS__REG_RST_RX_PHY_FIFO_N	0x80
	/* (ReadWrite, Bits 6)*/
	/* dviola rx logic reset*/
	#define BIT_MSK__VIOLA_STATUS__REG_RST_DVIOLA_RX_N	0x40
	/* (ReadWrite, Bits 5)*/
	/* tx fifo reset*/
	#define BIT_MSK__VIOLA_STATUS__REG_RST_TX_PHY_FIFO_N	0x20
	/* (ReadWrite, Bits 4)*/
	/* dviola rx logic reset*/
	#define BIT_MSK__VIOLA_STATUS__REG_RST_DVIOLA_TX_N	0x10
	/* (ReadOnly, Bits 1)*/
	/* earc lock detect*/
	#define BIT_MSK__VIOLA_STATUS__EARC_LOCK_DETECT		0x02
	/* (ReadOnly, Bits 0)*/
	/* earc clock detect*/
	#define BIT_MSK__VIOLA_STATUS__EARC_CLK_DETECT		0x01

/* Viola mode Register */
#define REG_ADDR__VIOLA_MODE				(TX_PHY_REG | 0x0064)
	/* (ReadWrite, Bits 0)*/
	/* PLL enable 0: disable 1: enable*/
	#define BIT_MSK__VIOLA_MODE__PLL_EN			0x01
	/* (ReadWrite, Bits 1)*/
	/* select bias reference for charge pump
	  0: constant-gm reference (default)
	  1: resistor divider reference enable */
	#define BIT_MSK__VIOLA_MODE__PLL_BIAS_CP		0x02
	/* (ReadWrite, Bits 2) */
	/* Choose Tx/Rx mode 0: ARC/eARC Tx mode 1: ARC/eARC Rx mode*/
	#define BIT_MSK__VIOLA_MODE__REG_ARC_DIR		0x04
	/* (ReadWrite, Bits 3) */
	/* Choose legacy ARC or eARC mode 0: legacy ARC mode 1: eARC mode*/
	#define BIT_MSK__VIOLA_MODE__REG_ARC_MODE		0x08
	/* (ReadWrite, Bits 5) */
	/* overwrite lock status*/
	#define BIT_MSK__VIOLA_MODE__REG_LOCK_OVR		0x20
	/* (ReadWrite, Bits 6) */
	/* reg lock status*/
	#define BIT_MSK__VIOLA_MODE__REG_LOCK			0x40
	/* (ReadWrite, Bits 7) */
	/* auto reg_earc_cfg setting for tx/rx*/
	#define BIT_MSK__VIOLA_MODE__REG_AUTO_CFG		0x80

/* Viola cfg 0 Register*/
#define REG_ADDR__EARC_CFG0				(TX_PHY_REG | 0x0065)
	/* (ReadWrite, Bits 7:0)*/
	/* [0]: PLL clock to Tx datapath
	 * (0: enable Tx path eARC datapath/ 1: disable)
	[1]: PLL clock to Rx datapath
	 (0: enable Rx path eARC datapath/ 1: disable)
	[3:2]: Tx datapath data polarity change
	 (00: eARC (phase inverted);
	  01: common-mode legacy ARC);
	  11: eARC (normal phase))
	[4]: CKDT mode setting (0: Not used/ 1: faster clock than 65MHz)
	[5]: CKDT block power down (0:power down/ 1: normal operation)
	[6]: Rx datapath power down (0: power down/ 1: normal operation)
	[7]: ARC data path filter enable*/
	#define BIT_MSK__EARC_CFG0__REG_EARC_CFG_B7_B0		0xFF
	#define BIT_MASK__EARC_CFG0__TX_DATA_POL_MASK		0x0C
	#define BIT_MASK__EARC_CFG0__TX_DATA_POL_INV		0x00
	#define BIT_MASK__EARC_CFG0__TX_DATA_POL_LEG_ARC	0x04
	#define BIT_MASK__EARC_CFG0__TX_DATA_POL_NORM		0x0C
	#define BIT_MASK__EARC_CFG0__TX_PLL_CLK_TO_TX_DP	0x01

/* Viola cfg 1 Register */
#define REG_ADDR__EARC_CFG_1				(TX_PHY_REG | 0x0066)
	/* (ReadWrite, Bits 7:0)*/
	/* [9:8]: Rx datapath clock output delay control
	  (00: No delay
	   01: one delay
	   10: opposite phase
	   11: opposite phase + one delay)*/
	/*[11:10]: legacy ARC mode control
	  (11: common-mode;
	   10: single-mode)*/
	#define BIT_MSK__EARC_CFG1__ARC_MODE_CTRL_CM		0x0C
	#define BIT_MSK__EARC_CFG1__CM_LEVEL_CTRL_SM		0x08
	/*[13:12]: rterm_sel for common-mode signal for replica bias
	  (2'b00 : select 50ohm Rterm case;
	   2'b01 : select 30ohm Rterm case)*/
	#define BIT_MSK__EARC_CFG1__RTERM_50OHM		0x00
	#define BIT_MSK__EARC_CFG1__RTERM_30OHM		0x10
	/*[15:14]: common-mode level control
	   (2'b00 : 200mV;
	    2'b01 : 250mV;
	    2'b10 : 300mV;
	    2'b11 : 350mV)*/
	#define BIT_MSK__EARC_CFG1__CM_LEVEL_CTRL_200MV		0x00
	#define BIT_MSK__EARC_CFG1__CM_LEVEL_CTRL_250MV		0x40
	#define BIT_MSK__EARC_CFG1__CM_LEVEL_CTRL_300MV		0x80
	#define BIT_MSK__EARC_CFG1__CM_LEVEL_CTRL_350MV		0xC0

	#define BIT_MSK__EARC_CFG1__REG_EARC_CFG1_B15_B8	0xFF


/* Viola pll 1 Register */
#define REG_ADDR__VIOLA_PLL_1				(TX_PHY_REG | 0x0068)
	/* (ReadWrite, Bits 7:0)*/
	/* reg_pll_cfg[14:9] : pll post divider ratio which control
	 *  pll_clk output
		1 : 1/1
		2 : 1/2
		10 : 1/10
	[15]: PLL loop filter cap discharge
	 (0: discharge/ 1: normal operation)*/
#define BIT_MSK__PLL_CFG1__REG_PLL_CFG_B15_B8			0xFF

/* Viola term60 Register*/
#define REG_ADDR__VIOLA_TERM60				(TX_PHY_REG | 0x006C)
	/* (ReadWrite, Bits 3)*/
	/* internal termination enable
	 *  0: disable termination
	 *  1: enable termination*/
	#define BIT_MSK__VIOLA_TERM60__REG_TERM60_EN		0x08
	/* (ReadWrite, Bits 2:0)*/
	/* To calibrate the eARC 60 ohm termination which is the binary code;
	 *  000 biggest value;
	 *  111: smallest value voltage calibration*/
	#define BIT_MSK__VIOLA_TERM60__EARC_TERM60_CTL		0x07

/* Viola term300 Register*/
#define REG_ADDR__VIOLA_TERM300				(TX_PHY_REG | 0x006D)
	/* (ReadWrite, Bits 3)*/
	/* internal termination enable
	 *  0: disable termination
	 *  1: enable termination*/
	#define BIT_MSK__VIOLA_TERM300__REG_TERM300_EN 0x08
	/* (ReadWrite, Bits 2:0)*/
	/* To calibrate the eARC 300 ohm termination which is the binary code;
	 *  000 biggest value;
	 *  111: smallest value voltage calibration*/
	#define BIT_MSK__VIOLA_TERM300__EARC_TERM300_CTL 0x07

/* Viola slew n swing Register */
#define REG_ADDR__VIOLA_SLEW_N_SWING			(TX_PHY_REG | 0x006E)
	/* (ReadWrite, Bits 6:4)*/
	/* eARC driver bias current output swing control;
	   which is the binary code;
	   000: smallest value 4mA;
	   111: biggest value 16mA*/
	#define BIT_MSK__VIOLA_SLEW_N_SWING__EARC_SW_CTL	0x70
	/* (ReadWrite, Bits 3:0)*/
	/* slew rate control of the eARC driver;
	   which is the thermometer-code;
	    0000: slowest mode;
	    1111: fastest mode*/
	#define BIT_MSK__VIOLA_SLEW_N_SWING__EARC_DR_SLEW	0x0F

/* Viola sprx Register */
#define REG_ADDR__VIOLA_SPRX				(TX_PHY_REG | 0x006F)
	/* (ReadWrite, Bits 7:5)*/
	/* <1>: swirchon4backward;
	   <0>: bwchannel_on(data detection)
	 i2csprxc<0> :
	   1'b1 = earc common mode on;
	   1'b0 = legacy ARC output*/
	#define BIT_MSK__VIOLA_SPRX__I2CSPRXC			0xE0
	/* (ReadWrite, Bits 4:0)*/
	/* <1:0> common-mode signal fine swing control
	   (2'b00 = low => 2'b11 = high)*/
	#define BIT_MSK__VIOLA_SPRX__I2CSPRXG			0x1F

/* Viola VCO calibration Register */
#define REG_ADDR__VIOLA_VCO_CAL				(TX_PHY_REG | 0x0070)
	/* (ReadWrite, Bits 7) */
	/* auto reg_earc_cfg setting for tx/rx*/
	#define BIT_MSK__VIOLA_MODE__REG_TX_ZONE		0x60
	#define BIT_MSK__VIOLA_MODE__REG_TX_ZONE_SHIFT		0x05
	/* (ReadWrite, Bits 7) */
	/* reg zone ovr*/
	#define BIT_MSK__VIOLA_VCO_CAL__REG_ZONE_OVR		0x80

/* Viola FEM Register*/
#define REG_ADDR__VIOLA_FEM_CFG				(TX_PHY_REG | 0x0072)
	/* (ReadWrite, Bits 7:4)*/
	/* falling edge modulation data 1 position*/
	#define BIT_MSK__VIOLA_FEM_CFG__REG_VIO_FE1		0xF0
	/* (ReadWrite, Bits 3:0)*/
	/* falling edge modulation data 0 position*/
	#define BIT_MSK__VIOLA_FEM_CFG__REG_VIO_FE0		0x0F

/* Viola CM BW control Register*/
#define REG_ADDR__VIOLA_CM_BW_CTL			(TX_PHY_REG | 0x0074)
	/* (ReadWrite, Bits 6)*/
	/* manual common mode bw control state*/
	#define BIT_MSK__VIOLA_CM_BW_CTL__REG_MAN_CM_FSM	0x40
	/* (ReadWrite, Bits 5:4)*/
	/* common mode bw control state*/
	#define BIT_MSK__VIOLA_CM_BW_CTL__REG_CM_FSM		0x30
	/* (ReadWrite, Bits 3:2)*/
	/* filter_config*/
	#define BIT_MSK__VIOLA_CM_BW_CTL__REG_FLT_CFG		0x0C
	/* (ReadWrite, Bits 0)*/
	/* select i2c bw control*/
	#define BIT_MSK__VIOLA_CM_BW_CTL__REG_MAN_BW_CFG	0x01

#endif /* _SII9438_REGS_H_ */
