/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2 of the GNU General Public License ("GPLv2 License")
 * or BSD License.
 *
 * GPLv2 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _HW_FG_H_
#define _HW_FG_H_

#include "x_hal_reg.h"

#define FG_BASE IO_VIRT_SRE + 0x27000

//Page FILM_GRAIN_1
#define REG_FG_00 (FG_BASE + 0x000)
    #define REG_FG_00_REG_SD_DC_START_PRE_SEL Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_FG_00_REG_HD_DC_START_PRE_SEL Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_FG_00_REG_SDC_OUT_SWAP Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_FG_00_REG_HDC_OUT_SWAP Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_FG_00_REG_SDC_IN_SWAP Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_FG_00_REG_HDC_IN_SWAP Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_FG_00_REG_FG_MONBUS_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_FG_00_REG_FG_RST Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG_00_REG_SD_FG_PIPE_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG_00_REG_HD_FG_PIPE_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG_00_REG_MIU2SMI_BURST_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG_00_REG_8K_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG_00_REG_SD_FG_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG_00_REG_HD_FG_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_FG_01 (FG_BASE + 0x004)
    #define REG_FG_01_REG_HD_VSYNC_P_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_01_REG_HD_VSYNC_P_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_02 (FG_BASE + 0x008)
    #define REG_FG_02_REG_HD_DC_START_PRE_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_02_REG_HD_DC_START_PRE_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_03 (FG_BASE + 0x00C)
    #define REG_FG_03_REG_HD_ADL_TRIG_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_04 (FG_BASE + 0x010)
    #define REG_FG_04_REG_HD_ADL_TRIG_HCNT1 Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_04_REG_HD_ADL_TRIG_HCNT0 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_05 (FG_BASE + 0x014)
    #define REG_FG_05_REG_HD_CLR_CRC_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_05_REG_HD_CLR_CRC_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_06 (FG_BASE + 0x018)
    #define REG_FG_06_REG_HD_CRC_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_06_REG_HD_CRC_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_07 (FG_BASE + 0x01C)
    #define REG_FG_07_REG_HD_DB0_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_FG_07_REG_HD_DB0_EN_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_07_REG_HD_DB0_EN_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_08 (FG_BASE + 0x020)
    #define REG_FG_08_REG_HD_DB1_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_FG_08_REG_HD_DB1_EN_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_08_REG_HD_DB1_EN_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_09 (FG_BASE + 0x024)
    #define REG_FG_09_REG_SD_VSYNC_P_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_09_REG_SD_VSYNC_P_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_0A (FG_BASE + 0x028)
    #define REG_FG_0A_REG_SD_DC_START_PRE_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_0A_REG_SD_DC_START_PRE_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_0B (FG_BASE + 0x02C)
    #define REG_FG_0B_REG_SD_ADL_TRIG_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_0C (FG_BASE + 0x030)
    #define REG_FG_0C_REG_SD_ADL_TRIG_HCNT1 Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_0C_REG_SD_ADL_TRIG_HCNT0 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_0D (FG_BASE + 0x034)
    #define REG_FG_0D_REG_SD_CLR_CRC_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_0D_REG_SD_CLR_CRC_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_0E (FG_BASE + 0x038)
    #define REG_FG_0E_REG_SD_CRC_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_0E_REG_SD_CRC_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_0F (FG_BASE + 0x03C)
    #define REG_FG_0F_REG_SD_DB0_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_FG_0F_REG_SD_DB0_EN_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_0F_REG_SD_DB0_EN_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_10 (FG_BASE + 0x040)
    #define REG_FG_10_REG_SD_DB1_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_FG_10_REG_SD_DB1_EN_HCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define REG_FG_10_REG_SD_DB1_EN_VCNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_FG_11 (FG_BASE + 0x044)
    #define REG_FG_11_FG_REG_FUSE_SEL Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_FG_11_FG_REG_LOAD_SEL Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_FG_11_FG3_SRAM1P1024X80_WP_MBIST_MODE Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_FG_11_FG3_SRAM1P256X8_WP_MBIST_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_FG_11_FG3_SRAM1P232X80_WP_MBIST_MODE Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_FG_11_FG3_SRAM1P816X80_WP_MBIST_MODE Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_FG_11_FG2_SRAM1P1024X80_WP_MBIST_MODE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_FG_11_FG2_SRAM1P256X8_WP_MBIST_MODE Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_FG_11_FG2_SRAM1P232X80_WP_MBIST_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_FG_11_FG2_SRAM1P816X80_WP_MBIST_MODE Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_FG_11_FG1_SRAM1P1024X80_WP_MBIST_MODE Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_FG_11_FG1_SRAM1P256X8_WP_MBIST_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG_11_FG1_SRAM1P232X80_WP_MBIST_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG_11_FG1_SRAM1P816X80_WP_MBIST_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG_11_FG0_SRAM1P1024X80_WP_MBIST_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG_11_FG0_SRAM1P256X8_WP_MBIST_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG_11_FG0_SRAM1P232X80_WP_MBIST_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG_11_FG0_SRAM1P816X80_WP_MBIST_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_FG_12 (FG_BASE + 0x048)
    #define REG_FG_12_FG3_SRAM1P1024X80_WP_MBIST_DONE Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_FG_12_FG3_SRAM1P256X8_WP_MBIST_DONE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_FG_12_FG3_SRAM1P232X80_WP_MBIST_DONE Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_FG_12_FG3_SRAM1P816X80_WP_MBIST_DONE Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_FG_12_FG2_SRAM1P1024X80_WP_MBIST_DONE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_FG_12_FG2_SRAM1P256X8_WP_MBIST_DONE Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_FG_12_FG2_SRAM1P232X80_WP_MBIST_DONE Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_FG_12_FG2_SRAM1P816X80_WP_MBIST_DONE Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_FG_12_FG1_SRAM1P1024X80_WP_MBIST_DONE Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_FG_12_FG1_SRAM1P256X8_WP_MBIST_DONE Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG_12_FG1_SRAM1P232X80_WP_MBIST_DONE Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG_12_FG1_SRAM1P816X80_WP_MBIST_DONE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG_12_FG0_SRAM1P1024X80_WP_MBIST_DONE Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG_12_FG0_SRAM1P256X8_WP_MBIST_DONE Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG_12_FG0_SRAM1P232X80_WP_MBIST_DONE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG_12_FG0_SRAM1P816X80_WP_MBIST_DONE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_FG_13 (FG_BASE + 0x04C)
    #define REG_FG_13_FG1_SRAM1P1024X80_WP_MBIST_FAIL_0 Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_FG_13_FG1_SRAM1P256X8_WP_MBIST_FAIL_7 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_FG_13_FG1_SRAM1P256X8_WP_MBIST_FAIL_6 Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_FG_13_FG1_SRAM1P256X8_WP_MBIST_FAIL_5 Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_FG_13_FG1_SRAM1P256X8_WP_MBIST_FAIL_4 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_FG_13_FG1_SRAM1P256X8_WP_MBIST_FAIL_3 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_FG_13_FG1_SRAM1P256X8_WP_MBIST_FAIL_2 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_FG_13_FG1_SRAM1P256X8_WP_MBIST_FAIL_1 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_FG_13_FG1_SRAM1P256X8_WP_MBIST_FAIL_0 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_FG_13_FG1_SRAM1P232X80_WP_MBIST_FAIL_1 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_FG_13_FG1_SRAM1P232X80_WP_MBIST_FAIL_0 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_FG_13_FG1_SRAM1P816X80_WP_MBIST_FAIL_0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_FG_13_FG0_SRAM1P1024X80_WP_MBIST_FAIL_0 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_FG_13_FG0_SRAM1P256X8_WP_MBIST_FAIL_7 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_FG_13_FG0_SRAM1P256X8_WP_MBIST_FAIL_6 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_FG_13_FG0_SRAM1P256X8_WP_MBIST_FAIL_5 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_FG_13_FG0_SRAM1P256X8_WP_MBIST_FAIL_4 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_FG_13_FG0_SRAM1P256X8_WP_MBIST_FAIL_3 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG_13_FG0_SRAM1P256X8_WP_MBIST_FAIL_2 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG_13_FG0_SRAM1P256X8_WP_MBIST_FAIL_1 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG_13_FG0_SRAM1P256X8_WP_MBIST_FAIL_0 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG_13_FG0_SRAM1P232X80_WP_MBIST_FAIL_1 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG_13_FG0_SRAM1P232X80_WP_MBIST_FAIL_0 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG_13_FG0_SRAM1P816X80_WP_MBIST_FAIL_0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_FG_14 (FG_BASE + 0x050)
    #define REG_FG_14_FG3_SRAM1P1024X80_WP_MBIST_FAIL_0 Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_FG_14_FG3_SRAM1P256X8_WP_MBIST_FAIL_7 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_FG_14_FG3_SRAM1P256X8_WP_MBIST_FAIL_6 Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_FG_14_FG3_SRAM1P256X8_WP_MBIST_FAIL_5 Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_FG_14_FG3_SRAM1P256X8_WP_MBIST_FAIL_4 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_FG_14_FG3_SRAM1P256X8_WP_MBIST_FAIL_3 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_FG_14_FG3_SRAM1P256X8_WP_MBIST_FAIL_2 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_FG_14_FG3_SRAM1P256X8_WP_MBIST_FAIL_1 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_FG_14_FG3_SRAM1P256X8_WP_MBIST_FAIL_0 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_FG_14_FG3_SRAM1P232X80_WP_MBIST_FAIL_1 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_FG_14_FG3_SRAM1P232X80_WP_MBIST_FAIL_0 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_FG_14_FG3_SRAM1P816X80_WP_MBIST_FAIL_0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_FG_14_FG2_SRAM1P1024X80_WP_MBIST_FAIL_0 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_FG_14_FG2_SRAM1P256X8_WP_MBIST_FAIL_7 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_FG_14_FG2_SRAM1P256X8_WP_MBIST_FAIL_6 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_FG_14_FG2_SRAM1P256X8_WP_MBIST_FAIL_5 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_FG_14_FG2_SRAM1P256X8_WP_MBIST_FAIL_4 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_FG_14_FG2_SRAM1P256X8_WP_MBIST_FAIL_3 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG_14_FG2_SRAM1P256X8_WP_MBIST_FAIL_2 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG_14_FG2_SRAM1P256X8_WP_MBIST_FAIL_1 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG_14_FG2_SRAM1P256X8_WP_MBIST_FAIL_0 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG_14_FG2_SRAM1P232X80_WP_MBIST_FAIL_1 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG_14_FG2_SRAM1P232X80_WP_MBIST_FAIL_0 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG_14_FG2_SRAM1P816X80_WP_MBIST_FAIL_0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_FG_15 (FG_BASE + 0x054)
    #define REG_FG_15_FG3_SRAM1P1024X80_WP_MBIST_RP_FAIL_0 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_FG_15_FG3_SRAM1P816X80_WP_MBIST_RP_FAIL_0 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_FG_15_FG2_SRAM1P1024X80_WP_MBIST_RP_FAIL_0 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_FG_15_FG2_SRAM1P816X80_WP_MBIST_RP_FAIL_0 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_FG_15_FG1_SRAM1P1024X80_WP_MBIST_RP_FAIL_0 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_FG_15_FG1_SRAM1P816X80_WP_MBIST_RP_FAIL_0 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_FG_15_FG0_SRAM1P1024X80_WP_MBIST_RP_FAIL_0 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_FG_15_FG0_SRAM1P816X80_WP_MBIST_RP_FAIL_0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_FG_15_FG3_SRAM1P1024X80_WP_MBIST_RP_OK_0 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_FG_15_FG3_SRAM1P816X80_WP_MBIST_RP_OK_0 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG_15_FG2_SRAM1P1024X80_WP_MBIST_RP_OK_0 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG_15_FG2_SRAM1P816X80_WP_MBIST_RP_OK_0 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG_15_FG1_SRAM1P1024X80_WP_MBIST_RP_OK_0 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG_15_FG1_SRAM1P816X80_WP_MBIST_RP_OK_0 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG_15_FG0_SRAM1P1024X80_WP_MBIST_RP_OK_0 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG_15_FG0_SRAM1P816X80_WP_MBIST_RP_OK_0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_FG_16 (FG_BASE + 0x058)
    #define REG_FG_16_FG1_SRAM1P1024X80_WP_MBIST_PRE_FUSE Fld(6,24,AC_MSKB3)//[29:24]
    #define REG_FG_16_FG1_SRAM1P816X80_WP_MBIST_PRE_FUSE Fld(6,16,AC_MSKB2)//[21:16]
    #define REG_FG_16_FG0_SRAM1P1024X80_WP_MBIST_PRE_FUSE Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_FG_16_FG0_SRAM1P816X80_WP_MBIST_PRE_FUSE Fld(6,0,AC_MSKB0)//[5:0]
#define REG_FG_17 (FG_BASE + 0x05C)
    #define REG_FG_17_FG3_SRAM1P1024X80_WP_MBIST_PRE_FUSE Fld(6,24,AC_MSKB3)//[29:24]
    #define REG_FG_17_FG3_SRAM1P816X80_WP_MBIST_PRE_FUSE Fld(6,16,AC_MSKB2)//[21:16]
    #define REG_FG_17_FG2_SRAM1P1024X80_WP_MBIST_PRE_FUSE Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_FG_17_FG2_SRAM1P816X80_WP_MBIST_PRE_FUSE Fld(6,0,AC_MSKB0)//[5:0]
#define REG_FG_18 (FG_BASE + 0x060)
    #define REG_FG_18_FG1_SRAM1P1024X80_WP_MBIST_FUSE Fld(6,24,AC_MSKB3)//[29:24]
    #define REG_FG_18_FG1_SRAM1P816X80_WP_MBIST_FUSE Fld(6,16,AC_MSKB2)//[21:16]
    #define REG_FG_18_FG0_SRAM1P1024X80_WP_MBIST_FUSE Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_FG_18_FG0_SRAM1P816X80_WP_MBIST_FUSE Fld(6,0,AC_MSKB0)//[5:0]
#define REG_FG_19 (FG_BASE + 0x064)
    #define REG_FG_19_FG3_SRAM1P1024X80_WP_MBIST_FUSE Fld(6,24,AC_MSKB3)//[29:24]
    #define REG_FG_19_FG3_SRAM1P816X80_WP_MBIST_FUSE Fld(6,16,AC_MSKB2)//[21:16]
    #define REG_FG_19_FG2_SRAM1P1024X80_WP_MBIST_FUSE Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_FG_19_FG2_SRAM1P816X80_WP_MBIST_FUSE Fld(6,0,AC_MSKB0)//[5:0]
#define REG_FG_1A (FG_BASE + 0x068)
    #define REG_FG_1A_FG_MBIST_PRE_FUSE_MERGE Fld(6,0,AC_MSKB0)//[5:0]
#define REG_FG_1B (FG_BASE + 0x06C)
    #define REG_FG_1B_FG_MONBUS Fld(32,0,AC_FULLDW)//[31:0]
#define REG_FG_1C (FG_BASE + 0x070)
    #define REG_FG_1C_FG_CRC0 Fld(32,0,AC_FULLDW)//[31:0]
#define REG_FG_1D (FG_BASE + 0x074)
    #define REG_FG_1D_FG_CRC1 Fld(32,0,AC_FULLDW)//[31:0]
#define REG_FG_1E (FG_BASE + 0x078)
    #define REG_FG_1E_FG_CRC2 Fld(32,0,AC_FULLDW)//[31:0]
#define REG_FG_1F (FG_BASE + 0x07C)
    #define REG_FG_1F_FG_CRC3 Fld(32,0,AC_FULLDW)//[31:0]
#define REG_FG0_00 (FG_BASE + 0x080)
    #define REG_FG0_00_FG0_REG_AR_COFF_Y_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_00_FG0_REG_AR_COFF_Y_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_00_FG0_REG_AR_COFF_Y_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_00_FG0_REG_AR_COFF_Y_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_01 (FG_BASE + 0x084)
    #define REG_FG0_01_FG0_REG_AR_COFF_Y_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_01_FG0_REG_AR_COFF_Y_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_01_FG0_REG_AR_COFF_Y_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_01_FG0_REG_AR_COFF_Y_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_02 (FG_BASE + 0x088)
    #define REG_FG0_02_FG0_REG_AR_COFF_Y_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_02_FG0_REG_AR_COFF_Y_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_02_FG0_REG_AR_COFF_Y_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_02_FG0_REG_AR_COFF_Y_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_03 (FG_BASE + 0x08C)
    #define REG_FG0_03_FG0_REG_AR_COFF_Y_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_03_FG0_REG_AR_COFF_Y_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_03_FG0_REG_AR_COFF_Y_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_03_FG0_REG_AR_COFF_Y_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_04 (FG_BASE + 0x090)
    #define REG_FG0_04_FG0_REG_AR_COFF_Y_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_04_FG0_REG_AR_COFF_Y_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_04_FG0_REG_AR_COFF_Y_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_04_FG0_REG_AR_COFF_Y_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_05 (FG_BASE + 0x094)
    #define REG_FG0_05_FG0_REG_AR_COFF_Y_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_05_FG0_REG_AR_COFF_Y_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_05_FG0_REG_AR_COFF_Y_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_05_FG0_REG_AR_COFF_Y_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_06 (FG_BASE + 0x098)
    #define REG_FG0_06_FG0_REG_AR_COFF_CB_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_06_FG0_REG_AR_COFF_CB_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_06_FG0_REG_AR_COFF_CB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_06_FG0_REG_AR_COFF_CB_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_07 (FG_BASE + 0x09C)
    #define REG_FG0_07_FG0_REG_AR_COFF_CB_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_07_FG0_REG_AR_COFF_CB_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_07_FG0_REG_AR_COFF_CB_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_07_FG0_REG_AR_COFF_CB_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_08 (FG_BASE + 0x0A0)
    #define REG_FG0_08_FG0_REG_AR_COFF_CB_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_08_FG0_REG_AR_COFF_CB_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_08_FG0_REG_AR_COFF_CB_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_08_FG0_REG_AR_COFF_CB_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_09 (FG_BASE + 0x0A4)
    #define REG_FG0_09_FG0_REG_AR_COFF_CB_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_09_FG0_REG_AR_COFF_CB_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_09_FG0_REG_AR_COFF_CB_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_09_FG0_REG_AR_COFF_CB_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_0A (FG_BASE + 0x0A8)
    #define REG_FG0_0A_FG0_REG_AR_COFF_CB_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_0A_FG0_REG_AR_COFF_CB_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_0A_FG0_REG_AR_COFF_CB_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_0A_FG0_REG_AR_COFF_CB_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_0B (FG_BASE + 0x0AC)
    #define REG_FG0_0B_FG0_REG_AR_COFF_CB_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_0B_FG0_REG_AR_COFF_CB_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_0B_FG0_REG_AR_COFF_CB_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_0B_FG0_REG_AR_COFF_CB_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_0C (FG_BASE + 0x0B0)
    #define REG_FG0_0C_FG0_REG_AR_COFF_CB_24 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_0D (FG_BASE + 0x0B4)
    #define REG_FG0_0D_FG0_REG_AR_COFF_CB_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_0D_FG0_REG_AR_COFF_CB_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_0D_FG0_REG_AR_COFF_CB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_0D_FG0_REG_AR_COFF_CB_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_0E (FG_BASE + 0x0B8)
    #define REG_FG0_0E_FG0_REG_AR_COFF_CB_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_0E_FG0_REG_AR_COFF_CB_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_0E_FG0_REG_AR_COFF_CB_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_0E_FG0_REG_AR_COFF_CB_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_0F (FG_BASE + 0x0BC)
    #define REG_FG0_0F_FG0_REG_AR_COFF_CB_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_0F_FG0_REG_AR_COFF_CB_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_0F_FG0_REG_AR_COFF_CB_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_0F_FG0_REG_AR_COFF_CB_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_10 (FG_BASE + 0x0C0)
    #define REG_FG0_10_FG0_REG_AR_COFF_CB_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_10_FG0_REG_AR_COFF_CB_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_10_FG0_REG_AR_COFF_CB_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_10_FG0_REG_AR_COFF_CB_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_11 (FG_BASE + 0x0C4)
    #define REG_FG0_11_FG0_REG_AR_COFF_CB_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_11_FG0_REG_AR_COFF_CB_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_11_FG0_REG_AR_COFF_CB_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_11_FG0_REG_AR_COFF_CB_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_12 (FG_BASE + 0x0C8)
    #define REG_FG0_12_FG0_REG_AR_COFF_CB_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_12_FG0_REG_AR_COFF_CB_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_12_FG0_REG_AR_COFF_CB_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_12_FG0_REG_AR_COFF_CB_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_13 (FG_BASE + 0x0CC)
    #define REG_FG0_13_FG0_REG_AR_COFF_SHIFT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_FG0_13_FG0_REG_AR_COFF_CB_24 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_14 (FG_BASE + 0x0D0)
    #define REG_FG0_14_FG0_REG_CROP_VSIZE Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG0_14_FG0_REG_CROP_VSTART Fld(14,0,AC_MSKW10)//[13:0]
#define REG_FG0_15 (FG_BASE + 0x0D4)
    #define REG_FG0_15_FG0_MASK_HSIZE_DIFF Fld(6,20,AC_MSKW32)//[25:20]
    #define REG_FG0_15_FG0_REG_HMASK_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_FG0_15_FG0_REG_FILM_GRAIN_FORCE_ACK Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_FG0_15_FG0_REG_SCALING_SHIFT Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_FG0_15_FG0_REG_CHROMA_SCALING_FROM_LUMA Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_FG0_15_FG0_REG_FILM_GRAIN_FORCE_WRITE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_FG0_15_FG0_REG_CHROMA_SCALING_MD Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_FG0_15_FG0_REG_OVERLAP_MD Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_FG0_15_FG0_REG_CLIP_TO_RESTRICTED_RANGE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_FG0_15_FG0_REG_FG_CR_BYPASS_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_FG0_15_FG0_REG_FG_CB_BYPASS_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_FG0_15_FG0_REG_FG_Y_BYPASS_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_FG0_15_FG0_REG_10B_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG0_15_FG0_REG_420_REPEAT_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG0_15_FG0_REG_420REPEAT_LA_MD Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG0_15_FG0_REG_FLD_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG0_15_FG0_REG_ORI_CEN_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG0_15_FG0_REG_VMIR Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG0_15_FG0_REG_CROP_EN Fld(1,0,AC_MSKB0)//[0:0]

//Page FILM_GRAIN_2
#define REG_FG0_16 (FG_BASE + 0x0D8)
    #define REG_FG0_16_FG0_REG_CR_LUMA_MULTI Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG0_16_FG0_REG_CB_LUMA_MULTI Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG0_16_FG0_REG_CR_CHROMA_MULTI Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG0_16_FG0_REG_CB_CHROMA_MULTI Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG0_17 (FG_BASE + 0x0DC)
    #define REG_FG0_17_FG0_DC_Y_LINES Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG0_17_FG0_GRAIN_SEED Fld(16,0,AC_FULLW10)//[15:0]
#define REG_FG0_18 (FG_BASE + 0x0E0)
    #define REG_FG0_18_FG0_REG_CROP_HSIZE Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG0_18_FG0_REG_CROP_HSTART Fld(14,0,AC_MSKW10)//[13:0]
#define REG_FG0_19 (FG_BASE + 0x0E4)
    #define REG_FG0_19_FG0_REG_MAX_IDENTIFY Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_FG0_19_FG0_REG_CR_OFF Fld(9,16,AC_MSKW32)//[24:16]
    #define REG_FG0_19_FG0_REG_CB_OFF Fld(9,0,AC_MSKW10)//[8:0]
#define REG_FG1_00 (FG_BASE + 0x100)
    #define REG_FG1_00_FG1_REG_AR_COFF_Y_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_00_FG1_REG_AR_COFF_Y_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_00_FG1_REG_AR_COFF_Y_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_00_FG1_REG_AR_COFF_Y_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_01 (FG_BASE + 0x104)
    #define REG_FG1_01_FG1_REG_AR_COFF_Y_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_01_FG1_REG_AR_COFF_Y_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_01_FG1_REG_AR_COFF_Y_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_01_FG1_REG_AR_COFF_Y_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_02 (FG_BASE + 0x108)
    #define REG_FG1_02_FG1_REG_AR_COFF_Y_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_02_FG1_REG_AR_COFF_Y_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_02_FG1_REG_AR_COFF_Y_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_02_FG1_REG_AR_COFF_Y_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_03 (FG_BASE + 0x10C)
    #define REG_FG1_03_FG1_REG_AR_COFF_Y_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_03_FG1_REG_AR_COFF_Y_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_03_FG1_REG_AR_COFF_Y_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_03_FG1_REG_AR_COFF_Y_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_04 (FG_BASE + 0x110)
    #define REG_FG1_04_FG1_REG_AR_COFF_Y_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_04_FG1_REG_AR_COFF_Y_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_04_FG1_REG_AR_COFF_Y_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_04_FG1_REG_AR_COFF_Y_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_05 (FG_BASE + 0x114)
    #define REG_FG1_05_FG1_REG_AR_COFF_Y_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_05_FG1_REG_AR_COFF_Y_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_05_FG1_REG_AR_COFF_Y_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_05_FG1_REG_AR_COFF_Y_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_06 (FG_BASE + 0x118)
    #define REG_FG1_06_FG1_REG_AR_COFF_CB_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_06_FG1_REG_AR_COFF_CB_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_06_FG1_REG_AR_COFF_CB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_06_FG1_REG_AR_COFF_CB_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_07 (FG_BASE + 0x11C)
    #define REG_FG1_07_FG1_REG_AR_COFF_CB_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_07_FG1_REG_AR_COFF_CB_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_07_FG1_REG_AR_COFF_CB_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_07_FG1_REG_AR_COFF_CB_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_08 (FG_BASE + 0x120)
    #define REG_FG1_08_FG1_REG_AR_COFF_CB_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_08_FG1_REG_AR_COFF_CB_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_08_FG1_REG_AR_COFF_CB_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_08_FG1_REG_AR_COFF_CB_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_09 (FG_BASE + 0x124)
    #define REG_FG1_09_FG1_REG_AR_COFF_CB_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_09_FG1_REG_AR_COFF_CB_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_09_FG1_REG_AR_COFF_CB_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_09_FG1_REG_AR_COFF_CB_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_0A (FG_BASE + 0x128)
    #define REG_FG1_0A_FG1_REG_AR_COFF_CB_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_0A_FG1_REG_AR_COFF_CB_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_0A_FG1_REG_AR_COFF_CB_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_0A_FG1_REG_AR_COFF_CB_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_0B (FG_BASE + 0x12C)
    #define REG_FG1_0B_FG1_REG_AR_COFF_CB_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_0B_FG1_REG_AR_COFF_CB_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_0B_FG1_REG_AR_COFF_CB_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_0B_FG1_REG_AR_COFF_CB_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_0C (FG_BASE + 0x130)
    #define REG_FG1_0C_FG1_REG_AR_COFF_CB_24 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_0D (FG_BASE + 0x134)
    #define REG_FG1_0D_FG1_REG_AR_COFF_CB_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_0D_FG1_REG_AR_COFF_CB_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_0D_FG1_REG_AR_COFF_CB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_0D_FG1_REG_AR_COFF_CB_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_0E (FG_BASE + 0x138)
    #define REG_FG1_0E_FG1_REG_AR_COFF_CB_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_0E_FG1_REG_AR_COFF_CB_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_0E_FG1_REG_AR_COFF_CB_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_0E_FG1_REG_AR_COFF_CB_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_0F (FG_BASE + 0x13C)
    #define REG_FG1_0F_FG1_REG_AR_COFF_CB_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_0F_FG1_REG_AR_COFF_CB_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_0F_FG1_REG_AR_COFF_CB_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_0F_FG1_REG_AR_COFF_CB_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_10 (FG_BASE + 0x140)
    #define REG_FG1_10_FG1_REG_AR_COFF_CB_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_10_FG1_REG_AR_COFF_CB_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_10_FG1_REG_AR_COFF_CB_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_10_FG1_REG_AR_COFF_CB_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_11 (FG_BASE + 0x144)
    #define REG_FG1_11_FG1_REG_AR_COFF_CB_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_11_FG1_REG_AR_COFF_CB_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_11_FG1_REG_AR_COFF_CB_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_11_FG1_REG_AR_COFF_CB_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_12 (FG_BASE + 0x148)
    #define REG_FG1_12_FG1_REG_AR_COFF_CB_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_12_FG1_REG_AR_COFF_CB_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_12_FG1_REG_AR_COFF_CB_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_12_FG1_REG_AR_COFF_CB_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_13 (FG_BASE + 0x14C)
    #define REG_FG1_13_FG1_REG_AR_COFF_SHIFT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_FG1_13_FG1_REG_AR_COFF_CB_24 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_14 (FG_BASE + 0x150)
    #define REG_FG1_14_FG1_REG_CROP_VSIZE Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG1_14_FG1_REG_CROP_VSTART Fld(14,0,AC_MSKW10)//[13:0]
#define REG_FG1_15 (FG_BASE + 0x154)
    #define REG_FG1_15_FG1_MASK_HSIZE_DIFF Fld(6,20,AC_MSKW32)//[25:20]
    #define REG_FG1_15_FG1_REG_HMASK_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_FG1_15_FG1_REG_FILM_GRAIN_FORCE_ACK Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_FG1_15_FG1_REG_SCALING_SHIFT Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_FG1_15_FG1_REG_CHROMA_SCALING_FROM_LUMA Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_FG1_15_FG1_REG_FILM_GRAIN_FORCE_WRITE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_FG1_15_FG1_REG_CHROMA_SCALING_MD Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_FG1_15_FG1_REG_OVERLAP_MD Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_FG1_15_FG1_REG_CLIP_TO_RESTRICTED_RANGE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_FG1_15_FG1_REG_FG_CR_BYPASS_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_FG1_15_FG1_REG_FG_CB_BYPASS_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_FG1_15_FG1_REG_FG_Y_BYPASS_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_FG1_15_FG1_REG_10B_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG1_15_FG1_REG_420_REPEAT_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG1_15_FG1_REG_420REPEAT_LA_MD Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG1_15_FG1_REG_FLD_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG1_15_FG1_REG_ORI_CEN_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG1_15_FG1_REG_VMIR Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG1_15_FG1_REG_CROP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_FG1_16 (FG_BASE + 0x158)
    #define REG_FG1_16_FG1_REG_CR_LUMA_MULTI Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG1_16_FG1_REG_CB_LUMA_MULTI Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG1_16_FG1_REG_CR_CHROMA_MULTI Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG1_16_FG1_REG_CB_CHROMA_MULTI Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG1_17 (FG_BASE + 0x15C)
    #define REG_FG1_17_FG1_DC_Y_LINES Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG1_17_FG1_GRAIN_SEED Fld(16,0,AC_FULLW10)//[15:0]
#define REG_FG1_18 (FG_BASE + 0x160)
    #define REG_FG1_18_FG1_REG_CROP_HSIZE Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG1_18_FG1_REG_CROP_HSTART Fld(14,0,AC_MSKW10)//[13:0]
#define REG_FG1_19 (FG_BASE + 0x164)
    #define REG_FG1_19_FG1_REG_MAX_IDENTIFY Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_FG1_19_FG1_REG_CR_OFF Fld(9,16,AC_MSKW32)//[24:16]
    #define REG_FG1_19_FG1_REG_CB_OFF Fld(9,0,AC_MSKW10)//[8:0]
#define REG_FG2_00 (FG_BASE + 0x180)
    #define REG_FG2_00_FG2_REG_AR_COFF_Y_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_00_FG2_REG_AR_COFF_Y_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_00_FG2_REG_AR_COFF_Y_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_00_FG2_REG_AR_COFF_Y_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_01 (FG_BASE + 0x184)
    #define REG_FG2_01_FG2_REG_AR_COFF_Y_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_01_FG2_REG_AR_COFF_Y_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_01_FG2_REG_AR_COFF_Y_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_01_FG2_REG_AR_COFF_Y_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_02 (FG_BASE + 0x188)
    #define REG_FG2_02_FG2_REG_AR_COFF_Y_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_02_FG2_REG_AR_COFF_Y_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_02_FG2_REG_AR_COFF_Y_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_02_FG2_REG_AR_COFF_Y_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_03 (FG_BASE + 0x18C)
    #define REG_FG2_03_FG2_REG_AR_COFF_Y_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_03_FG2_REG_AR_COFF_Y_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_03_FG2_REG_AR_COFF_Y_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_03_FG2_REG_AR_COFF_Y_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_04 (FG_BASE + 0x190)
    #define REG_FG2_04_FG2_REG_AR_COFF_Y_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_04_FG2_REG_AR_COFF_Y_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_04_FG2_REG_AR_COFF_Y_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_04_FG2_REG_AR_COFF_Y_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_05 (FG_BASE + 0x194)
    #define REG_FG2_05_FG2_REG_AR_COFF_Y_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_05_FG2_REG_AR_COFF_Y_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_05_FG2_REG_AR_COFF_Y_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_05_FG2_REG_AR_COFF_Y_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_06 (FG_BASE + 0x198)
    #define REG_FG2_06_FG2_REG_AR_COFF_CB_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_06_FG2_REG_AR_COFF_CB_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_06_FG2_REG_AR_COFF_CB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_06_FG2_REG_AR_COFF_CB_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_07 (FG_BASE + 0x19C)
    #define REG_FG2_07_FG2_REG_AR_COFF_CB_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_07_FG2_REG_AR_COFF_CB_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_07_FG2_REG_AR_COFF_CB_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_07_FG2_REG_AR_COFF_CB_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_08 (FG_BASE + 0x1A0)
    #define REG_FG2_08_FG2_REG_AR_COFF_CB_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_08_FG2_REG_AR_COFF_CB_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_08_FG2_REG_AR_COFF_CB_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_08_FG2_REG_AR_COFF_CB_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_09 (FG_BASE + 0x1A4)
    #define REG_FG2_09_FG2_REG_AR_COFF_CB_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_09_FG2_REG_AR_COFF_CB_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_09_FG2_REG_AR_COFF_CB_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_09_FG2_REG_AR_COFF_CB_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_0A (FG_BASE + 0x1A8)
    #define REG_FG2_0A_FG2_REG_AR_COFF_CB_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_0A_FG2_REG_AR_COFF_CB_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_0A_FG2_REG_AR_COFF_CB_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_0A_FG2_REG_AR_COFF_CB_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_0B (FG_BASE + 0x1AC)
    #define REG_FG2_0B_FG2_REG_AR_COFF_CB_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_0B_FG2_REG_AR_COFF_CB_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_0B_FG2_REG_AR_COFF_CB_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_0B_FG2_REG_AR_COFF_CB_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_0C (FG_BASE + 0x1B0)
    #define REG_FG2_0C_FG2_REG_AR_COFF_CB_24 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_0D (FG_BASE + 0x1B4)
    #define REG_FG2_0D_FG2_REG_AR_COFF_CB_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_0D_FG2_REG_AR_COFF_CB_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_0D_FG2_REG_AR_COFF_CB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_0D_FG2_REG_AR_COFF_CB_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_0E (FG_BASE + 0x1B8)
    #define REG_FG2_0E_FG2_REG_AR_COFF_CB_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_0E_FG2_REG_AR_COFF_CB_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_0E_FG2_REG_AR_COFF_CB_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_0E_FG2_REG_AR_COFF_CB_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_0F (FG_BASE + 0x1BC)
    #define REG_FG2_0F_FG2_REG_AR_COFF_CB_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_0F_FG2_REG_AR_COFF_CB_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_0F_FG2_REG_AR_COFF_CB_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_0F_FG2_REG_AR_COFF_CB_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_10 (FG_BASE + 0x1C0)
    #define REG_FG2_10_FG2_REG_AR_COFF_CB_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_10_FG2_REG_AR_COFF_CB_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_10_FG2_REG_AR_COFF_CB_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_10_FG2_REG_AR_COFF_CB_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_11 (FG_BASE + 0x1C4)
    #define REG_FG2_11_FG2_REG_AR_COFF_CB_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_11_FG2_REG_AR_COFF_CB_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_11_FG2_REG_AR_COFF_CB_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_11_FG2_REG_AR_COFF_CB_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_12 (FG_BASE + 0x1C8)
    #define REG_FG2_12_FG2_REG_AR_COFF_CB_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_12_FG2_REG_AR_COFF_CB_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_12_FG2_REG_AR_COFF_CB_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_12_FG2_REG_AR_COFF_CB_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_13 (FG_BASE + 0x1CC)
    #define REG_FG2_13_FG2_REG_AR_COFF_SHIFT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_FG2_13_FG2_REG_AR_COFF_CB_24 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_14 (FG_BASE + 0x1D0)
    #define REG_FG2_14_FG2_REG_CROP_VSIZE Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG2_14_FG2_REG_CROP_VSTART Fld(14,0,AC_MSKW10)//[13:0]
#define REG_FG2_15 (FG_BASE + 0x1D4)
    #define REG_FG2_15_FG2_MASK_HSIZE_DIFF Fld(6,20,AC_MSKW32)//[25:20]
    #define REG_FG2_15_FG2_REG_HMASK_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_FG2_15_FG2_REG_FILM_GRAIN_FORCE_ACK Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_FG2_15_FG2_REG_SCALING_SHIFT Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_FG2_15_FG2_REG_CHROMA_SCALING_FROM_LUMA Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_FG2_15_FG2_REG_FILM_GRAIN_FORCE_WRITE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_FG2_15_FG2_REG_CHROMA_SCALING_MD Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_FG2_15_FG2_REG_OVERLAP_MD Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_FG2_15_FG2_REG_CLIP_TO_RESTRICTED_RANGE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_FG2_15_FG2_REG_FG_CR_BYPASS_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_FG2_15_FG2_REG_FG_CB_BYPASS_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_FG2_15_FG2_REG_FG_Y_BYPASS_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_FG2_15_FG2_REG_10B_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG2_15_FG2_REG_420_REPEAT_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG2_15_FG2_REG_420REPEAT_LA_MD Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG2_15_FG2_REG_FLD_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG2_15_FG2_REG_ORI_CEN_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG2_15_FG2_REG_VMIR Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG2_15_FG2_REG_CROP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_FG2_16 (FG_BASE + 0x1D8)
    #define REG_FG2_16_FG2_REG_CR_LUMA_MULTI Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG2_16_FG2_REG_CB_LUMA_MULTI Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG2_16_FG2_REG_CR_CHROMA_MULTI Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG2_16_FG2_REG_CB_CHROMA_MULTI Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG2_17 (FG_BASE + 0x1DC)
    #define REG_FG2_17_FG2_DC_Y_LINES Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG2_17_FG2_GRAIN_SEED Fld(16,0,AC_FULLW10)//[15:0]
#define REG_FG2_18 (FG_BASE + 0x1E0)
    #define REG_FG2_18_FG2_REG_CROP_HSIZE Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG2_18_FG2_REG_CROP_HSTART Fld(14,0,AC_MSKW10)//[13:0]
#define REG_FG2_19 (FG_BASE + 0x1E4)
    #define REG_FG2_19_FG2_REG_MAX_IDENTIFY Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_FG2_19_FG2_REG_CR_OFF Fld(9,16,AC_MSKW32)//[24:16]
    #define REG_FG2_19_FG2_REG_CB_OFF Fld(9,0,AC_MSKW10)//[8:0]
#define REG_FG3_00 (FG_BASE + 0x200)
    #define REG_FG3_00_FG3_REG_AR_COFF_Y_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_00_FG3_REG_AR_COFF_Y_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_00_FG3_REG_AR_COFF_Y_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_00_FG3_REG_AR_COFF_Y_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_01 (FG_BASE + 0x204)
    #define REG_FG3_01_FG3_REG_AR_COFF_Y_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_01_FG3_REG_AR_COFF_Y_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_01_FG3_REG_AR_COFF_Y_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_01_FG3_REG_AR_COFF_Y_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_02 (FG_BASE + 0x208)
    #define REG_FG3_02_FG3_REG_AR_COFF_Y_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_02_FG3_REG_AR_COFF_Y_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_02_FG3_REG_AR_COFF_Y_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_02_FG3_REG_AR_COFF_Y_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_03 (FG_BASE + 0x20C)
    #define REG_FG3_03_FG3_REG_AR_COFF_Y_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_03_FG3_REG_AR_COFF_Y_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_03_FG3_REG_AR_COFF_Y_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_03_FG3_REG_AR_COFF_Y_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_04 (FG_BASE + 0x210)
    #define REG_FG3_04_FG3_REG_AR_COFF_Y_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_04_FG3_REG_AR_COFF_Y_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_04_FG3_REG_AR_COFF_Y_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_04_FG3_REG_AR_COFF_Y_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_05 (FG_BASE + 0x214)
    #define REG_FG3_05_FG3_REG_AR_COFF_Y_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_05_FG3_REG_AR_COFF_Y_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_05_FG3_REG_AR_COFF_Y_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_05_FG3_REG_AR_COFF_Y_20 Fld(8,0,AC_FULLB0)//[7:0]

//Page FILM_GRAIN_3
#define REG_FG3_06 (FG_BASE + 0x218)
    #define REG_FG3_06_FG3_REG_AR_COFF_CB_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_06_FG3_REG_AR_COFF_CB_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_06_FG3_REG_AR_COFF_CB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_06_FG3_REG_AR_COFF_CB_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_07 (FG_BASE + 0x21C)
    #define REG_FG3_07_FG3_REG_AR_COFF_CB_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_07_FG3_REG_AR_COFF_CB_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_07_FG3_REG_AR_COFF_CB_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_07_FG3_REG_AR_COFF_CB_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_08 (FG_BASE + 0x220)
    #define REG_FG3_08_FG3_REG_AR_COFF_CB_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_08_FG3_REG_AR_COFF_CB_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_08_FG3_REG_AR_COFF_CB_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_08_FG3_REG_AR_COFF_CB_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_09 (FG_BASE + 0x224)
    #define REG_FG3_09_FG3_REG_AR_COFF_CB_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_09_FG3_REG_AR_COFF_CB_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_09_FG3_REG_AR_COFF_CB_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_09_FG3_REG_AR_COFF_CB_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_0A (FG_BASE + 0x228)
    #define REG_FG3_0A_FG3_REG_AR_COFF_CB_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_0A_FG3_REG_AR_COFF_CB_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_0A_FG3_REG_AR_COFF_CB_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_0A_FG3_REG_AR_COFF_CB_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_0B (FG_BASE + 0x22C)
    #define REG_FG3_0B_FG3_REG_AR_COFF_CB_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_0B_FG3_REG_AR_COFF_CB_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_0B_FG3_REG_AR_COFF_CB_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_0B_FG3_REG_AR_COFF_CB_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_0C (FG_BASE + 0x230)
    #define REG_FG3_0C_FG3_REG_AR_COFF_CB_24 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_0D (FG_BASE + 0x234)
    #define REG_FG3_0D_FG3_REG_AR_COFF_CB_3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_0D_FG3_REG_AR_COFF_CB_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_0D_FG3_REG_AR_COFF_CB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_0D_FG3_REG_AR_COFF_CB_0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_0E (FG_BASE + 0x238)
    #define REG_FG3_0E_FG3_REG_AR_COFF_CB_7 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_0E_FG3_REG_AR_COFF_CB_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_0E_FG3_REG_AR_COFF_CB_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_0E_FG3_REG_AR_COFF_CB_4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_0F (FG_BASE + 0x23C)
    #define REG_FG3_0F_FG3_REG_AR_COFF_CB_11 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_0F_FG3_REG_AR_COFF_CB_10 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_0F_FG3_REG_AR_COFF_CB_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_0F_FG3_REG_AR_COFF_CB_8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_10 (FG_BASE + 0x240)
    #define REG_FG3_10_FG3_REG_AR_COFF_CB_15 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_10_FG3_REG_AR_COFF_CB_14 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_10_FG3_REG_AR_COFF_CB_13 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_10_FG3_REG_AR_COFF_CB_12 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_11 (FG_BASE + 0x244)
    #define REG_FG3_11_FG3_REG_AR_COFF_CB_19 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_11_FG3_REG_AR_COFF_CB_18 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_11_FG3_REG_AR_COFF_CB_17 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_11_FG3_REG_AR_COFF_CB_16 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_12 (FG_BASE + 0x248)
    #define REG_FG3_12_FG3_REG_AR_COFF_CB_23 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_12_FG3_REG_AR_COFF_CB_22 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_12_FG3_REG_AR_COFF_CB_21 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_12_FG3_REG_AR_COFF_CB_20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_13 (FG_BASE + 0x24C)
    #define REG_FG3_13_FG3_REG_AR_COFF_SHIFT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_FG3_13_FG3_REG_AR_COFF_CB_24 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_14 (FG_BASE + 0x250)
    #define REG_FG3_14_FG3_REG_CROP_VSIZE Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG3_14_FG3_REG_CROP_VSTART Fld(14,0,AC_MSKW10)//[13:0]
#define REG_FG3_15 (FG_BASE + 0x254)
    #define REG_FG3_15_FG3_MASK_HSIZE_DIFF Fld(6,20,AC_MSKW32)//[25:20]
    #define REG_FG3_15_FG3_REG_HMASK_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_FG3_15_FG3_REG_FILM_GRAIN_FORCE_ACK Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_FG3_15_FG3_REG_SCALING_SHIFT Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_FG3_15_FG3_REG_CHROMA_SCALING_FROM_LUMA Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_FG3_15_FG3_REG_FILM_GRAIN_FORCE_WRITE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_FG3_15_FG3_REG_CHROMA_SCALING_MD Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_FG3_15_FG3_REG_OVERLAP_MD Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_FG3_15_FG3_REG_CLIP_TO_RESTRICTED_RANGE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_FG3_15_FG3_REG_FG_CR_BYPASS_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_FG3_15_FG3_REG_FG_CB_BYPASS_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_FG3_15_FG3_REG_FG_Y_BYPASS_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_FG3_15_FG3_REG_10B_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_FG3_15_FG3_REG_420_REPEAT_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_FG3_15_FG3_REG_420REPEAT_LA_MD Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_FG3_15_FG3_REG_FLD_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_FG3_15_FG3_REG_ORI_CEN_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_FG3_15_FG3_REG_VMIR Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_FG3_15_FG3_REG_CROP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_FG3_16 (FG_BASE + 0x258)
    #define REG_FG3_16_FG3_REG_CR_LUMA_MULTI Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_FG3_16_FG3_REG_CB_LUMA_MULTI Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_FG3_16_FG3_REG_CR_CHROMA_MULTI Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_FG3_16_FG3_REG_CB_CHROMA_MULTI Fld(8,0,AC_FULLB0)//[7:0]
#define REG_FG3_17 (FG_BASE + 0x25C)
    #define REG_FG3_17_FG3_DC_Y_LINES Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG3_17_FG3_GRAIN_SEED Fld(16,0,AC_FULLW10)//[15:0]
#define REG_FG3_18 (FG_BASE + 0x260)
    #define REG_FG3_18_FG3_REG_CROP_HSIZE Fld(14,16,AC_MSKW32)//[29:16]
    #define REG_FG3_18_FG3_REG_CROP_HSTART Fld(14,0,AC_MSKW10)//[13:0]
#define REG_FG3_19 (FG_BASE + 0x264)
    #define REG_FG3_19_FG3_REG_MAX_IDENTIFY Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_FG3_19_FG3_REG_CR_OFF Fld(9,16,AC_MSKW32)//[24:16]
    #define REG_FG3_19_FG3_REG_CB_OFF Fld(9,0,AC_MSKW10)//[8:0]
#define REG_ADL_01 (FG_BASE + 0x404)
    #define REG_ADL_01_REG_CLIENT1_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_01_REG_CLIENT2_1_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_01_REG_CLIENT3_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_ADL_01_REG_CLIENT1_TRIG_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_ADL_01_REG_CLIENT2_TRIG_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_ADL_01_REG_CLIENT3_TRIG_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_ADL_01_REG_CLIENT4_TRIG_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_ADL_01_REG_CLIENT5_TRIG_MODE Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_ADL_01_REG_REQ_PRI Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_ADL_01_REG_CLIENT1_CLK_GATE_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_ADL_01_REG_CLIENT2_CLK_GATE_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_ADL_01_REG_CLIENT3_CLK_GATE_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_ADL_01_REG_CLIENT4_CLK_GATE_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_ADL_01_REG_CLIENT5_CLK_GATE_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_ADL_01_REG_CLIENT6_CLK_GATE_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_ADL_01_REG_CLIENT6_TRIG_MODE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_ADL_02 (FG_BASE + 0x408)
    #define REG_ADL_02_REG_CLIENT1_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_03 (FG_BASE + 0x40C)
    #define REG_ADL_03_REG_CLIENT1_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_04 (FG_BASE + 0x410)
    #define REG_ADL_04_REG_CLIENT2_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_05 (FG_BASE + 0x414)
    #define REG_ADL_05_REG_CLIENT2_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_06 (FG_BASE + 0x418)
    #define REG_ADL_06_REG_CLIENT3_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_07 (FG_BASE + 0x41C)
    #define REG_ADL_07_REG_CLIENT3_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_08 (FG_BASE + 0x420)
    #define REG_ADL_08_REG_CLIENT1_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_09 (FG_BASE + 0x424)
    #define REG_ADL_09_REG_CLIENT2_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_0A (FG_BASE + 0x428)
    #define REG_ADL_0A_REG_CLIENT3_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_0B (FG_BASE + 0x42C)
    #define REG_ADL_0B_REG_CLIENT1_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_0C (FG_BASE + 0x430)
    #define REG_ADL_0C_REG_CLIENT2_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_0D (FG_BASE + 0x434)
    #define REG_ADL_0D_REG_CLIENT3_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_0E (FG_BASE + 0x438)
    #define REG_ADL_0E_REG_CLIENT1_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_0F (FG_BASE + 0x43C)
    #define REG_ADL_0F_REG_CLIENT2_1_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_10 (FG_BASE + 0x440)
    #define REG_ADL_10_REG_CLIENT3_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_11 (FG_BASE + 0x444)
    #define REG_ADL_11_REG_CLIENT4_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_11_REG_CLIENT5_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_11_REG_CLIENT6_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_12 (FG_BASE + 0x448)
    #define REG_ADL_12_REG_CLIENT4_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_13 (FG_BASE + 0x44C)
    #define REG_ADL_13_REG_CLIENT4_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_14 (FG_BASE + 0x450)
    #define REG_ADL_14_REG_CLIENT5_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_15 (FG_BASE + 0x454)
    #define REG_ADL_15_REG_CLIENT5_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_16 (FG_BASE + 0x458)
    #define REG_ADL_16_REG_CLIENT6_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_17 (FG_BASE + 0x45C)
    #define REG_ADL_17_REG_CLIENT6_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_18 (FG_BASE + 0x460)
    #define REG_ADL_18_REG_CLIENT4_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_19 (FG_BASE + 0x464)
    #define REG_ADL_19_REG_CLIENT5_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_1A (FG_BASE + 0x468)
    #define REG_ADL_1A_REG_CLIENT6_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_1B (FG_BASE + 0x46C)
    #define REG_ADL_1B_REG_CLIENT4_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_1C (FG_BASE + 0x470)
    #define REG_ADL_1C_REG_CLIENT5_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_1D (FG_BASE + 0x474)
    #define REG_ADL_1D_REG_CLIENT6_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_1E (FG_BASE + 0x478)
    #define REG_ADL_1E_REG_CLIENT4_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_1F (FG_BASE + 0x47C)
    #define REG_ADL_1F_REG_CLIENT5_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_20 (FG_BASE + 0x480)
    #define REG_ADL_20_REG_CLIENT6_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_21 (FG_BASE + 0x484)
    #define REG_ADL_21_REG_CLIENT2_2_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_21_REG_CLIENT2_3_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_21_REG_CLIENT3_HIGH_PRI_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_22 (FG_BASE + 0x488)
    #define REG_ADL_22_REG_CLIENT7_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_22_REG_CLIENT7_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_22_REG_CLIENT7_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_23 (FG_BASE + 0x48C)
    #define REG_ADL_23_REG_CLIENT7_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_24 (FG_BASE + 0x490)
    #define REG_ADL_24_REG_CLIENT7_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_25 (FG_BASE + 0x494)
    #define REG_ADL_25_REG_CLIENT7_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_26 (FG_BASE + 0x498)
    #define REG_ADL_26_REG_CLIENT7_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_27 (FG_BASE + 0x49C)
    #define REG_ADL_27_REG_CLIENT7_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_28 (FG_BASE + 0x4A0)
    #define REG_ADL_28_REG_CLIENT8_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_28_REG_CLIENT8_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_28_REG_CLIENT8_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_29 (FG_BASE + 0x4A4)
    #define REG_ADL_29_REG_CLIENT8_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_2A (FG_BASE + 0x4A8)
    #define REG_ADL_2A_REG_CLIENT8_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_2B (FG_BASE + 0x4AC)
    #define REG_ADL_2B_REG_CLIENT8_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_2C (FG_BASE + 0x4B0)
    #define REG_ADL_2C_REG_CLIENT8_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_2D (FG_BASE + 0x4B4)
    #define REG_ADL_2D_REG_CLIENT8_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_2E (FG_BASE + 0x4B8)
    #define REG_ADL_2E_REG_CLIENT2_2_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_31 (FG_BASE + 0x4BC)
    #define REG_ADL_31_REG_CLIENT2_3_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_32 (FG_BASE + 0x4C8)
    #define REG_ADL_32_REG_CLIENT9_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_32_REG_CLIENT9_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_32_REG_CLIENT9_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_33 (FG_BASE + 0x4CC)
    #define REG_ADL_33_REG_CLIENT9_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_34 (FG_BASE + 0x4D0)
    #define REG_ADL_34_REG_CLIENT9_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_35 (FG_BASE + 0x4D4)
    #define REG_ADL_35_REG_CLIENT9_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_36 (FG_BASE + 0x4D8)
    #define REG_ADL_36_REG_CLIENT9_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_37 (FG_BASE + 0x4DC)
    #define REG_ADL_37_REG_CLIENT9_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_38 (FG_BASE + 0x4E0)
    #define REG_ADL_38_REG_ADL_SW_TRIG_EN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_39 (FG_BASE + 0x4E4)
    #define REG_ADL_39_REG_ADL_SW_TRIG Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_3A (FG_BASE + 0x4E8)
    #define REG_ADL_3A_REG_ADL_SW_TRIG_EN_EXT Fld(7,0,AC_MSKB0)//[6:0]
#define REG_ADL_3B (FG_BASE + 0x4EC)
    #define REG_ADL_3B_REG_ADL_SW_TRIG_EXT Fld(7,0,AC_MSKB0)//[6:0]
#define REG_ADL_3F (FG_BASE + 0x4FC)
    #define REG_ADL_3F_REG_MIU_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_ADL_40 (FG_BASE + 0x500)
    #define REG_ADL_40_REG_CLIENT4_1_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_41 (FG_BASE + 0x504)
    #define REG_ADL_41_REG_CLIENT4_1_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_ADL_41_REG_CLIENT4_TRIG_MODE_SEL Fld(1,15,AC_MSKB1)//[15:15]
#define REG_ADL_43 (FG_BASE + 0x50C)
    #define REG_ADL_43_REG_CLIENTF_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_43_REG_CLIENTF_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_43_REG_CLIENTF_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_44 (FG_BASE + 0x510)
    #define REG_ADL_44_REG_CLIENTF_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_45 (FG_BASE + 0x514)
    #define REG_ADL_45_REG_CLIENTF_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_46 (FG_BASE + 0x518)
    #define REG_ADL_46_REG_CLIENTB_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_46_REG_CLIENTB_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_46_REG_CLIENTB_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_47 (FG_BASE + 0x51C)
    #define REG_ADL_47_REG_CLIENTB_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_48 (FG_BASE + 0x520)
    #define REG_ADL_48_REG_CLIENTB_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_49 (FG_BASE + 0x524)
    #define REG_ADL_49_REG_CLIENTB_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_4A (FG_BASE + 0x528)
    #define REG_ADL_4A_REG_CLIENTB_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_4B (FG_BASE + 0x52C)
    #define REG_ADL_4B_REG_CLIENTB_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_4D (FG_BASE + 0x534)
    #define REG_ADL_4D_REG_CLIENTF_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_4E (FG_BASE + 0x538)
    #define REG_ADL_4E_REG_CLIENTF_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_4F (FG_BASE + 0x53C)
    #define REG_ADL_4F_REG_CLIENTF_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_50 (FG_BASE + 0x540)
    #define REG_ADL_50_REG_CLIENTC_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_50_REG_CLIENTC_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_50_REG_CLIENTC_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_51 (FG_BASE + 0x544)
    #define REG_ADL_51_REG_CLIENTC_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_52 (FG_BASE + 0x548)
    #define REG_ADL_52_REG_CLIENTC_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_53 (FG_BASE + 0x54C)
    #define REG_ADL_53_REG_CLIENTC_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_54 (FG_BASE + 0x550)
    #define REG_ADL_54_REG_CLIENTC_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_55 (FG_BASE + 0x554)
    #define REG_ADL_55_REG_CLIENTC_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_56 (FG_BASE + 0x558)
    #define REG_ADL_56_REG_CLIENTD_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_56_REG_CLIENTD_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_56_REG_CLIENTD_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_57 (FG_BASE + 0x55C)
    #define REG_ADL_57_REG_CLIENTD_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_58 (FG_BASE + 0x560)
    #define REG_ADL_58_REG_CLIENTD_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_59 (FG_BASE + 0x564)
    #define REG_ADL_59_REG_CLIENTD_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_5A (FG_BASE + 0x568)
    #define REG_ADL_5A_REG_CLIENTD_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_5B (FG_BASE + 0x56C)
    #define REG_ADL_5B_REG_CLIENTD_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_60 (FG_BASE + 0x580)
    #define REG_ADL_60_REG_CLIENTE_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_60_REG_CLIENTE_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_60_REG_CLIENTE_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_61 (FG_BASE + 0x584)
    #define REG_ADL_61_REG_CLIENTE_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_62 (FG_BASE + 0x588)
    #define REG_ADL_62_REG_CLIENTE_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_63 (FG_BASE + 0x58C)
    #define REG_ADL_63_REG_CLIENTE_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_64 (FG_BASE + 0x590)
    #define REG_ADL_64_REG_CLIENTE_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_65 (FG_BASE + 0x594)
    #define REG_ADL_65_REG_CLIENTE_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]

//Page FILM_GRAIN_4
#define REG_ADL_66 (FG_BASE + 0x598)
    #define REG_ADL_66_REG_CLIENTA_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_66_REG_CLIENTA_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_66_REG_CLIENTA_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_67 (FG_BASE + 0x59C)
    #define REG_ADL_67_REG_CLIENTA_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_68 (FG_BASE + 0x5A0)
    #define REG_ADL_68_REG_CLIENTA_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_69 (FG_BASE + 0x5A4)
    #define REG_ADL_69_REG_CLIENTA_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_6A (FG_BASE + 0x5A8)
    #define REG_ADL_6A_REG_CLIENTA_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_6B (FG_BASE + 0x5AC)
    #define REG_ADL_6B_REG_CLIENTA_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_6E (FG_BASE + 0x5B8)
    #define REG_ADL_6E_REG_ADL_HW_TRIG_INV Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_6F (FG_BASE + 0x5BC)
    #define REG_ADL_6F_REG_ADL_HW_TRIG_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_70 (FG_BASE + 0x5C0)
    #define REG_ADL_70_REG_WD_TIMER Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_ADL_70_REG_WD_TIME_OUT_CLR Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_ADL_70_REG_WD_TIME_OUT Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_ADL_70_REG_WD_TIMER_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_ADL_71 (FG_BASE + 0x5C4)
    #define REG_ADL_71_REG_CLIENTG_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_71_REG_CLIENTG_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_71_REG_CLIENTG_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_72 (FG_BASE + 0x5C8)
    #define REG_ADL_72_REG_CLIENTG_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_73 (FG_BASE + 0x5CC)
    #define REG_ADL_73_REG_CLIENTG_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_74 (FG_BASE + 0x5D0)
    #define REG_ADL_74_REG_CLIENTG_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_75 (FG_BASE + 0x5D4)
    #define REG_ADL_75_REG_CLIENTG_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_76 (FG_BASE + 0x5D8)
    #define REG_ADL_76_REG_CLIENTG_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_77 (FG_BASE + 0x5DC)
    #define REG_ADL_77_REG_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_77_REG_FORCE_IDX_0 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_77_REG_DEBUG_PROBE_EN Fld(1,3,AC_MSKB0)//[3:3]
#define REG_ADL_78 (FG_BASE + 0x5E0)
    #define REG_ADL_78_REG_CLIENTH_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_ADL_78_REG_CLIENTH_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_ADL_78_REG_CLIENTH_CLK_GATE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_ADL_79 (FG_BASE + 0x5E4)
    #define REG_ADL_79_REG_CLIENTH_BASEADR_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_7A (FG_BASE + 0x5E8)
    #define REG_ADL_7A_REG_CLIENTH_BASEADR_28_16 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_ADL_7B (FG_BASE + 0x5EC)
    #define REG_ADL_7B_REG_CLIENTH_DEPTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_7C (FG_BASE + 0x5F0)
    #define REG_ADL_7C_REG_CLIENTH_REQ_LEN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_7D (FG_BASE + 0x5F4)
    #define REG_ADL_7D_REG_CLIENTH_INI_ADDR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_ADL_7E (FG_BASE + 0x5F8)
    #define REG_ADL_7E_REG_ADL_HW_TRIG_INV_EXT Fld(5,0,AC_MSKB0)//[4:0]
#define REG_ADL_7F (FG_BASE + 0x5FC)
    #define REG_ADL_7F_REG_ADL_HW_TRIG_SEL_EXT Fld(5,0,AC_MSKB0)//[4:0]

#endif    

