/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: brianpc.huang $
 * $Date  $
 * $RCSfile: dram_map.h,v $
 * $Revision: #1 $
 *
 *---------------------------------------------------------------------------*/

#ifndef _DRAM_MAP_H_
#define _DRAM_MAP_H_

#include "typedef.h"
#include "vendor.h"
#include "feature.h"
#include "debug.h"

/*****************************************************************************
  Dram Allocation Mapping
  ***************************************************************************/
#define Macro8Align(value)  ((value + 7) & 0xFFFFFFF8)
#define Macro256Align(value)  ((value + 255) & 0xFFFFFF00)
#define Macro8KAlign(value) ((value + 0x2000 - 0x01) & 0xFFFFE000)
#define Macro128KAlign(value) ((value + 131071L) & 0xFFFE0000)

/* start */
//#define UP_DRAM_BASE 0x06000000

/* SI DRAM */
//#define SI_DRAM_BASE UP_DRAM_BASE
//#define SI_DRAM_SIZE 0x1000	//4096

/* EEP DRAM Allocate and Size */
// #define EEP_DRAM_BASE (SI_DRAM_BASE + SI_DRAM_SIZE)
// #define EEP_DRAM_SIZE 0x2000 // 8192

#if 0
/* VGA Table */
#define VGA_TABLE_BASE (SI_DRAM_BASE + SI_DRAM_SIZE)
#define MAX_VGA_TABLE_SIZE 0x1000 // ToDo
#endif

#if 0
/* VBI Working Size */
#define VBI_DRAM_BASE (SI_DRAM_BASE+SI_DRAM_SIZE)
#define VBI_DRAM_SIZE 0x1200
#endif

#if 0
/* TTX DRAM Allocate and Size */
#define TTX_DRAM_BASE (VGA_TABLE_BASE + MAX_VGA_TABLE_SIZE)
#if SUPPORT_TELETEXT
	#if TTX_1KPAGE_DEC
	#define TTX_DRAM_SIZE 0x12c640//0x12C000 // (1200*1024L)
	#else
	#define TTX_DRAM_SIZE 0x1E000	// (120*1024L)
	#endif
#else
	#define TTX_DRAM_SIZE 0
#endif

#define PAGEINFO_DRAM_BASE Macro8KAlign(VBI_DRAM_BASE + VBI_DRAM_SIZE)
#if SUPPORT_TELETEXT
#define PAGEINFO_DRAM_SIZE 0x10000
#else
#define PAGEINFO_DRAM_SIZE 0
#endif
#endif

/* Video Module DRAM Allocate */
// #define _VIDEO_DRAM_BASE	(PAGEINFO_DRAM_BASE + PAGEINFO_DRAM_SIZE)	// 5371 0x06000000//(OSD_DRAM_BASE+OSD_DRAM_SIZE)
//#define _VIDEO_DRAM_BASE	(SI_DRAM_BASE+SI_DRAM_SIZE)

/*****************************************************************************
  The following are VIDEO dram allocation
****************************************************************************/
#if 0
#define DI_DRAM_BASE VIDEO_DRAM_BASE

#define DI_MBA_SIZE 13312L //13*1024
#define DI_720_576I_SIZE 414720L //720*576
#define DI_720_1080I_SIZE 777600L //720*1080
#define DI_1440_1080I_SIZE 1555200L //1440*1080

#if SUPPORT_POP
	#define DI_MBUF_SIZE DI_1440_1080I_SIZE
	#define DI_PBUF_SIZE DI_720_1080I_SIZE
#else
		#define DI_MBUF_SIZE DI_1440_1080I_SIZE       
#endif //SUPPORT_POP

//Main MDDi
#define DI_MBUF0_Y_DRAM_BASE Macro8Align(DI_DRAM_BASE)
#define DI_MBUF0_C_DRAM_BASE Macro8Align(DI_MBUF0_Y_DRAM_BASE + DI_MBUF_SIZE)
#define DI_MBUF1_Y_DRAM_BASE Macro8Align(DI_MBUF0_C_DRAM_BASE + DI_MBUF_SIZE)
#define DI_MBUF1_C_DRAM_BASE Macro8Align(DI_MBUF1_Y_DRAM_BASE + DI_MBUF_SIZE)

#define DI_6FBUF0_DRAM_BASE Macro8Align(DI_MBUF1_C_DRAM_BASE + DI_720_576I_SIZE)
#define DI_6FBUF1_DRAM_BASE Macro8Align(DI_6FBUF0_DRAM_BASE + DI_MBA_SIZE)
#define DI_6FBUF2_DRAM_BASE Macro8Align(DI_6FBUF1_DRAM_BASE + DI_MBA_SIZE)
#define DI_6FBUF3_DRAM_BASE Macro8Align(DI_6FBUF2_DRAM_BASE + DI_MBA_SIZE)

#if SUPPORT_POP
//Pip MDDi
#define P_DI_MBUF0_Y_DRAM_BASE Macro8Align(DI_MBUF0_Y_DRAM_BASE + DI_PBUF_SIZE)
#define P_DI_MBUF0_C_DRAM_BASE Macro8Align(DI_MBUF0_C_DRAM_BASE + DI_PBUF_SIZE)
#define P_DI_MBUF1_Y_DRAM_BASE Macro8Align(DI_MBUF1_Y_DRAM_BASE + DI_PBUF_SIZE)
#define P_DI_MBUF1_C_DRAM_BASE Macro8Align(DI_MBUF1_C_DRAM_BASE + DI_PBUF_SIZE)

#define P_DI_6FBUF0_DRAM_BASE Macro8Align(P_DI_MBUF1_C_DRAM_BASE + DI_720_576I_SIZE)
#define P_DI_6FBUF1_DRAM_BASE Macro8Align(P_DI_6FBUF0_DRAM_BASE + DI_MBA_SIZE)
#define P_DI_6FBUF2_DRAM_BASE Macro8Align(P_DI_6FBUF1_DRAM_BASE + DI_MBA_SIZE)
#define P_DI_6FBUF3_DRAM_BASE Macro8Align(P_DI_6FBUF2_DRAM_BASE + DI_MBA_SIZE)
#endif //SUPPORT_POP
#endif

#if 0
// SCPOS
#if (DI_MBUF_SIZE == DI_720_576I_SIZE)
	#define SCPOS_DRAM_BASE Macro8Align(DI_MBUF0_Y_DRAM_BASE + ((DI_MBUF_SIZE + DI_MBA_SIZE) * 4))
#else
	#define SCPOS_DRAM_BASE Macro8Align(DI_MBUF0_Y_DRAM_BASE + (DI_MBUF_SIZE * 4))
#endif //(DI_MBUF_SIZE == DI_720_576I_SIZE)

	#define SCPOS_MAIN_SIZE Macro8KAlign((TV_WIDTH+4) * TV_HEIGHT * 3 * 2 + 64)

#if SUPPORT_POP
#define SCPOS_PIP_SIZE Macro8KAlign(724 * TV_HEIGHT * 2 * 3 + 64)
#else
	#define SCPOS_PIP_SIZE 0
	#endif
#endif


#define TDC_USE_FBM_POOL 1

#if !TDC_USE_FBM_POOL
#define TDC_BUF_SIZE 0x251ca0	//(304020*8) 
#endif

#if 0
//TDC
#define TDC_DRAM_BASE Macro8Align(SCPOS_DRAM_BASE + SCPOS_MAIN_SIZE + SCPOS_PIP_SIZE)

#if SUPPORT_3DCOMB
#define TDC_DRAM_SIZE 0x251ca0	//(304020*8) 
#else
#define TDC_DRAM_SIZE 0        
#endif
#endif

#if 0
//NR
#define NR_DRAM_BASE Macro8Align(TDC_DRAM_SIZE + TDC_DRAM_BASE)
#if SUPPORT_TDN
#define NR_DRAM_SIZE 0x90000	// (1024*576)
#else
#define NR_DRAM_SIZE 0x0
#endif //SUPPORT_TDN
#endif

extern UINT32 NR_DRAM_BASE;
extern UINT32 NR_DRAM_SIZE;
extern UINT32 TDC_DRAM_BASE;
extern UINT32 TDC_DRAM_SIZE;
extern UINT32 VBI_DRAM_BASE;
extern UINT32 VBI_DRAM_SIZE;

/*****************************************************************************
  Dram Allocation Variable Declaration
  ***************************************************************************/
// Audio
//extern UINT32 DSP_MOD_BASE;
// Video
//extern UINT32 VIDEO_DRAM_BASE;

#endif
