//***************************************************************************
//!file     si_device_edid.c
//!brief    HDMI/MHL, VGA EDID and NVRAM Boot data
//
// No part of this work may be reproduced, modified, distributed,
// transmitted, transcribed, or translated into any language or computer
// format, in any form or by any means without written permission of
// Silicon Image, Inc., 1060 East Arques Avenue, Sunnyvale, California 94085
//
// Copyright 2002-2010, Silicon Image, Inc.  All rights reserved.
//***************************************************************************/

#include "sk_configure.h"
#include "si_edid_component.h"
#include "si_c99support.h"

//------------------------------------------------------------------------------
//  Module Data
//------------------------------------------------------------------------------

/* VGA EDID Table */

const uint8_t gEdidFlashEdidVgaTable [ EDID_VGA_TABLE_LEN ] =
{
/*  00    01    02   03     04    05    06    07   08     09    0A    0B    0C    0D    0E    0F */
    0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x10, 0xAC, 0x12, 0x40, 0x51, 0x53, 0x44, 0x42,
    0x1C, 0x10, 0x01, 0x03, 0x0E, 0x22, 0x1B, 0x78, 0xEE, 0xE7, 0xE5, 0xA3, 0x59, 0x4A, 0x9E, 0x23,
    0x14, 0x50, 0x54, 0xA5, 0x4B, 0x00, 0x71, 0x4F, 0x81, 0x80, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x30, 0x2A, 0x00, 0x98, 0x51, 0x00, 0x2A, 0x40, 0x30, 0x70,
    0x13, 0x00, 0x52, 0x0E, 0x11, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x43, 0x43, 0x32,
    0x38, 0x30, 0x36, 0x37, 0x45, 0x42, 0x44, 0x53, 0x51, 0x0A, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x44,
    0x45, 0x4C, 0x4C, 0x20, 0x31, 0x37, 0x30, 0x37, 0x46, 0x50, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
    0x00, 0x38, 0x4C, 0x1E, 0x51, 0x0E, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x1D
};


/* HDMI/MHL EDID Table */

const uint8_t gEdidFlashEdidTable [ EDID_TABLE_LEN ] =
#if (FPGA_BUILD == DISABLE)
{
/*  00    01    02   03     04    05    06    07   08     09    0A    0B    0C    0D    0E    0F */
	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x50, 0x6C, 0x87, 0x96, 0x01, 0x00, 0x00, 0x00,
	0x14, 0x17, 0x01, 0x03, 0x80, 0x52, 0x2E, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
	0x12, 0x48, 0x4C, 0x21, 0x09, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
	0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0x66, 0x21, 0x50, 0xB0, 0x51, 0x00, 0x1B, 0x30,
	0x40, 0x70, 0x36, 0x00, 0x34, 0xCC, 0x31, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
	0x43, 0x4C, 0x20, 0x53, 0x4D, 0x41, 0x52, 0x54, 0x20, 0x54, 0x56, 0x0A, 0x00, 0x00, 0x00, 0xFD,
	0x00, 0x17, 0x78, 0x0F, 0x85, 0x1E, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xC9,
															       
	0x02, 0x03, 0x31, 0x72, 0x55, 0x90, 0x04, 0x03, 0x02, 0x0E, 0x0F, 0x07, 0x23, 0x24, 0x05, 0x14,
	0x13, 0x12, 0x11, 0x1D, 0x1E, 0x20, 0x21, 0x22, 0x01, 0x1F, 0x23, 0x09, 0x07, 0x07, 0x83, 0x01,
	0x00, 0x00, 0x6E, 0x03, 0x0C, 0x00, 0x10, 0x00, 0xF8, 0x3C, 0x21, 0x84, 0x60, 0x01, 0x02, 0x03,
	0x00, 0x02, 0x3A, 0x80, 0xD0, 0x72, 0x38, 0x2D, 0x40, 0x10, 0x2C, 0x45, 0x80, 0xC4, 0x8E, 0x21,
	0x00, 0x00, 0x1E, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xC4,
	0x8E, 0x21, 0x00, 0x00, 0x9E, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, 0x6E, 0x28, 0x55,
	0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0xBC, 0x52, 0xD0, 0x1E, 0x20, 0xB8,
	0x28, 0x55, 0x40, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55
};
#define EDID_B1_CSUM        0x55 // Last byte of EDID above ------------------------------------^
#define CEC_PA_ADDR         0xA6 // Offset of PA in EDID (... 03 0C 00 *10* 00 ...)
#else
{ // 720p limited, DC not supported
/*  00    01    02   03     04    05    06    07   08     09    0A    0B    0C    0D    0E    0F */
    0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x4D, 0x29, 0x87, 0x96, 0x01, 0x00, 0x00, 0x00,
    0x20, 0x15, 0x01, 0x03, 0x80, 0x52, 0x2E, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
    0x12, 0x48, 0x4C, 0x21, 0x09, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
    0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
    0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x43,
    0x50, 0x39, 0x36, 0x38, 0x37, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
    0x00, 0x17, 0x78, 0x0F, 0x85, 0x1E, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x15,

    0x02, 0x03, 0x3D, 0x72, 0x55, 0x01, 0x84, 0x03, 0x02, 0x0E, 0x0F, 0x07, 0x23, 0x24, 0x85, 0x94,
    0x13, 0x12, 0x11, 0x1D, 0x1E, 0x20, 0x21, 0x22, 0x01, 0x1F, 0x23, 0x09, 0x7F, 0x07, 0x83, 0x01,
    0x00, 0x00, 0x6D, 0x03, 0x0C, 0x00, 0x10, 0x00, 0x80, 0x10, 0x21, 0x84, 0x60, 0x01, 0x02, 0x03,
    0x00, 0x2C, 0x10, 0x10, 0x3E, 0x96, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18, 0x8C, 0x0A, 0xD0,
    0x90, 0x20, 0x40, 0x31, 0x20, 0x0C, 0x40, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18, 0x01,
    0x1D, 0x80, 0x18, 0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00,
    0x9E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE7
};
#define EDID_B1_CSUM        0xE7 // Last byte of EDID above ------------------------------------^
#define CEC_PA_ADDR         0xA6 // Offset of PA in EDID (... 03 0C 00 *10* 00 ...)
#endif

#if (MHL_EXTRA == ENABLE)
// TODO:: TV Vendor needs to populate this
// These are the 2D Short Video Descriptors that are supported also in 3D
// These should be exactly in the same order as they are listed in EDID Block 1 (CEA-861)
const uint8_t g3DEdidTableVIC [ EDID_3D_VIC_TABLE_LEN ] =
{
	0x00, 	// burst_id_h
	0x10, 	// burst_id_l
	0xC9, 	// checksum:: for this particular WRITE_BURST of max 16 bytes, this includes all the entries
			//			  along with checksum itself, pls see MHL spec for more info
	0x15, 	// total # of MHL Video Descriptors in 3D_VIC Write_Burst sequence
	0x01,	// sequence of this particular WRITE_BURST among others
	0x05,	// number of 2 byte entries in this WRITE_BURST, anywhere between 0 to 5
	0x00, 0x00, 0x00, 0x04, 0x00, 0x03, 0x00, 0x05, 0x00, 0x00, // entries

	0x00, 	// burst_id_h , ,
	0x10, 	// burst_id_l
	0xC4, 	// checksum:: for this particular WRITE_BURST of max 16 bytes, this includes all the entries
			//			  along with checksum itself, pls see MHL spec for more info
	0x15, 	// total # of MHL Video Descriptors in 3D_VIC Write_Burst sequence
	0x02,	// sequence of this particular WRITE_BURST among others
	0x05,	// number of 2 byte entries in this WRITE_BURST, anywhere between 0 to 5
	0x00, 0x00, 0x00, 0x04, 0x00, 0x03, 0x00, 0x07, 0x00, 0x02, // entries

	0x00, 	// burst_id_h , ,
	0x10, 	// burst_id_l
	0xC5, 	// checksum:: for this particular WRITE_BURST of max 16 bytes, this includes all the entries
			//			  along with checksum itself, pls see MHL spec for more info
	0x15, 	// total # of MHL Video Descriptors in 3D_VIC Write_Burst sequence
	0x03,	// sequence of this particular WRITE_BURST among others
	0x05,	// number of 2 byte entries in this WRITE_BURST, anywhere between 0 to 5
	0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x06, 0x00, 0x01, // entries

	0x00, 	// burst_id_h , ,
	0x10, 	// burst_id_l
	0xC1, 	// checksum:: for this particular WRITE_BURST of max 16 bytes, this includes all the entries
			//			  along with checksum itself, pls see MHL spec for more info
	0x15, 	// total # of MHL Video Descriptors in 3D_VIC Write_Burst sequence
	0x04,	// sequence of this particular WRITE_BURST among others
	0x05,	// number of 2 byte entries in this WRITE_BURST, anywhere between 0 to 5
	0x00, 0x00, 0x00, 0x03, 0x00, 0x04, 0x00, 0x03, 0x00, 0x07, // entries

	0x00, 	// burst_id_h , ,
	0x10, 	// burst_id_l
	0x5F, 	// checksum:: for this particular WRITE_BURST of max 16 bytes, this includes all the entries
			//			  along with checksum itself, pls see MHL spec for more info
	0x15, 	// total # of MHL Video Descriptors in 3D_VIC Write_Burst sequence
	0x05,	// sequence of this particular WRITE_BURST among others
	0x01,	// number of 2 byte entries in this WRITE_BURST, anywhere between 0 to 5
	0x00, 0x06, 0xDE, 0xAD, 0xBE, 0xEF, 0xDE, 0xAD, 0xBE, 0xEF, // entries
};

// TODO:: TV Vendor needs to populate this
// These are the 2D Detailed Timing Descriptors that are supported also in 3D
// These should be exactly in the same order as they are listed in EDID Block 0 and 1
// Block 1 (CEA-861) DTDs should follow after Block 0's
const uint8_t g3DEdidTableDTD [ EDID_3D_DTD_TABLE_LEN ] =
{
	0x00, 	// burst_id_h
	0x11, 	// burst_id_l
	0xA6, 	// checksum:: for this particular WRITE_BURST of max 16 bytes, this includes all the entries
			//			  along with checksum itself, pls see MHL spec for more info
	0x04, 	// total # of MHL Detailed Timing Descriptors in 3D_DTD Write_Burst sequence
	0x01,	// sequence of this particular WRITE_BURST among others
	0x02,	// number of 2 byte entries in this WRITE_BURST, anywhere between 0 to 5
	0x00, 0x06, 0x00, 0x05, 0xDE, 0xAD, 0xBE, 0xEF, 0xAA, 0x55, // entries

	0x00, 	// burst_id_h , ,
	0x11, 	// burst_id_l
	0xA5, 	// checksum:: for this particular WRITE_BURST of max 16 bytes, this includes all the entries
			//			  along with checksum itself, pls see MHL spec for more info
	0x04, 	// total # of MHL Detailed Timing Descriptors in 3D_DTD Write_Burst sequence
	0x02,	// sequence of this particular WRITE_BURST among others
	0x02,	// number of 2 byte entries in this WRITE_BURST, anywhere between 0 to 5
	0x00, 0x06, 0x00, 0x05, 0xDE, 0xAD, 0xBE, 0xEF, 0xAA, 0x55, // entries
};
#endif

// EDID table is supposed to have PA = 1000
#define CSUM_PA_0     EDID_B1_CSUM                    	    // PA = 1000
#define CSUM_PA_1   ((EDID_B1_CSUM - 0x10) & 0xFF)    // PA = 2000
#define CSUM_PA_2   ((EDID_B1_CSUM - 0x20) & 0xFF)    // PA = 3000
#define CSUM_PA_3   ((EDID_B1_CSUM - 0x30) & 0xFF)    // PA = 4000

const SiiDeviceBootData_t gEdidFlashDevBootData =
{
    0xAA,           //00: nvm_config
    0x55,           //01: edid_valid
    0x06,           //02: nvm_version
    0x0F,           //03: edid_copy_dest
    0x0F,           //04: hpd_hw_ctrl
    0x00,           //05: i2c_filter_sel, sda_delay_en & ddc_filter_sel. CAUTION: non-zero value may lock up I2C permanently
    0x00,           //06: wakeup_source
    0x00,           //07: edid_vga_copy_dest
    { 0xFF, 0xFF }, //08,09: spare1[2]
    CEC_PA_ADDR,    //0A: cec_pa_addr
    { 0xFF },       //0B: spare2[1]
    0x20,           //0C: cec_pad_h_ch0
    0x00,           //0D: cec_pad_l_ch0
    0x10,           //0E: cec_pad_h_ch1
    0x00,           //0F: cec_pad_l_ch1
    0x30,           //10: cec_pad_h_ch2
    0x00,           //11: cec_pad_l_ch2
    0x40,           //12: cec_pad_h_ch3
    0x00,           //13: cec_pad_l_ch3
    { 0xFF, 0xFF }, //14,15: spare3[2]
    0x00,           //16: reserved
    0x00,           //17: reserved
    { 0xFF, 0xFF, 0xFF, 0xFF },//18-1B: spare4[4]
    CSUM_PA_1,      //1C: checksum_ch0
    CSUM_PA_0,      //1D: checksum_ch1
    CSUM_PA_2,      //1E: checksum_ch2
    CSUM_PA_3,      //1F: checksum_ch3
    { 0xFF },       //20: spare5[1]
    0x00,           //21: reserved
    { 0xFF, 0xFF }, //22,23: spare6[2]
    (1 << SK_CBUS_PORT), //24: cbus_port_select
    0x00,           //25: mhl_version_supported
    0xC4,           //26: RSEN and External Reset, mhl_1x_en, mhl_hpd_en, term_timer_en
    { 0x00 },       //27: Spare7[1]
    0x27,           //28:
    {               //29-3F: spare8[24]
      0,            //29: reserved
      0,            //2A: reserved
      0,            //2B: reserved
      0             //2C: reserved
    }
};

