/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


/*****************************************************************************
 *
 * Filename:
 * ---------
 *   $Workfile: hw_tcon.h $ 
 *
 * Project:
 * --------
 *   MT5365
 *
 * Description:
 * ------------
 *   T-CON Module miscellaneous register definition
 *   
 * Author:
 * -------
 *   Nick674 Liu
 *
 * Last changed:
 * ------------- 
 * $Author: brianpc.huang $ 
 *
 * $Modtime: 10/02/04 1:22p $  
 *
 * $Revision: #1 $
****************************************************************************/

#ifndef _HW_TCON_
#define _HW_TCON_

#define EH_00 (IO_VIRT + 0x02008400)
	#define EH_FRAME_METER_EN_OSD Fld(1,30,AC_MSKB3)//[30:30]
	#define EH_DISPR_DETECT_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define EH_DISPR_PAT_LLRR Fld(1,28,AC_MSKB3)//[28:28]
    #define EH_DISPR_PAT_FIX_DISPR_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define EH_DISPR_PAT_FIX_DISPR_VAL Fld(1,26,AC_MSKB3)//[26:26]
    #define EH_DISPR_MUTE Fld(1,25,AC_MSKB3)//[25:25]
    #define EH_INPUT_SEL Fld(1,24,AC_MSKB3)//[24:24]
    #define EH_FRAME_METER_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define EH_INV_OUT_VS_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define EH_INV_OUT_HS_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define EH_DUAL_CHAN_PROCESS Fld(1,19,AC_MSKB2)//[19:19]
    #define EH_H_CALI_WO_FILTER Fld(1,18,AC_MSKB2)//[18:18]
    #define EH_REAL_TIME_CALI_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define EH_MUTE_MLVDS_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define EH_SET_DATA_TIME_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define EH_XTAL_CLK_RST Fld(1,2,AC_MSKB0)//[2:2]
    #define EH_OCLK_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define EH_REG_RST Fld(1,0,AC_MSKB0)//[0:0]
#define EH_01 (IO_VIRT + 0x02008404)
    #define EH_CLK_MISS_CHECK_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define EH_VDE_GEN_SEL Fld(1,30,AC_MSKB3)//[30:30]
    #define EH_MUTE_DDDS_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define EH_DE_MISS_MUTE_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define EH_USE_SC_TIMING_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define EH_INV_VS_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define IEH_NV_HS_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define EH_CLK_STABLE_CHECK_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define EH_VDE_STABLE_CHECK_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define EH_DE_STABLE_CHECK_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define EH_V_STABLE_CHECK_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define EH_H_STABLE_CHECK_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define EH_STABLE_CHECK_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define EH_CONFIG_RDY_WO_FM Fld(1,15,AC_MSKB1)//[15:15]
    #define EH_CONFIG_RDY_WO_STABLE Fld(1,14,AC_MSKB1)//[14:14]
    #define EH_DISP_MLVDS_WO_DDDS_LOCK Fld(1,13,AC_MSKB1)//[13:13]
    #define EH_DISP_MLVDS_WO_OD_RDY Fld(1,12,AC_MSKB1)//[12:12]
    #define EH_SW_MUTE Fld(1,9,AC_MSKB1)//[9:9]
    #define EH_SW_MUTE_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define EH_SCALER_MUTE_LVDS_RX_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define EH_H_MISS_MUTE_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define EH_CLK_MUTE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define EH_VDE_MUTE_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define EH_DE_MUTE_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define EH_V_MUTE_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define EH_H_MUTE_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define EH_FAST_MUTE_EN Fld(1,0,AC_MSKB0)//[0:0]
#define EH_02 (IO_VIRT + 0x02008408)
    #define EH_FAST_MUTE_H_TOTAL_HIGH_TH Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_FAST_MUTE_H_TOTAL_LOW_TH Fld(13,0,AC_MSKW10)//[12:0]
#define EH_03 (IO_VIRT + 0x0200840C)
    #define EH_FAST_MUTE_V_TOTAL_HIGH_TH Fld(12,16,AC_MSKW32)//[27:16]
    #define EH_FAST_MUTE_V_TOTAL_LOW_TH Fld(12,0,AC_MSKW10)//[11:0]
#define EH_04 (IO_VIRT + 0x02008410)
    #define EH_FAST_MUTE_DE_TOTAL_HIGH_TH Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_FAST_MUTE_DE_TOTAL_LOW_TH Fld(13,0,AC_MSKW10)//[12:0]
#define EH_05 (IO_VIRT + 0x02008414)
    #define EH_FAST_MUTE_VDE_TOTAL_HIGH_TH Fld(12,16,AC_MSKW32)//[27:16]
    #define EH_FAST_MUTE_VDE_TOTAL_LOW_TH Fld(12,0,AC_MSKW10)//[11:0]
#define EH_06 (IO_VIRT + 0x02008418)
    #define EH_FAST_MUTE_CLK_TOTAL_HIGH_TH Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_FAST_MUTE_CLK_TOTAL_LOW_TH Fld(13,0,AC_MSKW10)//[12:0]
#define EH_07 (IO_VIRT + 0x0200841C)
    #define EH_CLK_MUTE_TEST_PERIOD Fld(2,28,AC_MSKB3)//[29:28]
    #define EH_CLK_MISS_PERIOD_SEL Fld(3,24,AC_MSKB3)//[26:24]
    #define EH_FAST_MUTE_CLK_CNT_TH Fld(8,16,AC_FULLB2)//[23:16]
    #define EH_FAST_MUTE_V_CNT_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define EH_FAST_MUTE_H_CNT_TH Fld(8,0,AC_FULLB0)//[7:0]
#define EH_08 (IO_VIRT + 0x02008420)
    #define EH_V_STB_CNT_TH Fld(8,24,AC_FULLB3)//[31:24]
    #define EH_V_STB_DIFF_TH Fld(8,16,AC_FULLB2)//[23:16]
    #define EH_H_STB_CNT_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define EH_H_STB_DIFF_TH Fld(8,0,AC_FULLB0)//[7:0]
#define EH_09 (IO_VIRT + 0x02008424)
    #define EH_VDE_STB_CNT_TH Fld(8,24,AC_FULLB3)//[31:24]
    #define EH_VDE_STB_DIFF_TH Fld(8,16,AC_FULLB2)//[23:16]
    #define EH_DE_STB_CNT_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define EH_DE_STB_DIFF_TH Fld(8,0,AC_FULLB0)//[7:0]
#define EH_0A (IO_VIRT + 0x02008428)
    #define EH_CLK_STB_CNT_TH Fld(16,8,AC_FULLW21)//[23:8]
    #define EH_CLK_STB_DIFF_TH Fld(8,0,AC_FULLB0)//[7:0]
#define EH_0B (IO_VIRT + 0x0200842C)
    #define EH_CALI_RANGE_SEL Fld(2,30,AC_MSKB3)//[31:30]
    #define EH_CALI_WO_STABLE Fld(1,29,AC_MSKB3)//[29:29]
    #define EH_CALI_RANGE_L Fld(12,16,AC_MSKW32)//[27:16]
    #define EH_CALI_RANGE_H Fld(12,0,AC_MSKW10)//[11:0]
#define EH_0C (IO_VIRT + 0x02008430)
    #define EH_DE_MODE_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define EH_DE_HS_WIDTH Fld(12,16,AC_MSKW32)//[27:16]
    #define EH_DE_HS_START Fld(13,0,AC_MSKW10)//[12:0]
#define EH_0D (IO_VIRT + 0x02008434)
    #define EH_DE_VS_WIDTH Fld(12,16,AC_MSKW32)//[27:16]
    #define EH_DE_VS_START Fld(13,0,AC_MSKW10)//[12:0]
#define EH_0E (IO_VIRT + 0x02008438)
    #define EH_FIXED_DE_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define EH_FIXED_VDE_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define EH_SET_LOW_HTOTAL_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define EH_OD_VDE_FIX_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define EH_WXGA_DATA_DELAY_SEL Fld(1,23,AC_MSKB2)//[23:23]
    #define EH_CALI_MONI_SEL Fld(2,21,AC_MSKB2)//[22:21]
    #define EH_DE_COUNTER_RESET_SEL Fld(1,20,AC_MSKB2)//[20:20]
    #define EH_DE_DEGLITCH_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define EH_HTOTAL_CALI_MEDAIN_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define EH_HTOTAL_CALI_LOW_PASS_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define EH_MUTE_MLVDS_OFF_WHEN_PTGEN Fld(1,16,AC_MSKB2)//[16:16]
    #define EH_MUTE_MLVDS_PERIOD Fld(8,8,AC_FULLB1)//[15:8]
    #define EH_EH_MONI_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define EH_0F (IO_VIRT + 0x0200843C)  // delete ???
	#define EH_OSD_B_SWAP Fld(2,0,AC_MSKB0)//[7:6]
	#define EH_OSD_G_SWAP Fld(2,0,AC_MSKB0)//[5:4]
	#define EH_OSD_R_SWAP Fld(2,0,AC_MSKB0)//[3:2]
	#define EH_OSD_A_SWAP Fld(2,0,AC_MSKB0)//[1:0]
#define EH_10 (IO_VIRT + 0x02008440)
    #define EH_PTGEN_H_ACTIVE Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_PTGEN_H_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
#define EH_11 (IO_VIRT + 0x02008444)
    #define EH_PTGEN_H_WIDTH Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_PTGEN_H_START Fld(13,0,AC_MSKW10)//[12:0]
#define EH_12 (IO_VIRT + 0x02008448)
    #define EH_PTGEN_V_ACTIVE Fld(11,16,AC_MSKW32)//[26:16]
    #define EH_PTGEN_V_TOTAL Fld(11,0,AC_MSKW10)//[10:0]
#define EH_13 (IO_VIRT + 0x0200844C)
    #define EH_PTGEN_V_WIDTH Fld(11,16,AC_MSKW32)//[26:16]
    #define EH_PTGEN_V_START Fld(11,0,AC_MSKW10)//[10:0]
#define EH_14 (IO_VIRT + 0x02008450)
    #define EH_PTGEN_TYPE_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define EH_PTGEN_B Fld(8,16,AC_FULLB2)//[23:16]
    #define EH_PTGEN_G Fld(8,8,AC_FULLB1)//[15:8]
    #define EH_PTGEN_R Fld(8,0,AC_FULLB0)//[7:0]
#define EH_15 (IO_VIRT + 0x02008454)
    #define EH_AUTO_PTGEN_TIME_TH Fld(10,8,AC_MSKW21)//[17:8]
    #define EH_PTGEN_H_RUN Fld(1,7,AC_MSKB0)//[7:7]
    #define EH_PTGEN_V_RUN Fld(1,6,AC_MSKB0)//[6:6]
    #define RG_PTGEN_BD_DISABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define EH_AUTO_CHG_PTGEN_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define EH_PTGEN_TYPE Fld(2,0,AC_MSKB0)//[1:0]
#define EH_16 (IO_VIRT + 0x02008458)
    #define EH_INTR_CLR Fld(1,16,AC_MSKB2)//[16:16]
    #define EH_INTR_MASK Fld(8,0,AC_FULLB0)//[7:0]
#define EH_17 (IO_VIRT + 0x0200845C)
    #define EH_FAST_MUTE_DE_MISS_TH Fld(12,0,AC_MSKW10)//[11:0]
#define EH_18 (IO_VIRT + 0x02008460)
    #define EH_CALI_HS_USE_SW_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define EH_CALI_VS_USE_SW_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define EH_CALI_DE_USE_SW_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define EH_CALI_VDE_USE_SW_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define EH_DE_VS_TOTAL_SW Fld(12,16,AC_MSKW32)//[27:16]
    #define EH_DE_HS_TOTAL_SW Fld(13,0,AC_MSKW10)//[12:0]
#define EH_19 (IO_VIRT + 0x02008464)
    #define EH_FIX_HTOTAL_VALUE Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_FIX_HTOTAL_TH Fld(13,0,AC_MSKW10)//[12:0]
#define EH_1A (IO_VIRT + 0x02008468)
    #define EH_FIX_VDE_TH Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_FIXED_DE_TOATL Fld(13,0,AC_MSKW10)//[12:0]
#define EH_1B (IO_VIRT + 0x0200846C)  // delete ???
	#define EH_OSD_A7_SEL Fld(3,28,AC_MSKB3)//[30:28]
	#define EH_OSD_A6_SEL Fld(3,24,AC_MSKB3)//[26:24]
	#define EH_OSD_A5_SEL Fld(3,20,AC_MSKB2)//[22:20]
	#define EH_OSD_A4_SEL Fld(3,16,AC_MSKB2)//[18:16]
	#define EH_OSD_A3_SEL Fld(3,12,AC_MSKB1)//[14:12]
	#define EH_OSD_A2_SEL Fld(3,8,AC_MSKB1)//[10:8]
	#define EH_OSD_A1_SEL Fld(3,4,AC_MSKB0)//[6:4]
	#define EH_OSD_A0_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define EH_1C (IO_VIRT + 0x02008470)  // delete ???
	#define EH_OSD_R7_SEL Fld(3,28,AC_MSKB3)//[30:28]
	#define EH_OSD_R6_SEL Fld(3,24,AC_MSKB3)//[26:24]
	#define EH_OSD_R5_SEL Fld(3,20,AC_MSKB2)//[22:20]
	#define EH_OSD_R4_SEL Fld(3,16,AC_MSKB2)//[18:16]
	#define EH_OSD_R3_SEL Fld(3,12,AC_MSKB1)//[14:12]
	#define EH_OSD_R2_SEL Fld(3,8,AC_MSKB1)//[10:8]
	#define EH_OSD_R1_SEL Fld(3,4,AC_MSKB0)//[6:4]
	#define EH_OSD_R0_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define EH_1E (IO_VIRT + 0x02008478)  // delete ???
	#define EH_OSD_G7_SEL Fld(3,28,AC_MSKB3)//[30:28]
	#define EH_OSD_G6_SEL Fld(3,24,AC_MSKB3)//[26:24]
	#define EH_OSD_G5_SEL Fld(3,20,AC_MSKB2)//[22:20]
	#define EH_OSD_G4_SEL Fld(3,16,AC_MSKB2)//[18:16]
	#define EH_OSD_G3_SEL Fld(3,12,AC_MSKB1)//[14:12]
	#define EH_OSD_G2_SEL Fld(3,8,AC_MSKB1)//[10:8]
	#define EH_OSD_G1_SEL Fld(3,4,AC_MSKB0)//[6:4]
	#define EH_OSD_G0_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define EH_1F (IO_VIRT + 0x0200847C)  // delete ???
	#define EH_OSD_B7_SEL Fld(3,28,AC_MSKB3)//[30:28]
	#define EH_OSD_B6_SEL Fld(3,24,AC_MSKB3)//[26:24]
	#define EH_OSD_B5_SEL Fld(3,20,AC_MSKB2)//[22:20]
	#define EH_OSD_B4_SEL Fld(3,16,AC_MSKB2)//[18:16]
	#define EH_OSD_B3_SEL Fld(3,12,AC_MSKB1)//[14:12]
	#define EH_OSD_B2_SEL Fld(3,8,AC_MSKB1)//[10:8]
	#define EH_OSD_B1_SEL Fld(3,4,AC_MSKB0)//[6:4]
	#define EH_OSD_B0_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define EH_STATUS_00 (IO_VIRT + 0x02008480)
    #define EH_DE_TOTAL_MON Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_H_TOTAL_MON Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_01 (IO_VIRT + 0x02008484)
    #define EH_VDE_TOTAL_MON Fld(12,16,AC_MSKW32)//[27:16]
    #define EH_V_TOTAL_MON Fld(12,0,AC_MSKW10)//[11:0]
#define EH_STATUS_02 (IO_VIRT + 0x02008488)
    #define EH_MUTE_STATUS_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define EH_MUTE_STATUS Fld(8,8,AC_FULLB1)//[15:8]
    #define EH_STABLE_STATUS Fld(8,0,AC_FULLB0)//[7:0]
#define EH_FLD_ALL Fld(32, 0, AC_FULLDW) // 31:0
		#define EHS_OD_INTF_ERROR         24
		#define EHS_OD_READY              23
		#define EHS_OD_OK                 22
		#define EHS_MUTE_LVDS             21
		#define EHS_DE_MISS_MUTE          20
		#define EHS_DISP_OK               19
		#define EHS_INPUT_OK              18
		#define EHS_OD_BYPASS             17
		#define EHS_OD_MUTE_DDDS          16
		#define EHS_FAST_MUTE_READY       15
		#define EHS_H_MISS_MUTE           14
		#define EHS_CLOCK_MUTE            13
		#define EHS_VDE_MUTE              12
		#define EHS_V_MUTE                11
		#define EHS_DE_MUTE               10
		#define EHS_H_MUTE                 9
		#define EHS_MUTE                   8
		#define EHS_CONFIG_READY           7
		#define EHS_DDDS_LOCK              6
		#define EHS_CLOCK_STABLE           5
		#define EHS_VDE_STABLE             4
		#define EHS_V_STABLE               3
		#define EHS_DE_STABLE              2
		#define EHS_H_STABLE               1
		#define EHS_STABLE                 0
#define EH_STATUS_03 (IO_VIRT + 0x0200848C)
    #define EH_FAST_MUTE_RELAEASE_TIME Fld(8,8,AC_FULLB1)//[15:8]
    #define EH_STABLE_TIME Fld(8,0,AC_FULLB0)//[7:0]
#define EH_STATUS_04 (IO_VIRT + 0x02008490)
    #define EH_CLK_TOTAL_MON Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_05 (IO_VIRT + 0x02008494)
    #define EH_LVDS_RX_INTR Fld(9,0,AC_MSKW10)//[8:0]
#define EH_STATUS_06 (IO_VIRT + 0x02008498)
    #define EH_H_MAX_MONI Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_H_MIN_MONI Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_07 (IO_VIRT + 0x0200849C)
    #define EH_DE_MAX_MONI Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_DE_MIN_MONI Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_08 (IO_VIRT + 0x020084A0)
    #define EH_DE_TOTAL_CALI Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_H_TOTAL_CALI Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_09 (IO_VIRT + 0x020084A4)
    #define EH_VDE_TOTAL_CALI Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_V_TOTAL_CALI Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_0A (IO_VIRT + 0x020084A8)
    #define EH_H_WIDTH_CALI Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_V_WIDTH_CALI Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_0B (IO_VIRT + 0x020084AC)
    #define EH_H_START_CALI Fld(13,16,AC_MSKW32)//[28:16]
    #define EH_V_START_CALI Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_0D (IO_VIRT + 0x020084B4)
    #define EH_DISP_R_STATUS Fld(2,30,AC_MSKB3)//[31:30]
    #define EH_XCLK_IN_FRAME Fld(24,0,AC_MSKDW)//[23:0]
#define EH_STATUS_0E (IO_VIRT + 0x020084B8)
    #define EH_H_OSD_START_CALI Fld(13,16,AC_MSKW32)//[28:16]
#define EH_STATUS_10 (IO_VIRT + 0x020084C0)
	#define EH_VTOTAL_STATUS Fld(12,16,AC_MSKW32)//[27:16]
	#define EH_HTOTAL_STATUS Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_11 (IO_VIRT + 0x020084C4)
	#define EH_VSTART_STATUS Fld(12,16,AC_MSKW32)//[27:16]
	#define EH_HSTART_STATUS Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_12 (IO_VIRT + 0x020084C8)
    #define EH_VACTIVE_STATUS Fld(12,16,AC_MSKW32)//[27:16]
    #define EH_HACTIVE_STATUS Fld(13,0,AC_MSKW10)//[12:0]
#define EH_STATUS_13 (IO_VIRT + 0x020084CC)
    #define EH_OSD_FRATE_STATUS Fld(24,0,AC_MSKDW)//[23:0]

//Page PWM_INTR
#define PWM_HS_00 (IO_VIRT + 0x02008200)
    #define PWM_HIGH Fld(16,16,AC_FULLW32)//[31:16]
    #define PWM_LOW Fld(16,0,AC_FULLW10)//[15:0]
#define PWM_HS_01 (IO_VIRT + 0x02008204)
    #define PWM_HS_01_PWM_INIT_ATPG_CT Fld(1,31,AC_MSKB3)//[31:31]
    #define PWM_HS_01_PWM_INIT_ATPG_OB Fld(1,30,AC_MSKB3)//[30:30]
	#define TCON_BL_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_PWM_SCAN_BL_DIS_LATCH Fld(1,14,AC_MSKB1)//[14:14]
    #define TCON_BL_IN_POL Fld(1,13,AC_MSKB1)//[13:13]
	#define FRAME_CHANGE_IN_POL Fld(1, 11, AC_MSKB1) //[11:11]
    #define REG_PWM_SCAN_LATCH_OFF Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_PWM_IN_POL_HS Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_PWM_IN_POL_VS Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_PWM_SCAN_SET_DATA_EN Fld(1,7,AC_MSKB0)//[7:7] 
    #define REG_PWM_SCAN_LATCH_SEL Fld(1,6,AC_MSKB0)//[6:6] 
    #define REG_PWM_SCAN_LATCH_OFF2 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_PWM_SCAN_SET_DATA_EN2 Fld(1,4,AC_MSKB0)//[4:4] 
    #define REG_PWM_VSYNC Fld(4,0,AC_MSKB0)//[3:0]
#define PWM_SCAN_00 (IO_VIRT + 0x02008208)
	#define REG_PWM_SCAN1_HIGH_ENABLE Fld(5,27,AC_MSKB3)//[31:27]
	#define REG_PWM_SCAN1_HIGH_FRAME_MODE Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_PWM_SCAN1_START Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_01 (IO_VIRT + 0x0200820C)
	#define RG_VSYNC_SET_PWM_SEL Fld(1,27,AC_MSKDW)//[27:27]
	#define RG_VSYNC_F_DISP_SEL Fld(1,26,AC_MSKDW)//[26:26]
	#define RG_VSYNC_F_PWM_SEL Fld(1,25,AC_MSKDW)//[25:25]
    #define REG_PWM_SCAN1_HIGH Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_02 (IO_VIRT + 0x02008210)
    #define REG_PWM_SCAN1_LOW Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_03 (IO_VIRT + 0x02008214)
	#define REG_PWM_SCAN2_HIGH_ENABLE Fld(5,27,AC_MSKB3)//[31:27]
	#define REG_PWM_SCAN2_HIGH_FRAME_MODE Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_PWM_SCAN2_START Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_04 (IO_VIRT + 0x02008218)
    #define REG_PWM_SCAN2_HIGH Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_05 (IO_VIRT + 0x0200821C)
    #define REG_PWM_SCAN2_LOW Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_06 (IO_VIRT + 0x02008220)
    #define REG_PWM_SCAN2_FIXED_LOW Fld(1,28,AC_MSKB3)//[28:28]
	#define REG_PWM_SCAN2_FIXED_HIGH Fld(1,27,AC_MSKB3)//[27:27]
	#define REG_TCON_3DBL_OUT_EN2 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_PWM_SCAN2_POL Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_PWM_SCAN2_START_HIGH Fld(9,16,AC_MSKW32)//[24:16]
	#define REG_PWM_SCAN1_FIXED_LOW Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_PWM_SCAN1_FIXED_HIGH Fld(1, 11, AC_MSKB1) //[11:11]
    #define REG_TCON_3DBL_OUT_EN1 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_PWM_SCAN1_POL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_PWM_SCAN1_START_HIGH Fld(9,0,AC_MSKW10)//[8:0]
#define INTR_00 (IO_VIRT + 0x02008224)
    #define TCON_INTR_READ Fld(1,31,AC_MSKB3)//[31:31]
    #define FCONT Fld(2,28,AC_MSKB3)//[29:28]
    #define VCONT Fld(4,16,AC_MSKB2)//[19:16]   
    #define STATUS_INTR Fld(8,0,AC_FULLB0)//[7:0]
        #define STATUS_INTR_AMBILIT Fld(1,7,AC_MSKB0)//[7:7]
        #define STATUS_INTR_OSTGLINE Fld(1,6,AC_MSKB0)//[6:6] 
        #define STATUS_INTR_R_FALLING Fld(1,5,AC_MSKB0)//[5:5]
        #define STATUS_INTR_R_RISING Fld(1,4,AC_MSKB0)//[4:4]        
        #define STATUS_INTR_L_FALLING Fld(1,3,AC_MSKB0)//[3:3]
        #define STATUS_INTR_L_RISING Fld(1,2,AC_MSKB0)//[2:2]
        #define STATUS_INTR_LR_FALLING Fld(1,1,AC_MSKB0)//[1:1]
        #define STATUS_INTR_LR_RISING Fld(1,0,AC_MSKB0)//[0:0]          
#define INTR_01 (IO_VIRT + 0x02008228)
    #define FCONTCLR Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_INTR_LINE_LATCH_OFF Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_INTR_LINE Fld(12,0,AC_MSKW10)//[11:0]
#define INTR_02 (IO_VIRT + 0x0200822C)
    #define C_CLR_MODE Fld(1,24,AC_MSKB3)//[24:24]
    #define C_INTR_CLEAR Fld(8,16,AC_FULLB2)//[23:16]
        #define C_INTR_CLEAR_AMBILIT Fld(1,23,AC_MSKB2)//[23:23]
        #define C_INTR_CLEAR_OSTGLINE Fld(1,22,AC_MSKB2)//[22:22]	 
        #define C_INTR_CLEAR_R_FALLING Fld(1,21,AC_MSKB2)//[21:21]
        #define C_INTR_CLEAR_R_RISING Fld(1,20,AC_MSKB2)//[20:20]
        #define C_INTR_CLEAR_L_FALLING Fld(1,19,AC_MSKB2)//[19:19]
        #define C_INTR_CLEAR_L_RISING Fld(1,18,AC_MSKB2)//[18:18]
        #define C_INTR_CLEAR_LR_FALLING Fld(1,17,AC_MSKB2)//[17:17]
        #define C_INTR_CLEAR_LR_RISIN Fld(1,16,AC_MSKB2)//[16:16]        
    #define C_INTR_MASK Fld(8,8,AC_FULLB1)//[15:8]
    #define C_INTR_NEG_SEL Fld(8,0,AC_FULLB0)//[7:0]

// MT5396/68 New feature for ECO
#define PWM_SCAN_07 (IO_VIRT + 0x02008234)
	#define REG_PWM_SCAN3_HIGH_ENABLE Fld(5,27,AC_MSKB3)//[31:27]
	#define REG_PWM_SCAN3_HIGH_FRAME_MODE Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_PWM_SCAN3_START Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_08 (IO_VIRT + 0x02008238)
    #define REG_PWM_SCAN3_HIGH Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_09 (IO_VIRT + 0x0200823C)
    #define REG_PWM_SCAN3_LOW Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_0A (IO_VIRT + 0x02008240)
	#define REG_PWM_SCAN4_HIGH_ENABLE Fld(5,27,AC_MSKB3)//[31:27]
	#define REG_PWM_SCAN4_HIGH_FRAME_MODE Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_PWM_SCAN4_START Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_0B (IO_VIRT + 0x02008244)
    #define REG_PWM_SCAN4_HIGH Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_0C (IO_VIRT + 0x02008248)
    #define REG_PWM_SCAN4_LOW Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_0D (IO_VIRT + 0x0200824C)
	#define REG_PWM_SCAN5_HIGH_ENABLE Fld(5,27,AC_MSKB3)//[31:27]
	#define REG_PWM_SCAN5_HIGH_FRAME_MODE Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_PWM_SCAN5_START Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_0E (IO_VIRT + 0x02008250)
    #define REG_PWM_SCAN5_HIGH Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_0F (IO_VIRT + 0x02008254)
    #define REG_PWM_SCAN5_LOW Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_10 (IO_VIRT + 0x02008258)
	#define REG_PWM_SCAN4_FIXED_LOW Fld(1,28,AC_MSKB3)//[28:28]
	#define REG_PWM_SCAN4_FIXED_HIGH Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_TCON_3DBL_OUT_EN4 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_PWM_SCAN4_POL Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_PWM_SCAN4_START_HIGH Fld(9,16,AC_MSKW32)//[24:16]
    #define REG_PWM_SCAN3_FIXED_LOW Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_PWM_SCAN3_FIXED_HIGH Fld(1, 11, AC_MSKB1) //[11:11]
    #define REG_TCON_3DBL_OUT_EN3 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_PWM_SCAN3_POL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_PWM_SCAN3_START_HIGH Fld(9,0,AC_MSKW10)//[8:0]
#define PWM_SCAN_11 (IO_VIRT + 0x0200825C)
    #define REG_PWM_SCAN6_FIXED_LOW Fld(1,28,AC_MSKB3)//[28:28]
	#define REG_PWM_SCAN6_FIXED_HIGH Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_TCON_3DBL_OUT_EN6 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_PWM_SCAN6_POL Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_PWM_SCAN6_START_HIGH Fld(9,16,AC_MSKW32)//[24:16]
    #define REG_PWM_SCAN5_FIXED_LOW Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_PWM_SCAN5_FIXED_HIGH Fld(1, 11, AC_MSKB1) //[11:11]
    #define REG_TCON_3DBL_OUT_EN5 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_PWM_SCAN5_POL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_PWM_SCAN5_START_HIGH Fld(9,0,AC_MSKW10)//[8:0]
#define PWM_SCAN_12 (IO_VIRT + 0x02008260)
    #define REG_PWM_SCAN5_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_PWM_SCAN4_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_PWM_SCAN3_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_PWM_SCAN2_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_PWM_SCAN1_EN Fld(1,27,AC_MSKB3)//[27:27]
	#define REG_PWM_SCAN6_EN Fld(1,26,AC_MSKB3)//[26:26]
	#define REG_PWM_SCAN5_START_MODE Fld(1,23,AC_MSKB2)//[23:23]
	#define REG_PWM_SCAN4_START_MODE Fld(1,22,AC_MSKB2)//[22:22]	 
    #define REG_PWM_SCAN3_START_MODE Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_PWM_SCAN2_START_MODE Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_PWM_SCAN1_START_MODE Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_PWM_SCAN6_START_MODE Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_PWM_SCAN5_ASYNC_MODE Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_PWM_SCAN4_ASYNC_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_PWM_SCAN3_ASYNC_MODE Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_PWM_SCAN2_ASYNC_MODE Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_PWM_SCAN1_ASYNC_MODE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_PWM_SCAN6_ASYNC_MODE Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_PWM_SCAN_DBG_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define PWM_SCAN_1D (IO_VIRT + 0x02008290)
	#define REG_PWM_SCAN1_LOW_WIDTH_LIMIT Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_1E (IO_VIRT + 0x02008294)
	#define REG_PWM_SCAN2_LOW_WIDTH_LIMIT Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_1F (IO_VIRT + 0x02008298)
	#define REG_PWM_SCAN3_LOW_WIDTH_LIMIT Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_20 (IO_VIRT + 0x0200829C)
	#define REG_PWM_SCAN4_LOW_WIDTH_LIMIT Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_21 (IO_VIRT + 0x020082A0)
	#define REG_PWM_SCAN5_LOW_WIDTH_LIMIT Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_22 (IO_VIRT + 0x020082A4)
	#define REG_PWM_SCAN6_LOW_WIDTH_LIMIT Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_23 (IO_VIRT + 0x020082A8)
	#define REG_PWM_SCAN6_HIGH_ENABLE Fld(5,27,AC_MSKB3)//[31:27]
	#define REG_PWM_SCAN6_HIGH_FRAME_MODE Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_PWM_SCAN6_START Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_24 (IO_VIRT + 0x020082AC)
	#define REG_PWM_SCAN6_HIGH Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_25 (IO_VIRT + 0x020082B0)
	#define REG_PWM_SCAN6_LOW Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_29 (IO_VIRT + 0x020082C0)
	#define REG_PWM_SCAN1_START_PHASE Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_2A (IO_VIRT + 0x020082C4)
	#define REG_PWM_SCAN2_START_PHASE Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_2B (IO_VIRT + 0x020082C8)
	#define REG_PWM_SCAN3_START_PHASE Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_2C (IO_VIRT + 0x020082CC)
	#define REG_PWM_SCAN4_START_PHASE Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_2D (IO_VIRT + 0x020082D0)
	#define REG_PWM_SCAN5_START_PHASE Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_2E (IO_VIRT + 0x020082D4)
	#define REG_PWM_SCAN6_START_PHASE Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_2F (IO_VIRT + 0x020082D8)
	#define REG_PWM_SCAN7_EN Fld(1,31,AC_MSKB3)//[31:31]
	#define REG_PWM_SCAN7_START_MODE Fld(1,30,AC_MSKB3)//[30:30]
	#define REG_PWM_SCAN7_ASYNC_MODE Fld(1,29,AC_MSKB3)//[29:29]
	#define REG_TCON_3DBL_OUT_EN7 Fld(1,28,AC_MSKB3)//[28:28]
	#define REG_PWM_SCAN7_START_PHASE Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_30 (IO_VIRT + 0x020082DC)
	#define REG_PWM_SCAN7_FIXED_LOW Fld(1,31,AC_MSKB3)//[31:31]
	#define REG_PWM_SCAN7_FIXED_HIGH Fld(1,30,AC_MSKB3)//[30:30]
	#define REG_PWM_SCAN7_POL Fld(1,29,AC_MSKB3)//[29:29]
	#define REG_PWM_SCAN7_HIGH_FRAME_MODE Fld(1,28,AC_MSKB3)//[28:28]
	#define REG_PWM_SCAN7_START Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_31 (IO_VIRT + 0x020082E0)
	#define REG_PWM_SCAN7_HIGH Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_32 (IO_VIRT + 0x020082E4)
	#define REG_PWM_SCAN7_LOW Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_33 (IO_VIRT + 0x020082E8)
	#define REG_PWM_SCAN7_LOW_WIDTH_LIMIT Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_36 (IO_VIRT + 0x020082F4)
	#define REG_PWM_SCAN8_EN Fld(1,31,AC_MSKB3)//[31:31]
	#define REG_PWM_SCAN8_START_MODE Fld(1,30,AC_MSKB3)//[30:30]
	#define REG_PWM_SCAN8_ASYNC_MODE Fld(1,29,AC_MSKB3)//[29:29]
	#define REG_TCON_3DBL_OUT_EN8 Fld(1,28,AC_MSKB3)//[28:28]
	#define REG_PWM_SCAN8_START_PHASE Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_37 (IO_VIRT + 0x020082F8)
	#define REG_PWM_SCAN8_FIXED_LOW Fld(1,31,AC_MSKB3)//[31:31]
	#define REG_PWM_SCAN8_FIXED_HIGH Fld(1,30,AC_MSKB3)//[30:30]
	#define REG_PWM_SCAN8_POL Fld(1,29,AC_MSKB3)//[29:29]
	#define REG_PWM_SCAN8_HIGH_FRAME_MODE Fld(1,28,AC_MSKB3)//[28:28]
	#define REG_PWM_SCAN8_START Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_38 (IO_VIRT + 0x020082FC)
	#define REG_PWM_SCAN8_HIGH Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_39 (IO_VIRT + 0x02008300)
	#define REG_PWM_SCAN8_LOW Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_3A (IO_VIRT + 0x02008304)
	#define REG_PWM_SCAN8_LOW_WIDTH_LIMIT Fld(25,0,AC_MSKDW)//[24:0]
#define PWM_SCAN_3D (IO_VIRT + 0x02008310)
	#define REG_PWM_SCAN8_HIGH_ENABLE Fld(5,27,AC_MSKB3)//[31:27]
	#define REG_PWM_SCAN8_START_HIGH Fld(9,16,AC_MSKW32)//[24:16]
	#define REG_PWM_SCAN7_HIGH_ENABLE Fld(5,11,AC_MSKB1)//[15:11]
	#define REG_PWM_SCAN7_START_HIGH Fld(9,0,AC_MSKW10)//[8:0]

#endif
