/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: brianpc.huang $
 * $Date: 2015/05/29 $
 * $RCSfile: drv_async.h,v $
 * $Revision: #1 $
 *
 *---------------------------------------------------------------------------*/

#ifndef _DRV_ASYNC_H_
#define _DRV_ASYNC_H_

#include "typedef.h"
#include "hw_vdoin.h"
#include  "drv_vdoclk.h"
#include "hw_async.h"

#define PIP5382Enable		(SUPPORT_POP)
#define SUPPORT_82xx_ASYNC		0

#define HDTV_MV_DETECT_SUPPORT 1
#define ASYNC_FULL_SCREEN_WA	1
#define VSYNC_OUT_UPDATE_TRIGGER 1
/* ====================================================================
      SYNC TYPE SELECT
  ====================================================================*/
 #define SEPERATESYNC       0
 #define COMPOSITESYNC     1
 #define SYNCONGREEN        2

#if SUPPORT_HDTV_HARDWARE_MUTE
/*=====================================================================
      HARDWARE MUTE TYPE
  ====================================================================*/
#define AS_MUTE_HSACT (1<<6)
#define AS_MUTE_VSACT (1<<5)
#define AS_MUTE_CSACT (1<<4)
#define AS_MUTE_HSPOL (1<<3)
#define AS_MUTE_VSPOL (1<<2)
#define AS_MUTE_HLEN  (1<<1)
#define AS_MUTE_VLEN  (1<<0)
#endif

/*=====================================================================
            CS SEPARATOR THRESHOLD SELTECT
  ====================================================================*/
#define CS_SEPARATOR_THU_DEFAULT   0x01a4
#define CS_SEPARATOR_THL_DEFAULT   0x00ff
#define CS_SEPARATOR_THU_DEFAULT_1080   0x01c4
#define CS_SEPARATOR_THL_DEFAULT_1080   0x00f0
#define CS_SEPARATOR_THH_DEFAULT	0x19c

#define vASPathReset()	vIO32WriteFldAlign(ASYNC_00,SEPERATESYNC,AS_SYNC_SEL)
#define vASSetSSync()	vIO32WriteFldAlign(ASYNC_00,SEPERATESYNC,AS_SYNC_SEL)
#define vASSetCSync()	vIO32WriteFldAlign(ASYNC_00,COMPOSITESYNC,AS_SYNC_SEL)
#define vASSetSOGSync()	vIO32WriteFldAlign(ASYNC_00,SYNCONGREEN,AS_SYNC_SEL)

//#define vASDeCompSel(bOn)	vIO32WriteFldAlign(ASYNC_01, bOn, AS_DE_COMP_SEL)

#define vDrvCsyncInvPol(bPol) vIO32WriteFldAlign(ASYNC_00,bPol,AS_CSYNC_INV)
#define vDrvHsLockInv(bOn) vIO32WriteFldAlign(ASYNC_0E, bOn, AS_HSYNC_LOCK_INV)
#define vDrvHsInv(bOn) vIO32WriteFldAlign(ASYNC_00,bOn,AS_HSYNC_INV)
#define vDrvVsInv(bOn) vIO32WriteFldAlign(ASYNC_00,bOn,AS_VSYNC_INV)
#define vDrvVsOutInvPol(bPol) vIO32WriteFldAlign(ASYNC_11,bPol,AS_VSYNC_OUTP_INV)

#define bDrvASFieldAct()  (IO32ReadFldAlign(STA_SYNC0_00, AS_FIELD_ACT))
#define bDrvASFieldNum()  (IO32ReadFldAlign(STA_SYNC0_00, AS_FIELD_CK27_DET))

#define fgIsCLKLock() (IO32ReadFldAlign(VFE_STA_00,DDS_LOCK))
#define vDDS_MAX_PERR() (IO32ReadFldAlign(VFE_STA_00,DDS_MAX_PERR))
#if 	SUPPORT_82xx_ASYNC
#define vDrvAsStatHold(bOn)	vIO32WriteFldAlign(ASYNC_02, bOn, AS_LONG_LENGTH_STATUS_HOLD);
#define vDrvDDSCwGate(bOn) vIO32WriteFldAlign(SYS_00,bOn,DDS_CW_GATE)
#else
#define vDrvAsStatHold(bOn)
#define vDrvDDSCwGate(bOn)
#endif



// SP0 Event Flag
#define vSetSP0Flg(arg) (_bSP0Flag |= (arg))
#define vClrSP0Flg(arg) (_bSP0Flag &= (~(arg)))
#define fgIsSP0FlgSet(arg) ((_bSP0Flag & (arg)) > 0)

#define SP0_MODE_DET_FLG (1<<0)
#define SP0_VGA_AUTO_FLG (1<<1)
#define SP0_AUTOCOLOR_FLG (1<<2)
#define SP0_MCHG_BYPASS_FLG (1<<7)


#if HDTV_MV_DETECT_SUPPORT
extern void vDrvAsyncMvDetectH (UINT16 wstart1, UINT16 wend1) ;
extern void vDrvAsyncMvDetectV (UINT16 wstart1, UINT16 wend1)  ;
extern BYTE bDrvAsyncMvStatus (void)  ;
extern UINT8 _bHdtvMvOn ;
#endif
void vDrvAsyncHsyncEnable(UINT8 bEnable);


enum{	
            HDTV_NO_SIGNAL,	
            HDTV_CHK_MODECHG,	
            HDTV_WAIT_STABLE
         };

enum{	
            VGA_NO_SIGNAL,	
            VGA_CHK_MODECHG,	
            VGA_WAIT_STABLE
         };


enum{	
            MCHG_NO_CHG = 0,
            MDCHG_CON =1,	
            MCHG_NOSIG =2 ,	 
            MCHG_SIGIN = 3,
            MCHG_UNLOCK =4,
            MCHG_ISR =5,
            MCHG_HVSYNC_LOSE =6,
            MCHG_POL_CHG =7,
            MCHG_HVLEN_CHG =8,
            MCHG_FLD_CHG =9,
            MCHG_HW_DET =10,
			MCHG_VGA_422=11
         };   

//#define VGA_DBG_MSG_DMP 1
extern UINT8   bVgadbgmask;

#define DBG_MDET_LVL    0
#define DBG_MCHG_LVL     0
#define DBG_AUTO_LVL     0
#define DBG_SLICER_LVL    0
#define VGA_Debug_LVL    0
#define  SCART_LOG_LVL 0
#define  AUTOCOLOR_LOG_LVL 0

#if 1
#define DBG_MDET_FLG    1
#define DBG_MCHG_FLG     2
#define DBG_AUTO_FLG     4
#define DBG_SLICER_FLG    8
#define VGA_Debug_FLG    16
#define  SCART_LOG_FLG  32
#define AUTOCOLOR_LOG_FLG 0x40
#define _MY_LOG(level, fmt...)  LOG(level, fmt)
#define DBG_Printf(flag,fmt...) {if(bVgadbgmask&(flag##_FLG)) _MY_LOG(flag##_LVL, fmt);}
#else
#define DBG_MDET    1
#define DBG_MCHG     2
#define DBG_AUTO     4
#define DBG_SLICER    8
#define VGA_Debug    16
#define  SCART_LOG  32
//#define DBG_Printf(msk,fmt...) if(bVgadbgmask&(msk)) Printf(fmt)
#define DBG_Printf(msk,fmt...) if(bVgadbgmask&(msk)) LOG(0, fmt)
#endif



/*======================================================
              crystal number
  ====================================================*/
#define CRYSTAL_27M               27
#define CRYSTAL_48M                48

#define CRYSTAL                    CRYSTAL_27M


/*======================================================
              H/V Sync Internal Delay
  ====================================================*/
#define HSync_Auto_Delay 8

#if ADAPTIVE_MONITOR_SLICER_MEASURE
typedef struct // SP2MonStr
{
	UINT16 SP2_V_LEN_S;
	UINT16 SP2_H_LEN_S;
	UINT16 SP2_V_WIDTH_S;
}  SP2MonStr;

typedef enum
{
	SP2_Specific_LVL,
	SP2_Default_LVL
}  SP2Mon_LVL;

#endif

enum 
{
	ZERO,
	NOT_FINISHED,
	FINISHED,
	VALID,
	INVALID
};

enum 
{
	DOMAIN_27MHz,
	DOMAIN_PIXEL
};


#define VGA_DBG_MSG_DMP 1
extern UINT8   bVgadbgmask;

#define PRE_DOWN_OFST   2

// SP0 Extern  
extern UINT16   wSP0Hclk;
extern UINT8   bSP0Vclk;
extern UINT16   wSP0Vtotal;
extern UINT16  _wSP0StableVtotal;
extern UINT16   wSP0HLength;
extern UINT8   bSP0VCount;
extern UINT8   bSP0SigChk;
extern UINT8   fgSP0DIChk;
extern UINT8   fgSP0Hpol;
extern UINT8   fgSP0Vpol;
extern UINT16   wSP0VCompare[4];
extern UINT16   wSP0HCompare1;
extern UINT8  _bSP0Flag ;

extern UINT8   bSP0TrySignalState;
extern UINT32 wVGAADSpec;
extern UINT32 wHFHeight;
extern UINT32 wHFLow;
extern UINT32 wVFHeight;
extern UINT32 wVFLow;
extern UINT8 bModeIndex;

//////////////////////////////////////////////////////////////////////////////////
extern void vResetVLen(void) ;

extern UINT8 fgASHPolarityMeasure(void) ;
extern UINT8 fgASVPolarityMeasure(void) ;
extern UINT16 wASHLenMeasure(void) ;
extern UINT16 wASHSyncWidthMeasure(void);
extern UINT16 wASVtotalMeasure(void) ;
#if ADAPTIVE_MONITOR_SLICER_MEASURE
#define wSP2VCompare_Num 2
extern SP2MonStr wSP2VCompare[wSP2VCompare_Num];
extern void vAS2SyncMeasure(SP2Mon_LVL type);
#endif
extern UINT16 wASTopBCLine(void);
extern UINT16 wASBottomBCLine(void);
extern UINT8 bASActiveChk(void) ;
extern UINT8 bASHDTVActiveChk(void);
extern void vASCSSeparatorThre(void);
extern void vSetAsyncMeasureBD(UINT8 bmode) ;
extern void vDrvAsyncVMask(UINT16 wstart1, UINT16 wend1) ;
extern void vDrvAsyncVMask2(UINT16 wstart1, UINT16 wend1) ;
extern void vDrvAsyncClampMask(UINT16 wstart1, UINT16 wend1) ;
extern void vDrvAsyncPreDataActive(UINT16 wstart,UINT16 wend);
extern void vDrvAsyncHBDMask(UINT16 Left, UINT16 Right);
extern void vDrvAsyncBDMask(UINT16 wstart1, UINT16 wend1)  ;
extern void  vDrvAsyncSetFieldDet(UINT16 wHLEN) ;


extern void vDrvAsyncVsyncStart(UINT16 wStart) ;
extern void vDrvAsyncVsyncOut(UINT16 wStart1, UINT16 wH1);

extern UINT16 wSP0IHSClock(UINT16 whtotal) ;
extern UINT8 bSP0IVSClock(UINT16 whtotal, UINT16 wvtotal) ;
extern UINT8 bDrvAsGetActive(UINT8 VSyncNo) ;
extern UINT8 bDrvAsGetVtotal(void) ;
extern UINT8  fgSP0NewSync(void) ;

extern void SP0Initial(void) ;
extern UINT8 SP0SignalIdentify(UINT8 SigMode) ;
extern UINT8 bSP0VsyncValid(void)  ;
extern UINT16 wASHSyncWidthMeasure(void) ;
extern UINT16 wASVSyncWidthMeasure(void);
//extern UINT16 wDrvAsyncGetVactive (void) ;
extern void vASDeCompSel(UINT8 DeCompSel);

#if SUPPORT_HDTV_HARDWARE_MUTE
void vDrvAsyncSetMuteCriteria(UINT32 u4MuteFlag);
#endif

extern void vDrvRETIMEReset(void);

#endif

