/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License 
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public 
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
/*-----------------------------------------------------------------------------
 *
 * $Author: brianpc.huang $
 * $Date: 2015/05/29 $
 * $RCSfile: gfx_dif_reg.h,v $
 * $Revision: #1 $
 *
 *---------------------------------------------------------------------------*/

/** @file gfx_dif_reg.h
 *  gfx driver hardware registers
 *  5371 specific
 */

/* 
 lint inhibition(s)
 46   : suppress MISRA rule 111, field type should be int
 960  : suppress MISRA rule 110, bitfields inside union
 here size of bitfield has been carefully calculated
 to fit union size
 */

/*lint -save -e46 -e960 */

#ifndef GFX_DIF_REG_H
#define GFX_DIF_REG_H

//---------------------------------------------------------------------------
// Include files
//---------------------------------------------------------------------------


//---------------------------------------------------------------------------
// Configurations
//---------------------------------------------------------------------------


//---------------------------------------------------------------------------
// Constant definitions
//---------------------------------------------------------------------------

// size of gfx register space (in unit sizeof(uint32))
#define GREG_FILE_SIZE          (INT32)(GREG_LAST)

#define GFX_ENABLE              1
#define GFX_DISABLE             0

#define GFX_FIELD_MODE          1
#define GFX_FRAME_MODE          0

#define GFX_CMD_BUF_CYLIC       0
#define GFX_CMD_BUF_SINGLE      1

#define GFX_SOFT_RESET          3

#define GFX_HW_IDLE             1
#define GFX_HW_BUSY             0

#define GFX_ENGINE_FIRE         1

#define GFX_MMU_ENABLE      1
#define GFX_MMU_DISABLE     0
#define GFX_MMU_SELF_FILE   1
#define GFX_MMU_AGENT_EN    1
#define GFX_MMU_AGENT_DISABLE   0
#define GFX_MMU_AGENT_MID0  0
#define GFX_MMU_AGENT_MID1  1
#define GFX_MMU_AGENT_MID2  2
#define GFX_MMU_AGENT_MID3  3
#define GFX_MMU_AGENT_MID4  4

#define GFX_MMU_PREFETCH_EN     1
#define GFX_MMU_2RD_PREFETCH_EN     1
#define GFX_MMU_IRQ_ENABLE  1
#define GFX_MMU_IRQ_DISABLE 0
#define GFX_MMU_IRQ_HALT    1
#define GFX_MMU_IRQ_MASK    1




//---------------------------------------------------------------------------
// Type definitions
//---------------------------------------------------------------------------

// gfx hardware register enumeration
typedef enum _E_GFX_REG_T
{
    GREG_G_CONFIG = 0x00, // 0x4000
    GREG_G_STATUS = 0x01, // 0x4004
    GREG_DRAMQ_STAD = 0x02, // 0x4008
    GREG_DRAMQ_LEN = 0x03, // 0x400C
    GREG_G_MODE = 0x04, // 0x4010
    GREG_RECT_COLOR = 0x05, // 0x4014
    GREG_SRC_BSAD = 0x06, // 0x4018
    GREG_DST_BSAD = 0x07, // 0x401C
    GREG_SRC_XY = 0x08, // 0x4020
    GREG_DST_XY = 0x09, // 0x4024
    GREG_SRC_SIZE = 0x0A, // 0x4028
    GREG_S_OSD_WIDTH = 0x0B, // 0x402C
    GREG_CLIP_BR = 0x0C, // 0x4030
    GREG_CLIP_TL = 0x0D, // 0x4034
    GREG_GRAD_X_DELTA = 0x0E, // 0x4038
    GREG_GRAD_Y_DELTA = 0x0F, // 0x403C
    GREG_GRAD_XY_INC = 0x10, // 0x4040
    GREG_BITBLT_MODE = 0x11, // 0x4044
    GREG_KEY_DATA0 = 0x12, // 0x4048
    GREG_KEY_DATA1 = 0x13, // 0x404C
    GREG_SRCCBCR_BSAD = 0x14, // 0x4050
    GREG_SRCCBCR_PITCH = 0x15, // 0x4054
    GREG_DSTCBCR_BSAD = 0x16, // 0x4058
    GREG_F_COLOR = 0x17, // 0x405C
    GREG_B_COLOR = 0x18, // 0x4060
    GREG_COL_TRAN0 = 0x19, // 0x4064
    GREG_COL_TRAN1 = 0x1A, // 0x4068
    GREG_COL_TRAN2 = 0x1B, // 0x406C
    GREG_COL_TRAN3 = 0x1C, // 0x4070
    GREG_COL_TRAN4 = 0x1D, // 0x4074
    GREG_COL_TRAN5 = 0x1E, // 0x4078
    GREG_COL_TRAN6 = 0x1F, // 0x407C
    GREG_COL_TRAN7 = 0x20, // 0x4080
    GREG_STR_BLT_H = 0x21, // 0x4084
    GREG_STR_BLT_V = 0x22, // 0x4088
    GREG_STR_DST_SIZE = 0x23, // 0x408C
    GREG_LEGAL_START_ADDR = 0x24, // 0x4090
    GREG_LEGAL_END_ADDR = 0x25, // 0x4094
    GREG_DUMMY = 0x26, // 0x4098
    GREG_ALCOM_LOOP = 0x27, // 0x409C
    GREG_ROP = 0x28, // 0x40A0
    GREG_IDX2DIR = 0x29, // 0x40A4
    GREG_COMPRESS = 0x2A, // 0x40A8
    GREG_BPCOMP_CFG = 0x2B, // 0x40AC
    GREG_BPCOMP_AD_END = 0x2C, // 0x40B0
    GREG_0x40B4 = 0x2D, // 0x40B4
    GREG_0x40B8 = 0x2E, // 0x40B8
    GREG_0x40BC = 0x2F, // 0x40BC
    GREG_0x40C0 = 0x30, // 0x40C0
    GREG_0x40C4 = 0x31, // 0x40C4
    GREG_0x40C8 = 0x32, // 0x40C8
    GREG_0x40CC = 0x33, // 0x40CC
    GREG_0x40D0 = 0x34, // 0x40D0
    GREG_0x40D4 = 0x35, // 0x40D4
    GREG_0x40D8 = 0x36, // 0x40D8
    GREG_0x40DC = 0x37, // 0x40DC
    GREG_0x40E0 = 0x38, // 0x40E0
    GREG_0x40E4 = 0x39, // 0x40E4
    GREG_0x40E8 = 0x3A, // 0x40E8
    GREG_0x40EC = 0x3B, // 0x40EC
    GREG_0x40F0 = 0x3C, // 0x40F0
    GREG_0x40F4 = 0x3D, // 0x40F4
    GREG_0x40F8 = 0x3E, // 0x40F8
    GREG_0x40FC = 0x3F, // 0x40FC
    GREG_0x4100 = 0x40, //0x4100
    GREG_0x4104 = 0x41, //0x4104
    GREG_0x4108 = 0x42, //0x4108
    GREG_0x410C = 0x43, //0x410c
    GREG_0x4110 = 0x44, //0x4110
    GREG_READ_ARGB_ORDER = 0x45, //0x4114
    GREG_ADDR_MSB1 = 0x46, //0x4118
    GREG_ADDR_MSB2 = 0x47, //0x411C
    GREG_0x4120 = 0x48, //0x4120
    GREG_0x4124 = 0x49, //0x4124
    GREG_0x4128 = 0x4A, //0x4128
    GREG_0x412c = 0x4B, //0x412c
    GREG_XOR_COLOR = 0x4C, //0x4130
    GREG_0x4134 = 0x4D,
    GREG_0x4138 = 0x4E,
    GREG_0x413c = 0x4F,
    GREG_0x4140 = 0x50,
    GREG_0x4144 = 0x51,
    GREG_0x4148 = 0x52,
    GREG_0x414c = 0x53,
    GREG_0x4150 = 0x54,
    GREG_0x4154 = 0x55,
    GREG_0x4158 = 0x56,
    GREG_0x415c = 0x57,
    GREG_0x4160 = 0x58,
    GREG_0x4164 = 0x59,
    GREG_0x4168 = 0x5A,
    GREG_0x416c = 0x5B,
    GREG_0x4170 = 0x5C,
    GREG_0x4174 = 0x5D,
    GREG_0x4178 = 0x5E,
    GREG_0x417c = 0x5F,
    GREG_0x4180 = 0x60,
    GREG_0x4184 = 0x61,
    GREG_0x4188 = 0x62,
    GREG_0x418c = 0x63,
    GREG_0x4190 = 0x64,
    GREG_0x4194 = 0x65,
    GREG_0x4198 = 0x66,
    GREG_0x419c = 0x67,
    GREG_0x41a0 = 0x68,
    GREG_0x41a4 = 0x69,
    GREG_0x41a8 = 0x6A,
    GREG_0x41ac = 0x6B,
    GREG_0x41b0 = 0x6C,
    GREG_0x41b4 = 0x6D,
    GREG_0x41b8 = 0x6E,
    GREG_0x41bc = 0x6F,
    GREG_0x41c0 = 0x70,
    GREG_0x41c4 = 0x71,
    GREG_0x41c8 = 0x72,
    GREG_0x41cc = 0x73,
    GREG_0x41d0 = 0x74,
    GREG_0x41d4 = 0x75,
    GREG_0x41d8 = 0x76,
    GREG_0x41dc = 0x77,
    GREG_0x41e0 = 0x78,
    GREG_0x41e4 = 0x79,
    GREG_0x41e8 = 0x7A,
    GREG_0x41ec = 0x7B,
    GREG_0x41f0 = 0x7C,
    GREG_0x41f4 = 0x7D,
    GREG_0x41f8 = 0x7E,
    GREG_0x41fc = 0x7F,
    GREG_0x4200 = 0x80,
    GREG_0x4204 = 0x81,
    GREG_0x4208 = 0x82,
    GREG_0x420c = 0x83,
    GREG_0x4210 = 0x84,
    GREG_0x4214 = 0x85,
    GREG_0x4218 = 0x86,
    GREG_0x421c = 0x87,
    GREG_0x4220 = 0x88,
    GREG_0x4224 = 0x89,
    GREG_0x4228 = 0x8A,
    GREG_0x422c = 0x8B,
    GREG_0x4230 = 0x8C,
    GREG_0x4234 = 0x8D,
    GREG_0x4238 = 0x8E,
    GREG_0x423c = 0x8F,
    GREG_0x4240 = 0x90,
    GREG_0x4244 = 0x91,
    GREG_0x4248 = 0x92,
    GREG_0x424c = 0x93,
    GREG_0x4250 = 0x94,
    GREG_0x4254 = 0x95,
    GREG_0x4258 = 0x96,
    GREG_0x425c = 0x97,
    GREG_0x4260 = 0x98,
    GREG_0x4264 = 0x99,
    GREG_0x4268 = 0x9A,
    GREG_0x426c = 0x9B,
    GREG_0x4270 = 0x9C,
    GREG_0x4274 = 0x9D,
    GREG_0x4278 = 0x9E,
    GREG_0x427c = 0x9F,
    GREG_0x4280 = 0xA0,
    GREG_0x4284 = 0xA1,
    GREG_LAST =   0xA2,
// 0x4120
} E_GFX_REG_T;

// gfx register name
typedef struct _MI_DIF_REG_T
{
    UINT32 u4_G_CONFIG;
    UINT32 u4_G_STATUS;
    UINT32 u4_DRAMQ_STAD;
    UINT32 u4_DRAMQ_LEN;
    UINT32 u4_G_MODE;
    UINT32 u4_RECT_COLOR;
    UINT32 u4_SRC_BSAD;
    UINT32 u4_DST_BSAD;
    UINT32 u4_SRC_XY;
    UINT32 u4_DST_XY;
    UINT32 u4_SRC_SIZE;
    UINT32 u4_S_OSD_WIDTH;
    UINT32 u4_CLIP_BR;
    UINT32 u4_CLIP_TL;
    UINT32 u4_GRAD_X_DELTA;
    UINT32 u4_GRAD_Y_DELTA;
    UINT32 u4_GRAD_XY_INC;
    UINT32 u4_BITBLT_MODE;
    UINT32 u4_KEY_DATA0;
    UINT32 u4_KEY_DATA1;
    UINT32 u4_SRCCBCR_BSA;
    UINT32 u4_SRCCBCR_PITC;
    UINT32 u4_DSTCBCR_BSA;
    UINT32 u4_F_COLOR;
    UINT32 u4_B_COLOR;
    UINT32 u4_COL_TRAN0;
    UINT32 u4_COL_TRAN1;
    UINT32 u4_COL_TRAN2;
    UINT32 u4_COL_TRAN3;
    UINT32 u4_COL_TRAN4;
    UINT32 u4_COL_TRAN5;
    UINT32 u4_COL_TRAN6;
    UINT32 u4_COL_TRAN7;
    UINT32 u4_STR_BLT_H;
    UINT32 u4_STR_BLT_V;
    UINT32 u4_STR_DST_SIZE;
    UINT32 u4_LEGAL_START_ADDR;
    UINT32 u4_LEGAL_END_ADDR;
    UINT32 u4_DUMMY;
    UINT32 u4_ALCOM_LOOP;
    UINT32 u4_ROP;
    UINT32 u4_IDX2DIR;
    UINT32 u4_COMPRESS;
    UINT32 u4_BPCOMP_CFG;
    UINT32 u4_BPCOMP_AD_END;
    UINT32 u4_Res40B4;
    UINT32 u4_Res40B8;
    UINT32 u4_Res40BC;
    UINT32 u4_Res40C0;
    UINT32 u4_Res40C4;
    UINT32 u4_Res40C8;
    UINT32 u4_Res40CC;
    UINT32 u4_Res40D0;
    UINT32 u4_Res40D4;
    UINT32 u4_Res40D8;
    UINT32 u4_Res40DC;
    UINT32 u4_Res40E0;
    UINT32 u4_Res40E4;
    UINT32 u4_Res40E8;
    UINT32 u4_Res40EC;
    UINT32 u4_Res40F0;
    UINT32 u4_Res40F4;
    UINT32 u4_Res40F8;
    UINT32 u4_Res40FC;
    UINT32 u4_Res4100;
    UINT32 u4_Res4104;
    UINT32 u4_Res4108;
    UINT32 u4_Res410C;
    UINT32 u4_Res4110;
    UINT32 u4_READ_ARGB_ORDER;
    UINT32 u4_ADDR_MSB1;
    UINT32 u4_ADDR_MSB2;
     UINT32 u4_Res4120;
    UINT32 u4_Res4124;
    UINT32 u4_Res4128;
    UINT32 u4_Res412c;
    UINT32 u4_XOR_COLOR;
    UINT32 u4_Res4134;
    UINT32 u4_Res4138;
    UINT32 u4_Res413c;
    UINT32 u4_Res4140;//new
    UINT32 u4_Res4144 ;
    UINT32 u4_Res4148 ;
    UINT32 u4_Res414c ;
    UINT32 u4_Res4150 ;
    UINT32 u4_Res4154 ;
    UINT32 u4_Res4158 ;
    UINT32 u4_Res415c ;
    UINT32 u4_Res4160 ;
    UINT32 u4_Res4164 ;
    UINT32 u4_Res4168 ;
    UINT32 u4_Res416c ;
    UINT32 u4_Res4170 ;
    UINT32 u4_Res4174 ;
    UINT32 u4_Res4178 ;
    UINT32 u4_Res417c ;
    UINT32 u4_Res4180 ;
    UINT32 u4_Res4184 ;
    UINT32 u4_Res4188 ;
    UINT32 u4_Res418c ;
    UINT32 u4_Res4190 ;
    UINT32 u4_Res4194 ;
    UINT32 u4_Res4198 ;
    UINT32 u4_Res419c ;
    UINT32 u4_Res41a0 ;
    UINT32 u4_Res41a4 ;
    UINT32 u4_Res41a8 ;
    UINT32 u4_Res41ac ;
    UINT32 u4_Res41b0 ;
    UINT32 u4_Res41b4 ;
    UINT32 u4_Res41b8 ;
    UINT32 u4_Res41bc ;
    UINT32 u4_Res41c0 ;
    UINT32 u4_Res41c4 ;
    UINT32 u4_Res41c8 ;
    UINT32 u4_Res41cc ;
    UINT32 u4_Res41d0 ;
    UINT32 u4_Res41d4 ;
    UINT32 u4_Res41d8 ;
    UINT32 u4_Res41dc ;
    UINT32 u4_Res41e0 ;
    UINT32 u4_Res41e4 ;
    UINT32 u4_Res41e8 ;
    UINT32 u4_Res41ec ;
    UINT32 u4_Res41f0 ;
    UINT32 u4_Res41f4 ;
    UINT32 u4_Res41f8 ;
    UINT32 u4_Res41fc ;
    UINT32 u4_Res4200 ;
    UINT32 u4_Res4204 ;
    UINT32 u4_Res4208 ;
    UINT32 u4_Res420c ;
    UINT32 u4_Res4210 ;
    UINT32 u4_Res4214 ;
    UINT32 u4_Res4218 ;
    UINT32 u4_Res421c ;
    UINT32 u4_Res4220 ;
    UINT32 u4_Res4224 ;
    UINT32 u4_Res4228 ;
    UINT32 u4_Res422c ;
    UINT32 u4_Res4230 ;
    UINT32 u4_Res4234 ;
    UINT32 u4_Res4238 ;
    UINT32 u4_Res423c ;
    UINT32 u4_Res4240 ;
    UINT32 u4_Res4244 ;
    UINT32 u4_Res4248 ;
    UINT32 u4_Res424c ;
    UINT32 u4_Res4250 ;
    UINT32 u4_Res4254 ;
    UINT32 u4_Res4258 ;
    UINT32 u4_Res425c ;
    UINT32 u4_Res4260 ;
    UINT32 u4_Res4264 ;
    UINT32 u4_Res4268 ;
    UINT32 u4_Res426c ;
    UINT32 u4_Res4270 ;
    UINT32 u4_Res4274 ;
    UINT32 u4_Res4278 ;
    UINT32 u4_Res427c ;
    UINT32 u4_Res4280 ;
    UINT32 u4_Res4284 ;
    UINT32 GREG_LAST;
} MI_DIF_REG_T;

// gfx hw register bitfield
typedef struct _MI_DIF_FIELD_T
{
    // DWORD - G_CONFIG         (4000h)
    UINT32 fg_EN_DRAMQ :1;
    UINT32 fg_INT_MASK :1;
    UINT32 fg_POST_THRS :2;
    UINT32 fg_CMDFIFO_THRS :2;
    UINT32 fg_REQ_INTVAL :2;
    UINT32 fg_DRAMQ_MODE :1;
    UINT32 fg_SDFIFO_THRS :2;
    UINT32 :5;
    UINT32 fg_SHT_CMDQ :1;
    UINT32 fg_ENG_LP :1;
    UINT32 :3;
    UINT32 fg_CHECKSUM_SEL :1;
    UINT32 :2;
    UINT32 fg_REG_RST :2;
    UINT32 fg_G_RST_CMDQ :2;
    UINT32 fg_CQ_RST :2;
    UINT32 fg_G_RST :2;

    // DWORD - G_STATUS         (4004h)
    UINT32 fg_IDLE :1;
    UINT32 fg_HWQ_LEN :4;
    UINT32 :3;
    UINT32 fg_VERSION_ID :8;
    UINT32 fg_CURR_Y_LINE :11;
    UINT32 :5;

    // DWORD - DRAMQ_STAD       (4008h)
    UINT32 fg_DRAMQ_BSAD :30;
    UINT32 fg_CYC_SIZE :2;

    // DWORD - DRAMQ_LEN        (400Ch)
    UINT32 fg_DRAMQ_LEN :18;
    UINT32 :14;

    // DWORD - G_MODE           (4010h)
    UINT32 fg_CM :4;
    UINT32 fg_OP_MODE :5;
    UINT32 :2;
    UINT32 fg_FIRE :1;
    UINT32 fg_BURST_READ :1;
    UINT32 fg_BURST_READ_MODE :2;
    UINT32 :1;
    UINT32 fg_DSTOWN :1;
    UINT32 fg_SRCOWN :1;
    UINT32 fg_DSTWR_RGB_24BIT :1;
    UINT32 fg_A1555_EN :1;
    UINT32 fg_USE_RECT_SRC :1;
    UINT32 fg_ALWAYS_RD_SRC :1;
    UINT32 fg_WRITE_NO_PITCH :1;
    UINT32 fg_APP_BPCOMP :1;
    UINT32 fg_ALCOM_THIRD_KEY_EN :1;
    UINT32 fg_ALCOM_SRC_KEY_EN :1;
    UINT32 fg_ALCOM_DIFF_CM :1;
    UINT32 fg_THIRD_BUF_EN :1;
    UINT32 fg_THIRD_CM :4;

    // DWORD - RECT_COLOR       (4014h)
    UINT32 fg_RECT_COLOR :32;

    // DWORD - SRC_BSAD         (4018h)
    UINT32 fg_SRC_BSAD :30;
    UINT32 fg_CHAR_CM :2;

    // DWORD - DST_BSAD         (401Ch)
    UINT32 fg_DST_BSAD :30;
    UINT32 :2;

    // DWORD - SRC_XY           (4020h)
    UINT32 fg_SRCX :15;
    UINT32 :1;
    UINT32 fg_SRCY :11;
    UINT32 :5;

    // DWORD - DST_XY           (4024h)
    UINT32 fg_DSTX :15;
    UINT32 :1;
    UINT32 fg_DSTY :11;
    UINT32 :5;

    // DWORD - SRC_SIZE         (4028h)
    UINT32 fg_SRC_WIDTH :15;
    UINT32 fg_RL_DEC :1;
    UINT32 fg_SRC_HEIGHT :11;
    UINT32 fg_SRC_CM :4;
    UINT32 fg_SPU_RLDEC :1;

    // DWORD - S_OSD_WIDTH      (402Ch)
    UINT32 fg_OSD_WIDTH :16;
    UINT32 fg_SRC_PITCH :16;

    // DWORD - CLIP_BR          (4030h)
    UINT32 fg_CLIP_RIGHT :11;
    UINT32 fg_CLR_ENA :1;
    UINT32 :4;
    UINT32 fg_CLIP_BOT :11;
    UINT32 fg_CLB_ENA :1;
    UINT32 :4;

    // DWORD - CLIP_TL          (4034h)
    UINT32 fg_CLIP_LEFT :11;
    UINT32 fg_CLL_ENA :1;
    UINT32 :4;
    UINT32 fg_CLIP_TOP :11;
    UINT32 fg_CLT_ENA :1;
    UINT32 :4;

    // DWORD - GRAD_X_DELTA     (4038h)
    UINT32 fg_DELTA_X_C0 :8;
    UINT32 fg_DELTA_X_C1 :8;
    UINT32 fg_DELTA_X_C2 :8;
    UINT32 fg_DELTA_X_C3 :8;

    // DWORD - GRAD_Y_DELTA     (403Ch)
    UINT32 fg_DELTA_Y_C0 :8;
    UINT32 fg_DELTA_Y_C1 :8;
    UINT32 fg_DELTA_Y_C2 :8;
    UINT32 fg_DELTA_Y_C3 :8;

    // DWORD - GRAD_XY_INC      (4040h)
    UINT32 fg_GRAD_X_PIX_INC :11;
    UINT32 :5;
    UINT32 fg_GRAD_Y_PIX_INC :11;
    UINT32 :3;
    UINT32 fg_GRAD_MODE :2;

    // DWORD - BITBLT_MODE      (4044h)
    UINT32 fg_TRANS_ENA :1;
    UINT32 fg_KEYNOT_ENA :1;
    UINT32 fg_COLCHG_ENA :1;
    UINT32 :1;
    UINT32 fg_CFMT_ENA :1;
    UINT32 fg_KEYSDSEL :1;
    UINT32 fg_PRCN_OPT :1;
    UINT32 fg_FORCE_USE_ALPHA :1;
    UINT32 fg_ALPHA_VALUE :8;
    UINT32 fg_ALCOM_PASS :3;
    UINT32 :5;
    UINT32 fg_DSTPITCH_DEC :1;
    UINT32 fg_MIRROR :1;
    UINT32 fg_SRCPITCH_DEC :1;
    UINT32 fg_SRCMIRROR :1;
    UINT32 :4;

    // DWORD - KEY_DATA0        (4048h)
    UINT32 fg_COLOR_KEY_MIN :32;

    // DWORD - KEY_DATA1        (404Ch)
    UINT32 fg_COLOR_KEY_MAX :32;

    // DWORD - SRCCBCR_BSA      (4050h)
    UINT32 fg_SRCCBCR_BSAD :30;
    UINT32 fg_YC_FMT :2;

    // DWORD - SRCCBCR_PITCH    (4054h)
    UINT32 fg_SRCCBCR_PITCH :16;
    UINT32 fg_VSTD :1;
    UINT32 fg_VSYS :1;
    UINT32 fg_VSCLIP :1;
    UINT32 fg_FLD_PIC :1;
    UINT32 fg_SWAP_MODE :2;
    UINT32 fg_PROJ_CODE :1;
    UINT32 fg_VFULL :1;
    UINT32 :8;

    // DWORD - DSTCBCR_BSAD     (4058h)
    UINT32 fg_DSTCBCR_BSAD :30;
    UINT32 :2;

    // DWORD - F_COLOR (1)      (405Ch)
    UINT32 fg_FORE_COLOR :32;

    // DWORD - B_COLOR (0)      (4060h)
    UINT32 fg_BACK_COLOR :32;

    // DWORD - COL_TRAN0        (4064h)
    UINT32 fg_COLOR_TRANS0 :32;

    // DWORD - COL_TRAN1        (4068h)
    UINT32 fg_COLOR_TRANS1 :32;

    // DWORD - COL_TRAN2        (406Ch)
    UINT32 fg_COLOR_TRANS2 :32;

    // DWORD - COL_TRAN3        (4070h)
    UINT32 fg_COLOR_TRANS3 :32;

    // DWORD - COL_TRAN4        (4074h)
    UINT32 fg_COLOR_TRANS4 :32;

    // DWORD - COL_TRAN5        (4078h)
    UINT32 fg_COLOR_TRANS5 :32;

    // DWORD - COL_TRAN6        (407Ch)
    UINT32 fg_COLOR_TRANS6 :32;

    // DWORD - COL_TRAN7        (4080h)
    UINT32 fg_COLOR_TRANS7 :32;

    // DWORD - STR_BLT_H        (4084h)
    UINT32 fg_STR_BLT_H :24;
    UINT32 :8;

    // DWORD - STR_BLT_V        (4088h)
    UINT32 fg_STR_BLT_V :24;
    UINT32 :8;

    // DWORD - STR_DST_SIZE     (408Ch)
    UINT32 fg_STR_DST_WIDTH :15;
    UINT32 :1;
    UINT32 fg_STR_DST_HEIGHT :11;
    UINT32 :5;

    // DWORD - LEGAL_START_ADDR (4090h)
    UINT32 fg_LEGAL_START_ADDR :28;
    UINT32 :3;
    UINT32 fg_MEM_PROTECT_EN :1;

    // DWORD - LEGAL_END_ADDR   (4094h)
    UINT32 fg_LEGAL_END_ADDR :28;
    UINT32 :4;

    // DWORD - DUMMY            (4098h)
    UINT32 fg_DUMMY :32;

    // DWORD - ALCOM_LOOP       (409Ch)
    UINT32 fg_ALCOM_AR :8;
    UINT32 fg_ALCOM_OPCODE :4;
    UINT32 :4;
    UINT32 fg_ALCOM_RECT_SRC :1;
    UINT32 fg_ALCOM_NORMAL :1;
    UINT32 fg_PREMULT_DST_W :1;
    UINT32 fg_PREMULT_DST_R :1;
    UINT32 fg_PREMULT_SRC_R :1;
    UINT32 fg_PREMULT_OVERFLOW_EN :1;
    UINT32 :10;

    // DWORD - ROP              (40A0h)
    UINT32 fg_ROP_OPCODE :4;
    UINT32 :4;
    UINT32 fg_ROP_NO_WR :1;
    UINT32 fg_ROP_CMP_FLAG :1;
    UINT32 :22;

    // DWORD - IDX2DIR          (40A4h)
    UINT32 fg_PAL_BSAD :30;
    UINT32 fg_MSB_LEFT :1;
    UINT32 fg_LN_ST_BYTE_AL :1;

    // DWORD - COMPRESS         (40A8h)
    UINT32 fg_A_METHOD :1;
    UINT32 fg_COMPRESS_LP :1;
    UINT32 :30;

    //DWORD - BPCOMP_CFG for new compression (40ACh)
    UINT32 fg_ROLL_BACK_EN :1;
    UINT32 fg_QUALITY_MODE :2;
    UINT32 fg_LINE_SEPARATE :1;
    UINT32 :28;

    //DWORD - BPCOMP_AD_END for new compression (40B0h)
    UINT32 :4;
    UINT32 fg_BPCOMP_AD_END :24;
    UINT32 :4;
    // DWORD - Reserved 19 Regs
    UINT32 fg_Res40B4 :32;
    UINT32 fg_Res40B8 :32;
    UINT32 fg_Res40BC :32;
    UINT32 fg_Res40C0 :32;
    UINT32 fg_Res40C4 :32;
    UINT32 fg_Res40C8 :32;
    UINT32 fg_Res40CC :32;
    UINT32 fg_THIRD_BSAD :30;
    UINT32 fg_THIRD_CHAR_CM :2;
    UINT32 fg_THIRD_PAL_BSAD :30;
    UINT32 fg_THIRD_MSB_LEFT :1;
    UINT32 fg_THIRD_LN_ST_BYTE_AL :1;
    UINT32 fg_THIRD_PITCH :16;
    UINT32 :16;
    UINT32 fg_ALCOM_SRC_KEY :32;
    UINT32 fg_ALCOM_THIRD_KEY :32;
    UINT32 fg_Res40E4 :32;
    UINT32 fg_Res40E8 :32;
    UINT32 fg_Res40EC :32;
    UINT32 fg_Res40F0 :32;
    UINT32 fg_Res40F4 :32;
    UINT32 fg_Res40F8 :32;
    UINT32 fg_Res40FC :32;
    // DWORD - LAST            (4100h)
    UINT32 fg_Res4100 :32;
    UINT32 fg_Res4104 :32;
    UINT32 fg_Res4108 :32;
    UINT32 fg_Res410C :32;
    UINT32 fg_Res4110 :32;
    UINT32 fg_DST_RD_B_ORDER :2;
    UINT32 fg_DST_RD_G_ORDER :2;
    UINT32 fg_DST_RD_R_ORDER :2;
    UINT32 fg_DST_RD_A_ORDER :2;
    UINT32 fg_SRC_RD_B_ORDER :2;
    UINT32 fg_SRC_RD_G_ORDER :2;
    UINT32 fg_SRC_RD_R_ORDER :2;
    UINT32 fg_SRC_RD_A_ORDER :2;
    UINT32 :8;
    UINT32 fg_DST_WR_B_ORDER :2;
    UINT32 fg_DST_WR_G_ORDER :2;
    UINT32 fg_DST_WR_R_ORDER :2;
    UINT32 fg_DST_WR_A_ORDER :2;

    // DWORD -    (4118h)  addr msb 1
    UINT32 fg_THIRD_PAL_BSAD_MSB :2;
    UINT32 :2;
    UINT32 fg_THIRD_BSAD_MSB :2;
    UINT32 :2;
    UINT32 fg_PAL_BSAD_MSB :2;
    UINT32 :2;
    UINT32 fg_SRC_BSAD_MSB :2;
    UINT32 :2;
    UINT32 fg_DST_BSAD_MSB :2;
    UINT32 :2;
    UINT32 fg_SRCCBCR_BSAD_MSB :2;
    UINT32 :2;
    UINT32 fg_BPCOMP_AD_END_MSB :2;
    UINT32 :6;
    // DWORD -    (411ch)  addr msb 2
    UINT32 fg_LEGAL_END_ADDR_MSB :2;
    UINT32 :2;
    UINT32 fg_LEGAL_START_ADDR_MSB :2;
    UINT32 :2;
    UINT32 fg_DRAMQ_BSAD_MSB :2;
    UINT32 :22;
        //DWORD -  (4120h)
    UINT32 fg_Res4120 :32;
    //DWORD -  (4124h)
    UINT32 fg_Res4124 :32;
    //DWORD -  (4128h)
    UINT32 fg_Res4128 :32;
    //DWORD -  (412ch)
    UINT32 fg_Res412c :32;
    //DWORD -XOR COLOR  (4130h)
    UINT32 fg_XOR_COLOR :32;
    //DWORD -LAST    (4134h)
    UINT32 fg_Res4134 :32;
    UINT32 fg_Res4138 :32;
    UINT32 fg_Res413c :32;

    //DWORD new add
    UINT32 fg_Res4140 :32;
    UINT32 fg_Res4144 :32;
    UINT32 fg_Res4148 :32;
    UINT32 fg_Res414c :32;
    UINT32 fg_Res4150 :32;
    UINT32 fg_Res4154 :32;
    UINT32 fg_Res4158 :32;
    UINT32 fg_Res415c :32;
    UINT32 fg_Res4160 :32;
    UINT32 fg_Res4164 :32;
    UINT32 fg_Res4168 :32;
    UINT32 fg_Res416c :32;
    UINT32 fg_Res4170 :32;
    UINT32 fg_Res4174 :32;
    UINT32 fg_Res4178 :32;
    UINT32 fg_Res417c :32;
    UINT32 fg_Res4180 :32;
    UINT32 fg_Res4184 :32;
    UINT32 fg_Res4188 :32;
    UINT32 fg_Res418c :32;
    UINT32 fg_Res4190 :32;
    UINT32 fg_Res4194 :32;
    UINT32 fg_Res4198 :32;
    UINT32 fg_Res419c :32;
    UINT32 fg_Res41a0 :32;
    UINT32 fg_Res41a4 :32;
    UINT32 fg_Res41a8 :32;
    UINT32 fg_Res41ac :32;
    UINT32 fg_Res41b0 :32;
    UINT32 fg_Res41b4 :32;
    UINT32 fg_Res41b8 :32;
    UINT32 fg_Res41bc :32;
    UINT32 fg_Res41c0 :32;
    UINT32 fg_Res41c4 :32;
    UINT32 fg_Res41c8 :32;
    UINT32 fg_Res41cc :32;
    UINT32 fg_Res41d0 :32;
    UINT32 fg_Res41d4 :32;
    UINT32 fg_Res41d8 :32;
    UINT32 fg_Res41dc :32;
    UINT32 fg_Res41e0 :32;
    UINT32 fg_Res41e4 :32;
    UINT32 fg_Res41e8 :32;
    UINT32 fg_Res41ec :32;
    UINT32 fg_Res41f0 :32;
    UINT32 fg_Res41f4 :32;
    UINT32 fg_Res41f8 :32;
    UINT32 fg_Res41fc :32;
    UINT32 fg_Res4200 :32;
    UINT32 fg_Res4204 :32;
    UINT32 fg_Res4208 :32;
    UINT32 fg_Res420c :32;
    UINT32 fg_Res4210 :32;
    UINT32 fg_Res4214 :32;
    UINT32 fg_Res4218 :32;
    UINT32 fg_Res421c :32;
    UINT32 fg_Res4220 :32;
    UINT32 fg_Res4224 :32;
    UINT32 fg_Res4228 :32;
    UINT32 fg_Res422c :32;
    UINT32 fg_Res4230 :32;
    UINT32 fg_Res4234 :32;
    UINT32 fg_Res4238 :32;
    UINT32 fg_Res423c :32;
    UINT32 fg_Res4240 :32;
    UINT32 fg_Res4244 :32;
    UINT32 fg_Res4248 :32;
    UINT32 fg_Res424c :32;
    UINT32 fg_Res4250 :32;
    UINT32 fg_Res4254 :32;
    UINT32 fg_Res4258 :32;
    UINT32 fg_Res425c :32;
    UINT32 fg_Res4260 :32;
    UINT32 fg_Res4264 :32;
    UINT32 fg_Res4268 :32;
    UINT32 fg_Res426c :32;
    UINT32 fg_Res4270 :32;
    UINT32 fg_Res4274 :32;
    UINT32 fg_Res4278 :32;
    UINT32 fg_Res427c :32;
    UINT32 fg_Res4280 :32;
    //DWORD -4284
    UINT32 :8;
    UINT32 fg_SRC_HEIGHT_12 :1;
    UINT32 :7;
    UINT32 fg_YuyvConv :1;
    UINT32 :15;
    UINT32 fg_LAST :32;
} MI_DIF_FIELD_T;

// gfx hw register name/bitfield union
typedef union _MI_DIF_UNION_T
{
    MI_DIF_REG_T rReg;
    MI_DIF_FIELD_T rField;
} MI_DIF_UNION_T;

// mmu hardware register enumeration
typedef enum _E_GFX_MMU_REG_T
{
    GREG_MMU_CFG0 = 0x00, // 0x68000
    GREG_MMU_CFG1 = 0x01, // 0x68004
    GREG_MMU_CFG2 = 0x02, // 0x68008
    GREG_MMU_CFG3 = 0x03, // 0x6800C
    GREG_MMU_CFG4 = 0x04, // 0x68010
    GREG_MMU_CFG5 = 0x05, // 0x68014
    GREG_MMU_CFG6 = 0x06, // 0x68018
    GREG_MMU_CFG7 = 0x07, // 0x6801c
    GREG_MMU_CFG8 = 0x08, // 0x68020
    GREG_MMU_CFG9 = 0x09, // 0x68024
    GREG_MMU_CFGA = 0xA, // 0x68028
    GREG_MMU_CFGB = 0xB, //0x6802c
    GREG_MMU_CFGC = 0xC, //0x68030
    GREG_MMU_CFGD = 0xD, //0x68034
    GREG_MMU_LAST
// num
} E_GFX_MMU_REG_T;

enum
{
    GREG_MMU_CFG0_NUM = 0x00, // 0x68000
    GREG_MMU_CFG1_NUM = 0x01, // 0x68004
    GREG_MMU_CFG2_NUM = 0x02, // 0x68008
    GREG_MMU_CFG3_NUM = 0x03, // 0x6800C
    GREG_MMU_CFG4_NUM = 0x04, // 0x68010
    GREG_MMU_CFG5_NUM = 0x05, // 0x68014
    GREG_MMU_CFG6_NUM = 0x06, // 0x68018
    GREG_MMU_CFG7_NUM = 0x07, // 0x6801c
    GREG_MMU_CFG8_NUM = 0x08, // 0x68020
    GREG_MMU_CFG9_NUM = 0x09, // 0x68024
    GREG_MMU_CFGA_NUM = 0xA, // 0x68028
    GREG_MMU_CFGB_NUM = 0xB, //0x6802c
    GREG_MMU_CFGC_NUM = 0xC, //0x68030
    GREG_MMU_CFGD_NUM = 0xD, //0x68034
    GREG_MMU_LAST_NUM
// num
};

// gfx hw register bitfield
typedef struct _MI_DIF_GFX_MMU_T0
{
    // DWORD - G_CONFIG         (68000h)
    UINT32 fg_MMU_EN :1;
    UINT32 fg_MMU_CFG0_DEFAULT :7;
    UINT32 :24;

    // DWORD IO_MMU_CFG1         (68004h)
    UINT32 fg_MMU_TTB :32; // (68004h)

    // DWORD - IO_MMU_CFG2       (68008h)
    UINT32 fg_MMU_A0_EN :1; //agent 0 enable
    UINT32 fg_MMU_A0_MID :3; //agent 0 MID
    UINT32 fg_MMU_A0_PREFETCH :1; //agent 0 prefetch
    UINT32 fg_MMU_A0_2D_PREFETCH :1; //agent 0 prefetch
    UINT32 :10;
    UINT32 fg_MMU_A1_EN :1; //agent 1 enable
    UINT32 fg_MMU_A1_MID :3; //agent 1 MID
    UINT32 fg_MMU_A1_PREFETCH :1; //agent 0 prefetch
    UINT32 fg_MMU_A1_2D_PREFETCH :1; //agent 0 prefetch
    UINT32 :10;

    // DWORD - IO_MMU_CFG3      (6800ch)
    UINT32 fg_MMU_A2_EN :1; //agent 2 enable
    UINT32 fg_MMU_A2_MID :3; //agent 2 MID
    UINT32 fg_MMU_A2_PREFETCH :1; //agent 0 prefetch
    UINT32 fg_MMU_A2_2D_PREFETCH :1; //agent 0 prefetch
    UINT32 :10;
    UINT32 fg_MMU_A3_EN :1; //agent 3 enable
    UINT32 fg_MMU_A3_MID :3; //agent 3 MID
    UINT32 fg_MMU_A3_PREFETCH :1; //agent 0 prefetch
    UINT32 fg_MMU_A3_2D_PREFETCH :1; //agent 0 prefetch
    UINT32 :10;
    // DWORD - IO_MMU_CFG4      (68010h)
    UINT32 fg_MMU_INT_CLR0 :1; // clear 1M table error interrupt
    UINT32 fg_MMU_INT_EN0 :1; //1M table error interrupt enable
    UINT32 fg_MMU_INT_CLR1 :1; // clear 4K table error interrupt
    UINT32 fg_MMU_INT_EN1 :1; //4K table error interrupt enable
    UINT32 :16;
    UINT32 fg_MMU_INT_HALT :1;
    UINT32 fg_MMU_INT_MASK :1;
    UINT32 :9;
    UINT32 fg_MMU_SELF_FIRE :1; //self fire trig
    UINT32 :32; //(68014h)
    UINT32 :32; //(68018h)
    UINT32 :32; //(6801ch)
    UINT32 :32; //(68020h)
    // DWORD - IO_MMU_CFG9      (68024h)
    UINT32 fg_MMU_OVERREAD_EN0 :1; //(68024h)
    UINT32 fg_MMU_OVERREAD_ID0 :3;
    UINT32 :8;
    UINT32 fg_MMU_OVERREAD_ADD0 :20;
    UINT32 :32; //(68028h)
    // DWORD - IO_MMU_CFGB      (6802ch)
    UINT32 fg_MMU_OVERREAD_ADD0_EN :1;
    UINT32 :31;
    UINT32 :32; //(68030h)
    UINT32 :32; //(68034h)

} MI_DIF_GFX_MMU_T0;

// gfx hw register name/bitfield union
typedef union _MI_DIF_GFX_MMU_UNION_T
{
    E_GFX_MMU_REG_T rReg;
    MI_DIF_GFX_MMU_T0 rField;
} MI_DIF_GFX_MMU_UNION_T;

#endif // GFX_DIF_REG_H
