/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author$
 * $Date  $
 * $RCSfile: drv_hdmi.h,v $
 * $Revision$
 *
 *---------------------------------------------------------------------------*/
#ifndef _DRV_HDMI21COM_H_
#define _DRV_HDMI21COM_H_

#include "drv_hdmi21phy.h"
#include "drv_hdmi21.h"
#include "x_timer.h"

#define DEF_HDMI21_XTAL_FREQ 24000000
#define ABSDIFF(a,b) ((a)>(b)?((a)-(b)):((b)-(a)))


//packet relative
#define DEF_H21_PKT_AVI_TYPE_ID     0x82
#define DEF_H21_PKT_AVI_LENGTH      0x0D

#define DEF_H21_PKT_SPD_TYPE_ID     0x83
#define DEF_H21_PKT_SPD_VER         0x01
#define DEF_H21_PKT_SPD_LENGTH      0x19

#define DEF_H21_PKT_AUD_TYPE_ID     0x84
#define DEF_H21_PKT_AUD_VER         0x01
#define DEF_H21_PKT_AUD_LENGTH      0x0A

#define DEF_H21_PKT_MPEG_TYPE_ID    0x85
#define DEF_H21_PKT_MPEG_VER        0x01
#define DEF_H21_PKT_MPEG_LENGTH     0x0A

#define DEF_H21_PKT_VBI_TYPE_ID     0x86
#define DEF_H21_PKT_VBI_LENGTH      0x1C

#define DEF_H21_PKT_HDR_TYPE_ID     0x87
#define DEF_H21_PKT_HDR_LENGTH      0x1C

#define DEF_H21_PKT_ACP_TYPE_ID     0x04
#define DEF_H21_PKT_ACP_LENGTH      0x1C

#define DEF_H21_PKT_VSIF_TYPE_ID    0x81
#define DEF_H21_PKT_VSIF_LENGTH     0x1F

#define DEF_H21_PKT_ISRC_TYPE_ID    0x06
#define DEF_H21_PKT_ISRC_LENGTH     0x10

#define DEF_H21_PKT_GCP_TYPE_ID     0x03
#define DEF_H21_PKT_GCP_LENGTH      0x07

enum
{
    E_HDMI21_Timing_8K_60_444 = 0x00,
    E_HDMI21_Timing_8K_60_420 = 0x01,
    E_HDMI21_Timing_8K_30_444 = 0x02,
    E_HDMI21_Timing_4K_120_444 = 0x03,
    E_HDMI21_Timing_4K_120_420 = 0x04,
    E_HDMI21_Timing_4K_60_444 = 0x05,
    E_HDMI21_Timing_4K_60_420 = 0x06,
    E_HDMI21_Timing_4K_30_444 = 0x07,
    E_HDMI21_Timing_2K_120_444 = 0x08,
    E_HDMI21_Timing_2K_120_420 = 0x09,
    E_HDMI21_Timing_2K_60_444 = 0x0A,
    E_HDMI21_Timing_2K_60_420 = 0x0B,
    E_HDMI21_Timing_2K_30_444 = 0x0C
};

enum
{
    E_HDMI21_Source_Input_444 = 0,
    E_HDMI21_Source_Input_422_Tuning,
    E_HDMI21_Source_Input_422,
    E_HDMI21_Source_Input_420
};

enum
{
    E_HDMI_SCDC_INT_STATUS_UPDATE =         0x01,
    E_HDMI_SCDC_INT_CED_UPDATE =            0x02,
    E_HDMI_SCDC_INT_RR_TEST =               0x04,
    E_HDMI_SCDC_INT_RSVD =                  0x08,
    E_HDMI_SCDC_INT_CLOCK_STRETCH_OFFSET =  0x10,
    E_HDMI_SCDC_INT_HPD_5V =                0x20,
    E_HDMI_SCDC_INT_ACCESS_A8 =             0x40,
    E_HDMI_SCDC_INT_ACCESS_A9 =             0x80,
    E_HDMI_SCDC_INT_FLT_NO_RETRAIN =        0x800,
    E_HDMI_SCDC_INT_FRL_RATE =              0x4000,
    E_HDMI_SCDC_INT_READ_L0 =               0x1000,
    E_HDMI_SCDC_INT_READ_L1 =               0x1001,
    E_HDMI_SCDC_INT_READ_L2 =               0x1002,
    E_HDMI_SCDC_INT_READ_L3 =               0x1003,
    E_HDMI_SCDC_INT_READ_RS =               0x1004,
};

enum
{
    E_H21_SCDC_FLD_SINK_VER_IDX_01 =            0x01,
    E_H21_SCDC_FLD_SRC_VER_IDX_02 =             0x02,
    E_H21_SCDC_FLD_UPDATE_0_IDX_10 =            0x10,
    E_H21_SCDC_FLD_UPDATE_1_IDX_11=             0x11,
    E_H21_SCDC_FLD_TMDS_CONFIG_IDX_20 =         0x20,
    E_H21_SCDC_FLD_SCRAMBLE_STAT_IDX_21 =       0x21,
    E_H21_SCDC_FLD_CONFIG_0_IDX_30 =            0x30,
    E_H21_SCDC_FLD_CONFIG_1_IDX_31 =            0x31,
    E_H21_SCDC_FLD_STATFLAG_0_IDX_40 =          0x40,
    E_H21_SCDC_FLD_STATFLAG_1_IDX_41 =          0x41,
    E_H21_SCDC_FLD_STATFLAG_2_IDX_42 =          0x42,
    E_H21_SCDC_FLD_ERR_DET_CH0_LOW_IDX_50 =     0x50,
    E_H21_SCDC_FLD_ERR_DET_CH0_HI_IDX_51 =      0x51,
    E_H21_SCDC_FLD_ERR_DET_CH1_LOW_IDX_52 =     0x52,
    E_H21_SCDC_FLD_ERR_DET_CH1_HI_IDX_53 =      0x53,
    E_H21_SCDC_FLD_ERR_DET_CH2_LOW_IDX_54 =     0x54,
    E_H21_SCDC_FLD_ERR_DET_CH2_HI_IDX_55 =      0x55,
    E_H21_SCDC_FLD_ERR_DET_CHKSUM_IDX_56 =      0x56,
    E_H21_SCDC_FLD_ERR_DET_CH3_LOW_IDX_57 =     0x57,
    E_H21_SCDC_FLD_ERR_DET_CH3_HI_IDX_58 =      0x58,
    E_H21_SCDC_FLD_RSCC_LOW_IDX_59 =            0x59,
    E_H21_SCDC_FLD_RSCC_HI_IDX_5A =             0x5A,
    E_H21_SCDC_FLD_TEST_CONFIG_0_IDX_C0 =       0xC0,
    E_H21_SCDC_FLD_MANUFACTURER_OUI_IDX_D0 =    0xD0,
    E_H21_SCDC_FLD_MANUFACTURER_OUI_IDX_D1 =    0xD1,
    E_H21_SCDC_FLD_MANUFACTURER_OUI_IDX_D2 =    0xD2,
    E_H21_SCDC_FLD_DEVICE_ID_IDX_D3 =           0xD3,
    E_H21_SCDC_FLD_MANUFACTURER_SPEC_IDX_DE =   0xDE
};

enum
{
    E_H21_SCDC_RD_INT_MODE_MUX_NONE =           0x00,
    E_H21_SCDC_RD_INT_MODE_MUX_ADDR_LSB =       0x01,
    E_H21_SCDC_RD_INT_MODE_MUX_ADDR_MSB =       0x02,
    E_H21_SCDC_RD_INT_MODE_MUX_ADDR_USER_DEF =  0x03
};

enum
{
    E_H21_SCDC_18B16B_RED_CNT_FLD = 0,
    E_H21_SCDC_18B16B_RMD_CNT_FLD = 1,
    E_H21_SCDC_18B16B_SYMBOL_ERR_FLD = 2
};

typedef enum
{
    E_HDMI_SCDC_SW_MODE_STATUS_UPDATE =         0x01,  // 0x10[0]
    E_HDMI_SCDC_SW_MODE_CED_UPDATE =            0x02,  // 0x10[1] & 0x50~0x58
    E_HDMI_SCDC_SW_MODE_RR_TEST =               0x04,  // 0x10[2]
    E_HDMI_SCDC_SW_MODE_SOURCE_TEST_UPDATE =    0x08,  // 0x10[3]
    E_HDMI_SCDC_SW_MODE_FRL_START =             0x10,  // 0x10[4]
    E_HDMI_SCDC_SW_MODE_FLT_UPDATE =            0x20,  // 0x10[5]
    E_HDMI_SCDC_SW_MODE_RSED_UPDATE =           0x40,  // 0x10[6]
    E_HDMI_SCDC_SW_MODE_RSVD =                  0x80,  // 0x10[7]
    E_HDMI_SCDC_SW_MODE_RSCC =                  0x100,  // 0x59, 0x5A
    E_HDMI_SCDC_SW_MODE_STATUS_FLAG =           0x200,  // 0x40
} ENUM_HDMI_SCDC_FIELD_SW_MODE;

typedef enum
{
    E_HDMI_CLK_PATH_HDMI20,
    E_HDMI_CLK_PATH_HDMI21_P2,
    E_HDMI_CLK_PATH_HDMI21_P3
} ENUM_HDMI_CLK_PATH;

typedef struct
{
    HAL_TIME_T stLogTime;
    HdmiRxSettingState_t enAnaState;
    UINT8 u1FRLState;
    UINT8 u1WBDet_L0;
    UINT8 u1WBDet_L1;
    UINT8 u1WBDet_L2;
    UINT8 u1WBDet_L3;

    UINT8 u1SLock_L0;
    UINT8 u1SLock_L1;
    UINT8 u1SLock_L2;
    UINT8 u1SLock_L3;

    UINT16 u2FRLErr_L0;
    UINT16 u2FRLErr_L1;
    UINT16 u2FRLErr_L2;
    UINT16 u2FRLErr_L3;

    UINT16 u21618bPreErr_L0;
    UINT16 u21618bPreErr_L1;
    UINT16 u21618bPreErr_L2;
    UINT16 u21618bPreErr_L3;

    UINT16 u21618bErr_L0;
    UINT16 u21618bErr_L1;
    UINT16 u21618bErr_L2;
    UINT16 u21618bErr_L3;

} st_dump_obj;

/**
 * @brief        HDMI 2.1 get MAC register base offset for corresponding port
 * @param        ePort ---- port index
 * @retval       register base offset
*/
extern UINT16 u2HDMI21ComGetMacBaseOffset(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 get vidoe processor register base offset for corresponding port
 * @param        ePort ---- port index
 * @retval       register base offset
*/
extern UINT16 _u2HDMI21ComGetVPBaseOffset(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 get SCDC register base offset for corresponding port
 * @param        ePort ---- port index
 * @retval       register base offset
*/
extern UINT16 _u2HDMI21ComGetSCDCBaseOffset(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 Initial settings of MAC clock
 * @param        ePort ---- port index
 * @param        bEnableClk ---- flag of enabling clock or not
*/
extern void vHDMI21ComInitClockSettings(E_HDMI_SWITCH_NUM ePort, BOOL bfgEnableClk);

/**
 * @brief        HDMI 2.1 Initial settings of MAC
 * @param        ePort ---- port index
*/
extern void vHDMI21ComMacInitSettings(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 switching audio mux
*/
extern void vHDMI21ComAudSwitchAudioSel(void);

/**
 * @brief        HDMI 2.1 Check APLL lock status;
*/
extern BOOL fgHDMI21ComAudPollPLLLock(void);

/**
 * @brief        HDMI 2.1 config sampling rate;
*/
extern void vHDMI21ComAudConfigSamplingRate(UINT8 u1SamplingRateIdx);

/**
 * @brief        HDMI 2.1 clear AFifo error status;
*/
extern void vHDMI21ComAudClrFifoErrStatus(void);

/**
 * @brief        HDMI 2.1 reset Afifo;
*/
extern void vHDMI21ComAudResetAFifo(void);

/**
 * @brief        HDMI 2.1 clear audio mute;
*/
extern void vHDMI21ComAudClrMute(void);

/**
 * @brief        HDMI 2.1 audio mute;
*/
extern void vHDMI21ComAudMute(BOOL bMute);

/**
 * @brief        HDMI 2.1 select audio out;
*/
extern void vHDMI21ComAudOutSel(BOOL bEn);

/**
 * @brief        HDMI 2.1 AAC enable;
*/
extern void vHDMI21ComAacEn(BOOL bEn);

/**
 * @brief        HDMI 2.1 audio reset;
*/
extern void vHDMI21ComAudReset(void);
/**
 * @brief        HDMI 2.1 Audio settings
*/
extern void vHDMI21ComAudInitSetting(void);

/**
 * @brief        HDMI 2.1 Audio settings
 * @param        ePort ---- port index
 * @param        u1SamplingRateIdx ---- enum of sampling rate
*/
extern void vHDMI21ComAudioSetting(E_HDMI_SWITCH_NUM ePort, UINT8 u1SamplingRateIdx);

/**
 * @brief        HDMI 2.1 Get AFIFO status;
 * @retval       Audio fifo status;
*/
extern UINT8 fgHDMI21ComAudFifoFault(void);

/**
 * @brief        HDMI 2.1 check Audio is PCM or not
 * @param        ePort ---- port index
 * @retval       TRUE if audio is PCM format;
*/
extern BOOL fgHDMI21ComAudIsPCM(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 Get Audio N value
 * @retval       Audio N value;
*/
extern UINT16 u2HDMI21ComAudGetNValue(void);

/**
 * @brief        HDMI 2.1 Get Audio CTS value
 * @retval       Audio CTS value;
*/
extern UINT32 u2HDMI21ComAudGetCTSValue(void);

/**
 * @brief        HDMI 2.1 calculate Audio sampling rate by CTS/N value
 * @param        u1FRLRate ---- current frl rate
 * @retval       Audio sampling rate (unit: 10Khz)
*/
extern UINT32 u4HDMI21ComAudCalculateSamplingRate(UINT8 u1FRLRate);

/**
 * @brief        HDMI 2.1 calculate Audio sampling rate by CTS/N value
 * @param        ePort ---- port index
 * @retval       bit width of audio sample
*/
extern UINT8 bHDMI21ComAudGetBitWidth(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 settings for switching port
 * @param        ePort ---- port index
*/
extern void vHDMI21ComSwitchPort(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 settings for switching port
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
 * @retval       flag to indicate if DSC is enabled or not
*/
extern BOOL fgHDMI21ComGetDSCFlag(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 config decoder
 * @param        ePort ---- port index
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        bEnableClk ---- flag of enabling DSC or not
*/
extern void vHDMI21ComConfigDecoder(E_HDMI_SWITCH_NUM ePort, UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        switch the timing detect spot in MAC
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        u1TDetSpot ---- timing detect spot enum
*/
extern void vHDMI21ComSwitchTimingDetSpot(UINT16 u2Hdmi21Base, UINT8 u1TDetSpot);

/**
 * @brief        Dump timing detect information of different spot
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
 * @param        u1TDetSpot ---- timing detect spot enum
*/
extern void vHDMI21ComDBGDumpTimingDetectInfo(UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj, UINT8 u1TDetSpot);

/**
 * @brief        Enable HDMI2.1 pattern gen
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        u1EnableFlag ---- enable flag
 * @param        u1PGType ---- pattern gen type select
*/
extern void vHDMI21ComEnablePG(UINT16 u2Hdmi21Base, UINT8 u1EnableFlag, UINT8 u1PGType);

/**
 * @brief        get latest timing detect info
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        HdmiRxTimingInfo_t ---- timing info struct
*/
extern void vHDMI21ComGetCurrentTimingInfo(UINT16 u2Hdmi21Base, HdmiRxTimingInfo_t* pstHdmi21TimingInfo);

/**
 * @brief        HDMI 2.1 Enable SDM PLL
 * @param        ePort ---- port index
 * @param        fgEnableFlag ---- enable flag
*/
extern void vHDMI21ComEnableSDMPLL(E_HDMI_SWITCH_NUM ePort, BOOL fgEnableFlag);

/**
 * @brief        HDMI 2.1 Enable Frame LPLL
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        fgEnableFlag ---- enable flag
*/
extern void vHDMI21ComEnableFrameLPLL(UINT16 u2Hdmi21Base, BOOL fgEnableFlag);

/**
 * @brief        HDMI 2.1 reset hardware timing detect info
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        bEnableReset ---- reset flag
*/
extern void vHDMI21ComResetHWTimingDetInfo(UINT16 u2Hdmi21Base, BOOL bEnableReset);

/**
 * @brief        HDMI 2.1 check if the timing detect info is correct
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
 * @retVal       flag to indicate if the timing detect info is stable
*/
extern BOOL fgHDMI21ComCheckTimingInfoStable(UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        HDMI 2.1 check if the timing detect info is match regen value
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
 * @retVal       flag to indicate if the timing detect info and regen value are matched
*/
extern BOOL vHDMI21ComChkTgenTimingInfo(UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        HDMI 2.1 Configure timing re-gen module
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
 * @param        pstHdmi21Context ---- HDMI21 context struct
*/
extern void vHDMI21ComConfigTGen(UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj, HDMI21_CONTEXT_T* pstHdmi21Context);

/**
 * @brief        HDMI 2.1 Configure sync PLL
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
*/
extern void vHDMI21ComConfigSyncPLL(UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        HDMI 2.1 for 420 flag setting
 * @param        ePort ---- port index
 * @param        u1Is420 ---- indicate if 420 format
*/
extern void vHDMI21ComConfig420FormatSetting(E_HDMI_SWITCH_NUM ePort, UINT8 u1Is420);

/**
 * @brief        HDMI 2.1 detect and set color format relative settings
 * @param        ePort ---- port index
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
*/
extern void vHDMI21ComDetectColorFormat(E_HDMI_SWITCH_NUM ePort, UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        HDMI 2.1 calcualtes pixel clock and information which is used to set clock div
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
*/
extern BOOL fgHDMI21ComCalculatePixelClock(UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        HDMI 2.1 Configurates SDM PLL setting
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
*/
extern void vHDMI21ComConfigSDMPLL(UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        HDMI 2.1 Configurates Distribution pixel clock
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
*/
extern void vHDMI21ComConfigDistributionPixelClk(UINT16 u2Hdmi21Base, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        HDMI 2.1 video processor initial setting
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        u1InterClk ---- VP inter clock
 * @param        u11POutClk ---- VP 1P out clock
 * @param        u12POutClk ---- VP 2P out clock
 * @param	     eOutPathNum ---- VP out path number 1P/2P/8P
*/
extern void vHDMI21ComVPConfigInitSetting(UINT16 u2HdmiVPBase, UINT8 u1InterClk, UINT8 u11POutClk, UINT8 u12PLROutClk, ENUM_HDMI21_VP_OUT_PATH_NUM eOutPathNum);

/**
 * @brief        HDMI 2.1 video processor initial setting
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        fgSrcIs422 ---- indicate if source input color format is 422
 * @param        fg420to422Bypass ---- indicate if needs 420 to 422 bypass
 * @param        u1422to444MDMethod ---- chose 422 to 444 MD method
*/
extern void vHDMI21ComVPConfig420to444(UINT16 u2HdmiVPBase, BOOL fgSrcIs422, BOOL fg420to422Bypass, UINT8 u1422to444MDMethod);

/**
 * @brief        HDMI 2.1 video processor source setting
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        fgSrcIs420 ---- indicate if source input color format is 420
 * @param        u2Hde420 ---- 420 HDE value
*/
extern void vHDMI21ComVPSettingSrc(UINT16 u2HdmiVPBase, BOOL fgSrcIs420, UINT16 u2Hde420);

/**
 * @brief        HDMI 2.1 video processor initial setting
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        fgDitherEnable ---- dither enable flag
 * @param        fgTruncEnable ---- truncate enable flag
*/
extern void vHDMI21ComVPConfig12Bto10BMethod(UINT16 u2HdmiVPBase, BOOL fgDitherEnable, BOOL fgTruncEnable);

/**
 * @brief        HDMI 2.1 video processor initial setting
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        eOutPathNum ---- VP out path number 1P/2P/8P
*/
extern void vHDMI21ComVPConfig2PLRor1PMux(UINT16 u2HdmiVPBase,  ENUM_HDMI21_VP_OUT_PATH_NUM eOutPathNum);
/**
 * @brief        HDMI 2.1 video processor initial setting
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        eOutTiming ---- VP out timing 861G/CCIR
*/
extern void vHDMI21ComVPConfig861GorCCIR(UINT16 u2HdmiVPBase, ENUM_HDMI21_VP_OUT_TIMING eOutTiming);

/**
 * @brief        HDMI 2.1 Configurates video processor for HDMI2.0
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        fgHdmi20En ---- HDMI2.0 Enable
*/
extern void vHDMI21ComVPHDMI20PathEn(UINT16 u2HdmiVPBase, BOOL fgHdmi20En);

/**
 * @brief        HDMI 2.1 configure how to handle multi-VSIF packets
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        fgVDEEndClrCnt ---- flag to indicate if VSIF counter is cleared when VDE End
 * @param        fgShiftOrderFIFO ---- flag to indicate if the lastest VSIF shift out the ordest packet
*/
extern void vHDMI21ComConfigMultiVSIF(UINT16 u2Hdmi21Base, BOOL fgVDEEndClrCnt, BOOL fgShiftOrderFIFO);

/**
 * @brief        HDMI 2.1 Get Multi-VSIF clear machianism
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @retval       TURE if Multi-VSIF counter is cleared when VDE end
*/
extern BOOL fgHDMI21ComGetMultiVSIFClrVDEEndFlag(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 Get Multi-VSIF shift machianism
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @retval       TURE if the receive order of Multi-VSIF packet is FIFO
*/
extern BOOL fgHDMI21ComGetMultiVSIFShiftOrderFIFO(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 Get Multi-VSIF counter in one VBD
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @retval       mutli-VSIF counter
*/
extern UINT8 u1HDMI21ComGetMultiVSIFCounter(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 Clear Multi-VSIF counter
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
*/
extern void vHDMI21ComClrMutliVSIFCounter(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 Get packet receive status
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
*/
extern UINT32 u4HDMI21ComGetPacketReceiveStatus(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 Get packet receive status
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
 * @param        u2Hdmi21Base ---- register base offset of HDMI Digital
 * @param        u1PktType ---- packet type
*/
extern void vHDMI21ComGetPacketContent(HdmiRxInfo_t *pstH21RxInfoObj, UINT16 u2Hdmi21Base, UINT8 u1PktType, UINT8 u1PktIdx);

/**
 * @brief        HDMI 2.1 Get FRL Link rate
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
 * @retval       FRL rate enum value: 1 ~ 6: HDMI 2.1; 0: legacy mode;
*/
extern UINT8 u1HDMI21ComGetLinkRate(UINT16 u2HdmiAnaBase, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        set FRL rate info to HDMi21 context
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
 * @param        FRL rate enum value: 1 ~ 6: HDMI 2.1; 0: legacy mode;
*/
extern void u1HDMI21ComSetFRLRate(HdmiRxObject_t* pstHdmi21RxObj, UINT8 u1FrlRate);

/**
 * @brief        HDMI 2.1 return FRL rate info in HDMI21 context
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
 * @retval       FRL rate enum value: 1 ~ 6: HDMI 2.1; 0: legacy mode;
*/
extern UINT8 u1HDMI21ComGetFRLRate(UINT16 u2HdmiAnaBase, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        HDMI 2.1 Get TxFFE level of specific data lane
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        u1HDMILaneIdx ---- data lane index
 * @retval       TxFFE level, should be 0~3
*/
extern UINT8 u1HDMI21ComGetLaneFFELevel(UINT16 u2HdmiAnaBase, UINT8 u1HDMILaneIdx);

/**
 * @brief        HDMI 2.1 Get FLT_Done flag
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        pstHdmi21RxObj ---- general structure of HDMI 2.1 info
*/
extern BOOL fgHDMI21ComGetFLTDoneFlag(UINT16 u2HdmiAnaBase, HdmiRxObject_t* pstHdmi21RxObj);

/**
 * @brief        HDMI 2.1 Get VDE stable status under TMDS domain
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern BOOL fgHDMI21ComChkTMDSVdeStable(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 Get HDE stable status under TMDS domain
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern BOOL fgHDMI21ComChkTMDSHdeStable(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 Get VDE stable status under FRL domain
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern BOOL fgHDMI21ComChkFRLVdeStable(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 Get HDE stable status under FRL domain
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern BOOL fgHDMI21ComChkFRLHdeStable(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 check singal stable status;
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern BOOL fgHDMI21ComChkSignalStable(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 Set FLT ready bit
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        fgEnable ---- true or false for FLT ready bit
*/
extern void vHDMI21ComSetFLTReadyFlag(UINT16 u2HdmiAnaBase, BOOL fgEnable);

/**
 * @brief        HDMI 2.1 reset word boundary detect hw state machine
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        fgReset ---- reset flag
*/
extern void vHDMI21ComResetWordBoundaryDetFSM(UINT16 u2Hdmi21Base, BOOL fgReset);

/**
 * @brief        HDMI 2.1 reset FRL timing detect module
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        fgReset ---- reset flag
*/
extern void vHDMI21ComResetFRLTimingDetect(UINT16 u2Hdmi21Base, BOOL fgReset);

/**
 * @brief        HDMI 2.1 Get error detect status
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        pstHdmi21ErrDetStatObj ---- general structure of HDMI 2.1 error status
*/
extern void u2HDMI21ComGetErrorDetectStatus(UINT16 u2Hdmi21Base, HDMI21_ERR_DET_STAT_T* pstHdmi21ErrDetStatObj);

/**
 * @brief        HDMI 2.1 Get Hardware FLT state
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @retval       current FLT state;
*/
extern UINT8 bHDMI21ComGetFLTState(UINT16 u2HdmiAnaBase);

/**
 * @brief        HDMI 2.1 Set Check link quality start timer
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        adjust value of start timer, only 10bit
*/
extern void vHDMI21ComSetChkLinkQualStartTimer(UINT16 u2HdmiAnaBase, UINT16 u2Offset);

/**
 * @brief        HDMI 2.1 Set Check link quality end timer
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        adjust value of end timer, only 10bit
*/
extern void vHDMI21ComSetChkLinkQualEndTimer(UINT16 u2HdmiAnaBase, UINT16 u2Offset);

/**
 * @brief        HDMI 2.1 bypass link training decoder check
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        offset of check start timer
*/
extern void vHDMI21ComBypassFLTDecoderCheck(UINT16 u2HdmiAnaBase, BOOL fgEnableBypass);

/**
 * @brief        HDMI 2.1 bypass link trainig SR/SSB lock check
 * @param        u2HdmiAnaBase ---- register base offset of HDMI v2.1 PHY
 * @param        offset of check end timer
*/
extern void vHDMI21ComBypassFLTSRSSBLockCheck(UINT16 u2HdmiAnaBase, BOOL fgEnableBypass);

/**
 * @brief        HDMI 2.1 reset index of debug info array
 * @param        ePort ---- port index
*/
extern void u2HDMI2ComResetDebugInfo(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 dump debug info content
 * @param        ePort ---- port index
*/
extern void HDMI21ComDumpInfoContent(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 dump debug info content
 * @param        ePort ---- port index
 * @param        enumState ---- indicate in which analog state
*/
extern void u2HDMI2ComStoreDebugInfo(E_HDMI_SWITCH_NUM ePort, HdmiRxSettingState_t enumState);

/**
 * @brief        Set Audio Source
 * @param	     u1Sel ---- select index
*/
extern void dwHDMI21ComSetAudSrc(UINT8 u1Sel);

/**
 * @brief        Get Audio Source Select
*/
extern UINT32 dwHDMI21ComGetAudSrc(void);

/**
 * @brief        Get H total value
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComGetHTotal(UINT16 u2Hdmi21Base);

/**
 * @brief        Get V total value
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComGetVTotal(UINT16 u2Hdmi21Base);

/**
 * @brief        Get H active value
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComGetHActive(UINT16 u2Hdmi21Base);

/**
 * @brief        Get V active value
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComGetVActive(UINT16 u2Hdmi21Base);

/**
 * @brief        Get frame rate
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComGetFrameRate(UINT16 u2Hdmi21Base);

/**
 * @brief        Get pixel clock
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT64 dwHDMI21ComGetPixelClk(UINT16 u2Hdmi21Base);

/**
 * @brief        Get H clock
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComGetHClk(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 get whether DSC enable
 * @param        ePort ---- port index
*/
extern UINT32 dwHDMI21ComGetDscEn(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        HDMI 2.1 reset depack engine
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern void vHDMI21ComResetDepackHW(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI 2.1 set DSC enable
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        fgEnable ---- true or false for enable or disable DSC
*/
extern void vHDMI21ComSetDscEn(UINT16 u2Hdmi21Base,BOOL fgEnable);

/**
 * @brief        set DSC info
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        pstHdmi21DscTimingInfo ---- DSC timing info
 * @param        pstHdmi21Context ---- HDMI21 Context struct
*/
extern void _vHDMI21ComUpdateDscInfo(UINT16 u2Hdmi21Base, HdmiRxDSCTimingInfo_t *pstHdmi21DscTimingInfo, HDMI21_CONTEXT_T* pstHdmi21Context);

/**
 * @brief        set PPS to DSC register
 * @param        ePort ---- port index
*/
extern void vHDMI21ComDSCSetPPS(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        set slice shift to DSC register
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern void vHDMI21ComDSC_SetSliceShiftBlanking(UINT16 u2Hdmi21Base, UINT16 u1SliceNumber, UINT16 u2SLiceWidth, UINT32 u4InputPixelClk, UINT32 u4HTotal, HdmiRxDSCTimingInfo_t *pstHdmi21DscTimingInfo);

/**
 * @brief        Check CRC value for HDMI v2.1 FRL
 * @param        u2Hdmi21VPBase ---- register base offset of HDMI v2.1 VP module
 * @param        u1LorRSide ---- L or R side of CRC
 * @param        u2Times ---- CRC check routine number
 * @retval       CRC check process is ok or fail
*/
extern BOOL fgHDMI21ComCheckCRC(UINT16 u2Hdmi21VPBase, UINT8 u1LorRSide, UINT16 u2Times);

/**
 * @brief        Check HDMI 21 CRC value
 * @param        u2Hdmi21VPBase ---- register base offset of HDMI v2.1 VP module
 * @param        u1LorRSide ---- L or R side of CRC
 * @param        u2Times ---- CRC check routine number
 * @retval       CRC check process is ok or fail
*/
extern BOOL fgHDMI21ComCheckCRC(UINT16 u2Hdmi21VPBase, UINT8 u1LorRSide, UINT16 u2Times);

/**
 * @brief        Reset all SCDC Status(scramble/tmds_ratio...)
 * @param        ePort ---- port index
 * @retval       void
*/
extern void vHDMI21ComClearSCDCStatus(E_HDMI_SWITCH_NUM ePort);

/**
 * @brief        Set tirgger address of SCDC ISR
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        u1SCDCOffset ---- offset address of SCDC
*/
extern void vHDMI21ComSetSCDCISRAddr(UINT16 u2Hdmi21SCDCBase, UINT8 u1SCDCOffset);

/**
 * @brief        Get tirgger address of SCDC ISR
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @retval       tirgger address of SCDC ISR
*/
extern UINT8 vHDMI21ComGetSCDCISRAddr(UINT16 u2Hdmi21SCDCBase);

/**
 * @brief        Enable Software overwrite mode of specific SCDC offset
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        enSCDCField ---- SCDC offset address
 * @param        bEnable ---- enable flag
*/
extern void vHDMI21ComEnableSWModeForSCDCField(UINT16 u2Hdmi21SCDCBase, ENUM_HDMI_SCDC_FIELD_SW_MODE enSCDCField, BOOL bEnable);

/**
 * @brief        Get value of specific SCDC offset address
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        u1SCDCOffset ---- SCDC offset address
 * @retval       current value of SCDC offset address
*/
extern UINT8 vHDMI21ComGetSCDCFieldValue(UINT16 u2Hdmi21SCDCBase, UINT8 u1SCDCOffset);

/**
 * @brief        Set value of specific SCDC offset address
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        u1SCDCOffset ---- SCDC offset address
 * @param        u1Value ---- value to be set into SCDC offset
*/
extern void vHDMI21ComSetSCDCFieldValue(UINT16 u2Hdmi21SCDCBase, UINT8 u1SCDCOffset, UINT8 u1Value);

/**
 * @brief        enable or disable interrupt mask of specific SCDC offset
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        u2StatusField ---- SCDC offset address
 * @param        bEnableMask ---- enable flag of ISR mask
*/
extern void vHDMI21ComSetSCDCIntMask(UINT16 u2Hdmi21SCDCBase, UINT16 u2StatusField, BOOL bEnableMask);

/**
 * @brief        Get interrupt status of specific SCDC offset
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        u2StatusField ---- SCDC offset address
 * @retval       interrupt status of specific SCDC offset
*/
extern UINT8 vHDMI21ComGetSCDCIntStatus(UINT16 u2Hdmi21SCDCBase, UINT16 u2StatusField);

/**
 * @brief        Set mode mux of SCDC read interrupt
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        u2StatusField ---- SCDC offset address
 * @param        u2SCDCRdModeMux ---- mode mux value
*/
extern void vHDMI21ComSetSCDCReadIntMode(UINT16 u2Hdmi21SCDCBase, UINT16 u2SCDCRdField, UINT16 u2SCDCRdModeMux);

/**
 * @brief        Setup specific SCDC offset address which will trigger interrupt while under mode 3;
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        u2StatusField ---- SCDC offset address
 * @param        u1SCDCOffset ---- SCDC offset address
*/
extern void vHDMI21ComSetSCDCReadIntOffset(UINT16 u2Hdmi21SCDCBase, UINT16 u2SCDCRdField, UINT8 u1SCDCOffset);

/**
 * @brief        clear hardware internal error count
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 SCDC module
 * @param        u1ErrCntFld ---- specific error type
*/
extern void vHDMI21ComClearErrorCount(UINT16 u2Hdmi21Base, UINT8 u1ErrCntFld);

/**
 * @brief        dump debug information of CED
*/
extern void vHDMI21ComDBGDumpCEDCount(void);

/**
 * @brief        dump debug information of RS
*/
extern void vHDMI21ComDBGDumpRSCount(void);

/**
 * @brief        overwrite Clock_Detected field of SCDC offst 0x40
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        bEnableOverwrite ---- overwrite flag
*/
extern void vHDMI21ComOverwriteSCDCClkDetField(UINT16 u2Hdmi21SCDCBase, BOOL bEnableOverwrite);

/**
 * @brief        Software patch for CED CTS testing items
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        pstHdmi21RxObj ---- pointer of HDMI RX Software context structure
 * @param        pHdmi21Context ---- pointer of HDMI21 Software context structure
*/
extern void vHDMI21ComUpdateCEDField(UINT16 u2Hdmi21Base, UINT16 u2Hdmi21SCDCBase, HdmiRxObject_t* pstHdmi21RxObj, HDMI21_CONTEXT_T *pHdmi21Context);

/**
 * @brief        Reset SR/SSB error counter
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        bFlag ---- reset flag
*/
extern void vHDMI21ComResetSRSSB(UINT16 u2Hdmi21Base, BOOL bFlag);

/**
 * @brief        Reset FEC/REC error counter
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern void vHDMI21ComResetFECRecErrCnt(UINT16 u2Hdmi21Base);

/**
 * @brief        Software patch for RS CTS testing items
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        u2Hdmi21SCDCBase ---- register base offset of HDMI v2.1 SCDC module
 * @param        pstHdmi21RxObj ---- pointer of HDMI RX Software context structure
 * @param        pHdmi21Context ---- pointer of HDMI21 Software context structure
*/
extern void vHDMI21ComUpdateRSField(UINT16 u2Hdmi21Base, UINT16 u2Hdmi21SCDCBase, HdmiRxObject_t* pstHdmi21RxObj, HDMI21_CONTEXT_T *pHdmi21Context);

/**
 * @brief        Select Video LR MUX
 * @param        bHDMI21_In ---- HDMI2.0 or HDMI2.1
 * @param        ePort ---- port index
 * @param        eHdmiVpPathNum ---- VP out 1P/2P/8P
*/
extern void vHDMI21ComSelVideoLR(BOOL bHDMI21_In,E_HDMI_SWITCH_NUM ePort,ENUM_HDMI21_VP_OUT_PATH_NUM eHdmiVpPathNum);
/**
 * @brief        HDMI2.1 IP Enable/Disable
 * @param	     ePort ---- port index
 * @param        fgEnable ---- enable flag
*/
extern void vHDMI21ComHDMI21En(E_HDMI_SWITCH_NUM ePort,BOOL fgEnable);
/**
 * @brief        HDMI2.1/HDMI2.0 clk mux select
 * @param        ePort ---- port index
*/
extern void vHDMI21ComHdmiClkPathSel(ENUM_HDMI_CLK_PATH ePath);
/**
 * @brief        HDMI2.1 get 420 mode
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern BOOL fgHDMI21ComGet420Mode(UINT16 u2Hdmi21Base);
/**
 * @brief        HDMI2.1 get 422 mode
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern BOOL fgHDMI21ComGet422Mode(UINT16 u2Hdmi21Base);
/**
 * @brief        HDMI2.1 get HSync Width
 * @param	     u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComHsyncWidth(UINT16 u2Hdmi21Base);
/**
 * @brief        HDMI2.1 get VSync Width
 * @param	     u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComVsyncWidth(UINT16 u2Hdmi21Base);
/**
 * @brief        HDMI2.1 get HBack Porch
 * @param	     u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComHBPCount(UINT16 u2Hdmi21Base);
/**
 * @brief        HDMI2.1 get VBack Porch
 * @param	     u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT32 dwHDMI21ComVBPCount(UINT16 u2Hdmi21Base);
/**
 * @brief        HDMI2.1 config vrr emp dma mode
 * @param     None
*/
extern BOOL bHDMI21ConfigEmpDma(HDMI21_SHARE_MEMORY_INFO *pgHDMI21EmpDmaInfo);
/**
 * @brief        HDMI2.1 config  EMP Int Mask
 * @param     0x1 enable emp interrupt
*/
extern void vHDMI21ComSetEMPIntMask(UINT8 bEnableMask);
/**
 * @brief        HDMI2.1 get  EMP Int status
 * @param     0x1 emp interrupt happan
*/
extern UINT8 u1HDMI21ComGetEMPIntStatus(void);
/**
 * @brief        HDMI2.1 config  EMP Int Mask
 * @param     0x1 clear emp interrup status
*/
extern void vHDMI21ComClrEMPIntStatus(UINT8 bClrMask);

extern void vHDMI21ComHDR10PlusVsiClrInt(UINT16 u2Hdmi21Base);

extern void vHDMI21ComHDR10PlusVsiEn(E_HDMI_SWITCH_NUM ePort);

extern void vHDMI21ComSetVdeEndIntEnable(UINT16 u2Hdmi21Base, UINT8 u1Enable);
extern void vHDMI21ComSetVdeEndIntMask(UINT16 u2Hdmi21Base, UINT8 u1Mask);
extern UINT8 u1HDMI21ComGetVdeEndntStatus(UINT16 u2Hdmi21Base);
extern void vHDMI21ComClrVdeEndIntStatus(UINT16 u2Hdmi21Base, UINT8 u1Clear);

/**
 * @brief        HDMI2.1 get color depth
 * @param	     u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @retval       color depth value from GCP packet
*/
extern UINT8 u1HDMI21ComGetColorDepth(UINT16 u2Hdmi21Base);
/**
 * @brief        HDMI2.1 get whether interlaced
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern BOOL fgHDMI21ComGetInterlaced(UINT16 u2Hdmi21Base);
/**
 * @brief        HDMI2.1 get whether signal lock
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern UINT8 fgHDMI21ComGetSignalLockStatus(UINT16 u2Hdmi21Base);
/**
 * @brief        HDMI2.1 clock set user mode
 * @param        ePort ---- port index
*/
extern void vHDMI21ComSetUsrMode(E_HDMI_SWITCH_NUM ePort,UINT8 u1InterClk);

/**
 * @brief        HDMI2.1 Clear FRL Decode SRAM fifo status;
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
*/
extern void vHDMI21ComResetFRLDecSRAMFifo(UINT16 u2Hdmi21Base);

/**
 * @brief        HDMI2.1 Clear FRL Decode SRAM fifo status;
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @retVal       return flag to indicate if SRAM fifo status is correct. 1: normal, 0: abnormal;
*/
extern UINT8 vHDMI21ComCheckFRLSRAMFifoStable(UINT16 u2Hdmi21Base);

/**
 * @brief        Get HDMI2.1 current data rate;
 * @param        u2Hdmi21Base ---- register base offset of HDMI v2.1 MAC
 * @param        pstHdmi21RxObj ---- pointer of HDMI RX Software context structure
*/
extern UINT16 u2HDMI21ComGetDataRate(UINT16 u2Hdmi21Base, HdmiRxObject_t * pstHdmi21RxObj);
#endif //#ifndef _DRV_HDMI21COM_H_
