/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


#ifndef CONFIG_DEFAULT_H
#define CONFIG_DEFAULT_H

#include "x_pinmux.h"

//----------------------------------------------------------------------------
// Initial dram settings
//----------------------------------------------------------------------------
#define DEFAULT_DRAM_TYPE                   DDR_LP4_x4
#define DEFAULT_DDR_CLOCK                   (3504000000)
//for MTK turnkey PCB only (in bootp.c)
//#define DEFAULT_DRAM_PCB_CHK                (0)

//#ifndef DRAM_PRIORITY_LIST
// Audio/0 > B2R/5 > NR/PSCAN/4 > Scpip/7 > OSD/3 > Mjc_in/13 > Mjc_out/14 > VLD1/9 > Vdec_mc/8 > CPU/6 > Gfx/11 > Demux/PVR/1 > VBI/3D/TVE/2 >VENC/12 > Test/15 > Unused/10
//#define DRAM_PRIORITY_LIST                  ((UINT8*)"0c9421a387fbd56e")
//#endif

//----------------------------------------------------------------------------
// FBM setup
//----------------------------------------------------------------------------
#ifdef ANDROID
    #if defined(CONFIG_64BIT) || defined(CC_64BIT_SUPPORT)
		#if defined(CC_SUPPORT_DRAM_4GB)
			#define TOTAL_MEM_SIZE					(0x100000000) //(4 * 1024 * 1024 * 1024)
		#elif defined(CC_SUPPORT_DRAM_3GB)
			#define TOTAL_MEM_SIZE					(0xC0000000) //(3 * 1024 * 1024 * 1024)
		#elif defined(CC_SUPPORT_DRAM_2GB)
			#define TOTAL_MEM_SIZE					(0x80000000) //(2 * 1024 * 1024 * 1024)
		#else
			#define TOTAL_MEM_SIZE					(0xA0000000) //(2.5 * 1024 * 1024 * 1024)
		#endif
    #else
		#define TOTAL_MEM_SIZE						(0x60000000) //(1536 * 1024 * 1024)
    #endif
#else
    #if defined(CONFIG_64BIT) || defined(CC_64BIT_SUPPORT)
	    #if defined(CC_SUPPORT_DRAM_4GB)
            #define TOTAL_MEM_SIZE                      (0x100000000) // 8888Gb
            //#define DEFAULT_CHANNEL_A_SIZE            (0x60000000)
		#elif defined(CC_SUPPORT_DRAM_3GB)
			#define TOTAL_MEM_SIZE                      (0xC0000000) // 8844Gb
			//#define DEFAULT_CHANNEL_A_SIZE              (3 * 1024 * 1024 * 1024)
		#elif defined(CC_SUPPORT_DRAM_2GB)
			#define TOTAL_MEM_SIZE                      (0x80000000)//(2 * 1024 * 1024 * 1024) // 4444Gb
			//#define DEFAULT_CHANNEL_A_SIZE              (2 * 1024 * 1024 * 1024)
		#elif defined(CC_SUPPORT_DRAM_1_5GB)
			#define TOTAL_MEM_SIZE                      (0x60000000)
		#else   //CC_SUPPORT_DRAM_2_5GB
			#define TOTAL_MEM_SIZE                      (0xA0000000)//(2.5 * 1024 * 1024 * 1024) // 8444Gb
			//#define DEFAULT_CHANNEL_A_SIZE              (2.5 * 1024 * 1024 * 1024)
		#endif
    #else
        #define TOTAL_MEM_SIZE                      (0x60000000) //(1536 * 1024 * 1024) // 8888Gb
    #endif
#endif

#define EMI_MEM_OFFSET 0x40000000   // 1GB offset

#ifdef CC_FORCE_DRAM1_25G
        //#define TOTAL_CHB_MEM_SIZE                      (512 * 1024 * 1024) /* size of Channel B bank */
#elif defined (CC_FORCE_DRAM1_75G)
        //#define TOTAL_CHB_MEM_SIZE                      (512 * 1024 * 1024) /* size of Channel B bank */
#else
        //#define TOTAL_CHB_MEM_SIZE                      (1024 * 1024 * 1024) /* size of Channel B bank */
#endif

#if 1
#define CC_CONFIG_OSD_CM_SIZE               (4) // 4:argb 8888 ;2:argb 4444
#define CC_CONFIG_OSD_BUF_MODE              (2) // 2:double  buffer ;1:sngle buffer

#ifndef CC_CONFIG_OSD_PLANE1_MAX_W
#define CC_CONFIG_OSD_PLANE1_MAX_W          (0)
#endif
#ifndef CC_CONFIG_OSD_PLANE1_MAX_H
#define CC_CONFIG_OSD_PLANE1_MAX_H          (0)
#endif
#define CC_CONFIG_OSD_PLANE1_MEM_SIZE       (((CC_CONFIG_OSD_PLANE1_MAX_W*     \
                                        CC_CONFIG_OSD_PLANE1_MAX_H*        \
                                        CC_CONFIG_OSD_CM_SIZE*             \
                                        CC_CONFIG_OSD_BUF_MODE)+0x1000)&(0xFFFFF000))

        // osd 3d buffer size
#if (defined(CC_CONFIG_OSD_SBS_PLANE1)||defined(CC_CONFIG_OSD_TB_PLANE1))
#define CC_CONFIG_OSD_3D_PLANE1_MEM_SIZE    (CC_CONFIG_OSD_PLANE1_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE1_MEM_SIZE    (0)
#endif

        // osd decompress  buffer size
#ifdef CONFIG_OSD_PLANE1_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE1_MEM_SIZE   (CC_CONFIG_OSD_PLANE1_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE1_MEM_SIZE   (0)
#endif

#ifndef CC_CONFIG_OSD_PLANE2_MAX_W
#define CC_CONFIG_OSD_PLANE2_MAX_W          (1920)
#endif
#ifndef CC_CONFIG_OSD_PLANE2_MAX_H
#define CC_CONFIG_OSD_PLANE2_MAX_H          (1080)
#endif
#define CC_CONFIG_OSD_PLANE2_MEM_SIZE       (((CC_CONFIG_OSD_PLANE2_MAX_W*     \
                                            CC_CONFIG_OSD_PLANE2_MAX_H*        \
                                            CC_CONFIG_OSD_CM_SIZE*             \
                                            CC_CONFIG_OSD_BUF_MODE)+0x1000)&(0xFFFFF000))

#if (defined(CC_CONFIG_OSD_SBS_PLANE2)||defined(CC_CONFIG_OSD_TB_PLANE2))
#define CC_CONFIG_OSD_3D_PLANE2_MEM_SIZE    (CC_CONFIG_OSD_PLANE2_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE2_MEM_SIZE    (0)
#endif

#ifndef CONFIG_OSD_PLANE2_COMPRESSION
        //#define  CONFIG_OSD_PLANE2_COMPRESSION
#endif

        // osd decompress  buffer size
#ifdef CONFIG_OSD_PLANE2_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE2_MEM_SIZE   (CC_CONFIG_OSD_PLANE2_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE2_MEM_SIZE   (0)
#endif

#ifndef CC_CONFIG_OSD_PLANE3_MAX_W
#ifdef CC_C4TV_SUPPORT
#define CC_CONFIG_OSD_PLANE3_MAX_W          (1920)
#else
#define CC_CONFIG_OSD_PLANE3_MAX_W          (1920)
#endif
#endif
#ifndef CC_CONFIG_OSD_PLANE3_MAX_H
#ifdef CC_C4TV_SUPPORT
#define CC_CONFIG_OSD_PLANE3_MAX_H          (1080)
#else
#define CC_CONFIG_OSD_PLANE3_MAX_H          (1080)
#endif
#endif
#define CC_CONFIG_OSD_PLANE3_MEM_SIZE       (((CC_CONFIG_OSD_PLANE3_MAX_W*     \
                                            CC_CONFIG_OSD_PLANE3_MAX_H*        \
                                            CC_CONFIG_OSD_CM_SIZE*             \
                                            CC_CONFIG_OSD_BUF_MODE)+0x1000)&(0xFFFFF000))

#if (defined(CC_CONFIG_OSD_SBS_PLANE3)||defined(CC_CONFIG_OSD_TB_PLANE3))
#define CC_CONFIG_OSD_3D_PLANE3_MEM_SIZE    (CC_CONFIG_OSD_PLANE3_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE3_MEM_SIZE    (0)
#endif

        // osd decompress  buffer size
#ifndef CONFIG_OSD_PLANE3_COMPRESSION
        // #define  CONFIG_OSD_PLANE3_COMPRESSION
#endif

#ifdef CONFIG_OSD_PLANE3_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE3_MEM_SIZE   (CC_CONFIG_OSD_PLANE3_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE3_MEM_SIZE   (0)
#endif

#ifndef CC_CONFIG_OSD_PLANE4_MAX_W
#define CC_CONFIG_OSD_PLANE4_MAX_W          (0)
#endif
#ifndef CC_CONFIG_OSD_PLANE4_MAX_H
#define CC_CONFIG_OSD_PLANE4_MAX_H          (0)
#endif
#define CC_CONFIG_OSD_PLANE4_MEM_SIZE       (((CC_CONFIG_OSD_PLANE4_MAX_W*     \
                                            CC_CONFIG_OSD_PLANE4_MAX_H*        \
                                            CC_CONFIG_OSD_CM_SIZE*             \
                                            CC_CONFIG_OSD_BUF_MODE)+0x1000)&(0xFFFFF000))

#if (defined(CC_CONFIG_OSD_SBS_PLANE4)||defined(CC_CONFIG_OSD_TB_PLANE4))
#define CC_CONFIG_OSD_3D_PLANE4_MEM_SIZE    (CC_CONFIG_OSD_PLANE4_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE4_MEM_SIZE    (0)
#endif

        // osd decompress  buffer size
#ifdef CONFIG_OSD_PLANE4_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE4_MEM_SIZE   (CC_CONFIG_OSD_PLANE4_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE4_MEM_SIZE   (0)
#endif

#ifndef CC_CONFIG_OSD_PLANE5_MAX_W
#define CC_CONFIG_OSD_PLANE5_MAX_W          (100)
#endif
#ifndef CC_CONFIG_OSD_PLANE5_MAX_H
#define CC_CONFIG_OSD_PLANE5_MAX_H          (100)
#endif

#define CC_CONFIG_OSD_PLANE5_MEM_SIZE       (((CC_CONFIG_OSD_PLANE5_MAX_W*     \
                                    CC_CONFIG_OSD_PLANE5_MAX_H*        \
                                    CC_CONFIG_OSD_CM_SIZE)+0x1000)&(0xFFFFF000))

        // osd 3d buffer size
#if (defined(CC_CONFIG_OSD_SBS_PLANE5)||defined(CC_CONFIG_OSD_TB_PLANE5))
#define CC_CONFIG_OSD_3D_PLANE5_MEM_SIZE    (CC_CONFIG_OSD_PLANE5_MEM_SIZE)
#else
#define CC_CONFIG_OSD_3D_PLANE5_MEM_SIZE    (0)
#endif

        // osd decompress  buffer size
#ifdef CONFIG_OSD_PLANE5_COMPRESSION
#define CC_CONFIG_OSD_DEC_PLANE5_MEM_SIZE   (CC_CONFIG_OSD_PLANE5_MEM_SIZE)
#else
#define CC_CONFIG_OSD_DEC_PLANE5_MEM_SIZE   (0)
#endif

#define CC_CONFIG_OSD_PLANE_BASIC_MEM_SIZE  (CC_CONFIG_OSD_PLANE1_MEM_SIZE+ \
                                        CC_CONFIG_OSD_PLANE2_MEM_SIZE+  \
                                        CC_CONFIG_OSD_PLANE3_MEM_SIZE+  \
                                        CC_CONFIG_OSD_PLANE4_MEM_SIZE+  \
                                        CC_CONFIG_OSD_PLANE5_MEM_SIZE)

#define CC_CONFIG_OSD_3D_PLANE_MEM_SIZE     (CC_CONFIG_OSD_3D_PLANE1_MEM_SIZE+  \
                                            CC_CONFIG_OSD_3D_PLANE2_MEM_SIZE+   \
                                            CC_CONFIG_OSD_3D_PLANE3_MEM_SIZE+   \
                                            CC_CONFIG_OSD_3D_PLANE4_MEM_SIZE+   \
                                            CC_CONFIG_OSD_3D_PLANE5_MEM_SIZE)

#define CC_CONFIG_OSD_DEC_PLANE_MEM_SIZE    (CC_CONFIG_OSD_DEC_PLANE1_MEM_SIZE+ \
                                            CC_CONFIG_OSD_DEC_PLANE2_MEM_SIZE+  \
                                            CC_CONFIG_OSD_DEC_PLANE3_MEM_SIZE+  \
                                            CC_CONFIG_OSD_DEC_PLANE4_MEM_SIZE+  \
                                            CC_CONFIG_OSD_DEC_PLANE5_MEM_SIZE)

#define CC_CONFIG_GFX_TEMP_MEM_SIZE         (CC_CONFIG_OSD_PLANE3_MAX_W*    \
                                            CC_CONFIG_OSD_PLANE3_MAX_H*     \
                                            CC_CONFIG_OSD_CM_SIZE)

#ifdef CC_LINUX_GPU_SUPPORT_DFB
#define LINUX_GPU_BUFFER_SIZE            (8 * 1024 * 1024)
#else
#define LINUX_GPU_BUFFER_SIZE            (0 * 1024 * 1024)
#endif

#define DFB_SUM_MEM_SIZE                    (CC_CONFIG_OSD_PLANE_BASIC_MEM_SIZE+\
                                            CC_CONFIG_OSD_3D_PLANE_MEM_SIZE+    \
                                            CC_CONFIG_OSD_DEC_PLANE_MEM_SIZE+   \
											CC_CONFIG_GFX_TEMP_MEM_SIZE+		\
											LINUX_GPU_BUFFER_SIZE)
#endif

#ifdef ANDROID
    #ifdef CC_GFX_MMU
		#if defined(CC_FBM_DFB_IN_CHANNELC)
			#define DIRECT_FB_MEM_SIZE                  0
			#define FBM_MTDFB_SIZE 						((DFB_SUM_MEM_SIZE+4*1024)&(0xFFFFF000))
		#else
		#define DIRECT_FB_MEM_SIZE                    ((DFB_SUM_MEM_SIZE+4*1024)&(0xFFFFF000))
		#if !defined(CC_MERGE_INTO_ONE_OSD)
			#define DIRECT_FB_MEM_SIZE_FHD              (DIRECT_FB_MEM_SIZE)
			#define DIRECT_FB_MEM_SIZE_UHD              (DIRECT_FB_MEM_SIZE)
		#else
			#define DIRECT_FB_MEM_SIZE_FHD              (0x1800000)
			#define DIRECT_FB_MEM_SIZE_UHD              (0x1800000)
		#endif
		#endif
    #else
		#if defined(CC_FBM_DFB_IN_CHANNELC)
			#define DIRECT_FB_MEM_SIZE                  0
			#define FBM_MTDFB_SIZE 						(96 * 1024 * 1024)
		#else
        	#define DIRECT_FB_MEM_SIZE                  (96 * 1024 * 1024)
		#endif
    #endif

    #ifdef OSD_RESOLUTION_1080p
		#if 1 //def CC_SUPPORT_4K2K_UI
			#if defined(CC_FBM_FB_IN_CHANNELB)
		        #define FB_MEM_SIZE                         (0)
				#define FBM_MTFB_SIZE                       (120 * 1024 * 1024)
			#else
				#if !defined(CC_OSD3_M4U_IOVA_SUPPORT)
				#define FB_MEM_SIZE                         (144 * 1024 * 1024)
				#define FB_MEM_SIZE_UHD                     (144 * 1024 * 1024)
				#define FB_MEM_SIZE_FHD                     (48 * 1024 * 1024)
				#else
				#define FB_MEM_SIZE                         (96 * 1024 * 1024)
				#define FB_MEM_SIZE_UHD                     (96 * 1024 * 1024)
				#define FB_MEM_SIZE_FHD                     (32 * 1024 * 1024)
				#endif
			#endif
		#else
			#if defined(CC_FBM_FB_IN_CHANNELB)
		        #define FB_MEM_SIZE                         (0)
			#define FBM_MTFB_SIZE                       (48 * 1024 * 1024)
			#else
        	#define FB_MEM_SIZE                         (48 * 1024 * 1024)
			#endif
		#endif
    #else
		#if defined(CC_FBM_FB_IN_CHANNELB)
	        #define FB_MEM_SIZE                         (0)
			#define FBM_MTFB_SIZE                       (24 * 1024 * 1024)
		#else
        	#define FB_MEM_SIZE                         (24 * 1024 * 1024)
		#endif
    #endif
#else
	#ifdef CC_GFX_MMU
		#if defined(CC_LINUX_GPU_SUPPORT) && defined(CC_LINUX_GPU_SUPPORT_DFB)
			#if defined(CC_FBM_DFB_IN_CHANNELC)
			#define DIRECT_FB_MEM_SIZE					0
			#define FBM_MTDFB_SIZE						((DFB_SUM_MEM_SIZE+4*1024 + 32*1024*1024)&(0xFFFFF000))
			#else
			#define DIRECT_FB_MEM_SIZE					((DFB_SUM_MEM_SIZE+4*1024 + 32*1024*1024)&(0xFFFFF000))    /*openGL Base on DFB window need use DFB pool memory*/
			#endif
		#else
			#if defined(CC_FBM_DFB_IN_CHANNELC)
			#define DIRECT_FB_MEM_SIZE					0
			#define FBM_MTDFB_SIZE						((DFB_SUM_MEM_SIZE + 4*1024)&(0xFFFFF000))
			#else
			#define DIRECT_FB_MEM_SIZE					((DFB_SUM_MEM_SIZE + 4*1024)&(0xFFFFF000))
			#endif
		#endif

	#else
		#if defined(CC_FBM_DFB_IN_CHANNELC)
			#define DIRECT_FB_MEM_SIZE                  0
			#define FBM_MTDFB_SIZE 						(76 * 1024 * 1024)
		#else
        	#define DIRECT_FB_MEM_SIZE                  (76 * 1024 * 1024)
		#endif
    #endif

	#if defined(CC_LINUX_GPU_SUPPORT) && !defined(CC_LINUX_GPU_SUPPORT_DFB)
		#ifdef CC_C4TV_SUPPORT
			#ifndef CC_SUPPORT_CAST_1080P
				#if defined(CC_FBM_FB_IN_CHANNELB)
				#define FB_MEM_SIZE 						(0)
				#define FBM_MTFB_SIZE						(16 * 1024 * 1024)
				#else
				#define FB_MEM_SIZE 						(16 * 1024 * 1024)
				#endif
			#else
				#if defined(CC_FBM_FB_IN_CHANNELB)
				#define FB_MEM_SIZE 						(0)
				#define FBM_MTFB_SIZE						(24 * 1024 * 1024)
				#else
				#define FB_MEM_SIZE 						(24 * 1024 * 1024)
				#endif
			#endif
		#else
			#if defined(CC_FBM_FB_IN_CHANNELB)
			#define FB_MEM_SIZE 						(0)
			#define FBM_MTFB_SIZE						(20 * 1024 * 1024)
			#else
			#define FB_MEM_SIZE 						(20 * 1024 * 1024)
			#endif
		#endif
	#else
		#if defined(CC_FBM_FB_IN_CHANNELB)
		#define FB_MEM_SIZE 						(0)
		#define FBM_MTFB_SIZE						(40*1024*1024)
		#else
		#define FB_MEM_SIZE 						(40*1024*1024)
		#endif
	#endif

#endif

#ifndef FBM_MEM_CFG_SIZE
#ifdef  CC_FBM_CONFIG_WITH_3DTV_4K_SUPPORT
#define FBM_MEM_CFG_SIZE                        	(FBM_MEM_CFG_MT5895_3DTV)
#else
#define FBM_MEM_CFG_SIZE                            (FBM_MEM_CFG_MT5895_3DTV)
#endif
#endif /* FBM_MEM_CFG_SIZE */

#ifndef FBM_MEM_CHB_CFG_SIZE
	#ifdef  CC_FBM_CONFIG_WITH_3DTV_4K_SUPPORT
	//#define FBM_MEM_CHB_CFG_SIZE                        (FBM_MEM_CFG_MT5895_3DTV_CHB)
	#else
	//#define FBM_MEM_CHB_CFG_SIZE                        (FBM_MEM_CFG_MT5895_3DTV_CHB)
	#endif
#endif /* FBM_MEM_CHB_CFG_SIZE */

#ifndef FBM_MEM_CHC_CFG_SIZE
	#ifdef  CC_FBM_CONFIG_WITH_3DTV_4K_SUPPORT
	//#define FBM_MEM_CHC_CFG_SIZE                        (FBM_MEM_CFG_MT5895_3DTV_CHC)
	#else
	//#define FBM_MEM_CHC_CFG_SIZE                        (FBM_MEM_CFG_MT5895_3DTV_CHC)
	#endif
#endif /* FBM_MEM_CHC_CFG_SIZE */

#if defined(CC_SVP_SUPPORT) && defined(CC_SUPPORT_4K2K)
    #define VFIFO_MAIN   (35*1024*1024 + 35*1024*1024) // 4k(35M) + 4k(35M)
    #define VFIFO_SUB    0
    #define VFIFO_TOTAL VFIFO_SUB + VFIFO_MAIN
#else
    #define VFIFO_MAIN   (10*1024*1024)
    #define VFIFO_SUB    0
    #define VFIFO_TOTAL  VFIFO_SUB + VFIFO_MAIN
#endif

#if defined(CC_TRUSTZONE_64_SUPPORT)
#define TRUSTZONE_CODE_BASE                 (0x10000)
#define TRUSTZONE_CODE_BASE_BL32            (0x5000)
#define TRUSTZONE_MEM_SIZE                  ((20 * 1024 * 1024) + VFIFO_TOTAL)
#define TRUSTZONE_MEM_SIZE_BL32             (TRUSTZONE_MEM_SIZE-0x30000)

#elif defined(CC_TRUSTZONE_SUPPORT)
#define TRUSTZONE_CODE_BASE                 (0x5000)
#define TRUSTZONE_MEM_SIZE                  (20 * 1024 * 1024) + VFIFO_TOTAL

#else
#define TRUSTZONE_MEM_SIZE                  (0)
#endif

#if defined(CC_TRUSTZONE_IN_CHB)
#define TRUSTZONE_MEM_SIZE_CHA (0)
#else
#define TRUSTZONE_MEM_SIZE_CHA TRUSTZONE_MEM_SIZE
#endif

#ifdef CC_SUPPORT_MULTI_DRAM_COMBINATION
    #define DEFAULT_LINUX_KERNEL_MEM_SIZE       ((TOTAL_MEM_SIZE > (FBM_MEM_CFG_SIZE + DIRECT_FB_MEM_SIZE + FB_MEM_SIZE + TRUSTZONE_MEM_SIZE_CHA)) ?\
                                                (TOTAL_MEM_SIZE - FBM_MEM_CFG_SIZE - DIRECT_FB_MEM_SIZE - FB_MEM_SIZE - TRUSTZONE_MEM_SIZE_CHA) : (54 * 1024 * 1024))
#else
    #ifndef CONFIG_TV_DRV_VFY
        #define LINUX_KERNEL_MEM_SIZE           ((TOTAL_MEM_SIZE > (FBM_MEM_CFG_SIZE + DIRECT_FB_MEM_SIZE + FB_MEM_SIZE + TRUSTZONE_MEM_SIZE_CHA)) ?\
                                                (TOTAL_MEM_SIZE - FBM_MEM_CFG_SIZE - DIRECT_FB_MEM_SIZE - FB_MEM_SIZE - TRUSTZONE_MEM_SIZE_CHA) : (54 * 1024 * 1024))
    #else
        #define LINUX_MM_VFY_RESERVE_SIZE       (512*1024*1024)
        #define LINUX_KERNEL_MEM_SIZE           (TOTAL_MEM_SIZE - LINUX_MM_VFY_RESERVE_SIZE)
    #endif
#endif

#define DEFAULT_TARGET_COUNTRY              (COUNTRY_EU)  

//----------------------------------------------------------------------------
// Default Panel setting
//----------------------------------------------------------------------------
#ifndef DEFAULT_PANEL_SELECT
#define DEFAULT_PANEL_SELECT                (PANEL_DEFAULT)
#endif

#define BACKLIGHT_GPIO                      (GPIO(66))
#define BACKLIGHT_ON_VAL                    (1) // ((((DRVCUST_Get_Series()+2014) >= 2018) && (DRVCUST_Get_TrialLv() < 0x03)) ? 0 : 1)

#ifdef CC_COMBINE_4K_2K
#define PANELPOWER_GPIO_2K                  (GPIO(116))
#define PANELPOWER_GPIO_4K_NO_BE            (GPIO(116))
#define PANELPOWER_GPIO_4K                  (0xFFFFFFFF)
#define PANELPOWER_ON_VAL                   (1)
#else
#ifdef CC_4K_MODEL
#define PANELPOWER_GPIO                     (0xFFFFFFFF)
#define PANELPOWER_ON_VAL                   (0)
#else
#define PANELPOWER_GPIO                     (GPIO(116))
#define PANELPOWER_ON_VAL                   (1)
#endif
#endif

#define PANELPOWER_1_GPIO                   (GPIO(116)) //SD_D2
#define PANELPOWER_1_ON_VAL                 (1)
#define PANELPOWER_2_GPIO                   (GPIO(66))   // For OLED mode, other is for backlight
#define PANELPOWER_2_ON_VAL                 (1)

// disable spread spectrum for vga output
#define SPREAD_SPECTRUM_PERMILLAGE          (0)

// pwm backlight adjustment setting
#define PANEL_BACKLIGHT_PWM_PORT            (1)

//3D Enable & LR GPIO
//#define EXT_3D_ENABLE_PORT                  (GPIO(52))
//#define EXT_3D_LR_PIN                      (PIN_GPIO53)
//#define EXT_3D_LR_PIN_FUNC                    (1)

// VB1 lockn & htpdn [Sony]
#define PANEL_VB1_LOCKN_PIN          (PIN_GPIO50)
#define PANEL_VB1_LOCKN_PIN_FUNC     (2)
#define PANEL_VB1_HTPDN_PIN          (PIN_ALIN)    //no connect from BE to M3M5, but M3M5 side directly connect to GND
#define PANEL_VB1_HTPDN_PIN_FUNC     (5)
#define PANEL_VB1_OSD_LOCKN_PIN      (PIN_GPIO54)
#define PANEL_VB1_OSD_LOCKN_PIN_FUNC (2)
#define PANEL_VB1_OSD_HTPDN_PIN      (0x0)//(PIN_GPIO53)  // no conect from BE to M3M5
#define PANEL_VB1_OSD_HTPDN_PIN_FUNC (5)

#define PDWNC_POLARITY                      (0)
#define SYS_RESET_TIMER                     324000
//----------------------------------------------------------------------------
// Suspend power control GPIO Number, it must be PDWNC GPIO
//----------------------------------------------------------------------------
#define  SUSPEND_GPIO_NUMBER   0xffffffff        //suspend , dram power control GPIO.
#define  SUSPEND_WOL_GPIO      (GPIO(219)) //    actually it is ether power enble pin
#define  SUSPEND_WOWL_GPIO     (GPIO(217))  // WIFI power control , it is shared with dram power control. But only one will enable by HW mount
/*
 *  ENABLE WOW for WiFi
*/
#ifdef WIFI_WOWLAN_SUPPORT
#define WAKEUP_ON_WLAN_GPIO 	(218) // OPCTRL(18)
#define WAKEUP_ON_WLAN_POL 	(0)
#endif

#define WAKEUP_ON_BT_ENB_FUNC   CustomGetBTWakeupEnable
#define WAKEUP_ON_BT_GPIO       (210)
#define WAKEUP_ON_BT_POL          (0)

#define MODEL_4K2K_GPIO          (72)  // actually no one use it now . 20190221

//----------------------------------------------------------------------------
// Loader logo 
//----------------------------------------------------------------------------
//#ifdef CC_LOADER_LOGO_SUPPORT
#ifdef CC_UPGRADING_DYNAMIC_LOGO_SUPPORT
#define LOADER_LOGO_NUMBER                  (5)
#else
#define LOADER_LOGO_NUMBER                  (1)
#endif
#define LOADER_LOGO_H_FILE                  "sony/valhalla_drv/sony_logo.h"
//#endif

//----------------------------------------------------------------------------
// Audio Customization
//----------------------------------------------------------------------------
#define AUDIO_INCLUDE_FILE                  "sony/Mustang_aud.h"

#ifdef CC_COMBINE_4K_2K
#define AUDIO_Mute_Gpio_Num_2K              (GPIO(52))       //headphone mute
#define AUDIO_Mute_Gpio_Num_4K              (GPIO(52))
#define AUDIO_Amp_Gpio_Num_4K               (GPIO(117))      // sd_d3 Speaker mute
#define AUDIO_Amp_Gpio_Num_2K               (GPIO(117))
#else
#ifdef CC_4K_MODEL
#define AUDIO_Mute_Gpio_Num                 (GPIO(52))
#define AUDIO_Amp_Gpio_Num                  (GPIO(117))
#else
#define AUDIO_Mute_Gpio_Num                 (GPIO(52))
#define AUDIO_Amp_Gpio_Num                  (GPIO(117))
#endif
#endif//CC_COMBINE_4K_2K

#define AUDIO_HP_PLUG_IN_GPIO                   (GPIO(115))
#define AUDIO_HP_PLUG_IN_POLARITY               (AUD_GPIO_HIGH_ENALBE)

#define AUDIO_MUTE_GPIO_POLARITY                AUD_MUTE_GPIO_LOW_ENALBE
#define AUDIO_AMP_GPIO_POLARITY                 AUD_AMP_GPIO_HIGH_ENALBE

#define AUDIO_DIGITAL_AMP_RESET_GPIO            (GPIO(114))
#define AUDIO_DIGITAL_AMP_RESET_GPIO_POLARITY   AUD_AMP_GPIO_HIGH_ENALBE

#define AUDIO_SCART_Gpio_Num                    (0xffffffff)
#define AUDIO_SCART_GPIO_POLARITY               AUD_GPIO_LOW_ENALBE

#define AUDIO_AL1AR1_PHASE_INVERSE              (TRUE)
#define AUDIO_AL2AR2_PHASE_INVERSE              (TRUE)
#define AUDIO_AL3AR3_PHASE_INVERSE              (TRUE)

#define AUDIO_INPUT_MUX_SEL_TABLE               (&_rMustangAudInputMuxTable)
#define AUDIO_IEC_WORD_LENGTH                   (&_au1SakuraAudIecWordLength)
#define AUDIO_IEC_CATEGORY                      (&_au1UroborosEuAudIecCategory)
#define AUDIO_APROC_ENABLE                      (FALSE)
#define AUDIO_DOWNMIX_CHANNEL_POSITION          (DOWNMIX_CH_BEFORE_AVC)
#define AUDIO_HEAAC_MULTICHL_DDCO               (FALSE)
#define AUDIO_ADAC_USAGE                        (&_arSakuraAdacUsage)  //Fix Audio delay cause performance bad issue.

#define AUDIO_MTS_FACTORY_MODE                  (&_arSonyMtsFactory)
#define AUDIO_A2_FACTORY_MODE                   (&_arSonyA2Factory)
#define AUDIO_PAL_FACTORY_MODE                  (&_arSonyPalFactory)
#define AUD_FLASH_AQ_FILE                       "sony/sakura_aud_flash_aq.c" //CC_AUD_AQ_IN_DRVCUST
#define AUD_AMP_EXT_IMPL_FILE                   "sony/aud_cust_amp_if.c"

#define VAD_DMIC_PWR_ON_GPIO                    (GPIO(213))
#define VAD_DMIC_PWR_ON_POLARITY               (AUD_GPIO_HIGH_ENALBE)

#define VAD_DMIC_PDM0_DATA0_PIN                 PIN_OPCTRL4
#define VAD_DMIC_PDM_CLK                        PIN_OPCTRL6
#define VAD_DMIC_PDM1_DATA0_PIN                 PIN_OPCTRL7

#define VAD_I2S_BCK_PIN                         PIN_OPWM0
#define VAD_I2S_LRCK_PIN                        PIN_OPWM1
#define VAD_I2S_SDATA_PIN                       PIN_OPWM2

//----------------------------------------------------------------------------
// Other GPIO customization
#define DEFAULT_TUNER_RFAGC_SWITCH_GPIO         (0xFFFFFFFF)
//#define DEFAULT_DEMOD_RESET_GPIO            (GPIO(82))
#define DEFAULT_DEMOD_RESET_GPIO            (GPIO(224))   // OPCTRL24
#define DEFAULT_DEMOD_RESET_GPIO_2          (GPIO(226))   // U2RX
#define DEFAULT_DEMOD_EWS_PWR_ON_GPIO       (GPIO(220))   // OPTCTRL20
#define WAKEUP_ON_PH_EWBS_GPIO              (GPIO(223))   // Change to OPCRTL23 due to U2TX not support wakeup
#define WAKEUP_ON_PH_EWBS_POL               (1)           //H detect the TMCC signal

//Tuner I2C channel ID
#ifndef DEFAULT_TUNER_I2C_BUS_ID
#define DEFAULT_TUNER_I2C_BUS_ID  5 //M5 use OPCTRL2 & 3
#endif

//Demod I2C channel ID
#ifndef DEFAULT_DEMOD_I2C_BUS_ID
#define DEFAULT_DEMOD_I2C_BUS_ID  5 //M5 use OPCTRL2 & 3
#endif

//----------------------------------------------------------------------------
#define FLAG_EXT_STATUS                     (0)

//----------------------------------------------------------------------------
// EEPROM customization
//----------------------------------------------------------------------------
#if (defined(REPLACE_EEPROM_WITH_EMMC)||defined(REPLACE_EEPROM_WITH_FLASH))
#define SYSTEM_EEPROM_SIZE                  (307200)
#else
#define SYSTEM_EEPROM_SIZE                  (4096)
#endif
//#define SYSTEM_EEPROM_WP_GPIO               (GPIO(46)) // OPCTRL9.
//#define SYSTEM_EEPROM_WP_ENABLE_POLARITY    (1)
#ifdef CC_EEP2EMMC_DUAL_BANK_SUPPORT
#define SYSTEM_EEPROM_INIT_HEADER_SIZE      (102400)
#define SYSTEM_EEPROM_HEADER_SIZE           (307200)
#endif

//eeprom layout for MTK use
#ifdef CC_ENABLE_REBOOT_REASON
#ifndef DRVCUST_EEPROM_ANDROID_OTA_SIZE
#define DRVCUST_EEPROM_ANDROID_OTA_SIZE     ((UINT32)16)
#endif

#ifndef DRVCUST_EEPROM_ANDROID_OTA_OFFSET
#define DRVCUST_EEPROM_ANDROID_OTA_OFFSET   ((UINT32)0x800)
#endif
#endif

#define DRVCUST_EEPROM_EXTEND_OFFSET		((UINT32)0x4000)
#define DRVCUST_EEPROM_EXTEND_SIZE			((UINT32)1024)

#define DRVCUST_EEPROM_EMMC_USB_RECOVERY_OFFSET ((UINT32)0x7BE)   /*1 byte only, in APP space */

#define DRVCUST_EEPROM_AUTOTEST_UPGRADED_PKG_OFFSET  ((UINT32)0x7BD)   /*1 byte only, in APP space, applied when AUTO_TEST=true */

#include            "sony/Sakura_eeprom_layout.h"   //!!!!this stage do not change this layout!!!!!!

//----------------------------------------------------------------------------
// European CI (Common Interface) customization
//----------------------------------------------------------------------------
//#define CI_EXTERNAL_IC_INT_GPIO             (GPIO(84))  // Set:Interrupt Mode, UnSet:Polling Mode
#define CI_5V_OC_GPIO                       (GPIO(42))
#define CI_5V_POWERON_GPIO                  (GPIO(48))
#define CI_5V_POWERON_POLARITY              (1)
#define CI_5V_OC_POLARITY                   (0)
#define CI_EXTERNAL_IC_DRIVING_CURRENT      (2)         // 2mA
#define CI_SYSTEM_CLOCK                     (72)        // 72 MHz
#define CI_TS_CLOCK                         (108)       // 108 MHz
#define CI_SPI_CLOCK                        (27)        // 72 MHz
//----------------------------------------------------------------------------
// USB Customization
//----------------------------------------------------------------------------
// "USBx_PORT_USING_LOADER & USBx_PORT_USING" related define is only for USB2.0 port
// 1. Loader, USB port using define (1)=used (0)=not used
#define USB0_PORT_USING_LOADER              (1)
#define USB1_PORT_USING_LOADER              (1)
#define USB2_PORT_USING_LOADER              (0)
#define USB3_PORT_USING_LOADER              (0)

// 2. Nuclues/Linux/Android System USB port using define (1)=used (0)=not used
#define USB0_PORT_USING                     (1)
#define USB1_PORT_USING                     (1) 
#define USB2_PORT_USING                     (1) 
#define USB3_PORT_USING                     (1)

// 3. USB +5V power switch Vbus GPIO control, if vbus not control by GPIO, mark off it.
#define USB0_VBUS_GPIO                      (GPIO(45))    // for M5 proto board 
#define USB0_VBUS_GPIO_POLARITY		        (1)
#define USB1_VBUS_GPIO                      (GPIO(43))   // GPIO43
#define USB1_VBUS_GPIO_POLARITY		        (1)
#define USB2_VBUS_GPIO                      (GPIO(44) )   // GPIO44
#define USB2_VBUS_GPIO_POLARITY		        (1)
//#define USB3_VBUS_GPIO                      OPCTRL(10)  // OPCTRL10.
//#define USB3_VBUS_GPIO_POLARITY		        (1)

// 4. USB power switch overcurrent GPIO control, if have not ic to control by GPIO, mark off it.
#define USB0_OC_GPIO                        GPIO(46)   // for proto board 
#define USB0_OC_GPIO_POLARITY		        (0)
#define USB1_OC_GPIO                        GPIO(58)
#define USB1_OC_GPIO_POLARITY		        (0)
#define USB2_OC_GPIO                        GPIO(61)
#define USB2_OC_GPIO_POLARITY		        (0)
//#define USB3_OC_GPIO                        ADIN(5)     // ADIN 5.
//#define USB3_OC_GPIO_POLARITY		        (0)

// 5. Detect USB upgrade time, default is 0, but some device maybe can't detect when upgrade.
// If possible, set it to (300)ms when in customer's module.
#ifdef CC_MTK_AUTO_TEST
#define USB_LOADER_WAIT_TIME                (3000)
#else
#define USB_LOADER_WAIT_TIME                (1000)
#endif

// 6.delay resume support
#define USB0_DELAY_RESUME_USING             (0)
#define USB1_DELAY_RESUME_USING             (0)
#define USB2_DELAY_RESUME_USING             (0)
#define USB3_DELAY_RESUME_USING             (0)

//#define USB_DISABLE_SUSPEND_MODE /* Disable USB suspend, share 240 Mhz with H.264.*/
//----------------------------------------------------------------------------
// Button Customization
//----------------------------------------------------------------------------
#define FLAG_BUTTON_SUPPORT                 (1)
#define BUTTON_INCLUDE_FILE                 "sony/maple_button.h"

#ifndef KEYPAD_POLLING_TIME
#define KEYPAD_POLLING_TIME         (20)
#endif
#ifndef KEYPAD_CHECK_TIME
#define KEYPAD_CHECK_TIME           (2)
#endif

#ifndef T8032UP_INCLUDE_FILE
#ifdef CC_MAPLE_IR_DRV
#ifdef CC_IR_AUTO_EMIT_SUPPORT
#define T8032UP_INCLUDE_FILE                "sony/valhalla_drv/valhalla_t8032fw_ir.h"
#else
#define T8032UP_INCLUDE_FILE                "sony/valhalla_drv/valhalla_t8032fw.h"
#endif
#define T8032UP_OFFSET                      au1T8032FW
//#define T8032UP_SIZE                                      26750//24576//16384
#define T8032UP_SIZE                        T8032FW_SIZE 
#else
#define T8032UP_INCLUDE_FILE                "mediatek/mtk_t8032fw.h"
#define T8032UP_OFFSET                      au1T8032FW
#define T8032UP_SIZE                        24576//16384
#endif
#endif

//----------------------------------------------------------------------------
// MTK IR only setting
//----------------------------------------------------------------------------
//#define IR_INCLUDE_FILE                     "mediatek/mtk_ir.h"
#ifdef CC_MAPLE_IR_DRV
#define IR_INCLUDE_FILE                     "sony/valhalla_drv/sirc_ir.h"
#else
#define IR_INCLUDE_FILE                     "sony/mtk_ir_SONY_IPTV.h"
#endif
#define IRRX_LED_BLINK_DURATION               (50)

#ifndef NPTV_SOURCE_TABLE
#define NPTV_SOURCE_TABLE                   "sony/source_table_sony.c"
#endif

#define SCART1_FB_IN_SELECT                 SCART_FB_IN_SOY0
//----------------------------------------------------------------------------
// default HDMI GPIO control
//----------------------------------------------------------------------------
#ifndef HDMI_GPIO_CONF
#ifdef CC_HDMI_USE_DEMO_BOARD
#define HDMI_GPIO_CONF                      "mediatek/hdmi_conf.c"
#else
#define HDMI_GPIO_CONF                      "sony/hdmi_conf_mtk.c"
#endif
#endif

#ifndef HDMI_INCLUDE_FILE
#define HDMI_INCLUDE_FILE               "sony/uroboros_hdmi.h"
#endif

/*
 * default VGA table
*/
#ifndef VGA_INCLUDE_FILE
#define VGA_INCLUDE_FILE                    "sony/sony_vga.h"
#endif

#ifndef EDID_INCLUDE_FILE
#ifdef CC_SONY_EDID_ADD_ON
#define EDID_INCLUDE_FILE                "sony/valhalla_edid/sony_ext_edid.h"
#else
#define EDID_INCLUDE_FILE                "sony/sony_edid.h"
#endif
#endif


//----------------------------------------------------------------------------
// Tcon Customization
//----------------------------------------------------------------------------
// support LVDS and MLVDS both
#define PANEL_DISPLAY_TYPE_ALLOWED_MASK ((1<<PANEL_DISPLAY_TYPE_LVDS) | (1 << PANEL_DISPLAY_TYPE_MLVDS) | (1 << PANEL_DISPLAY_TYPE_EPI) | (1 << PANEL_DISPLAY_TYPE_VB1))

#ifndef TCON_CUST_FILE
#define TCON_CUST_FILE                      "mediatek/Husky_tcon_cust.c"
#endif
#define SUPPORT_LOCK_FROM_SRVAD 

//----------------------------------------------------------------------------
// BE configuration
//----------------------------------------------------------------------------
#ifdef CC_MAPLE_BE_LOADER_BOOT_FLOW
#ifndef BE_CTRL_INCLUDE_FILE
#define BE_CTRL_INCLUDE_FILE                    "sony/valhalla_drv/valhalla_be_ctrl.h"
#endif
#endif

//----------------------------------------------------------------------------
// default PIN Setup
//----------------------------------------------------------------------------
#ifndef PINMUX_INCLUDE_FILE
#define PINMUX_INCLUDE_FILE                 "sony/valhalla_drv/valhalla_pin_setup.h"
#endif

//----------------------------------------------------------------------------
// SCART out configuration
//----------------------------------------------------------------------------
#ifndef TVE_INCLUDE_FILE
#define TVE_INCLUDE_FILE                    "mediatek/mtk_tve.c"
#endif

//----------------------------------------------------------------------------
// DMX configuration
//----------------------------------------------------------------------------
#ifndef DMX_INCLUDE_FILE
#define DMX_INCLUDE_FILE                    "sony/uroboros_dvb_dual_dmx.h"
#endif

//----------------------------------------------------------------------------
// Loader configuration
//----------------------------------------------------------------------------
#if defined(LINUX_TURNKEY_SOLUTION) || defined(__KERNEL__)
//----------------------------------------------------------------------------
// Flash Partition configuration
#define MAX_UPGRADE_IMAGE_FILE_SIZE     ((UINT64)4*1024*1024*1024)
#define PART_LOADER_SIZE                ((UINT64)4*1024*1024)
//----------------------------------------------------------------------------
#define NAND_INCLUDE_FILE                   "sony/Sakura_flash_layout.h"

//EDID
#ifndef CC_DUALLOADER_SUPPORT
#define HDMI2_EDID_STANDARD_PART_ID  (19)
#else
#define HDMI2_EDID_STANDARD_PART_ID  (15)
#endif

//HDCP
#ifndef CC_DUALLOADER_SUPPORT
#define HDCP2X_NAND_FLASH_PART_ID (25)
#define FLASH_HDCP14_BIN_PARTITION (15)
#define FLASH_HDCP_BIN_PARTITION (25)
#define FLASH_HDMI_1_4_HDCP1_4_KEY_OFFSET (0)
#define FLASH_HDMI_2_0_HDCP2_2_KEY_OFFSET   (0x800)
#else
#define HDCP2X_NAND_FLASH_PART_ID (4)
#define FLASH_HDCP14_BIN_PARTITION (4)
#define FLASH_HDCP_BIN_PARTITION (4)
#define FLASH_HDMI_1_4_HDCP1_4_KEY_OFFSET (0)
#define FLASH_HDMI_2_0_HDCP2_2_KEY_OFFSET   (0x800)
#endif
#endif //defined(LINUX_TURNKEY_SOLUTION) || defined(__KERNEL__)

#if defined(LINUX_TURNKEY_SOLUTION) || defined(__KERNEL__)
#ifdef CC_FBM_MAPPING_ONE_BY_ONE
#ifndef FBM_BOOT_MMAP_INCLUDE_FILE
#define FBM_BOOT_MMAP_INCLUDE_FILE           "sony/sony_fbm_mmap.h"
#endif
#endif
#endif

#ifdef CC_SAKURA_CUST_DRV
#define GPIO_INCLUDE_FILE                       "sony/valhalla_drv/valhalla_gpio.h"
#define PDWNC_EXT_IMPL                          "sony/valhalla_drv/valhalla_pdwnc.h"
#endif

/*
 * default quality table
*/
#ifndef QTYTBL_INCLUDE_FILE
//#define QTYTBL_INCLUDE_FILE               "mediatek/QTY_DEFAULT/mtk_QtyTbl.h"
#endif

/*
 * default color parameter
*/
#ifndef COLOR_PARAM_INCLUDE_FILE
//#define COLOR_PARAM_INCLUDE_FILE          "mediatek/PANEL_DEFAULT/color_param.h"
#endif

/*
 * dynamic backlight parameter
*/

//----------------------------------------------------------------------------
// D-interface Customization
//----------------------------------------------------------------------------
#ifdef CC_SAKURA_CUST_DRV
#ifndef DRV_CUSTOM_CUST_FILE
#define DRV_CUSTOM_CUST_FILE                    "sony/maple_d_custom.c"
#endif

#ifndef DRV_CUSTOM_CUST_SPEC_SET
#define DRV_CUSTOM_CUST_SPEC_SET                d_maple_cust_spec_set
#endif

#ifndef DRV_CUSTOM_CUST_SPEC_GET
#define DRV_CUSTOM_CUST_SPEC_GET                d_maple_cust_spec_get
#endif
#endif

#ifdef CC_SAKURA_CUST_DRV
#ifndef CUSTOM_VIDEO_DRV_BODY_FILE
#define CUSTOM_VIDEO_DRV_BODY_FILE              "sony/maple_video_drv.c"
#endif

#ifndef CUSTOM_BACKLIGHT_DRV_BODY_FILE
#define CUSTOM_BACKLIGHT_DRV_BODY_FILE          "sony/maple_backlight_drv.c"
#endif
#endif

/*
 * default quality table
*/

#ifdef CC_MAPLE_CUST_DRV
#ifndef QTYTBL_INCLUDE_FILE
#define QTYTBL_INCLUDE_FILE               "sony/QTY_drv_Sony_mt5895_linux/mtk_QtyTbl.h"
#endif
#endif


/*
 * default color parameter
*/

#ifdef CC_MAPLE_CUST_DRV
#ifndef COLOR_PARAM_INCLUDE_FILE
#define COLOR_PARAM_INCLUDE_FILE          "sony/PANEL_DEFAULT/color_param.h"
#endif
#endif

#define SUPPORT_OD                          (0)

//For internal Demod use
#ifndef SIF_ENABLE_PDWNC_MASTER
#define SIF_ENABLE_PDWNC_MASTER      (1)
#endif

#ifndef SIF_ENABLE_PDWNC_MASTER1
#define SIF_ENABLE_PDWNC_MASTER1      (1)
#endif

//#define SIF_ENABLE_SCL_STRETCH        (1)

//----------------------------------------------------------------------------
// SCART Pin8 Threshold Servo ADC Customization
//----------------------------------------------------------------------------
#ifndef SCART_PIN8_LOW_THRES
#define SCART_PIN8_LOW_THRES (11)
#endif

#ifndef SCART_PIN8_HI_THRES
#define SCART_PIN8_HI_THRES (31)
#endif

//----------------------------------------------------------------------------
// I2C Customization
//----------------------------------------------------------------------------
#ifndef DRV_CUST_FIXED_SIF_CLK_DIV
#define DRV_CUST_FIXED_SIF_CLK_DIV (0x48)
#endif

/* Flash Panel Table */
#ifdef CC_PANEL_FROM_FLASH
#ifndef LOAD_PANEL_FROM_FLASH_CUSTOM
#define LOAD_PANEL_FROM_FLASH_CUSTOM        CustomPanelLoadTableFromFlash
#define DUMP_PANEL_LIST_FROM_FLASH_CUSTOM   CustomDumpPanelListFromFlash
#define PANEL_VERSION_LENGTH                16
#endif
#define PANEL_FLASH_HEADER_ADDRESS          (0)
#define PANEL_FLASH_HEADER_LENGTH           (32)
#define PANEL_FLASH_TABLE_SIZE              (1056)//(180)
#ifndef CC_DUALLOADER_SUPPORT
#define PANEL_FLASH_TABLE_BASE_PARTITION    (17)
#else
#define PANEL_FLASH_TABLE_BASE_PARTITION    (5)
#endif
#define PANEL_FLASH_TABLE_ADDRESS           (32)
#endif

#ifdef CC_MAPLE_CUST_DRV
#ifdef CC_MAPLE_LOADER_UPGRADE_VERSION_CTRL_FLOW
//#define USB_UPGRADE_FILE_NAME           ("upgrade_sony_fw_2015_1000_eua.pkg")
//#define USB_UPGRADE_FILE_NAME_PREFIX    ("upgrade_sony_fw_2015_")
//#define USB_UPGRADE_FILE_NAME_SUFFIX    (".pkg")
#endif
#define SDCARD_UPGRADE_SUPPORT_FLAG     (1)
#ifndef CC_DUALLOADER_SUPPORT
#define SDCARD_UPGRADE_PART_OFFSET      (NAND_PART_OFFSET_40)
#else
#define SDCARD_UPGRADE_PART_OFFSET      (NAND_PART_OFFSET_48)
#endif
#endif
#ifdef CC_LDR_ATOMIC_MODE_SUPPORT
#ifndef LDR_ATOMIC_UPG_FILE_NAME
#define LDR_ATOMIC_UPG_FILE_NAME       ("factory_shipsetting.pkg")
#endif
#ifndef LDR_ATOMIC_UPG_FILE_NAME_PREFIX
#define LDR_ATOMIC_UPG_FILE_NAME_PREFIX    ("factory_shipsetting")
#endif
#ifndef LDR_ATOMIC_UPG_FILE_NAME_SUFFIX
#define LDR_ATOMIC_UPG_FILE_NAME_SUFFIX    (".pkg")
#endif
#endif

#define CUSTOMIZE_FLASHPQ_TOTAL_TIMING (31)

#ifndef UBOOT_ENV_OFFSET
#ifndef CC_DUALLOADER_SUPPORT
#define UBOOT_ENV_OFFSET                (NAND_FLASH_LOADER_SIZE)
#else
// Uboot ENV start address at flash.
#define UBOOT_ENV_OFFSET                ((4+8+1+8+1+1+1+96+4+4+1)*1024*1024)
#endif
#endif

#ifndef CC_DUALLOADER_SUPPORT
#define HDCP_NAND_FLASH_PART_ID             (15)
#define HDCP_NAND_FLASH_OFFSET              (0)
#else
#define HDCP_NAND_FLASH_PART_ID             (4)
#define HDCP_NAND_FLASH_OFFSET              (0)
#endif

// for CPU temperature settings
#define THERMAL_REBOOT_TEMP     113000  // 113 degree-C
#define THERMAL_TRIGGER_HOT     107000  // 107 degree-C
#define THERMAL_TRIGGER_HOT2NOR  90000  //  90 degree-C
#define THERMAL_TRIGGER_COLD2NOR 85000  //  85 degree-C
#define THERMAL_TRIGGER_COLD     70000  //  70 degree-C


#define THERMAL_CPUFREQ_HOT          (1200000)
#define THERMAL_CPUFREQ_NOR          (1596000)
#define THERMAL_CPUFREQ_COLD         (1800000)

//AUD I2S PAD TABLE
#define AUDIO_AOUT_PAD_CFG              (&_arSonyAoutPadTable)

//AAC dialnorm
#define HEAAC_DEFAULT_DIALORM           (&_arSonyEuHeaacDefaultDialnormTable)

#ifdef CC_AOS_PMIC
//for PMIC S
#ifdef CC_CUSTOM_PMIC_I2C_SUPPORT
#ifndef SIF_ENABLE_PDWNC_MASTER1
#define SIF_ENABLE_PDWNC_MASTER1      (1)
#endif
#define PMIC_VCPU_DEVICE_ADDR    (0x6e)
#define PMIC_VCPU_DATA_ADDR      (0x00)
#define PMIC_VCPU_MODE_ADDR      (0x01)
#define PMIC_VCPU_MODE_MASK      (0x08)
#define PMIC_VCPU_MODE_PWM_EN    (1)
#define PMIC_VCPU_VMIN           (700) //unit: mV
#define PMIC_VCPU_VMAX           (925)//unit: mV
#define PMIC_VCPU_VSTEP          (729)//unit: 10uV
#define PMIC_VCPU_CHANNEL_ID     (3)
#define PMIC_VGPU_DEVICE_ADDR    (0x6a)
#define PMIC_VGPU_DATA_ADDR      (0x00)
#define PMIC_VGPU_MODE_ADDR      (0x01)
#define PMIC_VGPU_MODE_MASK      (0x08)
#define PMIC_VGPU_MODE_PWM_EN    (1)
#define PMIC_VGPU_VMIN           (700) //unit: mV
#define PMIC_VGPU_VMAX           (925)//unit: mV
#define PMIC_VGPU_VSTEP          (729)//unit: 10uV
#define PMIC_VGPU_CHANNEL_ID     (3)
#endif

#else
//for PMIC M
#ifdef CC_CUSTOM_PMIC_I2C_SUPPORT
#ifndef SIF_ENABLE_PDWNC_MASTER1
#define SIF_ENABLE_PDWNC_MASTER1      (1)
#endif
#define PMIC_VCPU_DEVICE_ADDR    (0xc6)
#define PMIC_VCPU_DATA_ADDR      (0x02)
#define PMIC_VCPU_MODE_ADDR      (0x03)
#define PMIC_VCPU_MODE_MASK      (0x04)
#define PMIC_VCPU_MODE_PWM_EN    (1)
#define PMIC_VCPU_VMIN           (600) //unit: mV
#define PMIC_VCPU_VMAX           (1500)//unit: mV
#define PMIC_VCPU_VSTEP          (1000)//unit: 10uV
#define PMIC_VCPU_CHANNEL_ID     (3)
#define PMIC_VGPU_DEVICE_ADDR    (0xc8)
#define PMIC_VGPU_DATA_ADDR      (0x05)
#define PMIC_VGPU_MODE_ADDR      (0x06)
#define PMIC_VGPU_MODE_MASK      (0x10)
#define PMIC_VGPU_MODE_PWM_EN    (1)
#define PMIC_VGPU_VMIN           (700) //unit: mV
#define PMIC_VGPU_VMAX           (1500)//unit: mV
#define PMIC_VGPU_VSTEP          (1000)//unit: 10uV
#define PMIC_VGPU_CHANNEL_ID     (3)
#endif

#endif

#define DRAM_RESET_BY_EXT_GPIO (209)
//this config only need for capy es1 dram reset workaround 


#else /* CONFIG_DEFAULT_H */
#error "Cannot include multi-config files"
#endif /* CONFIG_DEFAULT_H */

