/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


/*-----------------------------------------------------------------------------
 * Copyright (c) 2005, MediaTek, Inc.
 * All rights reserved.
 *
 * Unauthorized use, practice, perform, copy, distribution, reproduction,
 * or disclosure of this information in whole or in part is prohibited.
 *-----------------------------------------------------------------------------
 *
 * $Author: binghe.li $
 * $Date: 2016/05/12 $
 * $RCSfile: drv_mjc_sys.h $
 * $Revision: #4 $
 *
 *----------------------------------------------------------------------------*/

#ifndef _DRV_MJC_SYS_H_
#define _DRV_MJC_SYS_H_

/*----------------------------------------------------------------------------*
 * Header Files
*----------------------------------------------------------------------------*/
#include "drv_mjc_hw.h"
#include "typedef.h"

/*====================End  Header Files ============================*/

/*----------------------------------------------------------------------------*
 * Definitions 
 *----------------------------------------------------------------------------*/
//#define MJC_FPGA_V7_ARM11_TEST                    (0)
#define MJC_REG_TBL_END 0xffffffff
#define MJC_BUFFER_NUM     9 //CMQ using total buffer numbers


// mjc align

#define MJC_ALIGN_MASK(VAL, MSK) (((VAL) + (MSK)) & (~(MSK)))
#define MJC_ALIGN_64BYTE(val) (((val) + 0x0000003f) & (~0x0000003f))
#define MJC_ALIGN_256_CEIL(val) ALIGN_MASK((val), 255)
#define MJC_ALIGN_128_CEIL(val) ALIGN_MASK((val), 127)
#define MJC_ALIGN_64_CEIL(val) ALIGN_MASK((val), 63)
#define MJC_ALIGN_32_CEIL(val) ALIGN_MASK((val), 31)
#define MJC_ALIGN_16_CEIL(val) ALIGN_MASK((val), 15)
#define MJC_ALIGN_8_CEIL(val) ALIGN_MASK((val), 7)
#define MJC_ALIGN_4_CEIL(val) ALIGN_MASK((val), 3)
#define MJC_ALIGN_2_CEIL(val) ALIGN_MASK((val), 1)

#define MJC_QSIZE 256

/*====================End  Definitions ============================*/


/*----------------------------------------------------------------------------*
 *  typedef Struct
 *----------------------------------------------------------------------------*/
typedef void (*MailBoxCb)(BOOL exec_res, UINT32 req_id, void *ret_value);

 #if 0
typedef struct
{
    UINT8 	u1BufferNum;         // use total buffer number
    UINT8 	u18BitMode;         // dram in 8 bit or 10 bit mode
    UINT32	u4StartAddrY1;     // fbm allocate buffer start Physic address
    UINT32	u4SizeY1;    
    UINT32	u4StartAddrY2; 
    UINT32	u4SizeY2;
    UINT32	u4StartAddrY3; 
    UINT32	u4SizeY3;
    UINT32	u4StartAddrMV;
    UINT32	u4SizeMV;
    UINT32	u4StartAddrC1; 
    UINT32	u4SizeC1;
    UINT32	u4StartAddrC2; 
    UINT32	u4SizeC2;
    UINT32	u4StartAddrC3;
    UINT32	u4SizeC3;
    UINT32	u4Width;       // per buffer width
    UINT32	u4Height;     // per buffer heigh
} MJC_DRAM_CONFIG_T;
#endif
typedef struct
{
    UINT8 u1W10bitMode;         // set 10 bit or 8 bit mode
    UINT8 u1RepeatEn;          // WDMA repeat mode on off
    UINT8 u1RepeatMode;       // repeat mode select 
    UINT8 u1WAddrSelect;     // WDMA dram address from CMQ or register
    UINT8 u1WTriggerMode;   //Set WDMA trigger cmq signal
    UINT8 u1W420En;        // WDMA  444 to 420 on or off
    UINT8 u1WYUVEn;       //  WDMA  RGB to YUV on or off
    
}MJC_WDMA_T;

typedef struct
{
    UINT8 u1R10bitMode;   // set 10 bit or 8 bit mode
    UINT8 u1RAddrSelect; // RDMA dram address from CMQ or register
    UINT8 u1R444En;     // 420 to 444 enable
    UINT8 u1RGBEn;     // YUV to RGB enable
    UINT32 u4RVbp;    //vsync back proch 
    UINT32 u4RVDisp; // vsync back proch + v blanking
    
}MJC_RDMA_T;

typedef enum
{
    MJC_OUT_MODE_ORI = 0,
    MJC_OUT_MODE_MC,
    MJC_OUT_MODE_ORI_MC,
    MJC_OUT_MODE_DEBUG,
    MJC_OUT_MODE_MAX
}MJC_OUT_MODE;

typedef struct
{
    UINT8 u1BlkMode;
    UINT8 u1VsrchMode;
    UINT8  u1ActM3En;
    UINT8  u1ActM2En;
    UINT8  u1ActFilmMode;
    UINT8  u1ActIntpDen;
    UINT8  u1InitLoadMode;
    UINT8  u1ActPairFirst;
    UINT8  u1ActRescanEn;
    UINT8  u1ActBgmvKeep;
    UINT8  u1MvReadZeroPv;
    UINT8  u1MvReadZeroCu;
    UINT8  u1MvReadZeroBi;    
    UINT8  u1MvReadZeroTd;
    UINT8  u1Seq1stFrm;
    UINT32 u4PWidth;      
    UINT32 u4PHeight;     
    UINT32 u4RBlkPitch;
    UINT32 u4RYPitch;
    UINT32 u4RCbPitch;
    UINT32 u4RCrPitch;
    UINT32 u4WFrmPitch;
    UINT32 u4ActPbndDn;
    UINT32 u4ActPbndRt;
    UINT32 u4ActLpbDn;
    UINT32 u4ActLpbdRt;
}MJC_CORE_FS_T;
#if 0
typedef struct
{
    UINT32 u1ActFbY1Addr       : 4; // LSB
    UINT32 u1ActFbC1Addr       : 4;
    UINT32 u1ActFbY2Addr       : 4;
    UINT32 u1ActFbC2Addr       : 4;
    UINT32 u1ActFbY3Addr       : 4;
    UINT32 u1PldFbY1Addr       : 4;
    UINT32 u1PldFbC1Addr       : 4;
    UINT32 u1PldFbY2Addr       : 4; // MSB
} MJC_CMQ_REG00_T;

typedef union
{
    UINT32 u4Cmq00Data;
    MJC_CMQ_REG00_T arCmq00;
} MJC_CMQ_REG00_U;

typedef struct
{
    UINT32 u1PldFbC2Addr       : 4; // LSB
    UINT32 u1PldFbY3Addr       : 4;
    UINT32 u1MvBiWrAddr        : 4;
    UINT32 u1MvBiRdAddr        : 4;
    UINT32 u1MvCuWrAddr        : 4;
    UINT32 u1MvCuRdAddr        : 4;
    UINT32 u1MvPvRdAddr        : 4;
    UINT32 u1MvTdWrAddr        : 4; // MSB
} MJC_CMQ_REG01_T;

typedef union
{
    UINT32 u4Cmq01Data;
    MJC_CMQ_REG01_T arCmq01;
} MJC_CMQ_REG01_U;

typedef struct
{
    UINT32 u1MvTdRdAddr        : 4; // LSB
    UINT32 u1MvReadZeroPv      : 1;
    UINT32 u1MvReadZeroCu      : 1;
    UINT32 u1MvReadZeroBi      : 1;
    UINT32 u1MvReadZeroTd      : 1;
    UINT32 u1ActMePairFirst    : 1;
    UINT32 u1ActMePosOthrSel   : 2;
    UINT32 u1ActMeIdxToggle    : 1;
    UINT32 u1ActMe2460PreBi    : 1;
    UINT32 u1ActMe2460PreBiDly : 1;
    UINT32 u1PldMe2460PreBi    : 1;
    UINT32 u1ActMvExpFlag      : 1;
    UINT32 u1ActBgMvKeep       : 1;
    UINT32 u1ActMe3En          : 1;
    UINT32 u1ActMe2En          : 1;
    UINT32 u1ActMc2xMode       : 1;
    UINT32 u1Fs02NoCtrl        : 12; // MSB    
} MJC_CMQ_REG02_T;

typedef union
{
    UINT32 u4Cmq02Data;
    MJC_CMQ_REG02_T arCmq02;
} MJC_CMQ_REG02_U;
typedef struct
{
    UINT32 u1ActIntpDen        : 4; // LSB
    UINT32 u1ActIntpNum1       : 5;
    UINT32 u1ActIntpNum2       : 5;
    UINT32 u1ActPairFirst      : 1;
    UINT32 u1ActPairFirstDly   : 1;
    UINT32 u1PldPairFirst      : 1;
    UINT32 u1ActRescanFrmEn    : 1;
    UINT32 u1PldRescanFrmEn    : 1;
    UINT32 u1ActMeOnlyFrm      : 1;
    UINT32 u1PldMeOnlyFrm      : 1;
    UINT32 u1ActMcOriEn        : 1;
    UINT32 u1Fs03NoCtrl        : 10; // MSB
} MJC_CMQ_REG03_T;

typedef union
{
    UINT32 u4Cmq03Data;
    MJC_CMQ_REG03_T arCmq03;
} MJC_CMQ_REG03_U;
typedef struct
{
    UINT32 u2ActMv1Num         : 8; // LSB
    UINT32 u2ActMc1NumRgn0     : 8;
    UINT32 u2ActMc2NumRgn0     : 8;
    UINT32 u2Fs04NoCtrl        : 8; // MSB
} MJC_CMQ_REG04_T;

typedef union
{
    UINT32 u4Cmq04Data;
    MJC_CMQ_REG04_T arCmq04;
} MJC_CMQ_REG04_U;

typedef struct
{
    UINT32 u2ActMc2NumRgn1     : 8; // LSB
    UINT32 u2ActMc2NumRgn2     : 8;
    UINT32 u2ActMv2Num         : 8; 
    UINT32 u2Fs05NoCtrl        : 8; // MSB
} MJC_CMQ_REG05_T;

typedef union
{
    UINT32 u4Cmq05Data;
    MJC_CMQ_REG05_T arCmq05;
} MJC_CMQ_REG05_U;

typedef struct
{
    UINT32 u2ActMc1NumRgn1     : 8; // LSB
    UINT32 u2ActMc1NumRgn2     : 8;
    UINT32 u2Fs06NoCtrl        : 16; // MSB
} MJC_CMQ_REG06_T;

typedef union
{
    UINT32 u4Cmq06Data;
    MJC_CMQ_REG06_T arCmq06;
} MJC_CMQ_REG06_U;
typedef struct
{
    UINT32 u1RdmaReadYAddr     : 4; // LSB
    UINT32 u1RdmaReadCAddr     : 4;
    UINT32 u1WdmaWriteYAddr    : 4; 
    UINT32 u1WdmaWriteCAddr    : 4;
    UINT32 u1RdmaReadEn        : 1;
    UINT32 u1WdmaWrite         : 1;
    UINT32 u2Fs07NoCtrl        : 14; // MSB
} MJC_CMQ_REG07_T;

typedef union
{
    UINT32 u4Cmq07Data;
    MJC_CMQ_REG07_T arCmq07;
} MJC_CMQ_REG07_U;
#endif
#if 0
typedef struct
{
   MJC_CMQ_REG00_U unCmq00;
   MJC_CMQ_REG01_U unCmq01;
   MJC_CMQ_REG02_U unCmq02;
   MJC_CMQ_REG03_U unCmq03;
   MJC_CMQ_REG04_U unCmq04;
   MJC_CMQ_REG05_U unCmq05;
   MJC_CMQ_REG06_U unCmq06;
   MJC_CMQ_REG07_U unCmq07;
}MJC_CMQ_T;
typedef struct
{
    MJC_WDMA_T   rWdma;
    MJC_RDMA_T   rRdma;
    MJC_CMQ_T    rCmq;
    MJC_CORE_FS_T   rCoreFS;
    MJC_DRAM_CONFIG_T rMemory;
}MJC_DRV_HANDLE_T;

#endif
typedef enum
{
    FILM_DETECT_32322 = 0,
    FILM_DETECT_21111,
    FILM_DETECT_22,
    FILM_DETECT_32,
    FILM_DETECT_11,
    FILM_DETECT_MAX
}FILM_DETECT_MODE;
#if 0
enum
{
    E_Y_ADDR = 0,
    E_C_ADDR = 1,
};
enum
{
    E_MV_BI_ADDR = 0,
    E_MV_TD_ADDR = 1,
	E_MV_CU_WR_ADDR = 2,
	E_MV_CU_RD_ADDR = 3,
    E_MV_PV_ADDR = 4    
};
// 0 : Y1 address 1: c1 address 2: v1 address 3:y2 address 4: c2 address 5 :v2 address  6: y3 address
enum
{
    E_CORE_ACT_Y1_ADDR = 0,
    E_CORE_ACT_C1_ADDR = 1,
	E_CORE_ACT_V1_ADDR = 2,
	E_CORE_ACT_Y2_ADDR = 3,
    E_CORE_ACT_C2_ADDR = 4,
	E_CORE_ACT_V2_ADDR = 5,
    E_CORE_ACT_Y3_ADDR = 6    
};
enum
{
    E_CORE_PLD_Y1_ADDR = 0,
    E_CORE_PLD_C1_ADDR = 1,
	E_CORE_PLD_V1_ADDR = 2,
	E_CORE_PLD_Y2_ADDR = 3,
    E_CORE_PLD_C2_ADDR = 4,
	E_CORE_PLD_V2_ADDR = 5,
    E_CORE_PLD_Y3_ADDR = 6    
};
typedef enum
{
    CMQ_NONE      = 0,
    CMQ_32322_TO_60,
    CMQ_21111_TO_60,
    CMQ_22_TO_60,
    CMQ_32_TO_60, 
    CMQ_24_TO_48  ,
    CMQ_24_TO_60  ,
    CMQ_25_TO_50  ,
    CMQ_25_TO_60  ,
    CMQ_30_TO_60  ,
    CMQ_50_TO_50  ,
    CMQ_50_TO_60  ,
    CMQ_60_TO_60  ,
    CMQ_22_TO_120 ,
    CMQ_32_TO_120 ,
    CMQ_24_TO_120 ,
    CMQ_25_TO_100 ,
    CMQ_25_TO_120 ,
    CMQ_30_TO_120 ,
    CMQ_48_TO_120 ,
    CMQ_50_TO_100 ,
    CMQ_50_TO_120 ,
    CMQ_60_TO_120 ,
    CMQ_120_TO_120,
    CMQ_DYNA_MAX
}CMQ_DYNA_MODE;
#endif
typedef enum
{
     BYP_MJC_BY_FBM        = 0,
     BYP_MJC_BY_CLI        = 1,
     BYP_MJC_BY_APP        = 2,
     BYP_MJC_BY_GAME_MODE  = 3,
     BYP_MJC_BY_MJC        = 4,
     BYP_MJC_BY_EFUSE      = 5,
     BYP_MJC_BY_DEFINE     = 6,
     BYP_MJC_BY_PANEL      = 7,
     BYP_MJC_BY_MAX        = 8
}BYP_MJC_MODULE;


typedef enum
{
    RESET_RDMA_DONE = 0,
    RESET_RDMA_DONE_2,
    RESET_RDMA_OFF,
    ENABLE_CORE_IP,
    RESET_RDMA_ON,
    RESET_RDMA_ON_2
}RESET_RDMA_FLOW;


//-------------------------

#if 1
//#ifdef  BOAR_MJC
typedef enum
{
    MODE_10BITS = 0,
    MODE_8BITS  = 1,
    MODE_6BITS  = 2
}MJC_DRAM_MODE;

typedef enum
{
    MJC_NORMAL_MODE  = 0,
    MJC_REPEAT_MODE  = 1,
    MJC_GAME_MODE    = 2,
    MJC_BYPASS_MODE  =3,
    MJC_4K1K_REPEAT_MODE  =4,
	MJC_4K1K_NORMAL_MODE  =5,
	MJC_REPEAT422_MODE	= 6,
	MJC_4K1K_REPEAT422_MODE	= 7,
	MJC_MODE_MAX
}MJC_CTRL_MODE;

typedef enum
{
    MJC_NORMAL_MODE_4K2K  = 0,
    MJC_REPEAT_MODE_4K2K  = 1,
    MJC_NORMAL_MODE_4K1K  =2,
	MJC_REPEAT_MODE_4K1K  =3,
	MJC_MEMCMODE_MAX
}MJC_MODE;


typedef enum
{
    MJC_YUV422_MODE  = 0,
    MJC_RGB444_MODE  = 1,
	MJC_COLORIMETRY_MODE_MAX
}MJC_COLORIMETRY_MODE;


typedef enum
{
    MJC_INIT_DISP  = 0,
    MJC_MAIN_ONLY  = 1,
    MJC_PIP_MODE   = 2,
    MJC_PAP_MODE   = 3
}MJC_DISP_MODE;

typedef enum
{
    MJC_PIC_DEFAULT_MODE = 0,
    MJC_PIC_VIVID_MODE   = 1,
    MJC_PIC_STANDARD_MODE= 2,
    MJC_PIC_CUSTOM_MODE  =3,
    MJC_PIC_CINEMA_MODE  =4,
	MJC_PIC_GAME_GRAPHIC_PHOTO_MODE  =5,
	MJC_PIC_NEW_MODE1	= 6,
	MJC_PIC_NEW_MODE2	= 7,
	MJC_PIC_NEW_MODE3	= 8,
	MJC_PIC_NEW_MODE4	= 9,
	MJC_PIC_NEW_MODE5	= 10,
	MJC_PIC_MODE_MAX
}MJC_PIC_MODE;



typedef enum
{
    FRC_MB_CMD_NONE = 0x00,
    FRC_MB_CMD_SET_CHIP_TYPE_REVISION = 0x001,
    FRC_MB_CMD_SET_CUSTOMER_TYPE = 0x02,
    FRC_MB_CMD_GET_SW_VERSION = 0x03,
    FRC_MB_CMD_SET_MIRROR_MODE = 0x04, 
    
    FRC_MB_CMD_HV_ACTIVE = 0x10,
    FRC_MB_CMD_IN_OUT_FRAME_RATE = 0x11,
    FRC_MB_CMD_SET_FRC_RATE = 0x12,
    FRC_MB_CMD_SET_LOCK_STATUS = 0x13,
    FRC_MB_CMD_SET_MEMC_MODE = 0x14,
    FRC_MB_CMD_SET_FRAME_NUMBER = 0x15,
    
    FRC_MB_CMD_SET_MFC_DEMO_MODE = 0x17,
    FRC_MB_CMD_PAP_WINDOW_CTRL=0x18,
    FRC_MB_CMD_PIP_WINDOW_CTRL=0x1A,

    FRC_MB_CMD_SET_MFC_LEVEL = 0x1B,
    FRC_MB_CMD_SET_DEBLUR    = 0x1C,
    FRC_MB_CMD_SET_DEJUDDER = 0x1D,

    FRC_MB_CMD_SET_FILM_INK_ENABLE = 0x1E,
    FRC_MB_CMD_SET_FILM_LOG_ENABLE = 0x1F,
    FRC_MB_CMD_SET_FALLBACK_ENABLE = 0x20,
    FRC_MB_CMD_SET_SMALL_OBJECT = 0x21,
    FRC_MB_CMD_SET_HALO_WEIGHT = 0x22,
    FRC_MB_CMD_SET_GMV = 0x23,
    FRC_MB_CMD_SET_FAVOR = 0x24,
    FRC_MB_CMD_SET_ME_DEFORM = 0x25,
    FRC_MB_CMD_SET_ME_TRIBALL = 0x26,
    FRC_MB_CMD_SET_OOF_SAD = 0x27,
    FRC_MB_CMD_SET_ME_FLATDISSH4MV = 0x28,
    FRC_MB_CMD_SET_SNR_STRENGHT = 0x29,
    FRC_MB_CMD_SET_ERRBLK_MV0 = 0x2A,
    FRC_MB_CMD_SET_MI_DEFORM = 0x2B,
    FRC_MB_CMD_SET_SAD_CORING = 0x2C,
    FRC_MB_CMD_SET_BRIGHTNESS = 0x2D,
    FRC_MB_CMD_SET_SHIFT_8_MV = 0x2E,
    FRC_MB_CMD_SET_SIZE_PENALTY = 0x2F,
    FRC_MB_CMD_SET_OTHER_PAT_PATCH = 0x30,
    FRC_MB_CMD_SET_LETTERBOX_INK= 0x31,
    FRC_MB_CMD_SET_MV_INK= 0x32,
    FRC_MB_CMD_SET_LOG_DEBUG= 0x33,
    FRC_MB_CMD_SET_OTHER_DEBUG= 0x34,
    FRC_MB_CMD_SET_REGISTER = 0x35,
    FRC_MB_CMD_GET_REGISTER = 0x36,
    FRC_MB_CMD_SET_VRR_EN = 0x37,
    
    FRC_MB_CMD_SET_FREEZE = 0x100,
    
    FRC_MB_CMD_INIT = 0x800,
    FRC_MB_CMD_SET_FRAME_RATE = 0x801,
    FRC_MB_CMD_MJC_STS_DUMP = 0x802,
    FRC_MB_CMD_SET_DBG_LVL = 0x803,

	FRC_MB_CMD_SET_VDO_FMT = 0xD01,
	FRC_MB_CMD_SET_VDO_MODE = 0xD02,
	FRC_MB_CMD_SET_OSD_BYP_WIN = 0xD03,
	FRC_MB_CMD_SET_MFC_DEMO = 0xD04,
	FRC_MB_CMD_SET_FILM_CADNC_CTRL = 0xD05,
	FRC_MB_CMD_SET_VDO_DLY_ADJ = 0xD06,
	FRC_MB_CMD_SET_DEFLKER_CTRL = 0xD07,
	FRC_MB_CMD_SET_REL_POS_RATIO_IDX = 0xD0B,
	FRC_MB_CMD_SET_CHAOS_LVL_KEEP = 0xDE7,
	FRC_MB_CMD_SET_BLACK_BELT_SEL = 0xDE6,
	FRC_MB_CMD_SET_FUNC_EN = 0xD0C,
	FRC_MB_CMD_SET_ORI_IN_RES_INFO = 0xD0D,
	FRC_MB_CMD_SET_MODEL_NAME = 0xD0E,
	FRC_MB_CMD_SET_PIC_MODE = 0xD0F,
	FRC_MB_CMD_SET_IMPREME_FRM = 0xD10,
	FRC_MB_CMD_SET_POS_RATIO_TBL = 0xDE5,
	FRC_MB_CMD_SET_SHOW_FILE_CADNC_ERR_EN = 0xDEB,
} EnuFrcMailboxCmdType;



typedef struct
{
    UINT16 u2OnStartX;
    UINT16 u2OnStartY;
    UINT16 u2OnWidth;
    UINT16 u2OnHeight;

    UINT16 u2OffStartX;
    UINT16 u2OffStartY;
    UINT16 u2OffWidth;
    UINT16 u2OffHeight;

   // UINT8  fgMjcCtrlMode;
    UINT8  fgMjcDramMode;
    UINT8  fgMjcMuteSts;
    UINT8  u1MjcLevel;
    UINT8  u1MjcDeBlur;
    UINT8  u1MjcDeJudder;
    UINT16  u1MjcDemoMode;
    UINT8  u1MjcFrameNum;
    UINT8  u1MjcMemcMode;
    UINT8  u1MjcDispMode;
	
    UINT8  fgMjcFrameLockSts;
    UINT8  u1MjcInFramerate;
    UINT8  u1MjcOutFramerate;
	UINT8  u1FRCRate;
	UINT8  u1PictureMode;
	
    UINT8  u1MjcFreeze;
	UINT8  fg4K60;

	UINT16 u2MjcAddFrameDelay;
    
} MJC_CTRL_PARAS;

typedef struct 
{
	UINT16 message[16];
	MailBoxCb u4FuncPtr;
	UINT32 request_id;
	//UINT8  cmdType; //0:set, 1:get
	//void (*callback)(BOOL execution_result, UINT32 request_id); 
}MJC_QUEUE_ITEM;

typedef struct  
{
	UINT8 rptr;
	UINT8 wptr;
	MJC_QUEUE_ITEM q[MJC_QSIZE];
}MJC_MAILBOX_QUEUE;


//MODULE_OPM_MI_F3 base addr=0x10427800
//MODULE_OPM_ME_F2F3 base addr=0x10427400
//MODULE_OPM_MI_F2 base addr=0x10426800
//MODULE_IPM base addr=0x10426800
//IPM_MEDS, OPM_MEDS address
//X1,X2,Y2,F2,LP,S1,S2,HR23,HR
typedef struct
{
    UINT8   u1BufferNum;        // use total buffer number
    UINT8   u18BitMode;         // dram in 8 bit or 10 bit mode
    UINT32  u4Width;            // per buffer width
    UINT32  u4Height;           // per buffer heigh    

    UINT32 u4OpmMiF3Addr_L;
    UINT32 u4OpmMeF2F3Addr_L;
    UINT32 u4OpmMiF2Addr_L;
    UINT32 u4IpmAddr_L;
    UINT32 u4IpmMedsAddr_L;
    UINT32 u4OpmMedsAddr_L;

	UINT32 u4OpmMiF3Addr_R;
    UINT32 u4OpmMeF2F3Addr_R;
    UINT32 u4OpmMiF2Addr_R;
    UINT32 u4IpmAddr_R;
    UINT32 u4IpmMedsAddr_R;
    UINT32 u4OpmMedsAddr_R;

    UINT32 u4MemcX1S1Addr;
    UINT32 u4MemcX2Y2F2S2WrAddr;
	UINT32 u4MemcX2Y2F2S2RdAddr;
    UINT32 u4MemcHrRdAddr;
    UINT32 u4MemcHrWrAddr;	
    UINT32 u4MemcHr23RdAddr;
    UINT32 u4MemcHr23WrAddr;
	UINT32 u4MemcLOGOAddr;
	UINT32 u4MemcDEFLICKERAddr;
	UINT32 u4MemcOSDYSAddr;
} MJC_FBM_CONFIG_T;
#endif
//-------------------------
/*====================typedef Struct=====================*/


/*----------------------------------------------------------------------------*
 * Global/Static variables
 *----------------------------------------------------------------------------*/
//extern UINT8 fgIsMJCFlimMode ;
extern MJC_FBM_CONFIG_T arMJCDramConfig;  //update in mt5887
extern UINT8 fgSetCmqForceChg;
//extern UINT8 u1ForceMJCBypass;
//extern FILM_DETECT_MODE eCurFlimMode;
//extern FILM_DETECT_MODE ePreFlimMode;
//extern CMQ_DYNA_MODE u1CMQDynType;
//extern CMQ_DYNA_MODE u1MEMCModeStart;




/*====================End Global/Static variables =====================*/


/*----------------------------------------------------------------------------*
 * Function Members
 *----------------------------------------------------------------------------*/ 

void vDrvMJCSrmCb(UINT32 u4VdpId, UINT32 u4Mode, UINT32 u4PDSize, UINT32 u4SramMode);
UINT16 u1DrvMJCGetFrmDelay10x(void);
UINT8 u1DrvMJCIsOnOff(void);
UINT32 fgDrvMJCGetFlipMirror(void);
void vDrvMJCInit(UINT8 bForceInit);
void MJC_SetFilmMode(BOOL fgOnOff);
UINT32 u4DrvMJCGetFilmModeStatus(void);
void vDrvMJCMainloop(void);
//UINT8 fgDrvMJCIsMEMCSupported(VOID);
UINT8 vDrvMJCBufferInit(void);
void vDrvMJCBypassOnOff(BYP_MJC_MODULE eModule,UINT8 u1OnOff);
UINT8 vDrvMJCGetBypassVariable(BYP_MJC_MODULE eModule);
void vDrvMJCGameMode(UINT8 u1OnOff);
UINT8 u1DrvMJCInPipPopMode(void);
void vDrvMJCSetFreeze(UINT8 u1Onoff);
void vDrvMJCSetPatternGen(UINT32 u4InOut, UINT32 u4OnOff);
UINT8 u1DrvIsBypassPathToMJCPost(void);
#ifdef CC_SUPPORT_STR
void vDrvMJCSuspend(void);
void vDrvMJCResume(void);
#endif

//#ifdef MT5887_MJC 
void vDrvMJCBufferConfig(UINT32 u4MemcFbmStartAddr);
void vMjcSetMemcMode(UINT8 u1MemcMode);
void vMjcSetMemcModeIndex(UINT8 u1MemcMode, UINT8 u1TableIndex);
void vMjcSetMjcLevel(UINT8 u1MjcLevel);
UINT8 u1DrvGetMJCLevel(void);
UINT8 u1DrvGetMJCPictureMode(void);


UINT8 NptvMJCSetCommands(UINT16 *pBuf, UINT8 u1Len);
void vMjcMute(UINT8 u1MjcMuteCtrl);
void vMjcRegionUpdate(void);
void vMjcTestPattern(UINT8 fgCtrl);
void vMjcStatusQuery(void);
void vMjcControlMode(UINT8 u1CtrlMode);
void vMjcSetMemcFrameNum(UINT8 u1FrameNum);
void vDrvMJCRepeatMode(void);

void vDrvMJCSetISREnable(void);
void vDrvMJCInitISR(void);
void vDrvMJCSet3x3ExtTable(void);
void vMjcFunctionEnableStatus(void);
void vDrvMJCSetDramDisable(UINT8 bOnOff);


EXTERN void vDrvMjcOpmMiuCtrl( UINT8 fgMiuCtrl );
EXTERN void vDrvSetMjcIpmPten(UINT8 fgCtrl, UINT16 u2Width,UINT16 u2Height);
EXTERN void vDrvSetMjcOPmPat2F(UINT8 fgCtrl);
EXTERN void vDrvSetMjcOPmPatternSize(UINT8 u1Hsize,UINT8 u1Vsize);
EXTERN void vDrvSetMjcOPmPatternCtrl(UINT8 fgCtrl);
EXTERN void vDrvMjcCropInit(void);
EXTERN void vDrvMjcMiscOsdds(void);
EXTERN void vDrvMjcLineWidthHeight(UINT16 u2Width, UINT16 u2Height);


EXTERN void vDrvTriggerIRQToMJC(UINT32 u4IntNumber);
EXTERN void vDrvWriteMailBoxCmdtoMJC(UINT32 u4Addr,UINT16 u2CmdVal);
EXTERN void MHal_Cpu_SetRegR2En(UINT8 u1RiscSel,UINT8 u8val);
EXTERN void MHal_Cpu_SetRegR2SdrAddr(UINT8 u1RiscSel,UINT32 u4SdrAddr);
EXTERN void MHal_Cpu_SetRegR2QmemAddr(UINT8 u1RiscSel, UINT32 u4QmemAddr);
EXTERN void MHal_Cpu_R2QmemCtrl(UINT8 u1RiscSel,UINT8 u1QmemCtrl);
EXTERN void vMjcDemoMode(UINT16 u2DemoMode);
EXTERN void vMjcSetInoOutFrameRate(UINT8 u1InFrameRate,UINT8 u1OutFrameRate);
EXTERN void vMjcSetFRCRate(UINT8 u1FRCRate);
EXTERN void vMjcSetFrameLockSts(UINT8 fgLockSts);

EXTERN void vMjcSetVideoFormat(UINT8 u1InputWidth,UINT8 u1OutputWidth,UINT8 u1InputFrequency,UINT8 u1OutputFrequency);
EXTERN void vMjcSetVideoMode(UINT8 u1Mode);
EXTERN void vMjcSetOsdBypassWin(MailBoxCb callback, UINT32 req_id, UINT8 u1WinID,UINT8 u1WinEn,UINT16 u2WinStartX,UINT16 u2WinStartY,UINT16 u2WinWidth,UINT16 u2WinHeight);
EXTERN void vMjcSetMfcDemo(MailBoxCb callback, UINT32 req_id, UINT8 u1DemoMode,UINT8 u1BoarderLineWidth,UINT8 u1BoarderColor);
EXTERN void vMjcFilmCadanceControl(MailBoxCb callback, UINT32 req_id, UINT16 u2CadenceEnable);
EXTERN UINT8 vMjcVideoDelayAdjustment(MailBoxCb callback, UINT32 req_id, UINT16 u1AdditionalDelay, UINT16 *u2AdditionalDelayReturn);
EXTERN UINT16 vMjcGetVideoDelayAdjustment(UINT8 u1TotalDelay);
EXTERN void vMjcSetVideoDelayAdjustmentRuntime(UINT8 u1MemcMode);
EXTERN void vMjcVideoDelayAdjustmentIndex(UINT8 u1AdditionalDelay, UINT8 u1TableIndex);
EXTERN void vMjcDeflickerControl(MailBoxCb callback, UINT32 req_id, UINT8 u1DeflickerLevel,UINT8 u1AutoThLUp,UINT8 u1AutoThMUp,UINT8 u1AutoThHUp,UINT8 u1AutoThLDown,UINT8 u1AutoThMDown,UINT8 u1AutoThHDown); // reserved first
EXTERN void vMjcSet_RelPosRatioIndex(MailBoxCb callback, UINT32 req_id, UINT8 u1Index);
EXTERN void vMjcSetChaosLevelKeep(MailBoxCb callback, UINT32 req_id, UINT8 u1KeepValue);
EXTERN void vMjcSetBlackBeltSel(MailBoxCb callback, UINT32 req_id, UINT8 u1Sel);
EXTERN void vMjcFunctionEnable(MailBoxCb callback, UINT32 req_id, UINT8 u1FunctionSel,UINT8 u1Enable,UINT8 u1Parameter1);
EXTERN void vMjcOriInputResolutionInfo(MailBoxCb callback, UINT32 req_id, UINT16 u2Width,UINT16 u2Height);
EXTERN void vMjcSetModelName(MailBoxCb callback, UINT32 req_id, UINT8 u1ModelName,UINT8 u1PanelSize,UINT8 u1BackLightType);
EXTERN void vMjcPicMode(UINT8 u1PictureMode);
EXTERN void vMjcImpremetationFrame(MailBoxCb callback, UINT32 req_id, UINT8 u1Enable,UINT8 u1Index);
EXTERN void vMjcPositionRatioTable(MailBoxCb callback, UINT32 req_id, UINT8 u1Enable);
EXTERN void vMjcShowfileCadenceErrorEnable(MailBoxCb callback, UINT32 req_id, UINT8 u1Enable);

EXTERN void MEMC_VideoDelayAdjustmentCb(BOOL exec_res, UINT32 request_id, void *ret_value);

EXTERN BOOL vMjcSetMode(UINT8 u1MEMCMode, UINT8 u1ColorMode);
EXTERN void vMjcGetMode(UINT8 *u1MEMCMode, UINT8 *u1ColorMode);
EXTERN void vDrvMJCModeChangeDone(void);
void vMjcSetVrrEnable(MailBoxCb callback, UINT32 req_id,UINT8 u1Enable);
void vMjcSetLLDynMode(UINT8 u1Enable);

/*====================End  Function Members =======================*/
#endif
