
#ifndef _HW_SRS_H_
#define _HW_SRS_H_

#define SRS_TBL_A_SIZE  14336
#define SRS_TBL_B_SIZE  27776
#define SRS_TBL_A_NUM   20
#define SRS_TBL_B_NUM   8

#define SRS_BASE IO_VIRT+33000  //0x10033000

//Page SRS
#define SRS_0 (SRS_BASE + 0x500)
    #define C_SRS_DRAM_RD_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define C_TBL_UPDATE_TRIG Fld(1,30,AC_MSKB3)//[30:30]
    #define C_SRS_DRAM_ADR_A Fld(24,0,AC_MSKDW)//[23:0]
#define SRS_1 (SRS_BASE + 0x504)
    #define C_SRS_ADDR_MSB Fld(3,29,AC_MSKB3)//[31:29]
    #define C_SRS_RST_CTRL Fld(3,7,AC_MSKW10)//[9:7]
    #define C_DSR_DLY_SEL Fld(4,3,AC_MSKB0)//[6:3]
    #define C_SRS_DSR_ZERO_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define C_SRS_BYPASS Fld(1,1,AC_MSKB0)//[1:1]
    #define C_SRS_CLK_EN Fld(1,0,AC_MSKB0)//[0:0]
#define SRS_2 (SRS_BASE + 0x508)
    #define C_SRS_DRAM_ADR_B Fld(24,8,AC_MSKDW)//[31:8]
    #define C_SRS_DRAM_ADR_B_EN Fld(1,0,AC_MSKB0)//[0:0]
#define SRS_3 (SRS_BASE + 0x50C)
    #define C_SRS_4K1K_MASK_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define C_LUT_A_DAT_CNT Fld(8,23,AC_MSKW32)//[30:23]
    #define C_SRS_RDY_ERR_CLEAN Fld(1,22,AC_MSKB2)//[22:22]
    #define STA_SRS_RDY_ERR Fld(1,21,AC_MSKB2)//[21:21]
    #define STA_SRS_DSR Fld(11,10,AC_MSKW21)//[20:10]
    #define STA_DRAM_FIN_CNT Fld(8,2,AC_MSKW10)//[9:2]
    #define STA_TBL_UPDATE Fld(2,0,AC_MSKB0)//[1:0]

#define TDPROC_MISC_SRS (IO_VIRT+0x27350) //(0xF0027350)
    #define LINEBUF_4SRS_EN Fld(1,3,AC_MSKB0)//[3:3]

#define YCPROC_SRS (IO_VIRT+0x5D020)//(0xF005D020)
    #define SRS_EN Fld(1,27,AC_MSKB3)//[27:27]



#endif
