#ifndef __DT_BINDINGS_CLOCK_RLX_H
#define __DT_BINDINGS_CLOCK_RLX_H

#define RLX_CLK_DUMMY			0
#define RLX_CLK_SYS_OSC			1
#define RLX_CLK_USB_PLL			2
#define RLX_CLK_USB_PLL_2		3
#define RLX_CLK_USB_PLL_3		4
#define RLX_CLK_USB_PLL_5		5
#define RLX_CLK_USB_PLL_7		6
#define RLX_CLK_SYS_PLL0		7
#define RLX_CLK_SYS_PLL1		8
#define RLX_CLK_SYS_PLL2		9
#define RLX_CLK_SYS_PLL3		10
#define RLX_CLK_SYS_PLL0_2		11
#define RLX_CLK_SYS_PLL0_3		12
#define RLX_CLK_SYS_PLL0_5		13
#define RLX_CLK_SYS_PLL0_7		14
#define RLX_CLK_SYS_PLL1_2		15
#define RLX_CLK_SYS_PLL1_3		16
#define RLX_CLK_SYS_PLL1_5		17
#define RLX_CLK_SYS_PLL1_7		18
#define RLX_CLK_SYS_PLL2_2		19
#define RLX_CLK_SYS_PLL2_3		20
#define RLX_CLK_SYS_PLL2_5		21
#define RLX_CLK_SYS_PLL2_7		22
#define RLX_CLK_SYS_PLL3_2		23
#define RLX_CLK_SYS_PLL3_3		24
#define RLX_CLK_SYS_PLL3_5		25
#define RLX_CLK_SYS_PLL3_7		26
#define RLX_CLK_DMA_CK			27
#define RLX_CLK_USBPHY_HOST_CK		28
#define RLX_CLK_USBPHY_DEV_CK		29
#define RLX_CLK_ETHERNET_CK		30
#define RLX_CLK_CPU_CK_DIV		31
#define RLX_CLK_CPU_CK_DEC		32
#define RLX_CLK_CPU_CK			33
#define RLX_CLK_H264_CK_DIV		34
#define RLX_CLK_H264_CK_DEC		35
#define RLX_CLK_H264_CK			36
#define RLX_CLK_JPEG_CK_DIV		37
#define RLX_CLK_JPEG_CK_DEC		38
#define RLX_CLK_JPEG_CK			39
#define RLX_CLK_BUS_CK_DIV		40
#define RLX_CLK_BUS_CK_DEC		41
#define RLX_CLK_BUS_CK			42
#define RLX_CLK_DRAM_CK_DIV		43
#define RLX_CLK_DRAM_CK_DEC		44
#define RLX_CLK_DRAM_CK			45
#define RLX_CLK_ISP_CK_DIV		46
#define RLX_CLK_ISP_CK_DEC		47
#define RLX_CLK_ISP_CK			48
#define RLX_CLK_MIPI_CK_DIV		49
#define RLX_CLK_MIPI_CK_DEC		50
#define RLX_CLK_MIPI_CK			51
#define RLX_CLK_I2C_CK_DIV		52
#define RLX_CLK_I2C_CK			53
#define RLX_CLK_XB2_CK_DIV		54
#define RLX_CLK_XB2_CK			55
#define RLX_CLK_UART_CK_DIV		56
#define RLX_CLK_UART_CK			57
#define RLX_CLK_I2S_CK_DIV		58
#define RLX_CLK_I2S_CK			59
#define RLX_CLK_SPDIF_CK_DIV		60
#define RLX_CLK_SPDIF_CK		61
#define RLX_CLK_CODEC_CK_DIV		62
#define RLX_CLK_CODEC_CK		63
#define RLX_CLK_MCU_CK			64
#define RLX_CLK_CIPHER_CK		65
#define RLX_CLK_H265_ACLK_CK	66
#define RLX_CLK_H265_BCLK_CK_DIV	67
#define RLX_CLK_H265_BCLK_CK_DEC	68
#define RLX_CLK_H265_BCLK_CK	69
#define RLX_CLK_H265_CCLK_CK_DIV	70
#define RLX_CLK_H265_CCLK_CK_DEC	71
#define RLX_CLK_H265_CCLK_CK	72
#define RLX_CLK_H265_CK	73

#endif
